2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
3
4/*-
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
38 *
39 * #include <powerpc/aim/trap_subr.S>
40 */
41
42/*
43 * Save/restore segment registers
44 */
45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \
46 lwz sr,1*4(pmap); mtsr 1,sr; \
47 lwz sr,2*4(pmap); mtsr 2,sr; \
48 lwz sr,3*4(pmap); mtsr 3,sr; \
49 lwz sr,4*4(pmap); mtsr 4,sr; \
50 lwz sr,5*4(pmap); mtsr 5,sr; \
51 lwz sr,6*4(pmap); mtsr 6,sr; \
52 lwz sr,7*4(pmap); mtsr 7,sr; \
53 lwz sr,8*4(pmap); mtsr 8,sr; \
54 lwz sr,9*4(pmap); mtsr 9,sr; \
55 lwz sr,10*4(pmap); mtsr 10,sr; \
56 lwz sr,11*4(pmap); mtsr 11,sr; \
57 /* Skip segment 12 (USER_SR), which is restored differently */ \
58 lwz sr,13*4(pmap); mtsr 13,sr; \
59 lwz sr,14*4(pmap); mtsr 14,sr; \
60 lwz sr,15*4(pmap); mtsr 15,sr; isync;
61
62/*
63 * User SRs are loaded through a pointer to the current pmap.
64 */
65#define RESTORE_USER_SRS(pmap,sr) \
66 GET_CPUINFO(pmap); \
67 lwz pmap,PC_CURPMAP(pmap); \
68 lwzu sr,PM_SR(pmap); \
69 RESTORE_SRS(pmap,sr) \
70 /* Restore SR 12 */ \
71 lwz sr,12*4(pmap); mtsr 12,sr
72
73/*
74 * Kernel SRs are loaded directly from kernel_pmap_
75 */
76#define RESTORE_KERN_SRS(pmap,sr) \
77 lis pmap,CNAME(kernel_pmap_store)@ha; \
78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
79 RESTORE_SRS(pmap,sr)
80
81/*
82 * FRAME_SETUP assumes:
83 * SPRG1 SP (1)
84 * SPRG3 trap type
85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
86 * r28 LR
87 * r29 CR
88 * r30 scratch
89 * r31 scratch
90 * r1 kernel stack
91 * SRR0/1 as at start of trap
92 */
93#define FRAME_SETUP(savearea) \
94/* Have to enable translation to allow access of kernel stack: */ \
95 GET_CPUINFO(%r31); \
96 mfsrr0 %r30; \
97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
98 mfsrr1 %r30; \
99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
100 mfmsr %r30; \
101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
102 mtmsr %r30; /* stack can now be accessed */ \
103 isync; \
104 mfsprg1 %r31; /* get saved SP */ \
105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \
106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \
107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \
108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \
109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \
110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \
111 GET_CPUINFO(%r2); \
112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \
117 stw %r4, FRAME_4+8(%r1); \
118 stw %r5, FRAME_5+8(%r1); \
119 stw %r6, FRAME_6+8(%r1); \
120 stw %r7, FRAME_7+8(%r1); \
121 stw %r8, FRAME_8+8(%r1); \
122 stw %r9, FRAME_9+8(%r1); \
123 stw %r10, FRAME_10+8(%r1); \
124 stw %r11, FRAME_11+8(%r1); \
125 stw %r12, FRAME_12+8(%r1); \
126 stw %r13, FRAME_13+8(%r1); \
127 stw %r14, FRAME_14+8(%r1); \
128 stw %r15, FRAME_15+8(%r1); \
129 stw %r16, FRAME_16+8(%r1); \
130 stw %r17, FRAME_17+8(%r1); \
131 stw %r18, FRAME_18+8(%r1); \
132 stw %r19, FRAME_19+8(%r1); \
133 stw %r20, FRAME_20+8(%r1); \
134 stw %r21, FRAME_21+8(%r1); \
135 stw %r22, FRAME_22+8(%r1); \
136 stw %r23, FRAME_23+8(%r1); \
137 stw %r24, FRAME_24+8(%r1); \
138 stw %r25, FRAME_25+8(%r1); \
139 stw %r26, FRAME_26+8(%r1); \
140 stw %r27, FRAME_27+8(%r1); \
141 stw %r28, FRAME_28+8(%r1); \
142 stw %r29, FRAME_29+8(%r1); \
143 stw %r30, FRAME_30+8(%r1); \
144 stw %r31, FRAME_31+8(%r1); \
145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
149 mfxer %r3; \
150 mfctr %r4; \
151 mfsprg3 %r5; \
152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
153 stw %r4, FRAME_CTR+8(1); \
154 stw %r5, FRAME_EXC+8(1); \
155 stw %r28,FRAME_AIM_DAR+8(1); \
156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
157 stw %r30,FRAME_SRR0+8(1); \
158 stw %r31,FRAME_SRR1+8(1); \
159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */
160
161#define FRAME_LEAVE(savearea) \
162/* Disable exceptions: */ \
163 mfmsr %r2; \
164 andi. %r2,%r2,~PSL_EE@l; \
165 mtmsr %r2; \
166 isync; \
167/* Now restore regs: */ \
168 lwz %r2,FRAME_SRR0+8(%r1); \
169 lwz %r3,FRAME_SRR1+8(%r1); \
170 lwz %r4,FRAME_CTR+8(%r1); \
171 lwz %r5,FRAME_XER+8(%r1); \
172 lwz %r6,FRAME_LR+8(%r1); \
173 GET_CPUINFO(%r7); \
174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
176 lwz %r7,FRAME_CR+8(%r1); \
177 mtctr %r4; \
178 mtxer %r5; \
179 mtlr %r6; \
180 mtsprg1 %r7; /* save cr */ \
181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \
182 lwz %r30,FRAME_30+8(%r1); \
183 lwz %r29,FRAME_29+8(%r1); \
184 lwz %r28,FRAME_28+8(%r1); \
185 lwz %r27,FRAME_27+8(%r1); \
186 lwz %r26,FRAME_26+8(%r1); \
187 lwz %r25,FRAME_25+8(%r1); \
188 lwz %r24,FRAME_24+8(%r1); \
189 lwz %r23,FRAME_23+8(%r1); \
190 lwz %r22,FRAME_22+8(%r1); \
191 lwz %r21,FRAME_21+8(%r1); \
192 lwz %r20,FRAME_20+8(%r1); \
193 lwz %r19,FRAME_19+8(%r1); \
194 lwz %r18,FRAME_18+8(%r1); \
195 lwz %r17,FRAME_17+8(%r1); \
196 lwz %r16,FRAME_16+8(%r1); \
197 lwz %r15,FRAME_15+8(%r1); \
198 lwz %r14,FRAME_14+8(%r1); \
199 lwz %r13,FRAME_13+8(%r1); \
200 lwz %r12,FRAME_12+8(%r1); \
201 lwz %r11,FRAME_11+8(%r1); \
202 lwz %r10,FRAME_10+8(%r1); \
203 lwz %r9, FRAME_9+8(%r1); \
204 lwz %r8, FRAME_8+8(%r1); \
205 lwz %r7, FRAME_7+8(%r1); \
206 lwz %r6, FRAME_6+8(%r1); \
207 lwz %r5, FRAME_5+8(%r1); \
208 lwz %r4, FRAME_4+8(%r1); \
209 lwz %r3, FRAME_3+8(%r1); \
210 lwz %r2, FRAME_2+8(%r1); \
211 lwz %r0, FRAME_0+8(%r1); \
212 lwz %r1, FRAME_1+8(%r1); \
213/* Can't touch %r1 from here on */ \
214 mtsprg2 %r2; /* save r2 & r3 */ \
215 mtsprg3 %r3; \
216/* Disable translation, machine check and recoverability: */ \
217 mfmsr %r2; \
218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
219 mtmsr %r2; \
220 isync; \
221/* Decide whether we return to user mode: */ \
222 GET_CPUINFO(%r2); \
223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \
224 mtcr %r3; \
225 bf 17,1f; /* branch if PSL_PR is false */ \
226/* Restore user SRs */ \
227 RESTORE_USER_SRS(%r2,%r3); \
2281: mfsprg1 %r2; /* restore cr */ \
229 mtcr %r2; \
230 GET_CPUINFO(%r2); \
231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
232 mtsrr0 %r3; \
233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
234 \
235 /* Make sure HV bit of MSR propagated to SRR1 */ \
236 mfmsr %r2; \
237 or %r3,%r2,%r3; \
238 \
239 mtsrr1 %r3; \
240 mfsprg2 %r2; /* restore r2 & r3 */ \
241 mfsprg3 %r3
242
243#ifdef KDTRACE_HOOKS
244 .data
| 2/* $NetBSD: trap_subr.S,v 1.20 2002/04/22 23:20:08 kleink Exp $ */
3
4/*-
5 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
6 * Copyright (C) 1995, 1996 TooLs GmbH.
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed by TooLs GmbH.
20 * 4. The name of TooLs GmbH may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
27 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
28 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
29 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
31 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
32 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/*
36 * NOTICE: This is not a standalone file. to use it, #include it in
37 * your port's locore.S, like so:
38 *
39 * #include <powerpc/aim/trap_subr.S>
40 */
41
42/*
43 * Save/restore segment registers
44 */
45#define RESTORE_SRS(pmap,sr) mtsr 0,sr; \
46 lwz sr,1*4(pmap); mtsr 1,sr; \
47 lwz sr,2*4(pmap); mtsr 2,sr; \
48 lwz sr,3*4(pmap); mtsr 3,sr; \
49 lwz sr,4*4(pmap); mtsr 4,sr; \
50 lwz sr,5*4(pmap); mtsr 5,sr; \
51 lwz sr,6*4(pmap); mtsr 6,sr; \
52 lwz sr,7*4(pmap); mtsr 7,sr; \
53 lwz sr,8*4(pmap); mtsr 8,sr; \
54 lwz sr,9*4(pmap); mtsr 9,sr; \
55 lwz sr,10*4(pmap); mtsr 10,sr; \
56 lwz sr,11*4(pmap); mtsr 11,sr; \
57 /* Skip segment 12 (USER_SR), which is restored differently */ \
58 lwz sr,13*4(pmap); mtsr 13,sr; \
59 lwz sr,14*4(pmap); mtsr 14,sr; \
60 lwz sr,15*4(pmap); mtsr 15,sr; isync;
61
62/*
63 * User SRs are loaded through a pointer to the current pmap.
64 */
65#define RESTORE_USER_SRS(pmap,sr) \
66 GET_CPUINFO(pmap); \
67 lwz pmap,PC_CURPMAP(pmap); \
68 lwzu sr,PM_SR(pmap); \
69 RESTORE_SRS(pmap,sr) \
70 /* Restore SR 12 */ \
71 lwz sr,12*4(pmap); mtsr 12,sr
72
73/*
74 * Kernel SRs are loaded directly from kernel_pmap_
75 */
76#define RESTORE_KERN_SRS(pmap,sr) \
77 lis pmap,CNAME(kernel_pmap_store)@ha; \
78 lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
79 RESTORE_SRS(pmap,sr)
80
81/*
82 * FRAME_SETUP assumes:
83 * SPRG1 SP (1)
84 * SPRG3 trap type
85 * savearea r28-r31,DAR,DSISR (DAR & DSISR only for DSI traps)
86 * r28 LR
87 * r29 CR
88 * r30 scratch
89 * r31 scratch
90 * r1 kernel stack
91 * SRR0/1 as at start of trap
92 */
93#define FRAME_SETUP(savearea) \
94/* Have to enable translation to allow access of kernel stack: */ \
95 GET_CPUINFO(%r31); \
96 mfsrr0 %r30; \
97 stw %r30,(savearea+CPUSAVE_SRR0)(%r31); /* save SRR0 */ \
98 mfsrr1 %r30; \
99 stw %r30,(savearea+CPUSAVE_SRR1)(%r31); /* save SRR1 */ \
100 mfmsr %r30; \
101 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
102 mtmsr %r30; /* stack can now be accessed */ \
103 isync; \
104 mfsprg1 %r31; /* get saved SP */ \
105 stwu %r31,-FRAMELEN(%r1); /* save it in the callframe */ \
106 stw %r0, FRAME_0+8(%r1); /* save r0 in the trapframe */ \
107 stw %r31,FRAME_1+8(%r1); /* save SP " " */ \
108 stw %r2, FRAME_2+8(%r1); /* save r2 " " */ \
109 stw %r28,FRAME_LR+8(%r1); /* save LR " " */ \
110 stw %r29,FRAME_CR+8(%r1); /* save CR " " */ \
111 GET_CPUINFO(%r2); \
112 lwz %r28,(savearea+CPUSAVE_R28)(%r2); /* get saved r28 */ \
113 lwz %r29,(savearea+CPUSAVE_R29)(%r2); /* get saved r29 */ \
114 lwz %r30,(savearea+CPUSAVE_R30)(%r2); /* get saved r30 */ \
115 lwz %r31,(savearea+CPUSAVE_R31)(%r2); /* get saved r31 */ \
116 stw %r3, FRAME_3+8(%r1); /* save r3-r31 */ \
117 stw %r4, FRAME_4+8(%r1); \
118 stw %r5, FRAME_5+8(%r1); \
119 stw %r6, FRAME_6+8(%r1); \
120 stw %r7, FRAME_7+8(%r1); \
121 stw %r8, FRAME_8+8(%r1); \
122 stw %r9, FRAME_9+8(%r1); \
123 stw %r10, FRAME_10+8(%r1); \
124 stw %r11, FRAME_11+8(%r1); \
125 stw %r12, FRAME_12+8(%r1); \
126 stw %r13, FRAME_13+8(%r1); \
127 stw %r14, FRAME_14+8(%r1); \
128 stw %r15, FRAME_15+8(%r1); \
129 stw %r16, FRAME_16+8(%r1); \
130 stw %r17, FRAME_17+8(%r1); \
131 stw %r18, FRAME_18+8(%r1); \
132 stw %r19, FRAME_19+8(%r1); \
133 stw %r20, FRAME_20+8(%r1); \
134 stw %r21, FRAME_21+8(%r1); \
135 stw %r22, FRAME_22+8(%r1); \
136 stw %r23, FRAME_23+8(%r1); \
137 stw %r24, FRAME_24+8(%r1); \
138 stw %r25, FRAME_25+8(%r1); \
139 stw %r26, FRAME_26+8(%r1); \
140 stw %r27, FRAME_27+8(%r1); \
141 stw %r28, FRAME_28+8(%r1); \
142 stw %r29, FRAME_29+8(%r1); \
143 stw %r30, FRAME_30+8(%r1); \
144 stw %r31, FRAME_31+8(%r1); \
145 lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
146 lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
147 lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
148 lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
149 mfxer %r3; \
150 mfctr %r4; \
151 mfsprg3 %r5; \
152 stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
153 stw %r4, FRAME_CTR+8(1); \
154 stw %r5, FRAME_EXC+8(1); \
155 stw %r28,FRAME_AIM_DAR+8(1); \
156 stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
157 stw %r30,FRAME_SRR0+8(1); \
158 stw %r31,FRAME_SRR1+8(1); \
159 lwz %r2,PC_CURTHREAD(%r2) /* set curthread pointer */
160
161#define FRAME_LEAVE(savearea) \
162/* Disable exceptions: */ \
163 mfmsr %r2; \
164 andi. %r2,%r2,~PSL_EE@l; \
165 mtmsr %r2; \
166 isync; \
167/* Now restore regs: */ \
168 lwz %r2,FRAME_SRR0+8(%r1); \
169 lwz %r3,FRAME_SRR1+8(%r1); \
170 lwz %r4,FRAME_CTR+8(%r1); \
171 lwz %r5,FRAME_XER+8(%r1); \
172 lwz %r6,FRAME_LR+8(%r1); \
173 GET_CPUINFO(%r7); \
174 stw %r2,(savearea+CPUSAVE_SRR0)(%r7); /* save SRR0 */ \
175 stw %r3,(savearea+CPUSAVE_SRR1)(%r7); /* save SRR1 */ \
176 lwz %r7,FRAME_CR+8(%r1); \
177 mtctr %r4; \
178 mtxer %r5; \
179 mtlr %r6; \
180 mtsprg1 %r7; /* save cr */ \
181 lwz %r31,FRAME_31+8(%r1); /* restore r0-31 */ \
182 lwz %r30,FRAME_30+8(%r1); \
183 lwz %r29,FRAME_29+8(%r1); \
184 lwz %r28,FRAME_28+8(%r1); \
185 lwz %r27,FRAME_27+8(%r1); \
186 lwz %r26,FRAME_26+8(%r1); \
187 lwz %r25,FRAME_25+8(%r1); \
188 lwz %r24,FRAME_24+8(%r1); \
189 lwz %r23,FRAME_23+8(%r1); \
190 lwz %r22,FRAME_22+8(%r1); \
191 lwz %r21,FRAME_21+8(%r1); \
192 lwz %r20,FRAME_20+8(%r1); \
193 lwz %r19,FRAME_19+8(%r1); \
194 lwz %r18,FRAME_18+8(%r1); \
195 lwz %r17,FRAME_17+8(%r1); \
196 lwz %r16,FRAME_16+8(%r1); \
197 lwz %r15,FRAME_15+8(%r1); \
198 lwz %r14,FRAME_14+8(%r1); \
199 lwz %r13,FRAME_13+8(%r1); \
200 lwz %r12,FRAME_12+8(%r1); \
201 lwz %r11,FRAME_11+8(%r1); \
202 lwz %r10,FRAME_10+8(%r1); \
203 lwz %r9, FRAME_9+8(%r1); \
204 lwz %r8, FRAME_8+8(%r1); \
205 lwz %r7, FRAME_7+8(%r1); \
206 lwz %r6, FRAME_6+8(%r1); \
207 lwz %r5, FRAME_5+8(%r1); \
208 lwz %r4, FRAME_4+8(%r1); \
209 lwz %r3, FRAME_3+8(%r1); \
210 lwz %r2, FRAME_2+8(%r1); \
211 lwz %r0, FRAME_0+8(%r1); \
212 lwz %r1, FRAME_1+8(%r1); \
213/* Can't touch %r1 from here on */ \
214 mtsprg2 %r2; /* save r2 & r3 */ \
215 mtsprg3 %r3; \
216/* Disable translation, machine check and recoverability: */ \
217 mfmsr %r2; \
218 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
219 mtmsr %r2; \
220 isync; \
221/* Decide whether we return to user mode: */ \
222 GET_CPUINFO(%r2); \
223 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); \
224 mtcr %r3; \
225 bf 17,1f; /* branch if PSL_PR is false */ \
226/* Restore user SRs */ \
227 RESTORE_USER_SRS(%r2,%r3); \
2281: mfsprg1 %r2; /* restore cr */ \
229 mtcr %r2; \
230 GET_CPUINFO(%r2); \
231 lwz %r3,(savearea+CPUSAVE_SRR0)(%r2); /* restore srr0 */ \
232 mtsrr0 %r3; \
233 lwz %r3,(savearea+CPUSAVE_SRR1)(%r2); /* restore srr1 */ \
234 \
235 /* Make sure HV bit of MSR propagated to SRR1 */ \
236 mfmsr %r2; \
237 or %r3,%r2,%r3; \
238 \
239 mtsrr1 %r3; \
240 mfsprg2 %r2; /* restore r2 & r3 */ \
241 mfsprg3 %r3
242
243#ifdef KDTRACE_HOOKS
244 .data
|
252 .globl dtrace_invop_calltrap_addr
253 .align 4
254 .type dtrace_invop_calltrap_addr, @object
255 .size dtrace_invop_calltrap_addr, 4
256dtrace_invop_calltrap_addr:
257 .word 0
258 .word 0
259
260 .text
261#endif
262
263/*
264 * The next two routines are 64-bit glue code. The first is used to test if
265 * we are on a 64-bit system. By copying it to the illegal instruction
266 * handler, we can test for 64-bit mode by trying to execute a 64-bit
267 * instruction and seeing what happens. The second gets copied in front
268 * of all the other handlers to restore 32-bit bridge mode when traps
269 * are taken.
270 */
271
272/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */
273
274 .globl CNAME(testppc64),CNAME(testppc64size)
275CNAME(testppc64):
276 mtsprg1 %r31
277 mfsrr0 %r31
278 addi %r31, %r31, 4
279 mtsrr0 %r31
280
281 li %r31, 0
282 mtsprg2 %r31
283 mfsprg1 %r31
284
285 rfi
286CNAME(testppc64size) = .-CNAME(testppc64)
287
288
289/* 64-bit bridge mode restore snippet. Gets copied in front of everything else
290 * on 64-bit systems. */
291
292 .globl CNAME(restorebridge),CNAME(restorebridgesize)
293CNAME(restorebridge):
294 mtsprg1 %r31
295 mfmsr %r31
296 clrldi %r31,%r31,1
297 mtmsrd %r31
298 mfsprg1 %r31
299 isync
300CNAME(restorebridgesize) = .-CNAME(restorebridge)
301
302#ifdef SMP
303/*
304 * Processor reset exception handler. These are typically
305 * the first instructions the processor executes after a
306 * software reset. We do this in two bits so that we are
307 * not still hanging around in the trap handling region
308 * once the MMU is turned on.
309 */
310 .globl CNAME(rstcode), CNAME(rstsize)
311CNAME(rstcode):
312 ba cpu_reset
313CNAME(rstsize) = . - CNAME(rstcode)
314
315cpu_reset:
316 bl 1f
317
318 .space 124
319
3201:
321 mflr %r1
322 addi %r1,%r1,(124-16)@l
323
324 lis %r3,1@l
325 bla CNAME(cpudep_ap_early_bootstrap)
326 lis %r3,1@l
327 bla CNAME(pmap_cpu_bootstrap)
328 bla CNAME(cpudep_ap_bootstrap)
329 mr %r1,%r3
330 bla CNAME(machdep_ap_bootstrap)
331
332 /* Should not be reached */
3339:
334 b 9b
335#endif
336
337/*
338 * This code gets copied to all the trap vectors
339 * (except ISI/DSI, ALI, and the interrupts)
340 */
341
342 .globl CNAME(trapcode),CNAME(trapsize)
343CNAME(trapcode):
344 mtsprg1 %r1 /* save SP */
345 mflr %r1 /* Save the old LR in r1 */
346 mtsprg2 %r1 /* And then in SPRG2 */
347 li %r1, 0x20 /* How to get the vector from LR */
348 bla generictrap /* LR & SPRG3 is exception # */
349CNAME(trapsize) = .-CNAME(trapcode)
350
351/*
352 * 64-bit version of trapcode. Identical, except it calls generictrap64.
353 */
354 .globl CNAME(trapcode64)
355CNAME(trapcode64):
356 mtsprg1 %r1 /* save SP */
357 mflr %r1 /* Save the old LR in r1 */
358 mtsprg2 %r1 /* And then in SPRG2 */
359 li %r1, 0x20 /* How to get the vector from LR */
360 bla generictrap64 /* LR & SPRG3 is exception # */
361
362/*
363 * For ALI: has to save DSISR and DAR
364 */
365 .globl CNAME(alitrap),CNAME(alisize)
366CNAME(alitrap):
367 mtsprg1 %r1 /* save SP */
368 GET_CPUINFO(%r1)
369 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
370 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
371 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
372 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
373 mfdar %r30
374 mfdsisr %r31
375 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
376 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
377 mfsprg1 %r1 /* restore SP, in case of branch */
378 mflr %r28 /* save LR */
379 mfcr %r29 /* save CR */
380
381 /* Put our exception vector in SPRG3 */
382 li %r31, EXC_ALI
383 mtsprg3 %r31
384
385 /* Test whether we already had PR set */
386 mfsrr1 %r31
387 mtcr %r31
388 bla s_trap
389CNAME(alisize) = .-CNAME(alitrap)
390
391/*
392 * G2 specific: instuction TLB miss.
393 */
394 .globl CNAME(imisstrap),CNAME(imisssize)
395CNAME(imisstrap):
396 mfspr %r2, SPR_HASH1 /* get first pointer */
397 addi %r1, 0, 8 /* load 8 for counter */
398 mfctr %r0 /* save counter */
399 mfspr %r3, SPR_ICMP /* get first compare value */
400 addi %r2, %r2, -8 /* pre dec the pointer */
401im0:
402 mtctr %r1 /* load counter */
403im1:
404 lwzu %r1, 8(%r2) /* get next pte */
405 cmp 0, %r1, %r3 /* see if found pte */
406 bdnzf 2, im1 /* dec count br if cmp ne and if
407 * count not zero */
408 bne instr_sec_hash /* if not found set up second hash
409 * or exit */
410 lwz %r1, +4(%r2) /* load tlb entry lower-word */
411 andi. %r3, %r1, 8 /* check G bit */
412 bne do_isi_prot /* if guarded, take an ISI */
413 mtctr %r0 /* restore counter */
414 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */
415 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
416 mtcrf 0x80, %r3 /* restore CR0 */
417 mtspr SPR_RPA, %r1 /* set the pte */
418 ori %r1, %r1, 0x100 /* set reference bit */
419 srwi %r1, %r1, 8 /* get byte 7 of pte */
420 tlbli %r0 /* load the itlb */
421 stb %r1, +6(%r2) /* update page table */
422 rfi /* return to executing program */
423
424instr_sec_hash:
425 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
426 bne do_isi /* if so, go to ISI interrupt */
427 mfspr %r2, SPR_HASH2 /* get the second pointer */
428 ori %r3, %r3, 0x0040 /* change the compare value */
429 addi %r1, %r0, 8 /* load 8 for counter */
430 addi %r2, %r2, -8 /* pre dec for update on load */
431 b im0 /* try second hash */
432
433/* Create a faked ISI interrupt as the address was not found */
434do_isi_prot:
435 mfspr %r3, SPR_SRR1 /* get srr1 */
436 andi. %r2, %r3, 0xffff /* clean upper srr1 */
437 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot
438 * violation */
439 b isi1
440do_isi:
441 mfspr %r3, SPR_SRR1 /* get srr1 */
442 andi. %r2, %r3, 0xffff /* clean srr1 */
443 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte
444 * not found */
445isi1:
446 mtctr %r0 /* restore counter */
447 mtspr SPR_SRR1, %r2 /* set srr1 */
448 mfmsr %r0 /* get msr */
449 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
450 mtcrf 0x80, %r3 /* restore CR0 */
451 mtmsr %r0 /* flip back to the native gprs */
452 ba EXC_ISI /* go to instr. access interrupt */
453
454CNAME(imisssize) = .-CNAME(imisstrap)
455
456/*
457 * G2 specific: data load TLB miss.
458 */
459 .globl CNAME(dlmisstrap),CNAME(dlmisssize)
460CNAME(dlmisstrap):
461 mfspr %r2, SPR_HASH1 /* get first pointer */
462 addi %r1, 0, 8 /* load 8 for counter */
463 mfctr %r0 /* save counter */
464 mfspr %r3, SPR_DCMP /* get first compare value */
465 addi %r2, %r2, -8 /* pre dec the pointer */
466dm0:
467 mtctr %r1 /* load counter */
468dm1:
469 lwzu %r1, 8(%r2) /* get next pte */
470 cmp 0, 0, %r1, %r3 /* see if found pte */
471 bdnzf 2, dm1 /* dec count br if cmp ne and if
472 * count not zero */
473 bne data_sec_hash /* if not found set up second hash
474 * or exit */
475 lwz %r1, +4(%r2) /* load tlb entry lower-word */
476 mtctr %r0 /* restore counter */
477 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
478 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
479 mtcrf 0x80, %r3 /* restore CR0 */
480 mtspr SPR_RPA, %r1 /* set the pte */
481 ori %r1, %r1, 0x100 /* set reference bit */
482 srwi %r1, %r1, 8 /* get byte 7 of pte */
483 tlbld %r0 /* load the dtlb */
484 stb %r1, +6(%r2) /* update page table */
485 rfi /* return to executing program */
486
487data_sec_hash:
488 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
489 bne do_dsi /* if so, go to DSI interrupt */
490 mfspr %r2, SPR_HASH2 /* get the second pointer */
491 ori %r3, %r3, 0x0040 /* change the compare value */
492 addi %r1, 0, 8 /* load 8 for counter */
493 addi %r2, %r2, -8 /* pre dec for update on load */
494 b dm0 /* try second hash */
495
496CNAME(dlmisssize) = .-CNAME(dlmisstrap)
497
498/*
499 * G2 specific: data store TLB miss.
500 */
501 .globl CNAME(dsmisstrap),CNAME(dsmisssize)
502CNAME(dsmisstrap):
503 mfspr %r2, SPR_HASH1 /* get first pointer */
504 addi %r1, 0, 8 /* load 8 for counter */
505 mfctr %r0 /* save counter */
506 mfspr %r3, SPR_DCMP /* get first compare value */
507 addi %r2, %r2, -8 /* pre dec the pointer */
508ds0:
509 mtctr %r1 /* load counter */
510ds1:
511 lwzu %r1, 8(%r2) /* get next pte */
512 cmp 0, 0, %r1, %r3 /* see if found pte */
513 bdnzf 2, ds1 /* dec count br if cmp ne and if
514 * count not zero */
515 bne data_store_sec_hash /* if not found set up second hash
516 * or exit */
517 lwz %r1, +4(%r2) /* load tlb entry lower-word */
518 andi. %r3, %r1, 0x80 /* check the C-bit */
519 beq data_store_chk_prot /* if (C==0)
520 * go check protection modes */
521ds2:
522 mtctr %r0 /* restore counter */
523 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
524 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
525 mtcrf 0x80, %r3 /* restore CR0 */
526 mtspr SPR_RPA, %r1 /* set the pte */
527 tlbld %r0 /* load the dtlb */
528 rfi /* return to executing program */
529
530data_store_sec_hash:
531 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
532 bne do_dsi /* if so, go to DSI interrupt */
533 mfspr %r2, SPR_HASH2 /* get the second pointer */
534 ori %r3, %r3, 0x0040 /* change the compare value */
535 addi %r1, 0, 8 /* load 8 for counter */
536 addi %r2, %r2, -8 /* pre dec for update on load */
537 b ds0 /* try second hash */
538
539/* Check the protection before setting PTE(c-bit) */
540data_store_chk_prot:
541 rlwinm. %r3,%r1,30,0,1 /* test PP */
542 bge- chk0 /* if (PP == 00 or PP == 01)
543 * goto chk0: */
544 andi. %r3, %r1, 1 /* test PP[0] */
545 beq+ chk2 /* return if PP[0] == 0 */
546 b do_dsi_prot /* else DSIp */
547chk0:
548 mfspr %r3,SPR_SRR1 /* get old msr */
549 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */
550 beq chk2 /* if (KEY==0) goto chk2: */
551 b do_dsi_prot /* else do_dsi_prot */
552chk2:
553 ori %r1, %r1, 0x180 /* set reference and change bit */
554 sth %r1, 6(%r2) /* update page table */
555 b ds2 /* and back we go */
556
557/* Create a faked DSI interrupt as the address was not found */
558do_dsi:
559 mfspr %r3, SPR_SRR1 /* get srr1 */
560 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
561 * load/store, zero rest */
562 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte
563 * not found */
564 b dsi1
565
566do_dsi_prot:
567 mfspr %r3, SPR_SRR1 /* get srr1 */
568 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
569 *load/store, zero rest */
570 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot
571 * violation */
572
573dsi1:
574 mtctr %r0 /* restore counter */
575 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */
576 mtspr SPR_SRR1, %r2 /* set srr1 */
577 mtspr SPR_DSISR, %r1 /* load the dsisr */
578 mfspr %r1, SPR_DMISS /* get miss address */
579 rlwinm. %r2,%r2,0,31,31 /* test LE bit */
580 beq dsi2 /* if little endian then: */
581 xor %r1, %r1, 0x07 /* de-mung the data address */
582dsi2:
583 mtspr SPR_DAR, %r1 /* put in dar */
584 mfmsr %r0 /* get msr */
585 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
586 mtcrf 0x80, %r3 /* restore CR0 */
587 mtmsr %r0 /* flip back to the native gprs */
588 ba EXC_DSI /* branch to DSI interrupt */
589
590CNAME(dsmisssize) = .-CNAME(dsmisstrap)
591
592/*
593 * Similar to the above for DSI
594 * Has to handle BAT spills
595 * and standard pagetable spills
596 */
597 .globl CNAME(dsitrap),CNAME(dsisize)
598CNAME(dsitrap):
599 mtsprg1 %r1 /* save SP */
600 GET_CPUINFO(%r1)
601 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
602 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
603 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
604 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
605 mfsprg1 %r1 /* restore SP */
606 mfcr %r29 /* save CR */
607 mfxer %r30 /* save XER */
608 mtsprg2 %r30 /* in SPRG2 */
609 mfsrr1 %r31 /* test kernel mode */
610 mtcr %r31
611 bt 17,1f /* branch if PSL_PR is set */
612 mfdar %r31 /* get fault address */
613 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */
614
615 /* get batu */
616 addis %r31,%r31,CNAME(battable)@ha
617 lwz %r30,CNAME(battable)@l(31)
618 mtcr %r30
619 bf 30,1f /* branch if supervisor valid is
620 false */
621 /* get batl */
622 lwz %r31,CNAME(battable)+4@l(31)
623/* We randomly use the highest two bat registers here */
624 mftb %r28
625 andi. %r28,%r28,1
626 bne 2f
627 mtdbatu 2,%r30
628 mtdbatl 2,%r31
629 b 3f
6302:
631 mtdbatu 3,%r30
632 mtdbatl 3,%r31
6333:
634 mfsprg2 %r30 /* restore XER */
635 mtxer %r30
636 mtcr %r29 /* restore CR */
637 mtsprg1 %r1
638 GET_CPUINFO(%r1)
639 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */
640 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
641 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
642 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
643 mfsprg1 %r1
644 rfi /* return to trapped code */
6451:
646 mflr %r28 /* save LR (SP already saved) */
647 bla disitrap
648CNAME(dsisize) = .-CNAME(dsitrap)
649
650/*
651 * Preamble code for DSI/ISI traps
652 */
653disitrap:
654 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
655 mflr %r1
656 andi. %r1,%r1,0xff00
657 mtsprg3 %r1
658
659 GET_CPUINFO(%r1)
660 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
661 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
662 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
663 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
664 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
665 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
666 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
667 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
668 mfdar %r30
669 mfdsisr %r31
670 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
671 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
672
673#ifdef KDB
674 /* Try and detect a kernel stack overflow */
675 mfsrr1 %r31
676 mtcr %r31
677 bt 17,realtrap /* branch is user mode */
678 mfsprg1 %r31 /* get old SP */
679 sub. %r30,%r31,%r30 /* SP - DAR */
680 bge 1f
681 neg %r30,%r30 /* modulo value */
6821: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */
683 bge %cr0,realtrap /* no, too far away. */
684
685 /* Now convert this DSI into a DDB trap. */
686 GET_CPUINFO(%r1)
687 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
688 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
689 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
690 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
691 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
692 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
693 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
694 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
695 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
696 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
697 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
698 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
699 b dbtrap
700#endif
701
702 /* XXX need stack probe here */
703realtrap:
704/* Test whether we already had PR set */
705 mfsrr1 %r1
706 mtcr %r1
707 mfsprg1 %r1 /* restore SP (might have been
708 overwritten) */
709 bf 17,k_trap /* branch if PSL_PR is false */
710 GET_CPUINFO(%r1)
711 lwz %r1,PC_CURPCB(%r1)
712 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
713 ba s_trap
714
715/*
716 * generictrap does some standard setup for trap handling to minimize
717 * the code that need be installed in the actual vectors. It expects
718 * the following conditions.
719 *
720 * R1 - Trap vector = LR & (0xff00 | R1)
721 * SPRG1 - Original R1 contents
722 * SPRG2 - Original LR
723 */
724
725generictrap64:
726 mtsprg3 %r31
727 mfmsr %r31
728 clrldi %r31,%r31,1
729 mtmsrd %r31
730 mfsprg3 %r31
731 isync
732
733generictrap:
734 /* Save R1 for computing the exception vector */
735 mtsprg3 %r1
736
737 /* Save interesting registers */
738 GET_CPUINFO(%r1)
739 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
740 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
741 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
742 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
743 mfsprg1 %r1 /* restore SP, in case of branch */
744 mfsprg2 %r28 /* save LR */
745 mfcr %r29 /* save CR */
746
747 /* Compute the exception vector from the link register */
748 mfsprg3 %r31
749 ori %r31,%r31,0xff00
750 mflr %r30
751 and %r30,%r30,%r31
752 mtsprg3 %r30
753
754 /* Test whether we already had PR set */
755 mfsrr1 %r31
756 mtcr %r31
757
758s_trap:
759 bf 17,k_trap /* branch if PSL_PR is false */
760 GET_CPUINFO(%r1)
761u_trap:
762 lwz %r1,PC_CURPCB(%r1)
763 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
764
765/*
766 * Now the common trap catching code.
767 */
768k_trap:
769 FRAME_SETUP(PC_TEMPSAVE)
770 /* Restore USER_SR */
771 GET_CPUINFO(%r30)
772 lwz %r30,PC_CURPCB(%r30)
773 lwz %r30,PCB_AIM_USR_VSID(%r30)
774 mtsr USER_SR,%r30; sync; isync
775/* Call C interrupt dispatcher: */
776trapagain:
777 addi %r3,%r1,8
778 bl CNAME(powerpc_interrupt)
779 .globl CNAME(trapexit) /* backtrace code sentinel */
780CNAME(trapexit):
781
782/* Disable interrupts: */
783 mfmsr %r3
784 andi. %r3,%r3,~PSL_EE@l
785 mtmsr %r3
786/* Test AST pending: */
787 lwz %r5,FRAME_SRR1+8(%r1)
788 mtcr %r5
789 bf 17,1f /* branch if PSL_PR is false */
790
791 GET_CPUINFO(%r3) /* get per-CPU pointer */
792 lwz %r4, TD_FLAGS(%r2) /* get thread flags value
793 * (r2 is curthread) */
794 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
795 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
796 and. %r4,%r4,%r5
797 beq 1f
798 mfmsr %r3 /* re-enable interrupts */
799 ori %r3,%r3,PSL_EE@l
800 mtmsr %r3
801 isync
802 addi %r3,%r1,8
803 bl CNAME(ast)
804 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
805CNAME(asttrapexit):
806 b trapexit /* test ast ret value ? */
8071:
808 FRAME_LEAVE(PC_TEMPSAVE)
809
810 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */
811CNAME(rfi_patch1):
812 rfi
813
814 .globl CNAME(rfid_patch)
815CNAME(rfid_patch):
816 rfid
817
818#if defined(KDB)
819/*
820 * Deliberate entry to dbtrap
821 */
822 .globl CNAME(breakpoint)
823CNAME(breakpoint):
824 mtsprg1 %r1
825 mfmsr %r3
826 mtsrr1 %r3
827 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
828 mtmsr %r3 /* disable interrupts */
829 isync
830 GET_CPUINFO(%r3)
831 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
832 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
833 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
834 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
835 mflr %r28
836 li %r29,EXC_BPT
837 mtlr %r29
838 mfcr %r29
839 mtsrr0 %r28
840
841/*
842 * Now the kdb trap catching code.
843 */
844dbtrap:
845 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
846 mflr %r1
847 andi. %r1,%r1,0xff00
848 mtsprg3 %r1
849
850 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
851 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
852
853 FRAME_SETUP(PC_DBSAVE)
854/* Call C trap code: */
855 addi %r3,%r1,8
856 bl CNAME(db_trap_glue)
857 or. %r3,%r3,%r3
858 bne dbleave
859/* This wasn't for KDB, so switch to real trap: */
860 lwz %r3,FRAME_EXC+8(%r1) /* save exception */
861 GET_CPUINFO(%r4)
862 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
863 FRAME_LEAVE(PC_DBSAVE)
864 mtsprg1 %r1 /* prepare for entrance to realtrap */
865 GET_CPUINFO(%r1)
866 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
867 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
868 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
869 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
870 mflr %r28
871 mfcr %r29
872 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
873 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
874 mfsprg1 %r1
875 b realtrap
876dbleave:
877 FRAME_LEAVE(PC_DBSAVE)
878 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */
879CNAME(rfi_patch2):
880 rfi
881
882/*
883 * In case of KDB we want a separate trap catcher for it
884 */
885 .globl CNAME(dblow),CNAME(dbsize)
886CNAME(dblow):
887 mtsprg1 %r1 /* save SP */
888 mtsprg2 %r29 /* save r29 */
889 mfcr %r29 /* save CR in r29 */
890 mfsrr1 %r1
891 mtcr %r1
892 bf 17,1f /* branch if privileged */
893
894 /* Unprivileged case */
895 mtcr %r29 /* put the condition register back */
896 mfsprg2 %r29 /* ... and r29 */
897 mflr %r1 /* save LR */
898 mtsprg2 %r1 /* And then in SPRG2 */
899 li %r1, 0 /* How to get the vector from LR */
900
901 bla generictrap /* and we look like a generic trap */
9021:
903 /* Privileged, so drop to KDB */
904 GET_CPUINFO(%r1)
905 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
906 mfsprg2 %r28 /* r29 holds cr... */
907 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
908 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
909 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
910 mflr %r28 /* save LR */
911 bla dbtrap
912CNAME(dbsize) = .-CNAME(dblow)
913#endif /* KDB */
| 245 .globl dtrace_invop_calltrap_addr
246 .align 4
247 .type dtrace_invop_calltrap_addr, @object
248 .size dtrace_invop_calltrap_addr, 4
249dtrace_invop_calltrap_addr:
250 .word 0
251 .word 0
252
253 .text
254#endif
255
256/*
257 * The next two routines are 64-bit glue code. The first is used to test if
258 * we are on a 64-bit system. By copying it to the illegal instruction
259 * handler, we can test for 64-bit mode by trying to execute a 64-bit
260 * instruction and seeing what happens. The second gets copied in front
261 * of all the other handlers to restore 32-bit bridge mode when traps
262 * are taken.
263 */
264
265/* 64-bit test code. Sets SPRG2 to 0 if an illegal instruction is executed */
266
267 .globl CNAME(testppc64),CNAME(testppc64size)
268CNAME(testppc64):
269 mtsprg1 %r31
270 mfsrr0 %r31
271 addi %r31, %r31, 4
272 mtsrr0 %r31
273
274 li %r31, 0
275 mtsprg2 %r31
276 mfsprg1 %r31
277
278 rfi
279CNAME(testppc64size) = .-CNAME(testppc64)
280
281
282/* 64-bit bridge mode restore snippet. Gets copied in front of everything else
283 * on 64-bit systems. */
284
285 .globl CNAME(restorebridge),CNAME(restorebridgesize)
286CNAME(restorebridge):
287 mtsprg1 %r31
288 mfmsr %r31
289 clrldi %r31,%r31,1
290 mtmsrd %r31
291 mfsprg1 %r31
292 isync
293CNAME(restorebridgesize) = .-CNAME(restorebridge)
294
295#ifdef SMP
296/*
297 * Processor reset exception handler. These are typically
298 * the first instructions the processor executes after a
299 * software reset. We do this in two bits so that we are
300 * not still hanging around in the trap handling region
301 * once the MMU is turned on.
302 */
303 .globl CNAME(rstcode), CNAME(rstsize)
304CNAME(rstcode):
305 ba cpu_reset
306CNAME(rstsize) = . - CNAME(rstcode)
307
308cpu_reset:
309 bl 1f
310
311 .space 124
312
3131:
314 mflr %r1
315 addi %r1,%r1,(124-16)@l
316
317 lis %r3,1@l
318 bla CNAME(cpudep_ap_early_bootstrap)
319 lis %r3,1@l
320 bla CNAME(pmap_cpu_bootstrap)
321 bla CNAME(cpudep_ap_bootstrap)
322 mr %r1,%r3
323 bla CNAME(machdep_ap_bootstrap)
324
325 /* Should not be reached */
3269:
327 b 9b
328#endif
329
330/*
331 * This code gets copied to all the trap vectors
332 * (except ISI/DSI, ALI, and the interrupts)
333 */
334
335 .globl CNAME(trapcode),CNAME(trapsize)
336CNAME(trapcode):
337 mtsprg1 %r1 /* save SP */
338 mflr %r1 /* Save the old LR in r1 */
339 mtsprg2 %r1 /* And then in SPRG2 */
340 li %r1, 0x20 /* How to get the vector from LR */
341 bla generictrap /* LR & SPRG3 is exception # */
342CNAME(trapsize) = .-CNAME(trapcode)
343
344/*
345 * 64-bit version of trapcode. Identical, except it calls generictrap64.
346 */
347 .globl CNAME(trapcode64)
348CNAME(trapcode64):
349 mtsprg1 %r1 /* save SP */
350 mflr %r1 /* Save the old LR in r1 */
351 mtsprg2 %r1 /* And then in SPRG2 */
352 li %r1, 0x20 /* How to get the vector from LR */
353 bla generictrap64 /* LR & SPRG3 is exception # */
354
355/*
356 * For ALI: has to save DSISR and DAR
357 */
358 .globl CNAME(alitrap),CNAME(alisize)
359CNAME(alitrap):
360 mtsprg1 %r1 /* save SP */
361 GET_CPUINFO(%r1)
362 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
363 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
364 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
365 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
366 mfdar %r30
367 mfdsisr %r31
368 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
369 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
370 mfsprg1 %r1 /* restore SP, in case of branch */
371 mflr %r28 /* save LR */
372 mfcr %r29 /* save CR */
373
374 /* Put our exception vector in SPRG3 */
375 li %r31, EXC_ALI
376 mtsprg3 %r31
377
378 /* Test whether we already had PR set */
379 mfsrr1 %r31
380 mtcr %r31
381 bla s_trap
382CNAME(alisize) = .-CNAME(alitrap)
383
384/*
385 * G2 specific: instuction TLB miss.
386 */
387 .globl CNAME(imisstrap),CNAME(imisssize)
388CNAME(imisstrap):
389 mfspr %r2, SPR_HASH1 /* get first pointer */
390 addi %r1, 0, 8 /* load 8 for counter */
391 mfctr %r0 /* save counter */
392 mfspr %r3, SPR_ICMP /* get first compare value */
393 addi %r2, %r2, -8 /* pre dec the pointer */
394im0:
395 mtctr %r1 /* load counter */
396im1:
397 lwzu %r1, 8(%r2) /* get next pte */
398 cmp 0, %r1, %r3 /* see if found pte */
399 bdnzf 2, im1 /* dec count br if cmp ne and if
400 * count not zero */
401 bne instr_sec_hash /* if not found set up second hash
402 * or exit */
403 lwz %r1, +4(%r2) /* load tlb entry lower-word */
404 andi. %r3, %r1, 8 /* check G bit */
405 bne do_isi_prot /* if guarded, take an ISI */
406 mtctr %r0 /* restore counter */
407 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */
408 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
409 mtcrf 0x80, %r3 /* restore CR0 */
410 mtspr SPR_RPA, %r1 /* set the pte */
411 ori %r1, %r1, 0x100 /* set reference bit */
412 srwi %r1, %r1, 8 /* get byte 7 of pte */
413 tlbli %r0 /* load the itlb */
414 stb %r1, +6(%r2) /* update page table */
415 rfi /* return to executing program */
416
417instr_sec_hash:
418 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
419 bne do_isi /* if so, go to ISI interrupt */
420 mfspr %r2, SPR_HASH2 /* get the second pointer */
421 ori %r3, %r3, 0x0040 /* change the compare value */
422 addi %r1, %r0, 8 /* load 8 for counter */
423 addi %r2, %r2, -8 /* pre dec for update on load */
424 b im0 /* try second hash */
425
426/* Create a faked ISI interrupt as the address was not found */
427do_isi_prot:
428 mfspr %r3, SPR_SRR1 /* get srr1 */
429 andi. %r2, %r3, 0xffff /* clean upper srr1 */
430 addis %r2, %r2, 0x0800 /* or in srr<4> = 1 to flag prot
431 * violation */
432 b isi1
433do_isi:
434 mfspr %r3, SPR_SRR1 /* get srr1 */
435 andi. %r2, %r3, 0xffff /* clean srr1 */
436 addis %r2, %r2, 0x4000 /* or in srr1<1> = 1 to flag pte
437 * not found */
438isi1:
439 mtctr %r0 /* restore counter */
440 mtspr SPR_SRR1, %r2 /* set srr1 */
441 mfmsr %r0 /* get msr */
442 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
443 mtcrf 0x80, %r3 /* restore CR0 */
444 mtmsr %r0 /* flip back to the native gprs */
445 ba EXC_ISI /* go to instr. access interrupt */
446
447CNAME(imisssize) = .-CNAME(imisstrap)
448
449/*
450 * G2 specific: data load TLB miss.
451 */
452 .globl CNAME(dlmisstrap),CNAME(dlmisssize)
453CNAME(dlmisstrap):
454 mfspr %r2, SPR_HASH1 /* get first pointer */
455 addi %r1, 0, 8 /* load 8 for counter */
456 mfctr %r0 /* save counter */
457 mfspr %r3, SPR_DCMP /* get first compare value */
458 addi %r2, %r2, -8 /* pre dec the pointer */
459dm0:
460 mtctr %r1 /* load counter */
461dm1:
462 lwzu %r1, 8(%r2) /* get next pte */
463 cmp 0, 0, %r1, %r3 /* see if found pte */
464 bdnzf 2, dm1 /* dec count br if cmp ne and if
465 * count not zero */
466 bne data_sec_hash /* if not found set up second hash
467 * or exit */
468 lwz %r1, +4(%r2) /* load tlb entry lower-word */
469 mtctr %r0 /* restore counter */
470 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
471 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
472 mtcrf 0x80, %r3 /* restore CR0 */
473 mtspr SPR_RPA, %r1 /* set the pte */
474 ori %r1, %r1, 0x100 /* set reference bit */
475 srwi %r1, %r1, 8 /* get byte 7 of pte */
476 tlbld %r0 /* load the dtlb */
477 stb %r1, +6(%r2) /* update page table */
478 rfi /* return to executing program */
479
480data_sec_hash:
481 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
482 bne do_dsi /* if so, go to DSI interrupt */
483 mfspr %r2, SPR_HASH2 /* get the second pointer */
484 ori %r3, %r3, 0x0040 /* change the compare value */
485 addi %r1, 0, 8 /* load 8 for counter */
486 addi %r2, %r2, -8 /* pre dec for update on load */
487 b dm0 /* try second hash */
488
489CNAME(dlmisssize) = .-CNAME(dlmisstrap)
490
491/*
492 * G2 specific: data store TLB miss.
493 */
494 .globl CNAME(dsmisstrap),CNAME(dsmisssize)
495CNAME(dsmisstrap):
496 mfspr %r2, SPR_HASH1 /* get first pointer */
497 addi %r1, 0, 8 /* load 8 for counter */
498 mfctr %r0 /* save counter */
499 mfspr %r3, SPR_DCMP /* get first compare value */
500 addi %r2, %r2, -8 /* pre dec the pointer */
501ds0:
502 mtctr %r1 /* load counter */
503ds1:
504 lwzu %r1, 8(%r2) /* get next pte */
505 cmp 0, 0, %r1, %r3 /* see if found pte */
506 bdnzf 2, ds1 /* dec count br if cmp ne and if
507 * count not zero */
508 bne data_store_sec_hash /* if not found set up second hash
509 * or exit */
510 lwz %r1, +4(%r2) /* load tlb entry lower-word */
511 andi. %r3, %r1, 0x80 /* check the C-bit */
512 beq data_store_chk_prot /* if (C==0)
513 * go check protection modes */
514ds2:
515 mtctr %r0 /* restore counter */
516 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
517 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
518 mtcrf 0x80, %r3 /* restore CR0 */
519 mtspr SPR_RPA, %r1 /* set the pte */
520 tlbld %r0 /* load the dtlb */
521 rfi /* return to executing program */
522
523data_store_sec_hash:
524 andi. %r1, %r3, 0x0040 /* see if we have done second hash */
525 bne do_dsi /* if so, go to DSI interrupt */
526 mfspr %r2, SPR_HASH2 /* get the second pointer */
527 ori %r3, %r3, 0x0040 /* change the compare value */
528 addi %r1, 0, 8 /* load 8 for counter */
529 addi %r2, %r2, -8 /* pre dec for update on load */
530 b ds0 /* try second hash */
531
532/* Check the protection before setting PTE(c-bit) */
533data_store_chk_prot:
534 rlwinm. %r3,%r1,30,0,1 /* test PP */
535 bge- chk0 /* if (PP == 00 or PP == 01)
536 * goto chk0: */
537 andi. %r3, %r1, 1 /* test PP[0] */
538 beq+ chk2 /* return if PP[0] == 0 */
539 b do_dsi_prot /* else DSIp */
540chk0:
541 mfspr %r3,SPR_SRR1 /* get old msr */
542 andis. %r3,%r3,0x0008 /* test the KEY bit (SRR1-bit 12) */
543 beq chk2 /* if (KEY==0) goto chk2: */
544 b do_dsi_prot /* else do_dsi_prot */
545chk2:
546 ori %r1, %r1, 0x180 /* set reference and change bit */
547 sth %r1, 6(%r2) /* update page table */
548 b ds2 /* and back we go */
549
550/* Create a faked DSI interrupt as the address was not found */
551do_dsi:
552 mfspr %r3, SPR_SRR1 /* get srr1 */
553 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
554 * load/store, zero rest */
555 addis %r1, %r1, 0x4000 /* or in dsisr<1> = 1 to flag pte
556 * not found */
557 b dsi1
558
559do_dsi_prot:
560 mfspr %r3, SPR_SRR1 /* get srr1 */
561 rlwinm %r1,%r3,9,6,6 /* get srr1<flag> to bit 6 for
562 *load/store, zero rest */
563 addis %r1, %r1, 0x0800 /* or in dsisr<4> = 1 to flag prot
564 * violation */
565
566dsi1:
567 mtctr %r0 /* restore counter */
568 andi. %r2, %r3, 0xffff /* clear upper bits of srr1 */
569 mtspr SPR_SRR1, %r2 /* set srr1 */
570 mtspr SPR_DSISR, %r1 /* load the dsisr */
571 mfspr %r1, SPR_DMISS /* get miss address */
572 rlwinm. %r2,%r2,0,31,31 /* test LE bit */
573 beq dsi2 /* if little endian then: */
574 xor %r1, %r1, 0x07 /* de-mung the data address */
575dsi2:
576 mtspr SPR_DAR, %r1 /* put in dar */
577 mfmsr %r0 /* get msr */
578 xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
579 mtcrf 0x80, %r3 /* restore CR0 */
580 mtmsr %r0 /* flip back to the native gprs */
581 ba EXC_DSI /* branch to DSI interrupt */
582
583CNAME(dsmisssize) = .-CNAME(dsmisstrap)
584
585/*
586 * Similar to the above for DSI
587 * Has to handle BAT spills
588 * and standard pagetable spills
589 */
590 .globl CNAME(dsitrap),CNAME(dsisize)
591CNAME(dsitrap):
592 mtsprg1 %r1 /* save SP */
593 GET_CPUINFO(%r1)
594 stw %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
595 stw %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
596 stw %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
597 stw %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
598 mfsprg1 %r1 /* restore SP */
599 mfcr %r29 /* save CR */
600 mfxer %r30 /* save XER */
601 mtsprg2 %r30 /* in SPRG2 */
602 mfsrr1 %r31 /* test kernel mode */
603 mtcr %r31
604 bt 17,1f /* branch if PSL_PR is set */
605 mfdar %r31 /* get fault address */
606 rlwinm %r31,%r31,7,25,28 /* get segment * 8 */
607
608 /* get batu */
609 addis %r31,%r31,CNAME(battable)@ha
610 lwz %r30,CNAME(battable)@l(31)
611 mtcr %r30
612 bf 30,1f /* branch if supervisor valid is
613 false */
614 /* get batl */
615 lwz %r31,CNAME(battable)+4@l(31)
616/* We randomly use the highest two bat registers here */
617 mftb %r28
618 andi. %r28,%r28,1
619 bne 2f
620 mtdbatu 2,%r30
621 mtdbatl 2,%r31
622 b 3f
6232:
624 mtdbatu 3,%r30
625 mtdbatl 3,%r31
6263:
627 mfsprg2 %r30 /* restore XER */
628 mtxer %r30
629 mtcr %r29 /* restore CR */
630 mtsprg1 %r1
631 GET_CPUINFO(%r1)
632 lwz %r28,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* restore r28-r31 */
633 lwz %r29,(PC_DISISAVE+CPUSAVE_R29)(%r1)
634 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
635 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
636 mfsprg1 %r1
637 rfi /* return to trapped code */
6381:
639 mflr %r28 /* save LR (SP already saved) */
640 bla disitrap
641CNAME(dsisize) = .-CNAME(dsitrap)
642
643/*
644 * Preamble code for DSI/ISI traps
645 */
646disitrap:
647 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
648 mflr %r1
649 andi. %r1,%r1,0xff00
650 mtsprg3 %r1
651
652 GET_CPUINFO(%r1)
653 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1)
654 stw %r30,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
655 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1)
656 stw %r31,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
657 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1)
658 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
659 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1)
660 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
661 mfdar %r30
662 mfdsisr %r31
663 stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
664 stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
665
666#ifdef KDB
667 /* Try and detect a kernel stack overflow */
668 mfsrr1 %r31
669 mtcr %r31
670 bt 17,realtrap /* branch is user mode */
671 mfsprg1 %r31 /* get old SP */
672 sub. %r30,%r31,%r30 /* SP - DAR */
673 bge 1f
674 neg %r30,%r30 /* modulo value */
6751: cmplwi %cr0,%r30,4096 /* is DAR within a page of SP? */
676 bge %cr0,realtrap /* no, too far away. */
677
678 /* Now convert this DSI into a DDB trap. */
679 GET_CPUINFO(%r1)
680 lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
681 stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
682 lwz %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
683 stw %r31,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
684 lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
685 stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
686 lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
687 stw %r31,(PC_DBSAVE +CPUSAVE_R29)(%r1) /* save r29 */
688 lwz %r30,(PC_DISISAVE+CPUSAVE_R30)(%r1) /* get r30 */
689 stw %r30,(PC_DBSAVE +CPUSAVE_R30)(%r1) /* save r30 */
690 lwz %r31,(PC_DISISAVE+CPUSAVE_R31)(%r1) /* get r31 */
691 stw %r31,(PC_DBSAVE +CPUSAVE_R31)(%r1) /* save r31 */
692 b dbtrap
693#endif
694
695 /* XXX need stack probe here */
696realtrap:
697/* Test whether we already had PR set */
698 mfsrr1 %r1
699 mtcr %r1
700 mfsprg1 %r1 /* restore SP (might have been
701 overwritten) */
702 bf 17,k_trap /* branch if PSL_PR is false */
703 GET_CPUINFO(%r1)
704 lwz %r1,PC_CURPCB(%r1)
705 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
706 ba s_trap
707
708/*
709 * generictrap does some standard setup for trap handling to minimize
710 * the code that need be installed in the actual vectors. It expects
711 * the following conditions.
712 *
713 * R1 - Trap vector = LR & (0xff00 | R1)
714 * SPRG1 - Original R1 contents
715 * SPRG2 - Original LR
716 */
717
718generictrap64:
719 mtsprg3 %r31
720 mfmsr %r31
721 clrldi %r31,%r31,1
722 mtmsrd %r31
723 mfsprg3 %r31
724 isync
725
726generictrap:
727 /* Save R1 for computing the exception vector */
728 mtsprg3 %r1
729
730 /* Save interesting registers */
731 GET_CPUINFO(%r1)
732 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1) /* free r28-r31 */
733 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
734 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
735 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
736 mfsprg1 %r1 /* restore SP, in case of branch */
737 mfsprg2 %r28 /* save LR */
738 mfcr %r29 /* save CR */
739
740 /* Compute the exception vector from the link register */
741 mfsprg3 %r31
742 ori %r31,%r31,0xff00
743 mflr %r30
744 and %r30,%r30,%r31
745 mtsprg3 %r30
746
747 /* Test whether we already had PR set */
748 mfsrr1 %r31
749 mtcr %r31
750
751s_trap:
752 bf 17,k_trap /* branch if PSL_PR is false */
753 GET_CPUINFO(%r1)
754u_trap:
755 lwz %r1,PC_CURPCB(%r1)
756 RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
757
758/*
759 * Now the common trap catching code.
760 */
761k_trap:
762 FRAME_SETUP(PC_TEMPSAVE)
763 /* Restore USER_SR */
764 GET_CPUINFO(%r30)
765 lwz %r30,PC_CURPCB(%r30)
766 lwz %r30,PCB_AIM_USR_VSID(%r30)
767 mtsr USER_SR,%r30; sync; isync
768/* Call C interrupt dispatcher: */
769trapagain:
770 addi %r3,%r1,8
771 bl CNAME(powerpc_interrupt)
772 .globl CNAME(trapexit) /* backtrace code sentinel */
773CNAME(trapexit):
774
775/* Disable interrupts: */
776 mfmsr %r3
777 andi. %r3,%r3,~PSL_EE@l
778 mtmsr %r3
779/* Test AST pending: */
780 lwz %r5,FRAME_SRR1+8(%r1)
781 mtcr %r5
782 bf 17,1f /* branch if PSL_PR is false */
783
784 GET_CPUINFO(%r3) /* get per-CPU pointer */
785 lwz %r4, TD_FLAGS(%r2) /* get thread flags value
786 * (r2 is curthread) */
787 lis %r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@h
788 ori %r5,%r5, (TDF_ASTPENDING|TDF_NEEDRESCHED)@l
789 and. %r4,%r4,%r5
790 beq 1f
791 mfmsr %r3 /* re-enable interrupts */
792 ori %r3,%r3,PSL_EE@l
793 mtmsr %r3
794 isync
795 addi %r3,%r1,8
796 bl CNAME(ast)
797 .globl CNAME(asttrapexit) /* backtrace code sentinel #2 */
798CNAME(asttrapexit):
799 b trapexit /* test ast ret value ? */
8001:
801 FRAME_LEAVE(PC_TEMPSAVE)
802
803 .globl CNAME(rfi_patch1) /* replace rfi with rfid on ppc64 */
804CNAME(rfi_patch1):
805 rfi
806
807 .globl CNAME(rfid_patch)
808CNAME(rfid_patch):
809 rfid
810
811#if defined(KDB)
812/*
813 * Deliberate entry to dbtrap
814 */
815 .globl CNAME(breakpoint)
816CNAME(breakpoint):
817 mtsprg1 %r1
818 mfmsr %r3
819 mtsrr1 %r3
820 andi. %r3,%r3,~(PSL_EE|PSL_ME)@l
821 mtmsr %r3 /* disable interrupts */
822 isync
823 GET_CPUINFO(%r3)
824 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r3)
825 stw %r29,(PC_DBSAVE+CPUSAVE_R29)(%r3)
826 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r3)
827 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r3)
828 mflr %r28
829 li %r29,EXC_BPT
830 mtlr %r29
831 mfcr %r29
832 mtsrr0 %r28
833
834/*
835 * Now the kdb trap catching code.
836 */
837dbtrap:
838 /* Write the trap vector to SPRG3 by computing LR & 0xff00 */
839 mflr %r1
840 andi. %r1,%r1,0xff00
841 mtsprg3 %r1
842
843 lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
844 addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
845
846 FRAME_SETUP(PC_DBSAVE)
847/* Call C trap code: */
848 addi %r3,%r1,8
849 bl CNAME(db_trap_glue)
850 or. %r3,%r3,%r3
851 bne dbleave
852/* This wasn't for KDB, so switch to real trap: */
853 lwz %r3,FRAME_EXC+8(%r1) /* save exception */
854 GET_CPUINFO(%r4)
855 stw %r3,(PC_DBSAVE+CPUSAVE_R31)(%r4)
856 FRAME_LEAVE(PC_DBSAVE)
857 mtsprg1 %r1 /* prepare for entrance to realtrap */
858 GET_CPUINFO(%r1)
859 stw %r28,(PC_TEMPSAVE+CPUSAVE_R28)(%r1)
860 stw %r29,(PC_TEMPSAVE+CPUSAVE_R29)(%r1)
861 stw %r30,(PC_TEMPSAVE+CPUSAVE_R30)(%r1)
862 stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
863 mflr %r28
864 mfcr %r29
865 lwz %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1)
866 mtsprg3 %r31 /* SPRG3 was clobbered by FRAME_LEAVE */
867 mfsprg1 %r1
868 b realtrap
869dbleave:
870 FRAME_LEAVE(PC_DBSAVE)
871 .globl CNAME(rfi_patch2) /* replace rfi with rfid on ppc64 */
872CNAME(rfi_patch2):
873 rfi
874
875/*
876 * In case of KDB we want a separate trap catcher for it
877 */
878 .globl CNAME(dblow),CNAME(dbsize)
879CNAME(dblow):
880 mtsprg1 %r1 /* save SP */
881 mtsprg2 %r29 /* save r29 */
882 mfcr %r29 /* save CR in r29 */
883 mfsrr1 %r1
884 mtcr %r1
885 bf 17,1f /* branch if privileged */
886
887 /* Unprivileged case */
888 mtcr %r29 /* put the condition register back */
889 mfsprg2 %r29 /* ... and r29 */
890 mflr %r1 /* save LR */
891 mtsprg2 %r1 /* And then in SPRG2 */
892 li %r1, 0 /* How to get the vector from LR */
893
894 bla generictrap /* and we look like a generic trap */
8951:
896 /* Privileged, so drop to KDB */
897 GET_CPUINFO(%r1)
898 stw %r28,(PC_DBSAVE+CPUSAVE_R28)(%r1) /* free r28 */
899 mfsprg2 %r28 /* r29 holds cr... */
900 stw %r28,(PC_DBSAVE+CPUSAVE_R29)(%r1) /* free r29 */
901 stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
902 stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
903 mflr %r28 /* save LR */
904 bla dbtrap
905CNAME(dbsize) = .-CNAME(dblow)
906#endif /* KDB */
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