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if_nlge.c (212957) if_nlge.c (213377)
1/*-
2 * Copyright (c) 2003-2009 RMI Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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40 * The XLS device supports upto 8 10/100/1000 Ethernet MACs or max 2 10G
41 * Ethernet MACs. The 1G MACs are of SGMII and 10G MACs are of XAUI
42 * interface. These ports are part of two network accelerators.
43 * The nlge driver configures and initializes non-SPI4 Ethernet ports in the
44 * XLR/XLS devices and enables data transfer on them.
45 */
46
47#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003-2009 RMI Corporation
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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40 * The XLS device supports upto 8 10/100/1000 Ethernet MACs or max 2 10G
41 * Ethernet MACs. The 1G MACs are of SGMII and 10G MACs are of XAUI
42 * interface. These ports are part of two network accelerators.
43 * The nlge driver configures and initializes non-SPI4 Ethernet ports in the
44 * XLR/XLS devices and enables data transfer on them.
45 */
46
47#include <sys/cdefs.h>
48__FBSDID("$FreeBSD: head/sys/mips/rmi/dev/nlge/if_nlge.c 212957 2010-09-21 07:58:47Z jchandra $");
48__FBSDID("$FreeBSD: head/sys/mips/rmi/dev/nlge/if_nlge.c 213377 2010-10-03 04:33:58Z jchandra $");
49
50#ifdef HAVE_KERNEL_OPTION_HEADERS
51#include "opt_device_polling.h"
52#endif
53
54#include <sys/endian.h>
55#include <sys/systm.h>
56#include <sys/sockio.h>

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897 * Do:
898 * - Initialize common GMAC registers (index range 0x100-0x3ff).
899 */
900static void
901nlna_hw_init(struct nlna_softc *sc)
902{
903
904 /*
49
50#ifdef HAVE_KERNEL_OPTION_HEADERS
51#include "opt_device_polling.h"
52#endif
53
54#include <sys/endian.h>
55#include <sys/systm.h>
56#include <sys/sockio.h>

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897 * Do:
898 * - Initialize common GMAC registers (index range 0x100-0x3ff).
899 */
900static void
901nlna_hw_init(struct nlna_softc *sc)
902{
903
904 /*
905 * It is seen that this is a critical function in bringing up FreeBSD.
906 * When it is not invoked, FreeBSD panics and fails during the
907 * multi-processor init (SI_SUB_SMP of * mi_startup). The key function
908 * in this sequence seems to be platform_prep_smp_launch. */
909 if (register_msgring_handler(sc->station_id, nlge_msgring_handler, sc)) {
905 * Register message ring handler for the NA block, messages from
906 * the GMAC will have sourec station id to the first bucket of the
907 * NA FMN station, so register just that station id.
908 */
909 if (register_msgring_handler(sc->station_id, sc->station_id + 1,
910 nlge_msgring_handler, sc)) {
910 panic("Couldn't register msgring handler\n");
911 }
912 nlna_config_fifo_spill_area(sc);
913 nlna_config_pde(sc);
914 nlna_config_common(sc);
915 nlna_config_parser(sc);
916 nlna_config_classifier(sc);
917}

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1138 /*
1139 * rge may be called before SMP start in a BOOTP/NFSROOT
1140 * setup. we will distribute packets to other cpus only when
1141 * the SMP is started.
1142 */
1143 if (smp_started)
1144 cpumask = xlr_hw_thread_mask;
1145#endif
911 panic("Couldn't register msgring handler\n");
912 }
913 nlna_config_fifo_spill_area(sc);
914 nlna_config_pde(sc);
915 nlna_config_common(sc);
916 nlna_config_parser(sc);
917 nlna_config_classifier(sc);
918}

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1139 /*
1140 * rge may be called before SMP start in a BOOTP/NFSROOT
1141 * setup. we will distribute packets to other cpus only when
1142 * the SMP is started.
1143 */
1144 if (smp_started)
1145 cpumask = xlr_hw_thread_mask;
1146#endif
1146
1147 bucket_map = 0;
1148 for (i = 0; i < 32; i++) {
1149 if (cpumask & (1 << i)) {
1150 cpu = i;
1147 bucket_map = 0;
1148 for (i = 0; i < 32; i++) {
1149 if (cpumask & (1 << i)) {
1150 cpu = i;
1151 bucket = ((cpu >> 2) << 3);
1152 bucket_map |= (1ULL << bucket);
1151 /* use bucket 0 and 1 on every core for NA msgs */
1152 bucket = cpu/4 * 8;
1153 bucket_map |= (3ULL << bucket);
1153 }
1154 }
1155 NLGE_WRITE(sc->base, R_PDE_CLASS_0, (bucket_map & 0xffffffff));
1156 NLGE_WRITE(sc->base, R_PDE_CLASS_0 + 1, ((bucket_map >> 32) & 0xffffffff));
1157
1158 NLGE_WRITE(sc->base, R_PDE_CLASS_1, (bucket_map & 0xffffffff));
1159 NLGE_WRITE(sc->base, R_PDE_CLASS_1 + 1, ((bucket_map >> 32) & 0xffffffff));
1160
1161 NLGE_WRITE(sc->base, R_PDE_CLASS_2, (bucket_map & 0xffffffff));
1162 NLGE_WRITE(sc->base, R_PDE_CLASS_2 + 1, ((bucket_map >> 32) & 0xffffffff));
1163
1164 NLGE_WRITE(sc->base, R_PDE_CLASS_3, (bucket_map & 0xffffffff));
1165 NLGE_WRITE(sc->base, R_PDE_CLASS_3 + 1, ((bucket_map >> 32) & 0xffffffff));
1166}
1167
1154 }
1155 }
1156 NLGE_WRITE(sc->base, R_PDE_CLASS_0, (bucket_map & 0xffffffff));
1157 NLGE_WRITE(sc->base, R_PDE_CLASS_0 + 1, ((bucket_map >> 32) & 0xffffffff));
1158
1159 NLGE_WRITE(sc->base, R_PDE_CLASS_1, (bucket_map & 0xffffffff));
1160 NLGE_WRITE(sc->base, R_PDE_CLASS_1 + 1, ((bucket_map >> 32) & 0xffffffff));
1161
1162 NLGE_WRITE(sc->base, R_PDE_CLASS_2, (bucket_map & 0xffffffff));
1163 NLGE_WRITE(sc->base, R_PDE_CLASS_2 + 1, ((bucket_map >> 32) & 0xffffffff));
1164
1165 NLGE_WRITE(sc->base, R_PDE_CLASS_3, (bucket_map & 0xffffffff));
1166 NLGE_WRITE(sc->base, R_PDE_CLASS_3 + 1, ((bucket_map >> 32) & 0xffffffff));
1167}
1168
1169/*
1170 * Update the network accelerator packet distribution engine for SMP.
1171 * On bootup, we have just the boot hw thread handling all packets, on SMP
1172 * start, we can start distributing packets across all the cores which are up.
1173 */
1168static void
1169nlna_smp_update_pde(void *dummy __unused)
1170{
1171 device_t iodi_dev;
1172 struct nlna_softc *na_sc[XLR_MAX_NLNA];
1173 int i;
1174
1175 printf("Updating packet distribution for SMP\n");

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1230 * Complete a bunch of h/w register initializations that are common for all the
1231 * ports controlled by a NA.
1232 */
1233static void
1234nlna_config_common(struct nlna_softc *sc)
1235{
1236 struct xlr_gmac_block_t *block_info;
1237 struct stn_cc *gmac_cc_config;
1174static void
1175nlna_smp_update_pde(void *dummy __unused)
1176{
1177 device_t iodi_dev;
1178 struct nlna_softc *na_sc[XLR_MAX_NLNA];
1179 int i;
1180
1181 printf("Updating packet distribution for SMP\n");

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1236 * Complete a bunch of h/w register initializations that are common for all the
1237 * ports controlled by a NA.
1238 */
1239static void
1240nlna_config_common(struct nlna_softc *sc)
1241{
1242 struct xlr_gmac_block_t *block_info;
1243 struct stn_cc *gmac_cc_config;
1238 int i, id;
1244 int i;
1239
1240 block_info = device_get_ivars(sc->nlna_dev);
1245
1246 block_info = device_get_ivars(sc->nlna_dev);
1241
1242 id = device_get_unit(sc->nlna_dev);
1243 gmac_cc_config = block_info->credit_config;
1244 for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
1245 NLGE_WRITE(sc->base, R_CC_CPU0_0 + i,
1246 gmac_cc_config->counters[i >> 3][i & 0x07]);
1247 }
1248
1249 NLGE_WRITE(sc->base, R_MSG_TX_THRESHOLD, 3);
1250

--- 1177 unchanged lines hidden --- 		1247 gmac_cc_config = block_info->credit_config;
1248 for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) {
1249 NLGE_WRITE(sc->base, R_CC_CPU0_0 + i,
1250 gmac_cc_config->counters[i >> 3][i & 0x07]);
1251 }
1252
1253 NLGE_WRITE(sc->base, R_MSG_TX_THRESHOLD, 3);
1254

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