| maltareg.h (180332) | maltareg.h (202035) |
|---|---|
| 1/* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */ 2 3/* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * --- 20 unchanged lines hidden (view full) --- 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * | 1/* $NetBSD: maltareg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */ 2 3/* 4 * Copyright 2002 Wasabi Systems, Inc. 5 * All rights reserved. 6 * 7 * Written by Simon Burge for Wasabi Systems, Inc. 8 * --- 20 unchanged lines hidden (view full) --- 29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 35 * POSSIBILITY OF SUCH DAMAGE. 36 * |
| 37 * $FreeBSD: head/sys/mips/malta/maltareg.h 178173 2008-04-13 07:44:55Z imp $ | 37 * $FreeBSD: head/sys/mips/malta/maltareg.h 202035 2010-01-10 20:06:14Z imp $ |
| 38 */ 39 40/* 41 Memory Map 42 43 0000.0000 * 128MB Typically SDRAM (on Core Board) 44 0800.0000 * 256MB Typically PCI 45 1800.0000 * 62MB Typically PCI --- 43 unchanged lines hidden (view full) --- 89 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge) 90 PCI D,USB 91 12 Mouse SuperIO 92 13 Reserved by South Bridge 93 14 Primary IDE Primary IDE slot 94 15 Secondary IDE Secondary IDE slot/Compact flash connector 95 */ 96 | 38 */ 39 40/* 41 Memory Map 42 43 0000.0000 * 128MB Typically SDRAM (on Core Board) 44 0800.0000 * 256MB Typically PCI 45 1800.0000 * 62MB Typically PCI --- 43 unchanged lines hidden (view full) --- 89 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge) 90 PCI D,USB 91 12 Mouse SuperIO 92 13 Reserved by South Bridge 93 14 Primary IDE Primary IDE slot 94 15 Secondary IDE Secondary IDE slot/Compact flash connector 95 */ 96 |
| 97#define MALTA_SYSTEMRAM_BASE 0x00000000 /* System RAM: */ | 97#define MALTA_SYSTEMRAM_BASE 0x00000000ul /* System RAM: */ |
| 98#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ 99 | 98#define MALTA_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */ 99 |
| 100#define MALTA_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */ | 100#define MALTA_PCIMEM1_BASE 0x08000000ul /* PCI 1 memory: */ |
| 101#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ 102 | 101#define MALTA_PCIMEM1_SIZE 0x08000000 /* 128 MByte */ 102 |
| 103#define MALTA_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */ | 103#define MALTA_PCIMEM2_BASE 0x10000000ul /* PCI 2 memory: */ |
| 104#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ 105 | 104#define MALTA_PCIMEM2_SIZE 0x08000000 /* 128 MByte */ 105 |
| 106#define MALTA_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */ | 106#define MALTA_PCIMEM3_BASE 0x18000000ul /* PCI 3 memory */ |
| 107#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ 108 | 107#define MALTA_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */ 108 |
| 109#define MALTA_CORECTRL_BASE 0x1be00000 /* Core control: */ | 109#define MALTA_CORECTRL_BASE 0x1be00000ul /* Core control: */ |
| 110#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ 111 | 110#define MALTA_CORECTRL_SIZE 0x00200000 /* 2 MByte */ 111 |
| 112#define MALTA_RESERVED_BASE1 0x1c000000 /* Reserved: */ | 112#define MALTA_RESERVED_BASE1 0x1c000000ul /* Reserved: */ |
| 113#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ 114 | 113#define MALTA_RESERVED_SIZE1 0x02000000 /* 32 MByte */ 114 |
| 115#define MALTA_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */ | 115#define MALTA_MONITORFLASH_BASE 0x1e000000ul /* Monitor Flash: */ |
| 116#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ 117#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 118 | 116#define MALTA_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */ 117#define MALTA_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 118 |
| 119#define MALTA_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */ | 119#define MALTA_FILEFLASH_BASE 0x1e3e0000ul /* File Flash (for monitor): */ |
| 120#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ 121 122#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 123 | 120#define MALTA_FILEFLASH_SIZE 0x00020000 /* 128 KByte */ 121 122#define MALTA_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */ 123 |
| 124#define MALTA_RESERVED_BASE2 0x1e400000 /* Reserved: */ | 124#define MALTA_RESERVED_BASE2 0x1e400000ul /* Reserved: */ |
| 125#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ 126 | 125#define MALTA_RESERVED_SIZE2 0x00c00000 /* 12 MByte */ 126 |
| 127#define MALTA_FPGA_BASE 0x1f000000 /* FPGA: */ | 127#define MALTA_FPGA_BASE 0x1f000000ul /* FPGA: */ |
| 128#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ 129 130#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) 131#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ 132#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ 133 134#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) 135#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ --- 50 unchanged lines hidden (view full) --- 186#define MALTA_GPINP 0x8 187 188#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) 189#define MALTA_I2CINP 0x00 190#define MALTA_I2COE 0x08 191#define MALTA_I2COUT 0x10 192#define MALTA_I2CSEL 0x18 193 | 128#define MALTA_FPGA_SIZE 0x00c00000 /* 12 MByte */ 129 130#define MALTA_NMISTATUS (MALTA_FPGA_BASE + 0x24) 131#define MALTA_NMI_SB 0x2 /* Pending NMI from the South Bridge */ 132#define MALTA_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */ 133 134#define MALTA_NMIACK (MALTA_FPGA_BASE + 0x104) 135#define MALTA_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */ --- 50 unchanged lines hidden (view full) --- 186#define MALTA_GPINP 0x8 187 188#define MALTA_I2C_BASE (MALTA_FPGA_BASE + 0xb00) 189#define MALTA_I2CINP 0x00 190#define MALTA_I2COE 0x08 191#define MALTA_I2COUT 0x10 192#define MALTA_I2CSEL 0x18 193 |
| 194#define MALTA_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */ | 194#define MALTA_BOOTROM_BASE 0x1fc00000ul /* Boot ROM: */ |
| 195#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ 196 | 195#define MALTA_BOOTROM_SIZE 0x00400000 /* 4 MByte */ 196 |
| 197#define MALTA_REVISION 0x1fc00010 | 197#define MALTA_REVISION 0x1fc00010ul |
| 198#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ 199#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */ 200#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */ 201#define MALTA_REV_PROID 0x0000f0 /* Product ID */ 202#define MALTA_REV_PRORV 0x00000f /* Product Revision */ 203 204/* PCI definitions */ 205#define MALTA_SOUTHBRIDGE_INTR 0 --- 38 unchanged lines hidden --- | 198#define MALTA_REV_FPGRV 0xff0000 /* CBUS FPGA revision */ 199#define MALTA_REV_CORID 0x00fc00 /* Core Board ID */ 200#define MALTA_REV_CORRV 0x000300 /* Core Board Revision */ 201#define MALTA_REV_PROID 0x0000f0 /* Product ID */ 202#define MALTA_REV_PRORV 0x00000f /* Product Revision */ 203 204/* PCI definitions */ 205#define MALTA_SOUTHBRIDGE_INTR 0 --- 38 unchanged lines hidden --- |