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gt_pci.c (194082) gt_pci.c (202035)
1/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
2
3/*-
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *

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35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * PCI configuration support for gt I/O Processor chip.
40 */
41
42#include <sys/cdefs.h>
1/* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
2
3/*-
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *

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35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * PCI configuration support for gt I/O Processor chip.
40 */
41
42#include <sys/cdefs.h>
43__FBSDID("$FreeBSD: head/sys/mips/malta/gt_pci.c 194082 2009-06-12 22:49:35Z jmallett $");
43__FBSDID("$FreeBSD: head/sys/mips/malta/gt_pci.c 202035 2010-01-10 20:06:14Z imp $");
44
45#include <sys/param.h>
46#include <sys/systm.h>
47
48#include <sys/bus.h>
49#include <sys/interrupt.h>
50#include <sys/malloc.h>
51#include <sys/kernel.h>

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86#define PIC_OCW3 0
87
88#define OCW2_SELECT 0
89#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
90
91#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
92#define OCW3_POLL_PENDING (1U << 7)
93
44
45#include <sys/param.h>
46#include <sys/systm.h>
47
48#include <sys/bus.h>
49#include <sys/interrupt.h>
50#include <sys/malloc.h>
51#include <sys/kernel.h>

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86#define PIC_OCW3 0
87
88#define OCW2_SELECT 0
89#define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
90
91#define OCW3_POLL_IRQ(x) ((x) & 0x7f)
92#define OCW3_POLL_PENDING (1U << 7)
93
94struct gt_pci_softc;
95
96struct gt_pci_intr_cookie {
97 int irq;
98 struct gt_pci_softc *sc;
99};
100
94struct gt_pci_softc {
95 device_t sc_dev;
96 bus_space_tag_t sc_st;
101struct gt_pci_softc {
102 device_t sc_dev;
103 bus_space_tag_t sc_st;
97 bus_space_tag_t sc_pciio;
98 bus_space_tag_t sc_pcimem;
99 bus_space_handle_t sc_ioh_icu1;
100 bus_space_handle_t sc_ioh_icu2;
101 bus_space_handle_t sc_ioh_elcr;
102
103 int sc_busno;
104 struct rman sc_mem_rman;
105 struct rman sc_io_rman;
106 struct rman sc_irq_rman;
107 uint32_t sc_mem;
108 uint32_t sc_io;
109
110 struct resource *sc_irq;
111 struct intr_event *sc_eventstab[ICU_LEN];
104 bus_space_handle_t sc_ioh_icu1;
105 bus_space_handle_t sc_ioh_icu2;
106 bus_space_handle_t sc_ioh_elcr;
107
108 int sc_busno;
109 struct rman sc_mem_rman;
110 struct rman sc_io_rman;
111 struct rman sc_irq_rman;
112 uint32_t sc_mem;
113 uint32_t sc_io;
114
115 struct resource *sc_irq;
116 struct intr_event *sc_eventstab[ICU_LEN];
117 struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
112 uint16_t sc_imask;
113 uint16_t sc_elcr;
114
115 uint16_t sc_reserved;
116
117 void *sc_ih;
118};
119
118 uint16_t sc_imask;
119 uint16_t sc_elcr;
120
121 uint16_t sc_reserved;
122
123 void *sc_ih;
124};
125
126static void gt_pci_set_icus(struct gt_pci_softc *);
127static int gt_pci_intr(void *v);
128static int gt_pci_probe(device_t);
129static int gt_pci_attach(device_t);
130static int gt_pci_activate_resource(device_t, device_t, int, int,
131 struct resource *);
132static int gt_pci_setup_intr(device_t, device_t, struct resource *,
133 int, driver_filter_t *, driver_intr_t *, void *, void **);
134static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
135static int gt_pci_maxslots(device_t );
136static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
137 uint32_t *);
138static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
139static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
140 uint32_t, int);
141static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
142static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
143 int *, u_long, u_long, u_long, u_int);
144
120static void
145static void
146gt_pci_mask_irq(void *source)
147{
148 struct gt_pci_intr_cookie *cookie = source;
149 struct gt_pci_softc *sc = cookie->sc;
150 int irq = cookie->irq;
151
152 sc->sc_imask |= (1 << irq);
153 sc->sc_elcr |= (1 << irq);
154
155 gt_pci_set_icus(sc);
156}
157
158static void
159gt_pci_unmask_irq(void *source)
160{
161 struct gt_pci_intr_cookie *cookie = source;
162 struct gt_pci_softc *sc = cookie->sc;
163 int irq = cookie->irq;
164
165 /* Enable it, set trigger mode. */
166 sc->sc_imask &= ~(1 << irq);
167 sc->sc_elcr &= ~(1 << irq);
168
169 gt_pci_set_icus(sc);
170}
171
172static void
121gt_pci_set_icus(struct gt_pci_softc *sc)
122{
123 /* Enable the cascade IRQ (2) if 8-15 is enabled. */
124 if ((sc->sc_imask & 0xff00) != 0xff00)
125 sc->sc_imask &= ~(1U << 2);
126 else
127 sc->sc_imask |= (1U << 2);
128
173gt_pci_set_icus(struct gt_pci_softc *sc)
174{
175 /* Enable the cascade IRQ (2) if 8-15 is enabled. */
176 if ((sc->sc_imask & 0xff00) != 0xff00)
177 sc->sc_imask &= ~(1U << 2);
178 else
179 sc->sc_imask |= (1U << 2);
180
129 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW1,
181 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
130 sc->sc_imask & 0xff);
182 sc->sc_imask & 0xff);
131 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, PIC_OCW1,
183 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
132 (sc->sc_imask >> 8) & 0xff);
133
184 (sc->sc_imask >> 8) & 0xff);
185
134 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
186 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
135 sc->sc_elcr & 0xff);
187 sc->sc_elcr & 0xff);
136 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
188 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
137 (sc->sc_elcr >> 8) & 0xff);
138}
139
140static int
141gt_pci_intr(void *v)
142{
143 struct gt_pci_softc *sc = v;
144 struct intr_event *event;
145 int irq;
146
147 for (;;) {
189 (sc->sc_elcr >> 8) & 0xff);
190}
191
192static int
193gt_pci_intr(void *v)
194{
195 struct gt_pci_softc *sc = v;
196 struct intr_event *event;
197 int irq;
198
199 for (;;) {
148 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3,
200 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
149 OCW3_SEL | OCW3_P);
201 OCW3_SEL | OCW3_P);
150 irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW3);
202 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
151 if ((irq & OCW3_POLL_PENDING) == 0)
152 {
153 return FILTER_HANDLED;
154 }
155
156 irq = OCW3_POLL_IRQ(irq);
157
158 if (irq == 2) {
203 if ((irq & OCW3_POLL_PENDING) == 0)
204 {
205 return FILTER_HANDLED;
206 }
207
208 irq = OCW3_POLL_IRQ(irq);
209
210 if (irq == 2) {
159 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
211 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
160 PIC_OCW3, OCW3_SEL | OCW3_P);
212 PIC_OCW3, OCW3_SEL | OCW3_P);
161 irq = bus_space_read_1(sc->sc_pciio, sc->sc_ioh_icu2,
213 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
162 PIC_OCW3);
163 if (irq & OCW3_POLL_PENDING)
164 irq = OCW3_POLL_IRQ(irq) + 8;
165 else
166 irq = 2;
167 }
168
169 event = sc->sc_eventstab[irq];
170
171 if (!event || TAILQ_EMPTY(&event->ie_handlers))
172 continue;
173
174 /* TODO: frame instead of NULL? */
175 intr_event_handle(event, NULL);
176 /* XXX: Log stray IRQs */
177
178 /* Send a specific EOI to the 8259. */
179 if (irq > 7) {
214 PIC_OCW3);
215 if (irq & OCW3_POLL_PENDING)
216 irq = OCW3_POLL_IRQ(irq) + 8;
217 else
218 irq = 2;
219 }
220
221 event = sc->sc_eventstab[irq];
222
223 if (!event || TAILQ_EMPTY(&event->ie_handlers))
224 continue;
225
226 /* TODO: frame instead of NULL? */
227 intr_event_handle(event, NULL);
228 /* XXX: Log stray IRQs */
229
230 /* Send a specific EOI to the 8259. */
231 if (irq > 7) {
180 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2,
232 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
181 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
182 OCW2_ILS(irq & 7));
183 irq = 2;
184 }
185
233 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
234 OCW2_ILS(irq & 7));
235 irq = 2;
236 }
237
186 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, PIC_OCW2,
238 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
187 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
188 }
189
190 return FILTER_HANDLED;
191}
192
193static int
194gt_pci_probe(device_t dev)

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203
204 uint32_t busno;
205 struct gt_pci_softc *sc = device_get_softc(dev);
206 int rid;
207
208 busno = 0;
209 sc->sc_dev = dev;
210 sc->sc_busno = busno;
239 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
240 }
241
242 return FILTER_HANDLED;
243}
244
245static int
246gt_pci_probe(device_t dev)

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255
256 uint32_t busno;
257 struct gt_pci_softc *sc = device_get_softc(dev);
258 int rid;
259
260 busno = 0;
261 sc->sc_dev = dev;
262 sc->sc_busno = busno;
211 sc->sc_pciio = MIPS_BUS_SPACE_IO;
212 sc->sc_pcimem = MIPS_BUS_SPACE_MEM;
263 sc->sc_st = mips_bus_space_generic;
213
214 /* Use KSEG1 to access IO ports for it is uncached */
215 sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
216 sc->sc_io_rman.rm_type = RMAN_ARRAY;
217 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
218 if (rman_init(&sc->sc_io_rman) != 0 ||
219 rman_manage_region(&sc->sc_io_rman, 0, 0xffff) != 0) {
220 panic("gt_pci_attach: failed to set up I/O rman");

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234 if (rman_init(&sc->sc_irq_rman) != 0 ||
235 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
236 panic("gt_pci_attach: failed to set up IRQ rman");
237
238 /*
239 * Map the PIC/ELCR registers.
240 */
241#if 0
264
265 /* Use KSEG1 to access IO ports for it is uncached */
266 sc->sc_io = MIPS_PHYS_TO_KSEG1(MALTA_PCI0_IO_BASE);
267 sc->sc_io_rman.rm_type = RMAN_ARRAY;
268 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
269 if (rman_init(&sc->sc_io_rman) != 0 ||
270 rman_manage_region(&sc->sc_io_rman, 0, 0xffff) != 0) {
271 panic("gt_pci_attach: failed to set up I/O rman");

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285 if (rman_init(&sc->sc_irq_rman) != 0 ||
286 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
287 panic("gt_pci_attach: failed to set up IRQ rman");
288
289 /*
290 * Map the PIC/ELCR registers.
291 */
292#if 0
242 if (bus_space_map(sc->sc_pciio, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
293 if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
243 device_printf(dev, "unable to map ELCR registers\n");
294 device_printf(dev, "unable to map ELCR registers\n");
244 if (bus_space_map(sc->sc_pciio, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
295 if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
245 device_printf(dev, "unable to map ICU1 registers\n");
296 device_printf(dev, "unable to map ICU1 registers\n");
246 if (bus_space_map(sc->sc_pciio, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
297 if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
247 device_printf(dev, "unable to map ICU2 registers\n");
248#else
249 sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
250 sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
251 sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
252#endif
253
254
255 /* All interrupts default to "masked off". */
256 sc->sc_imask = 0xffff;
257
258 /* All interrupts default to edge-triggered. */
259 sc->sc_elcr = 0;
260
261 /*
262 * Initialize the 8259s.
263 */
264 /* reset, program device, 4 bytes */
298 device_printf(dev, "unable to map ICU2 registers\n");
299#else
300 sc->sc_ioh_elcr = sc->sc_io + 0x4d0;
301 sc->sc_ioh_icu1 = sc->sc_io + IO_ICU1;
302 sc->sc_ioh_icu2 = sc->sc_io + IO_ICU2;
303#endif
304
305
306 /* All interrupts default to "masked off". */
307 sc->sc_imask = 0xffff;
308
309 /* All interrupts default to edge-triggered. */
310 sc->sc_elcr = 0;
311
312 /*
313 * Initialize the 8259s.
314 */
315 /* reset, program device, 4 bytes */
265 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
316 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
266 ICW1_RESET | ICW1_IC4);
267 /*
268 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
269 */
317 ICW1_RESET | ICW1_IC4);
318 /*
319 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
320 */
270 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
321 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
271 0/*XXX*/);
322 0/*XXX*/);
272 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
323 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
273 1 << 2);
324 1 << 2);
274 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
325 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
275 ICW4_8086);
276
277 /* mask all interrupts */
326 ICW4_8086);
327
328 /* mask all interrupts */
278 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 0,
329 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
279 sc->sc_imask & 0xff);
280
281 /* enable special mask mode */
330 sc->sc_imask & 0xff);
331
332 /* enable special mask mode */
282 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
333 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
283 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
284
285 /* read IRR by default */
334 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
335
336 /* read IRR by default */
286 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu1, 1,
337 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
287 OCW3_SEL | OCW3_RR);
288
289 /* reset, program device, 4 bytes */
338 OCW3_SEL | OCW3_RR);
339
340 /* reset, program device, 4 bytes */
290 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
341 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
291 ICW1_RESET | ICW1_IC4);
342 ICW1_RESET | ICW1_IC4);
292 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
343 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
293 0/*XXX*/);
344 0/*XXX*/);
294 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
345 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
295 1 << 2);
346 1 << 2);
296 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
347 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
297 ICW4_8086);
298
299 /* mask all interrupts */
348 ICW4_8086);
349
350 /* mask all interrupts */
300 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 0,
351 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
301 sc->sc_imask & 0xff);
302
303 /* enable special mask mode */
352 sc->sc_imask & 0xff);
353
354 /* enable special mask mode */
304 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
355 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
305 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
306
307 /* read IRR by default */
356 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
357
358 /* read IRR by default */
308 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_icu2, 1,
359 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
309 OCW3_SEL | OCW3_RR);
310
311 /*
312 * Default all interrupts to edge-triggered.
313 */
360 OCW3_SEL | OCW3_RR);
361
362 /*
363 * Default all interrupts to edge-triggered.
364 */
314 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 0,
365 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
315 sc->sc_elcr & 0xff);
366 sc->sc_elcr & 0xff);
316 bus_space_write_1(sc->sc_pciio, sc->sc_ioh_elcr, 1,
367 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
317 (sc->sc_elcr >> 8) & 0xff);
318
319 /*
320 * Some ISA interrupts are reserved for devices that
321 * we know are hard-wired to certain IRQs.
322 */
323 sc->sc_reserved =
324 (1U << 0) | /* timer */

--- 240 unchanged lines hidden (view full) ---

565 bus_space_handle_t bh = 0;
566
567 switch (type) {
568 case SYS_RES_IRQ:
569 rm = &sc->sc_irq_rman;
570 break;
571 case SYS_RES_MEMORY:
572 rm = &sc->sc_mem_rman;
368 (sc->sc_elcr >> 8) & 0xff);
369
370 /*
371 * Some ISA interrupts are reserved for devices that
372 * we know are hard-wired to certain IRQs.
373 */
374 sc->sc_reserved =
375 (1U << 0) | /* timer */

--- 240 unchanged lines hidden (view full) ---

616 bus_space_handle_t bh = 0;
617
618 switch (type) {
619 case SYS_RES_IRQ:
620 rm = &sc->sc_irq_rman;
621 break;
622 case SYS_RES_MEMORY:
623 rm = &sc->sc_mem_rman;
573 bt = sc->sc_pcimem;
624 bt = sc->sc_st;
574 bh = sc->sc_mem;
575 break;
576 case SYS_RES_IOPORT:
577 rm = &sc->sc_io_rman;
625 bh = sc->sc_mem;
626 break;
627 case SYS_RES_IOPORT:
628 rm = &sc->sc_io_rman;
578 bt = sc->sc_pciio;
629 bt = sc->sc_st;
579 bh = sc->sc_io;
580 break;
581 default:
582 return (NULL);
583 }
584
585 rv = rman_reserve_resource(rm, start, end, count, flags, child);
586 if (rv == NULL)

--- 40 unchanged lines hidden (view full) ---

627 struct intr_event *event;
628 int irq, error;
629
630 irq = rman_get_start(ires);
631 if (irq >= ICU_LEN || irq == 2)
632 panic("%s: bad irq or type", __func__);
633
634 event = sc->sc_eventstab[irq];
630 bh = sc->sc_io;
631 break;
632 default:
633 return (NULL);
634 }
635
636 rv = rman_reserve_resource(rm, start, end, count, flags, child);
637 if (rv == NULL)

--- 40 unchanged lines hidden (view full) ---

678 struct intr_event *event;
679 int irq, error;
680
681 irq = rman_get_start(ires);
682 if (irq >= ICU_LEN || irq == 2)
683 panic("%s: bad irq or type", __func__);
684
685 event = sc->sc_eventstab[irq];
686 sc->sc_intr_cookies[irq].irq = irq;
687 sc->sc_intr_cookies[irq].sc = sc;
635 if (event == NULL) {
688 if (event == NULL) {
636 error = intr_event_create(&event, (void *)irq, 0, irq,
637 (mask_fn)mips_mask_irq, (mask_fn)mips_unmask_irq,
638 (mask_fn)mips_unmask_irq, NULL, "gt_pci intr%d:", irq);
689 error = intr_event_create(&event,
690 (void *)&sc->sc_intr_cookies[irq], 0, irq,
691 gt_pci_mask_irq, gt_pci_unmask_irq,
692 NULL, NULL, "gt_pci intr%d:", irq);
639 if (error)
640 return 0;
641 sc->sc_eventstab[irq] = event;
642 }
643
644 intr_event_add_handler(event, device_get_nameunit(child), filt,
645 handler, arg, intr_priority(flags), flags, cookiep);
646
693 if (error)
694 return 0;
695 sc->sc_eventstab[irq] = event;
696 }
697
698 intr_event_add_handler(event, device_get_nameunit(child), filt,
699 handler, arg, intr_priority(flags), flags, cookiep);
700
647 /* Enable it, set trigger mode. */
648 sc->sc_imask &= ~(1 << irq);
649 sc->sc_elcr &= ~(1 << irq);
650
651 gt_pci_set_icus(sc);
652
701 gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
653 return 0;
654}
655
656static int
657gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
658 void *cookie)
659{
702 return 0;
703}
704
705static int
706gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
707 void *cookie)
708{
709 struct gt_pci_softc *sc = device_get_softc(dev);
710 int irq;
711
712 irq = rman_get_start(res);
713 gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
714
660 return (intr_event_remove_handler(cookie));
661}
662
663static device_method_t gt_pci_methods[] = {
664 /* Device interface */
665 DEVMETHOD(device_probe, gt_pci_probe),
666 DEVMETHOD(device_attach, gt_pci_attach),
667 DEVMETHOD(device_shutdown, bus_generic_shutdown),

--- 32 unchanged lines hidden --- 		715 return (intr_event_remove_handler(cookie));
716}
717
718static device_method_t gt_pci_methods[] = {
719 /* Device interface */
720 DEVMETHOD(device_probe, gt_pci_probe),
721 DEVMETHOD(device_attach, gt_pci_attach),
722 DEVMETHOD(device_shutdown, bus_generic_shutdown),

--- 32 unchanged lines hidden ---