| ia64_cpu.h (66486) | ia64_cpu.h (66633) |
|---|---|
| 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 2000 Doug Rabson 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 66486 2000-09-30 17:48:44Z dfr $ | 26 * $FreeBSD: head/sys/ia64/include/ia64_cpu.h 66633 2000-10-04 17:53:03Z dfr $ |
| 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 143 unchanged lines hidden (view full) --- 178ia64_tpa(u_int64_t va) 179{ 180 u_int64_t result; 181 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va)); 182 return result; 183} 184 185/* | 27 */ 28 29#ifndef _MACHINE_IA64_CPU_H_ 30#define _MACHINE_IA64_CPU_H_ 31 32/* 33 * Definition of PSR and IPSR bits. 34 */ --- 143 unchanged lines hidden (view full) --- 178ia64_tpa(u_int64_t va) 179{ 180 u_int64_t result; 181 __asm __volatile("tpa %0=%1" : "=r" (result) : "r" (va)); 182 return result; 183} 184 185/* |
| 186 * Read the value of ar.k0. 187 */ 188static __inline u_int64_t 189ia64_get_k0(void) 190{ 191 u_int64_t result; 192 __asm __volatile("mov %0=ar.k0" : "=r" (result)); 193 return result; 194} 195 196/* 197 * Read the value of ar.k1. 198 */ 199static __inline u_int64_t 200ia64_get_k1(void) 201{ 202 u_int64_t result; 203 __asm __volatile("mov %0=ar.k1" : "=r" (result)); 204 return result; 205} 206 207/* 208 * Read the value of ar.k2. 209 */ 210static __inline u_int64_t 211ia64_get_k2(void) 212{ 213 u_int64_t result; 214 __asm __volatile("mov %0=ar.k2" : "=r" (result)); 215 return result; 216} 217 218/* 219 * Read the value of ar.k3. 220 */ 221static __inline u_int64_t 222ia64_get_k3(void) 223{ 224 u_int64_t result; 225 __asm __volatile("mov %0=ar.k3" : "=r" (result)); 226 return result; 227} 228 229/* 230 * Read the value of ar.k4. 231 */ 232static __inline u_int64_t 233ia64_get_k4(void) 234{ 235 u_int64_t result; 236 __asm __volatile("mov %0=ar.k4" : "=r" (result)); 237 return result; 238} 239 240/* 241 * Read the value of ar.k5. 242 */ 243static __inline u_int64_t 244ia64_get_k5(void) 245{ 246 u_int64_t result; 247 __asm __volatile("mov %0=ar.k5" : "=r" (result)); 248 return result; 249} 250 251/* 252 * Read the value of ar.k6. 253 */ 254static __inline u_int64_t 255ia64_get_k6(void) 256{ 257 u_int64_t result; 258 __asm __volatile("mov %0=ar.k6" : "=r" (result)); 259 return result; 260} 261 262/* 263 * Read the value of ar.k7. 264 */ 265static __inline u_int64_t 266ia64_get_k7(void) 267{ 268 u_int64_t result; 269 __asm __volatile("mov %0=ar.k7" : "=r" (result)); 270 return result; 271} 272 273/* 274 * Write the value of ar.k0. 275 */ 276static __inline void 277ia64_set_k0(u_int64_t v) 278{ 279 __asm __volatile("mov ar.k0=%0" :: "r" (v)); 280} 281 282/* 283 * Write the value of ar.k1. 284 */ 285static __inline void 286ia64_set_k1(u_int64_t v) 287{ 288 __asm __volatile("mov ar.k1=%0" :: "r" (v)); 289} 290 291/* 292 * Write the value of ar.k2. 293 */ 294static __inline void 295ia64_set_k2(u_int64_t v) 296{ 297 __asm __volatile("mov ar.k2=%0" :: "r" (v)); 298} 299 300/* 301 * Write the value of ar.k3. 302 */ 303static __inline void 304ia64_set_k3(u_int64_t v) 305{ 306 __asm __volatile("mov ar.k3=%0" :: "r" (v)); 307} 308 309/* 310 * Write the value of ar.k4. 311 */ 312static __inline void 313ia64_set_k4(u_int64_t v) 314{ 315 __asm __volatile("mov ar.k4=%0" :: "r" (v)); 316} 317 318/* 319 * Write the value of ar.k5. 320 */ 321static __inline void 322ia64_set_k5(u_int64_t v) 323{ 324 __asm __volatile("mov ar.k5=%0" :: "r" (v)); 325} 326 327/* 328 * Write the value of ar.k6. 329 */ 330static __inline void 331ia64_set_k6(u_int64_t v) 332{ 333 __asm __volatile("mov ar.k6=%0" :: "r" (v)); 334} 335 336/* 337 * Write the value of ar.k7. 338 */ 339static __inline void 340ia64_set_k7(u_int64_t v) 341{ 342 __asm __volatile("mov ar.k7=%0" :: "r" (v)); 343} 344 345/* |
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| 186 * Read the value of ar.itc. 187 */ 188static __inline u_int64_t 189ia64_get_itc(void) 190{ 191 u_int64_t result; 192 __asm __volatile("mov %0=ar.itc" : "=r" (result)); 193 return result; --- 33 unchanged lines hidden --- | 346 * Read the value of ar.itc. 347 */ 348static __inline u_int64_t 349ia64_get_itc(void) 350{ 351 u_int64_t result; 352 __asm __volatile("mov %0=ar.itc" : "=r" (result)); 353 return result; --- 33 unchanged lines hidden --- |