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initcpu.c (74903) initcpu.c (79609)
1/*
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
1/*
2 * Copyright (c) KATO Takenori, 1997, 1998.
3 *
4 * All rights reserved. Unpublished rights reserved under the copyright
5 * laws of Japan.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 12 unchanged lines hidden (view full) ---

21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/i386/i386/initcpu.c 74903 2001-03-28 03:06:10Z jhb $
29 * $FreeBSD: head/sys/i386/i386/initcpu.c 79609 2001-07-12 06:32:51Z peter $
30 */
31
32#include "opt_cpu.h"
33
34#include <sys/param.h>
35#include <sys/kernel.h>
36#include <sys/systm.h>
30 */
31
32#include "opt_cpu.h"
33
34#include <sys/param.h>
35#include <sys/kernel.h>
36#include <sys/systm.h>
37#include <sys/sysctl.h>
37
38#include <machine/cputypes.h>
39#include <machine/md_var.h>
40#include <machine/specialreg.h>
41
42void initializecpu(void);
43#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
44void enable_K5_wt_alloc(void);

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56#endif
57static void init_6x86(void);
58#endif /* I486_CPU */
59
60#ifdef I686_CPU
61static void init_6x86MX(void);
62static void init_ppro(void);
63static void init_mendocino(void);
38
39#include <machine/cputypes.h>
40#include <machine/md_var.h>
41#include <machine/specialreg.h>
42
43void initializecpu(void);
44#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
45void enable_K5_wt_alloc(void);

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57#endif
58static void init_6x86(void);
59#endif /* I486_CPU */
60
61#ifdef I686_CPU
62static void init_6x86MX(void);
63static void init_ppro(void);
64static void init_mendocino(void);
65void enable_sse();
64#endif
65
66#endif
67
68int hw_instruction_sse = 0;
69SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
70 &hw_instruction_sse, 0,
71 "SIMD/MMX2 instructions available in CPU");
72
66#ifdef I486_CPU
67/*
68 * IBM Blue Lightning
69 */
70static void
71init_bluelightning(void)
72{
73 u_long eflags;

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496 wrmsr(0x11e, bbl_cr_ctl3);
497 }
498
499 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
500 write_eflags(eflags);
501#endif /* CPU_PPRO2CELERON */
502}
503
73#ifdef I486_CPU
74/*
75 * IBM Blue Lightning
76 */
77static void
78init_bluelightning(void)
79{
80 u_long eflags;

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503 wrmsr(0x11e, bbl_cr_ctl3);
504 }
505
506 load_cr0(rcr0() & ~(CR0_CD | CR0_NW));
507 write_eflags(eflags);
508#endif /* CPU_PPRO2CELERON */
509}
510
511/*
512 * Initialize CR4 (Control register 4) to enable SSE instructions.
513 */
514void
515enable_sse(void)
516{
517#if defined(CPU_ENABLE_SSE)
518 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) {
519 load_cr4(rcr4() | CR4_FXSR | CR4_XMM);
520 cpu_fxsr = hw_instruction_sse = 1;
521 }
522#endif
523}
524
504#endif /* I686_CPU */
505
506void
507initializecpu(void)
508{
509
510 switch (cpu) {
511#ifdef I486_CPU

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539 switch (cpu_id & 0xff0) {
540 case 0x610:
541 init_ppro();
542 break;
543 case 0x660:
544 init_mendocino();
545 break;
546 }
525#endif /* I686_CPU */
526
527void
528initializecpu(void)
529{
530
531 switch (cpu) {
532#ifdef I486_CPU

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560 switch (cpu_id & 0xff0) {
561 case 0x610:
562 init_ppro();
563 break;
564 case 0x660:
565 init_mendocino();
566 break;
567 }
568 enable_sse();
547 }
548 break;
549#endif
550 default:
551 break;
552 }
553
554#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)

--- 271 unchanged lines hidden --- 		569 }
570 break;
571#endif
572 default:
573 break;
574 }
575
576#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)

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