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vf610.dtsi (262573) vf610.dtsi (270864)
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "skeleton.dtsi"
11#include "vf610-pinfunc.h"
12#include <dt-bindings/clock/vf610-clock.h>
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include "skeleton.dtsi"
11#include "vf610-pinfunc.h"
12#include <dt-bindings/clock/vf610-clock.h>
13#include <dt-bindings/interrupt-controller/irq.h>
13
14/ {
15 aliases {
14
15/ {
16 aliases {
17 can0 = &can0;
18 can1 = &can1;
16 serial0 = &uart0;
17 serial1 = &uart1;
18 serial2 = &uart2;
19 serial3 = &uart3;
20 serial4 = &uart4;
21 serial5 = &uart5;
22 gpio0 = &gpio1;
23 gpio1 = &gpio2;

--- 15 unchanged lines hidden (view full) ---

39 };
40
41 clocks {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 sxosc {
46 compatible = "fixed-clock";
19 serial0 = &uart0;
20 serial1 = &uart1;
21 serial2 = &uart2;
22 serial3 = &uart3;
23 serial4 = &uart4;
24 serial5 = &uart5;
25 gpio0 = &gpio1;
26 gpio1 = &gpio2;

--- 15 unchanged lines hidden (view full) ---

42 };
43
44 clocks {
45 #address-cells = <1>;
46 #size-cells = <0>;
47
48 sxosc {
49 compatible = "fixed-clock";
50 #clock-cells = <0>;
47 clock-frequency = <32768>;
48 };
49
50 fxosc {
51 compatible = "fixed-clock";
51 clock-frequency = <32768>;
52 };
53
54 fxosc {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
52 clock-frequency = <24000000>;
53 };
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";

--- 6 unchanged lines hidden (view full) ---

66 #size-cells = <1>;
67 interrupt-parent = <&intc>;
68 reg = <0x40000000 0x70000>;
69 ranges;
70
71 intc: interrupt-controller@40002000 {
72 compatible = "arm,cortex-a9-gic";
73 #interrupt-cells = <3>;
57 clock-frequency = <24000000>;
58 };
59 };
60
61 soc {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "simple-bus";

--- 6 unchanged lines hidden (view full) ---

71 #size-cells = <1>;
72 interrupt-parent = <&intc>;
73 reg = <0x40000000 0x70000>;
74 ranges;
75
76 intc: interrupt-controller@40002000 {
77 compatible = "arm,cortex-a9-gic";
78 #interrupt-cells = <3>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 interrupt-controller;
77 reg = <0x40003000 0x1000>,
78 <0x40002100 0x100>;
79 };
80
81 L2: l2-cache@40006000 {
82 compatible = "arm,pl310-cache";
83 reg = <0x40006000 0x1000>;
84 cache-unified;
85 cache-level = <2>;
86 arm,data-latency = <1 1 1>;
87 arm,tag-latency = <2 2 2>;
88 };
89
79 interrupt-controller;
80 reg = <0x40003000 0x1000>,
81 <0x40002100 0x100>;
82 };
83
84 L2: l2-cache@40006000 {
85 compatible = "arm,pl310-cache";
86 reg = <0x40006000 0x1000>;
87 cache-unified;
88 cache-level = <2>;
89 arm,data-latency = <1 1 1>;
90 arm,tag-latency = <2 2 2>;
91 };
92
93 edma0: dma-controller@40018000 {
94 #dma-cells = <2>;
95 compatible = "fsl,vf610-edma";
96 reg = <0x40018000 0x2000>,
97 <0x40024000 0x1000>,
98 <0x40025000 0x1000>;
99 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
100 <0 9 IRQ_TYPE_LEVEL_HIGH>;
101 interrupt-names = "edma-tx", "edma-err";
102 dma-channels = <32>;
103 clock-names = "dmamux0", "dmamux1";
104 clocks = <&clks VF610_CLK_DMAMUX0>,
105 <&clks VF610_CLK_DMAMUX1>;
106 };
107
108 can0: flexcan@40020000 {
109 compatible = "fsl,vf610-flexcan";
110 reg = <0x40020000 0x4000>;
111 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_FLEXCAN0>,
113 <&clks VF610_CLK_FLEXCAN0>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
90 uart0: serial@40027000 {
91 compatible = "fsl,vf610-lpuart";
92 reg = <0x40027000 0x1000>;
118 uart0: serial@40027000 {
119 compatible = "fsl,vf610-lpuart";
120 reg = <0x40027000 0x1000>;
93 interrupts = <0 61 0x00>;
121 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&clks VF610_CLK_UART0>;
95 clock-names = "ipg";
122 clocks = <&clks VF610_CLK_UART0>;
123 clock-names = "ipg";
124 dmas = <&edma0 0 2>,
125 <&edma0 0 3>;
126 dma-names = "rx","tx";
96 status = "disabled";
97 };
98
99 uart1: serial@40028000 {
100 compatible = "fsl,vf610-lpuart";
101 reg = <0x40028000 0x1000>;
127 status = "disabled";
128 };
129
130 uart1: serial@40028000 {
131 compatible = "fsl,vf610-lpuart";
132 reg = <0x40028000 0x1000>;
102 interrupts = <0 62 0x04>;
133 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clks VF610_CLK_UART1>;
104 clock-names = "ipg";
134 clocks = <&clks VF610_CLK_UART1>;
135 clock-names = "ipg";
136 dmas = <&edma0 0 4>,
137 <&edma0 0 5>;
138 dma-names = "rx","tx";
105 status = "disabled";
106 };
107
108 uart2: serial@40029000 {
109 compatible = "fsl,vf610-lpuart";
110 reg = <0x40029000 0x1000>;
139 status = "disabled";
140 };
141
142 uart2: serial@40029000 {
143 compatible = "fsl,vf610-lpuart";
144 reg = <0x40029000 0x1000>;
111 interrupts = <0 63 0x04>;
145 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_UART2>;
113 clock-names = "ipg";
146 clocks = <&clks VF610_CLK_UART2>;
147 clock-names = "ipg";
148 dmas = <&edma0 0 6>,
149 <&edma0 0 7>;
150 dma-names = "rx","tx";
114 status = "disabled";
115 };
116
117 uart3: serial@4002a000 {
118 compatible = "fsl,vf610-lpuart";
119 reg = <0x4002a000 0x1000>;
151 status = "disabled";
152 };
153
154 uart3: serial@4002a000 {
155 compatible = "fsl,vf610-lpuart";
156 reg = <0x4002a000 0x1000>;
120 interrupts = <0 64 0x04>;
157 interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clks VF610_CLK_UART3>;
122 clock-names = "ipg";
158 clocks = <&clks VF610_CLK_UART3>;
159 clock-names = "ipg";
160 dmas = <&edma0 0 8>,
161 <&edma0 0 9>;
162 dma-names = "rx","tx";
123 status = "disabled";
124 };
125
126 dspi0: dspi0@4002c000 {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 compatible = "fsl,vf610-dspi";
130 reg = <0x4002c000 0x1000>;
163 status = "disabled";
164 };
165
166 dspi0: dspi0@4002c000 {
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "fsl,vf610-dspi";
170 reg = <0x4002c000 0x1000>;
131 interrupts = <0 67 0x04>;
171 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&clks VF610_CLK_DSPI0>;
133 clock-names = "dspi";
134 spi-num-chipselects = <5>;
135 status = "disabled";
136 };
137
138 sai2: sai@40031000 {
139 compatible = "fsl,vf610-sai";
140 reg = <0x40031000 0x1000>;
172 clocks = <&clks VF610_CLK_DSPI0>;
173 clock-names = "dspi";
174 spi-num-chipselects = <5>;
175 status = "disabled";
176 };
177
178 sai2: sai@40031000 {
179 compatible = "fsl,vf610-sai";
180 reg = <0x40031000 0x1000>;
141 interrupts = <0 86 0x04>;
181 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
142 clocks = <&clks VF610_CLK_SAI2>;
143 clock-names = "sai";
182 clocks = <&clks VF610_CLK_SAI2>;
183 clock-names = "sai";
184 dma-names = "tx", "rx";
185 dmas = <&edma0 0 21>,
186 <&edma0 0 20>;
144 status = "disabled";
145 };
146
147 pit: pit@40037000 {
148 compatible = "fsl,vf610-pit";
149 reg = <0x40037000 0x1000>;
187 status = "disabled";
188 };
189
190 pit: pit@40037000 {
191 compatible = "fsl,vf610-pit";
192 reg = <0x40037000 0x1000>;
150 interrupts = <0 39 0x04>;
193 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&clks VF610_CLK_PIT>;
152 clock-names = "pit";
153 };
154
194 clocks = <&clks VF610_CLK_PIT>;
195 clock-names = "pit";
196 };
197
198 pwm0: pwm@40038000 {
199 compatible = "fsl,vf610-ftm-pwm";
200 #pwm-cells = <3>;
201 reg = <0x40038000 0x1000>;
202 clock-names = "ftm_sys", "ftm_ext",
203 "ftm_fix", "ftm_cnt_clk_en";
204 clocks = <&clks VF610_CLK_FTM0>,
205 <&clks VF610_CLK_FTM0_EXT_SEL>,
206 <&clks VF610_CLK_FTM0_FIX_SEL>,
207 <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
208 status = "disabled";
209 };
210
211 adc0: adc@4003b000 {
212 compatible = "fsl,vf610-adc";
213 reg = <0x4003b000 0x1000>;
214 interrupts = <0 53 0x04>;
215 clocks = <&clks VF610_CLK_ADC0>;
216 clock-names = "adc";
217 status = "disabled";
218 };
219
155 wdog@4003e000 {
156 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
157 reg = <0x4003e000 0x1000>;
158 clocks = <&clks VF610_CLK_WDT>;
159 clock-names = "wdog";
160 };
161
162 qspi0: quadspi@40044000 {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 compatible = "fsl,vf610-qspi";
166 reg = <0x40044000 0x1000>;
220 wdog@4003e000 {
221 compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
222 reg = <0x4003e000 0x1000>;
223 clocks = <&clks VF610_CLK_WDT>;
224 clock-names = "wdog";
225 };
226
227 qspi0: quadspi@40044000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,vf610-qspi";
231 reg = <0x40044000 0x1000>;
167 interrupts = <0 24 0x04>;
232 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&clks VF610_CLK_QSPI0_EN>,
169 <&clks VF610_CLK_QSPI0>;
170 clock-names = "qspi_en", "qspi";
171 status = "disabled";
172 };
173
174 iomuxc: iomuxc@40048000 {
175 compatible = "fsl,vf610-iomuxc";
176 reg = <0x40048000 0x1000>;
177 #gpio-range-cells = <3>;
233 clocks = <&clks VF610_CLK_QSPI0_EN>,
234 <&clks VF610_CLK_QSPI0>;
235 clock-names = "qspi_en", "qspi";
236 status = "disabled";
237 };
238
239 iomuxc: iomuxc@40048000 {
240 compatible = "fsl,vf610-iomuxc";
241 reg = <0x40048000 0x1000>;
242 #gpio-range-cells = <3>;
178
179 /* functions and groups pins */
180
181 dcu0 {
182 pinctrl_dcu0_1: dcu0grp_1 {
183 fsl,pins = <
184 VF610_PAD_PTB8__GPIO_30 0x42
185 VF610_PAD_PTE0__DCU0_HSYNC 0x42
186 VF610_PAD_PTE1__DCU0_VSYNC 0x42
187 VF610_PAD_PTE2__DCU0_PCLK 0x42
188 VF610_PAD_PTE4__DCU0_DE 0x42
189 VF610_PAD_PTE5__DCU0_R0 0x42
190 VF610_PAD_PTE6__DCU0_R1 0x42
191 VF610_PAD_PTE7__DCU0_R2 0x42
192 VF610_PAD_PTE8__DCU0_R3 0x42
193 VF610_PAD_PTE9__DCU0_R4 0x42
194 VF610_PAD_PTE10__DCU0_R5 0x42
195 VF610_PAD_PTE11__DCU0_R6 0x42
196 VF610_PAD_PTE12__DCU0_R7 0x42
197 VF610_PAD_PTE13__DCU0_G0 0x42
198 VF610_PAD_PTE14__DCU0_G1 0x42
199 VF610_PAD_PTE15__DCU0_G2 0x42
200 VF610_PAD_PTE16__DCU0_G3 0x42
201 VF610_PAD_PTE17__DCU0_G4 0x42
202 VF610_PAD_PTE18__DCU0_G5 0x42
203 VF610_PAD_PTE19__DCU0_G6 0x42
204 VF610_PAD_PTE20__DCU0_G7 0x42
205 VF610_PAD_PTE21__DCU0_B0 0x42
206 VF610_PAD_PTE22__DCU0_B1 0x42
207 VF610_PAD_PTE23__DCU0_B2 0x42
208 VF610_PAD_PTE24__DCU0_B3 0x42
209 VF610_PAD_PTE25__DCU0_B4 0x42
210 VF610_PAD_PTE26__DCU0_B5 0x42
211 VF610_PAD_PTE27__DCU0_B6 0x42
212 VF610_PAD_PTE28__DCU0_B7 0x42
213 >;
214 };
215 };
216
217 dspi0 {
218 pinctrl_dspi0_1: dspi0grp_1 {
219 fsl,pins = <
220 VF610_PAD_PTB19__DSPI0_CS0 0x1182
221 VF610_PAD_PTB20__DSPI0_SIN 0x1181
222 VF610_PAD_PTB21__DSPI0_SOUT 0x1182
223 VF610_PAD_PTB22__DSPI0_SCK 0x1182
224 >;
225 };
226 };
227
228 esdhc1 {
229 pinctrl_esdhc1_1: esdhc1grp_1 {
230 fsl,pins = <
231 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
232 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
233 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
234 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
235 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
236 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
237 VF610_PAD_PTA7__GPIO_134 0x219d
238 >;
239 };
240 };
241
242 fec0 {
243 pinctrl_fec0_1: fec0grp_1 {
244 fsl,pins = <
245 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
246 VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
247 VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
248 VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
249 VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
250 VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
251 VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
252 VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
253 VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
254 VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
255 >;
256 };
257 };
258
259 fec1 {
260 pinctrl_fec1_1: fec1grp_1 {
261 fsl,pins = <
262 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
263 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
264 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
265 VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
266 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
267 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
268 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
269 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
270 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
271 >;
272 };
273 };
274
275 i2c0 {
276 pinctrl_i2c0_1: i2c0grp_1 {
277 fsl,pins = <
278 VF610_PAD_PTB14__I2C0_SCL 0x30d3
279 VF610_PAD_PTB15__I2C0_SDA 0x30d3
280 >;
281 };
282 };
283
284 pwm0 {
285 pinctrl_pwm0_1: pwm0grp_1 {
286 fsl,pins = <
287 VF610_PAD_PTB0__FTM0_CH0 0x1582
288 VF610_PAD_PTB1__FTM0_CH1 0x1582
289 VF610_PAD_PTB2__FTM0_CH2 0x1582
290 VF610_PAD_PTB3__FTM0_CH3 0x1582
291 VF610_PAD_PTB6__FTM0_CH6 0x1582
292 VF610_PAD_PTB7__FTM0_CH7 0x1582
293 >;
294 };
295 };
296
297 qspi0 {
298 pinctrl_qspi0_1: qspi0grp_1 {
299 fsl,pins = <
300 VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b
301 VF610_PAD_PTD1__QSPI0_A_CS0 0x307f
302 VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073
303 VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073
304 VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073
305 VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b
306 VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b
307 VF610_PAD_PTD8__QSPI0_B_CS0 0x307f
308 VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073
309 VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073
310 VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073
311 VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b
312 >;
313 };
314 };
315
316 sai2 {
317 pinctrl_sai2_1: sai2grp_1 {
318 fsl,pins = <
319 VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
320 VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
321 VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
322 VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
323 VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
324 VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
325 VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
326 >;
327 };
328 };
329
330 uart1 {
331 pinctrl_uart1_1: uart1grp_1 {
332 fsl,pins = <
333 VF610_PAD_PTB4__UART1_TX 0x21a2
334 VF610_PAD_PTB5__UART1_RX 0x21a1
335 >;
336 };
337 };
338
339 usbvbus {
340 pinctrl_usbvbus_1: usbvbusgrp_1 {
341 fsl,pins = <
342 VF610_PAD_PTA24__USB1_VBUS_EN 0x219c
343 VF610_PAD_PTA16__USB0_VBUS_EN 0x219c
344 >;
345 };
346 };
347
348 };
349
350 gpio1: gpio@40049000 {
351 compatible = "fsl,vf610-gpio";
352 reg = <0x40049000 0x1000 0x400ff000 0x40>;
243 };
244
245 gpio1: gpio@40049000 {
246 compatible = "fsl,vf610-gpio";
247 reg = <0x40049000 0x1000 0x400ff000 0x40>;
353 interrupts = <0 107 0x04>;
248 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 gpio-ranges = <&iomuxc 0 0 32>;
359 };
360
361 gpio2: gpio@4004a000 {
362 compatible = "fsl,vf610-gpio";
363 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 gpio-ranges = <&iomuxc 0 0 32>;
254 };
255
256 gpio2: gpio@4004a000 {
257 compatible = "fsl,vf610-gpio";
258 reg = <0x4004a000 0x1000 0x400ff040 0x40>;
364 interrupts = <0 108 0x04>;
259 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
365 gpio-controller;
366 #gpio-cells = <2>;
367 interrupt-controller;
368 #interrupt-cells = <2>;
369 gpio-ranges = <&iomuxc 0 32 32>;
370 };
371
372 gpio3: gpio@4004b000 {
373 compatible = "fsl,vf610-gpio";
374 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
260 gpio-controller;
261 #gpio-cells = <2>;
262 interrupt-controller;
263 #interrupt-cells = <2>;
264 gpio-ranges = <&iomuxc 0 32 32>;
265 };
266
267 gpio3: gpio@4004b000 {
268 compatible = "fsl,vf610-gpio";
269 reg = <0x4004b000 0x1000 0x400ff080 0x40>;
375 interrupts = <0 109 0x04>;
270 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
376 gpio-controller;
377 #gpio-cells = <2>;
378 interrupt-controller;
379 #interrupt-cells = <2>;
380 gpio-ranges = <&iomuxc 0 64 32>;
381 };
382
383 gpio4: gpio@4004c000 {
384 compatible = "fsl,vf610-gpio";
385 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
271 gpio-controller;
272 #gpio-cells = <2>;
273 interrupt-controller;
274 #interrupt-cells = <2>;
275 gpio-ranges = <&iomuxc 0 64 32>;
276 };
277
278 gpio4: gpio@4004c000 {
279 compatible = "fsl,vf610-gpio";
280 reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
386 interrupts = <0 110 0x04>;
281 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
387 gpio-controller;
388 #gpio-cells = <2>;
389 interrupt-controller;
390 #interrupt-cells = <2>;
391 gpio-ranges = <&iomuxc 0 96 32>;
392 };
393
394 gpio5: gpio@4004d000 {
395 compatible = "fsl,vf610-gpio";
396 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
282 gpio-controller;
283 #gpio-cells = <2>;
284 interrupt-controller;
285 #interrupt-cells = <2>;
286 gpio-ranges = <&iomuxc 0 96 32>;
287 };
288
289 gpio5: gpio@4004d000 {
290 compatible = "fsl,vf610-gpio";
291 reg = <0x4004d000 0x1000 0x400ff100 0x40>;
397 interrupts = <0 111 0x04>;
292 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
398 gpio-controller;
399 #gpio-cells = <2>;
400 interrupt-controller;
401 #interrupt-cells = <2>;
402 gpio-ranges = <&iomuxc 0 128 7>;
403 };
404
405 anatop@40050000 {
406 compatible = "fsl,vf610-anatop";
407 reg = <0x40050000 0x1000>;
408 };
409
410 i2c0: i2c@40066000 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "fsl,vf610-i2c";
414 reg = <0x40066000 0x1000>;
293 gpio-controller;
294 #gpio-cells = <2>;
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 gpio-ranges = <&iomuxc 0 128 7>;
298 };
299
300 anatop@40050000 {
301 compatible = "fsl,vf610-anatop";
302 reg = <0x40050000 0x1000>;
303 };
304
305 i2c0: i2c@40066000 {
306 #address-cells = <1>;
307 #size-cells = <0>;
308 compatible = "fsl,vf610-i2c";
309 reg = <0x40066000 0x1000>;
415 interrupts =<0 71 0x04>;
310 interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
416 clocks = <&clks VF610_CLK_I2C0>;
417 clock-names = "ipg";
311 clocks = <&clks VF610_CLK_I2C0>;
312 clock-names = "ipg";
313 dmas = <&edma0 0 50>,
314 <&edma0 0 51>;
315 dma-names = "rx","tx";
418 status = "disabled";
419 };
420
421 clks: ccm@4006b000 {
422 compatible = "fsl,vf610-ccm";
423 reg = <0x4006b000 0x1000>;
424 #clock-cells = <1>;
425 };
426 };
427
428 aips1: aips-bus@40080000 {
429 compatible = "fsl,aips-bus", "simple-bus";
430 #address-cells = <1>;
431 #size-cells = <1>;
432 reg = <0x40080000 0x80000>;
433 ranges;
434
316 status = "disabled";
317 };
318
319 clks: ccm@4006b000 {
320 compatible = "fsl,vf610-ccm";
321 reg = <0x4006b000 0x1000>;
322 #clock-cells = <1>;
323 };
324 };
325
326 aips1: aips-bus@40080000 {
327 compatible = "fsl,aips-bus", "simple-bus";
328 #address-cells = <1>;
329 #size-cells = <1>;
330 reg = <0x40080000 0x80000>;
331 ranges;
332
333 edma1: dma-controller@40098000 {
334 #dma-cells = <2>;
335 compatible = "fsl,vf610-edma";
336 reg = <0x40098000 0x2000>,
337 <0x400a1000 0x1000>,
338 <0x400a2000 0x1000>;
339 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
340 <0 11 IRQ_TYPE_LEVEL_HIGH>;
341 interrupt-names = "edma-tx", "edma-err";
342 dma-channels = <32>;
343 clock-names = "dmamux0", "dmamux1";
344 clocks = <&clks VF610_CLK_DMAMUX2>,
345 <&clks VF610_CLK_DMAMUX3>;
346 };
347
435 uart4: serial@400a9000 {
436 compatible = "fsl,vf610-lpuart";
437 reg = <0x400a9000 0x1000>;
348 uart4: serial@400a9000 {
349 compatible = "fsl,vf610-lpuart";
350 reg = <0x400a9000 0x1000>;
438 interrupts = <0 65 0x04>;
351 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&clks VF610_CLK_UART4>;
440 clock-names = "ipg";
441 status = "disabled";
442 };
443
444 uart5: serial@400aa000 {
445 compatible = "fsl,vf610-lpuart";
446 reg = <0x400aa000 0x1000>;
352 clocks = <&clks VF610_CLK_UART4>;
353 clock-names = "ipg";
354 status = "disabled";
355 };
356
357 uart5: serial@400aa000 {
358 compatible = "fsl,vf610-lpuart";
359 reg = <0x400aa000 0x1000>;
447 interrupts = <0 66 0x04>;
360 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clks VF610_CLK_UART5>;
449 clock-names = "ipg";
450 status = "disabled";
451 };
452
361 clocks = <&clks VF610_CLK_UART5>;
362 clock-names = "ipg";
363 status = "disabled";
364 };
365
366 adc1: adc@400bb000 {
367 compatible = "fsl,vf610-adc";
368 reg = <0x400bb000 0x1000>;
369 interrupts = <0 54 0x04>;
370 clocks = <&clks VF610_CLK_ADC1>;
371 clock-names = "adc";
372 status = "disabled";
373 };
374
375 esdhc1: esdhc@400b2000 {
376 compatible = "fsl,imx53-esdhc";
377 reg = <0x400b2000 0x1000>;
378 interrupts = <0 28 0x04>;
379 clocks = <&clks VF610_CLK_IPG_BUS>,
380 <&clks VF610_CLK_PLATFORM_BUS>,
381 <&clks VF610_CLK_ESDHC1>;
382 clock-names = "ipg", "ahb", "per";
383 status = "disabled";
384 };
385
386 ftm: ftm@400b8000 {
387 compatible = "fsl,ftm-timer";
388 reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
389 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
390 clock-names = "ftm-evt", "ftm-src",
391 "ftm-evt-counter-en", "ftm-src-counter-en";
392 clocks = <&clks VF610_CLK_FTM2>,
393 <&clks VF610_CLK_FTM3>,
394 <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
395 <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
396 status = "disabled";
397 };
398
453 fec0: ethernet@400d0000 {
454 compatible = "fsl,mvf600-fec";
455 reg = <0x400d0000 0x1000>;
399 fec0: ethernet@400d0000 {
400 compatible = "fsl,mvf600-fec";
401 reg = <0x400d0000 0x1000>;
456 interrupts = <0 78 0x04>;
402 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clks VF610_CLK_ENET0>,
458 <&clks VF610_CLK_ENET0>,
459 <&clks VF610_CLK_ENET>;
460 clock-names = "ipg", "ahb", "ptp";
461 status = "disabled";
462 };
463
464 fec1: ethernet@400d1000 {
465 compatible = "fsl,mvf600-fec";
466 reg = <0x400d1000 0x1000>;
403 clocks = <&clks VF610_CLK_ENET0>,
404 <&clks VF610_CLK_ENET0>,
405 <&clks VF610_CLK_ENET>;
406 clock-names = "ipg", "ahb", "ptp";
407 status = "disabled";
408 };
409
410 fec1: ethernet@400d1000 {
411 compatible = "fsl,mvf600-fec";
412 reg = <0x400d1000 0x1000>;
467 interrupts = <0 79 0x04>;
413 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&clks VF610_CLK_ENET1>,
469 <&clks VF610_CLK_ENET1>,
470 <&clks VF610_CLK_ENET>;
471 clock-names = "ipg", "ahb", "ptp";
472 status = "disabled";
473 };
414 clocks = <&clks VF610_CLK_ENET1>,
415 <&clks VF610_CLK_ENET1>,
416 <&clks VF610_CLK_ENET>;
417 clock-names = "ipg", "ahb", "ptp";
418 status = "disabled";
419 };
420
421 can1: flexcan@400d4000 {
422 compatible = "fsl,vf610-flexcan";
423 reg = <0x400d4000 0x4000>;
424 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&clks VF610_CLK_FLEXCAN1>,
426 <&clks VF610_CLK_FLEXCAN1>;
427 clock-names = "ipg", "per";
428 status = "disabled";
429 };
430
474 };
475 };
476};
431 };
432 };
433};