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sama5d3.dtsi (262573) sama5d3.dtsi (270864)
1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include "skeleton.dtsi"
12#include <dt-bindings/dma/at91.h>
13#include <dt-bindings/pinctrl/at91.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h>
1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11#include "skeleton.dtsi"
12#include <dt-bindings/dma/at91.h>
13#include <dt-bindings/pinctrl/at91.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/gpio/gpio.h>
16#include
16#include <dt-bindings/clock/at91.h>
17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;

--- 29 unchanged lines hidden (view full) ---

54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
61 clocks {
17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;

--- 29 unchanged lines hidden (view full) ---

54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67
68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
73
62 adc_op_clk: adc_op_clk{
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <20000000>;
66 };
67 };
68
69 ahb {

--- 38 unchanged lines hidden (view full) ---

108 clock-names = "spi_clk";
109 status = "disabled";
110 };
111
112 ssc0: ssc@f0008000 {
113 compatible = "atmel,at91sam9g45-ssc";
114 reg = <0xf0008000 0x4000>;
115 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <20000000>;
78 };
79 };
80
81 ahb {

--- 38 unchanged lines hidden (view full) ---

120 clock-names = "spi_clk";
121 status = "disabled";
122 };
123
124 ssc0: ssc@f0008000 {
125 compatible = "atmel,at91sam9g45-ssc";
126 reg = <0xf0008000 0x4000>;
127 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
128 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
129 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
130 dma-names = "tx", "rx";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
118 clocks = <&ssc0_clk>;
119 clock-names = "pclk";
120 status = "disabled";
121 };
122
123 tcb0: timer@f0010000 {

--- 102 unchanged lines hidden (view full) ---

226 clock-names = "spi_clk";
227 status = "disabled";
228 };
229
230 ssc1: ssc@f800c000 {
231 compatible = "atmel,at91sam9g45-ssc";
232 reg = <0xf800c000 0x4000>;
233 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
133 clocks = <&ssc0_clk>;
134 clock-names = "pclk";
135 status = "disabled";
136 };
137
138 tcb0: timer@f0010000 {

--- 102 unchanged lines hidden (view full) ---

241 clock-names = "spi_clk";
242 status = "disabled";
243 };
244
245 ssc1: ssc@f800c000 {
246 compatible = "atmel,at91sam9g45-ssc";
247 reg = <0xf800c000 0x4000>;
248 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
249 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
250 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
251 dma-names = "tx", "rx";
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
236 clocks = <&ssc1_clk>;
237 clock-names = "pclk";
238 status = "disabled";
239 };
240
241 adc0: adc@f8018000 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
254 clocks = <&ssc1_clk>;
255 clock-names = "pclk";
256 status = "disabled";
257 };
258
259 adc0: adc@f8018000 {
242 compatible = "atmel,at91sam9260-adc";
260 #address-cells = <1>;
261 #size-cells = <0>;
262 compatible = "atmel,at91sam9x5-adc";
243 reg = <0xf8018000 0x100>;
244 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
245 pinctrl-names = "default";
246 pinctrl-0 = <
247 &pinctrl_adc0_adtrg
248 &pinctrl_adc0_ad0
249 &pinctrl_adc0_ad1
250 &pinctrl_adc0_ad2

--- 5 unchanged lines hidden (view full) ---

256 &pinctrl_adc0_ad8
257 &pinctrl_adc0_ad9
258 &pinctrl_adc0_ad10
259 &pinctrl_adc0_ad11
260 >;
261 clocks = <&adc_clk>,
262 <&adc_op_clk>;
263 clock-names = "adc_clk", "adc_op_clk";
263 reg = <0xf8018000 0x100>;
264 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
265 pinctrl-names = "default";
266 pinctrl-0 = <
267 &pinctrl_adc0_adtrg
268 &pinctrl_adc0_ad0
269 &pinctrl_adc0_ad1
270 &pinctrl_adc0_ad2

--- 5 unchanged lines hidden (view full) ---

276 &pinctrl_adc0_ad8
277 &pinctrl_adc0_ad9
278 &pinctrl_adc0_ad10
279 &pinctrl_adc0_ad11
280 >;
281 clocks = <&adc_clk>,
282 <&adc_op_clk>;
283 clock-names = "adc_clk", "adc_op_clk";
264 atmel,adc-channel-base = <0x50>;
265 atmel,adc-channels-used = <0xfff>;
284 atmel,adc-channels-used = <0xfff>;
266 atmel,adc-drdy-mask = <0x1000000>;
267 atmel,adc-num-channels = <12>;
268 atmel,adc-startup-time = <40>;
285 atmel,adc-startup-time = <40>;
269 atmel,adc-status-register = <0x30>;
270 atmel,adc-trigger-register = <0xc0>;
271 atmel,adc-use-external;
286 atmel,adc-use-external-triggers;
272 atmel,adc-vref = <3000>;
273 atmel,adc-res = <10 12>;
274 atmel,adc-res-names = "lowres", "highres";
275 status = "disabled";
276
277 trigger@0 {
287 atmel,adc-vref = <3000>;
288 atmel,adc-res = <10 12>;
289 atmel,adc-res-names = "lowres", "highres";
290 status = "disabled";
291
292 trigger@0 {
293 reg = <0>;
278 trigger-name = "external-rising";
279 trigger-value = <0x1>;
280 trigger-external;
281 };
282 trigger@1 {
294 trigger-name = "external-rising";
295 trigger-value = <0x1>;
296 trigger-external;
297 };
298 trigger@1 {
299 reg = <1>;
283 trigger-name = "external-falling";
284 trigger-value = <0x2>;
285 trigger-external;
286 };
287 trigger@2 {
300 trigger-name = "external-falling";
301 trigger-value = <0x2>;
302 trigger-external;
303 };
304 trigger@2 {
305 reg = <2>;
288 trigger-name = "external-any";
289 trigger-value = <0x3>;
290 trigger-external;
291 };
292 trigger@3 {
306 trigger-name = "external-any";
307 trigger-value = <0x3>;
308 trigger-external;
309 };
310 trigger@3 {
311 reg = <3>;
293 trigger-name = "continuous";
294 trigger-value = <0x6>;
295 };
296 };
297
312 trigger-name = "continuous";
313 trigger-value = <0x6>;
314 };
315 };
316
298 tsadcc: tsadcc@f8018000 {
299 compatible = "atmel,at91sam9x5-tsadcc";
300 reg = <0xf8018000 0x4000>;
301 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
302 atmel,tsadcc_clock = <300000>;
303 atmel,filtering_average = <0x03>;
304 atmel,pendet_debounce = <0x08>;
305 atmel,pendet_sensitivity = <0x02>;
306 atmel,ts_sample_hold_time = <0x0a>;
307 status = "disabled";
308 };
309
310 i2c2: i2c@f801c000 {
311 compatible = "atmel,at91sam9x5-i2c";
312 reg = <0xf801c000 0x4000>;
313 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
314 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
315 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
316 dma-names = "tx", "rx";
317 pinctrl-names = "default";

--- 265 unchanged lines hidden (view full) ---

583 nand0 {
584 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
585 atmel,pins =
586 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
587 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
588 };
589 };
590
317 i2c2: i2c@f801c000 {
318 compatible = "atmel,at91sam9x5-i2c";
319 reg = <0xf801c000 0x4000>;
320 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
321 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
322 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
323 dma-names = "tx", "rx";
324 pinctrl-names = "default";

--- 265 unchanged lines hidden (view full) ---

590 nand0 {
591 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
592 atmel,pins =
593 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
594 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
595 };
596 };
597
598 pwm0 {
599 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
600 atmel,pins =
601 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
602 };
603 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
604 atmel,pins =
605 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
606 };
607 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
608 atmel,pins =
609 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
610 };
611 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
612 atmel,pins =
613 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
614 };
615
616 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
617 atmel,pins =
618 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
619 };
620 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
621 atmel,pins =
622 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
623 };
624 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
625 atmel,pins =
626 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
627 };
628 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
629 atmel,pins =
630 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
631 };
632 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
633 atmel,pins =
634 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
635 };
636 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
637 atmel,pins =
638 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
639 };
640
641 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
642 atmel,pins =
643 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
644 };
645 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
646 atmel,pins =
647 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
648 };
649 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
650 atmel,pins =
651 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
652 };
653 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
654 atmel,pins =
655 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
656 };
657
658 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
659 atmel,pins =
660 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
661 };
662 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
663 atmel,pins =
664 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
665 };
666 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
667 atmel,pins =
668 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
669 };
670 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
671 atmel,pins =
672 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
673 };
674 };
675
591 spi0 {
592 pinctrl_spi0: spi0-0 {
593 atmel,pins =
594 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
595 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
596 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
597 };
598 };

--- 156 unchanged lines hidden (view full) ---

755 compatible = "atmel,sama5d3-pmc";
756 reg = <0xfffffc00 0x120>;
757 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
758 interrupt-controller;
759 #address-cells = <1>;
760 #size-cells = <0>;
761 #interrupt-cells = <1>;
762
676 spi0 {
677 pinctrl_spi0: spi0-0 {
678 atmel,pins =
679 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
680 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
681 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
682 };
683 };

--- 156 unchanged lines hidden (view full) ---

840 compatible = "atmel,sama5d3-pmc";
841 reg = <0xfffffc00 0x120>;
842 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
843 interrupt-controller;
844 #address-cells = <1>;
845 #size-cells = <0>;
846 #interrupt-cells = <1>;
847
763 clk32k: slck {
764 compatible = "fixed-clock";
848 main_rc_osc: main_rc_osc {
849 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
765 #clock-cells = <0>;
850 #clock-cells = <0>;
766 clock-frequency = <32768>;
851 interrupt-parent = <&pmc>;
852 interrupts = <AT91_PMC_MOSCRCS>;
853 clock-frequency = <12000000>;
854 clock-accuracy = <50000000>;
767 };
768
855 };
856
769 main: mainck {
770 compatible = "atmel,at91rm9200-clk-main";
857 main_osc: main_osc {
858 compatible = "atmel,at91rm9200-clk-main-osc";
771 #clock-cells = <0>;
772 interrupt-parent = <&pmc>;
773 interrupts = <AT91_PMC_MOSCS>;
859 #clock-cells = <0>;
860 interrupt-parent = <&pmc>;
861 interrupts = <AT91_PMC_MOSCS>;
774 clocks = <&clk32k>;
862 clocks = <&main_xtal>;
775 };
776
863 };
864
865 main: mainck {
866 compatible = "atmel,at91sam9x5-clk-main";
867 #clock-cells = <0>;
868 interrupt-parent = <&pmc>;
869 interrupts = <AT91_PMC_MOSCSELS>;
870 clocks = <&main_rc_osc &main_osc>;
871 };
872
777 plla: pllack {
778 compatible = "atmel,sama5d3-clk-pll";
779 #clock-cells = <0>;
780 interrupt-parent = <&pmc>;
781 interrupts = <AT91_PMC_LOCKA>;
782 clocks = <&main>;
783 reg = <0>;
784 atmel,clk-input-range = <8000000 50000000>;

--- 310 unchanged lines hidden (view full) ---

1095 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1096 atmel,watchdog-type = "hardware";
1097 atmel,reset-type = "all";
1098 atmel,dbg-halt;
1099 atmel,idle-halt;
1100 status = "disabled";
1101 };
1102
873 plla: pllack {
874 compatible = "atmel,sama5d3-clk-pll";
875 #clock-cells = <0>;
876 interrupt-parent = <&pmc>;
877 interrupts = <AT91_PMC_LOCKA>;
878 clocks = <&main>;
879 reg = <0>;
880 atmel,clk-input-range = <8000000 50000000>;

--- 310 unchanged lines hidden (view full) ---

1191 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1192 atmel,watchdog-type = "hardware";
1193 atmel,reset-type = "all";
1194 atmel,dbg-halt;
1195 atmel,idle-halt;
1196 status = "disabled";
1197 };
1198
1199 sckc@fffffe50 {
1200 compatible = "atmel,at91sam9x5-sckc";
1201 reg = <0xfffffe50 0x4>;
1202
1203 slow_rc_osc: slow_rc_osc {
1204 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1205 #clock-cells = <0>;
1206 clock-frequency = <32768>;
1207 clock-accuracy = <50000000>;
1208 atmel,startup-time-usec = <75>;
1209 };
1210
1211 slow_osc: slow_osc {
1212 compatible = "atmel,at91sam9x5-clk-slow-osc";
1213 #clock-cells = <0>;
1214 clocks = <&slow_xtal>;
1215 atmel,startup-time-usec = <1200000>;
1216 };
1217
1218 clk32k: slowck {
1219 compatible = "atmel,at91sam9x5-clk-slow";
1220 #clock-cells = <0>;
1221 clocks = <&slow_rc_osc &slow_osc>;
1222 };
1223 };
1224
1103 rtc@fffffeb0 {
1104 compatible = "atmel,at91rm9200-rtc";
1105 reg = <0xfffffeb0 0x30>;
1106 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1107 };
1108 };
1109
1110 usb0: gadget@00500000 {

--- 140 unchanged lines hidden (view full) ---

1251 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1252 0xffffc070 0x00000490 /* SMC PMECC regs */
1253 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1254 0x00110000 0x00018000 /* ROM code */
1255 >;
1256 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1257 atmel,nand-addr-offset = <21>;
1258 atmel,nand-cmd-offset = <22>;
1225 rtc@fffffeb0 {
1226 compatible = "atmel,at91rm9200-rtc";
1227 reg = <0xfffffeb0 0x30>;
1228 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1229 };
1230 };
1231
1232 usb0: gadget@00500000 {

--- 140 unchanged lines hidden (view full) ---

1373 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1374 0xffffc070 0x00000490 /* SMC PMECC regs */
1375 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1376 0x00110000 0x00018000 /* ROM code */
1377 >;
1378 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1379 atmel,nand-addr-offset = <21>;
1380 atmel,nand-cmd-offset = <22>;
1381 atmel,nand-has-dma;
1259 pinctrl-names = "default";
1260 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1261 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1262 status = "disabled";
1263
1264 nfc@70000000 {
1265 compatible = "atmel,sama5d3-nfc";
1266 #address-cells = <1>;
1267 #size-cells = <1>;
1268 reg = <
1269 0x70000000 0x10000000 /* NFC Command Registers */
1270 0xffffc000 0x00000070 /* NFC HSMC regs */
1271 0x00200000 0x00100000 /* NFC SRAM banks */
1272 >;
1273 };
1274 };
1275 };
1276};
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1384 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1385 status = "disabled";
1386
1387 nfc@70000000 {
1388 compatible = "atmel,sama5d3-nfc";
1389 #address-cells = <1>;
1390 #size-cells = <1>;
1391 reg = <
1392 0x70000000 0x10000000 /* NFC Command Registers */
1393 0xffffc000 0x00000070 /* NFC HSMC regs */
1394 0x00200000 0x00100000 /* NFC SRAM banks */
1395 >;
1396 };
1397 };
1398 };
1399};