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imx6sl.dtsi (262573) imx6sl.dtsi (270864)
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#include <dt-bindings/interrupt-controller/irq.h>
10#include "skeleton.dtsi"
11#include "imx6sl-pinfunc.h"
12#include <dt-bindings/clock/imx6sl-clock.h>
13
14/ {
15 aliases {
11#include "skeleton.dtsi"
12#include "imx6sl-pinfunc.h"
13#include <dt-bindings/clock/imx6sl-clock.h>
14
15/ {
16 aliases {
17 ethernet0 = &fec;
16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 gpio4 = &gpio5;
21 serial0 = &uart1;
22 serial1 = &uart2;
23 serial2 = &uart3;
24 serial3 = &uart4;
25 serial4 = &uart5;
26 spi0 = &ecspi1;
27 spi1 = &ecspi2;
28 spi2 = &ecspi3;
29 spi3 = &ecspi4;
18 gpio0 = &gpio1;
19 gpio1 = &gpio2;
20 gpio2 = &gpio3;
21 gpio3 = &gpio4;
22 gpio4 = &gpio5;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 spi0 = &ecspi1;
29 spi1 = &ecspi2;
30 spi2 = &ecspi3;
31 spi3 = &ecspi4;
32 usbphy0 = &usbphy1;
33 usbphy1 = &usbphy2;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 cpu@0 {
37 compatible = "arm,cortex-a9";
38 device_type = "cpu";
39 reg = <0x0>;
40 next-level-cache = <&L2>;
34 };
35
36 cpus {
37 #address-cells = <1>;
38 #size-cells = <0>;
39
40 cpu@0 {
41 compatible = "arm,cortex-a9";
42 device_type = "cpu";
43 reg = <0x0>;
44 next-level-cache = <&L2>;
45 operating-points = <
46 /* kHz uV */
47 996000 1275000
48 792000 1175000
49 396000 975000
50 >;
51 fsl,soc-operating-points = <
52 /* ARM kHz SOC-PU uV */
53 996000 1225000
54 792000 1175000
55 396000 1175000
56 >;
57 clock-latency = <61036>; /* two CLK32 periods */
58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
61 clock-names = "arm", "pll2_pfd2_396m", "step",
62 "pll1_sw", "pll1_sys";
63 arm-supply = <&reg_arm>;
64 pu-supply = <&reg_pu>;
65 soc-supply = <&reg_soc>;
41 };
42 };
43
44 intc: interrupt-controller@00a01000 {
45 compatible = "arm,cortex-a9-gic";
46 #interrupt-cells = <3>;
66 };
67 };
68
69 intc: interrupt-controller@00a01000 {
70 compatible = "arm,cortex-a9-gic";
71 #interrupt-cells = <3>;
47 #address-cells = <1>;
48 #size-cells = <1>;
49 interrupt-controller;
50 reg = <0x00a01000 0x1000>,
51 <0x00a00100 0x100>;
52 };
53
54 clocks {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 ckil {
59 compatible = "fixed-clock";
72 interrupt-controller;
73 reg = <0x00a01000 0x1000>,
74 <0x00a00100 0x100>;
75 };
76
77 clocks {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 ckil {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
60 clock-frequency = <32768>;
61 };
62
63 osc {
64 compatible = "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 osc {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
65 clock-frequency = <24000000>;
66 };
67 };
68
69 soc {
70 #address-cells = <1>;
71 #size-cells = <1>;
72 compatible = "simple-bus";
73 interrupt-parent = <&intc>;
74 ranges;
75
90 clock-frequency = <24000000>;
91 };
92 };
93
94 soc {
95 #address-cells = <1>;
96 #size-cells = <1>;
97 compatible = "simple-bus";
98 interrupt-parent = <&intc>;
99 ranges;
100
101 ocram: sram@00900000 {
102 compatible = "mmio-sram";
103 reg = <0x00900000 0x20000>;
104 clocks = <&clks IMX6SL_CLK_OCRAM>;
105 };
106
76 L2: l2-cache@00a02000 {
77 compatible = "arm,pl310-cache";
78 reg = <0x00a02000 0x1000>;
107 L2: l2-cache@00a02000 {
108 compatible = "arm,pl310-cache";
109 reg = <0x00a02000 0x1000>;
79 interrupts = <0 92 0x04>;
110 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
80 cache-unified;
81 cache-level = <2>;
82 arm,tag-latency = <4 2 3>;
83 arm,data-latency = <4 2 3>;
84 };
85
86 pmu {
87 compatible = "arm,cortex-a9-pmu";
111 cache-unified;
112 cache-level = <2>;
113 arm,tag-latency = <4 2 3>;
114 arm,data-latency = <4 2 3>;
115 };
116
117 pmu {
118 compatible = "arm,cortex-a9-pmu";
88 interrupts = <0 94 0x04>;
119 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
91 aips1: aips-bus@02000000 {
92 compatible = "fsl,aips-bus", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 reg = <0x02000000 0x100000>;
96 ranges;
97
98 spba: spba-bus@02000000 {
99 compatible = "fsl,spba-bus", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 reg = <0x02000000 0x40000>;
103 ranges;
104
105 spdif: spdif@02004000 {
106 reg = <0x02004000 0x4000>;
120 };
121
122 aips1: aips-bus@02000000 {
123 compatible = "fsl,aips-bus", "simple-bus";
124 #address-cells = <1>;
125 #size-cells = <1>;
126 reg = <0x02000000 0x100000>;
127 ranges;
128
129 spba: spba-bus@02000000 {
130 compatible = "fsl,spba-bus", "simple-bus";
131 #address-cells = <1>;
132 #size-cells = <1>;
133 reg = <0x02000000 0x40000>;
134 ranges;
135
136 spdif: spdif@02004000 {
137 reg = <0x02004000 0x4000>;
107 interrupts = <0 52 0x04>;
138 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
108 };
109
110 ecspi1: ecspi@02008000 {
111 #address-cells = <1>;
112 #size-cells = <0>;
113 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
114 reg = <0x02008000 0x4000>;
139 };
140
141 ecspi1: ecspi@02008000 {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
145 reg = <0x02008000 0x4000>;
115 interrupts = <0 31 0x04>;
146 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&clks IMX6SL_CLK_ECSPI1>,
117 <&clks IMX6SL_CLK_ECSPI1>;
118 clock-names = "ipg", "per";
119 status = "disabled";
120 };
121
122 ecspi2: ecspi@0200c000 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
126 reg = <0x0200c000 0x4000>;
147 clocks = <&clks IMX6SL_CLK_ECSPI1>,
148 <&clks IMX6SL_CLK_ECSPI1>;
149 clock-names = "ipg", "per";
150 status = "disabled";
151 };
152
153 ecspi2: ecspi@0200c000 {
154 #address-cells = <1>;
155 #size-cells = <0>;
156 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
157 reg = <0x0200c000 0x4000>;
127 interrupts = <0 32 0x04>;
158 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
128 clocks = <&clks IMX6SL_CLK_ECSPI2>,
129 <&clks IMX6SL_CLK_ECSPI2>;
130 clock-names = "ipg", "per";
131 status = "disabled";
132 };
133
134 ecspi3: ecspi@02010000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
138 reg = <0x02010000 0x4000>;
159 clocks = <&clks IMX6SL_CLK_ECSPI2>,
160 <&clks IMX6SL_CLK_ECSPI2>;
161 clock-names = "ipg", "per";
162 status = "disabled";
163 };
164
165 ecspi3: ecspi@02010000 {
166 #address-cells = <1>;
167 #size-cells = <0>;
168 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
169 reg = <0x02010000 0x4000>;
139 interrupts = <0 33 0x04>;
170 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
140 clocks = <&clks IMX6SL_CLK_ECSPI3>,
141 <&clks IMX6SL_CLK_ECSPI3>;
142 clock-names = "ipg", "per";
143 status = "disabled";
144 };
145
146 ecspi4: ecspi@02014000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
150 reg = <0x02014000 0x4000>;
171 clocks = <&clks IMX6SL_CLK_ECSPI3>,
172 <&clks IMX6SL_CLK_ECSPI3>;
173 clock-names = "ipg", "per";
174 status = "disabled";
175 };
176
177 ecspi4: ecspi@02014000 {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
181 reg = <0x02014000 0x4000>;
151 interrupts = <0 34 0x04>;
182 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&clks IMX6SL_CLK_ECSPI4>,
153 <&clks IMX6SL_CLK_ECSPI4>;
154 clock-names = "ipg", "per";
155 status = "disabled";
156 };
157
158 uart5: serial@02018000 {
159 compatible = "fsl,imx6sl-uart",
160 "fsl,imx6q-uart", "fsl,imx21-uart";
161 reg = <0x02018000 0x4000>;
183 clocks = <&clks IMX6SL_CLK_ECSPI4>,
184 <&clks IMX6SL_CLK_ECSPI4>;
185 clock-names = "ipg", "per";
186 status = "disabled";
187 };
188
189 uart5: serial@02018000 {
190 compatible = "fsl,imx6sl-uart",
191 "fsl,imx6q-uart", "fsl,imx21-uart";
192 reg = <0x02018000 0x4000>;
162 interrupts = <0 30 0x04>;
193 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&clks IMX6SL_CLK_UART>,
164 <&clks IMX6SL_CLK_UART_SERIAL>;
165 clock-names = "ipg", "per";
166 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
167 dma-names = "rx", "tx";
168 status = "disabled";
169 };
170
171 uart1: serial@02020000 {
172 compatible = "fsl,imx6sl-uart",
173 "fsl,imx6q-uart", "fsl,imx21-uart";
174 reg = <0x02020000 0x4000>;
194 clocks = <&clks IMX6SL_CLK_UART>,
195 <&clks IMX6SL_CLK_UART_SERIAL>;
196 clock-names = "ipg", "per";
197 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
198 dma-names = "rx", "tx";
199 status = "disabled";
200 };
201
202 uart1: serial@02020000 {
203 compatible = "fsl,imx6sl-uart",
204 "fsl,imx6q-uart", "fsl,imx21-uart";
205 reg = <0x02020000 0x4000>;
175 interrupts = <0 26 0x04>;
206 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&clks IMX6SL_CLK_UART>,
177 <&clks IMX6SL_CLK_UART_SERIAL>;
178 clock-names = "ipg", "per";
179 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
180 dma-names = "rx", "tx";
181 status = "disabled";
182 };
183
184 uart2: serial@02024000 {
185 compatible = "fsl,imx6sl-uart",
186 "fsl,imx6q-uart", "fsl,imx21-uart";
187 reg = <0x02024000 0x4000>;
207 clocks = <&clks IMX6SL_CLK_UART>,
208 <&clks IMX6SL_CLK_UART_SERIAL>;
209 clock-names = "ipg", "per";
210 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
211 dma-names = "rx", "tx";
212 status = "disabled";
213 };
214
215 uart2: serial@02024000 {
216 compatible = "fsl,imx6sl-uart",
217 "fsl,imx6q-uart", "fsl,imx21-uart";
218 reg = <0x02024000 0x4000>;
188 interrupts = <0 27 0x04>;
219 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&clks IMX6SL_CLK_UART>,
190 <&clks IMX6SL_CLK_UART_SERIAL>;
191 clock-names = "ipg", "per";
192 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
193 dma-names = "rx", "tx";
194 status = "disabled";
195 };
196
197 ssi1: ssi@02028000 {
220 clocks = <&clks IMX6SL_CLK_UART>,
221 <&clks IMX6SL_CLK_UART_SERIAL>;
222 clock-names = "ipg", "per";
223 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
224 dma-names = "rx", "tx";
225 status = "disabled";
226 };
227
228 ssi1: ssi@02028000 {
198 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
229 compatible = "fsl,imx6sl-ssi",
230 "fsl,imx51-ssi";
199 reg = <0x02028000 0x4000>;
231 reg = <0x02028000 0x4000>;
200 interrupts = <0 46 0x04>;
232 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&clks IMX6SL_CLK_SSI1>;
202 dmas = <&sdma 37 1 0>,
203 <&sdma 38 1 0>;
204 dma-names = "rx", "tx";
205 fsl,fifo-depth = <15>;
206 status = "disabled";
207 };
208
209 ssi2: ssi@0202c000 {
233 clocks = <&clks IMX6SL_CLK_SSI1>;
234 dmas = <&sdma 37 1 0>,
235 <&sdma 38 1 0>;
236 dma-names = "rx", "tx";
237 fsl,fifo-depth = <15>;
238 status = "disabled";
239 };
240
241 ssi2: ssi@0202c000 {
210 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
242 compatible = "fsl,imx6sl-ssi",
243 "fsl,imx51-ssi";
211 reg = <0x0202c000 0x4000>;
244 reg = <0x0202c000 0x4000>;
212 interrupts = <0 47 0x04>;
245 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clks IMX6SL_CLK_SSI2>;
214 dmas = <&sdma 41 1 0>,
215 <&sdma 42 1 0>;
216 dma-names = "rx", "tx";
217 fsl,fifo-depth = <15>;
218 status = "disabled";
219 };
220
221 ssi3: ssi@02030000 {
246 clocks = <&clks IMX6SL_CLK_SSI2>;
247 dmas = <&sdma 41 1 0>,
248 <&sdma 42 1 0>;
249 dma-names = "rx", "tx";
250 fsl,fifo-depth = <15>;
251 status = "disabled";
252 };
253
254 ssi3: ssi@02030000 {
222 compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
255 compatible = "fsl,imx6sl-ssi",
256 "fsl,imx51-ssi";
223 reg = <0x02030000 0x4000>;
257 reg = <0x02030000 0x4000>;
224 interrupts = <0 48 0x04>;
258 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&clks IMX6SL_CLK_SSI3>;
226 dmas = <&sdma 45 1 0>,
227 <&sdma 46 1 0>;
228 dma-names = "rx", "tx";
229 fsl,fifo-depth = <15>;
230 status = "disabled";
231 };
232
233 uart3: serial@02034000 {
234 compatible = "fsl,imx6sl-uart",
235 "fsl,imx6q-uart", "fsl,imx21-uart";
236 reg = <0x02034000 0x4000>;
259 clocks = <&clks IMX6SL_CLK_SSI3>;
260 dmas = <&sdma 45 1 0>,
261 <&sdma 46 1 0>;
262 dma-names = "rx", "tx";
263 fsl,fifo-depth = <15>;
264 status = "disabled";
265 };
266
267 uart3: serial@02034000 {
268 compatible = "fsl,imx6sl-uart",
269 "fsl,imx6q-uart", "fsl,imx21-uart";
270 reg = <0x02034000 0x4000>;
237 interrupts = <0 28 0x04>;
271 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clks IMX6SL_CLK_UART>,
239 <&clks IMX6SL_CLK_UART_SERIAL>;
240 clock-names = "ipg", "per";
241 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
242 dma-names = "rx", "tx";
243 status = "disabled";
244 };
245
246 uart4: serial@02038000 {
247 compatible = "fsl,imx6sl-uart",
248 "fsl,imx6q-uart", "fsl,imx21-uart";
249 reg = <0x02038000 0x4000>;
272 clocks = <&clks IMX6SL_CLK_UART>,
273 <&clks IMX6SL_CLK_UART_SERIAL>;
274 clock-names = "ipg", "per";
275 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
276 dma-names = "rx", "tx";
277 status = "disabled";
278 };
279
280 uart4: serial@02038000 {
281 compatible = "fsl,imx6sl-uart",
282 "fsl,imx6q-uart", "fsl,imx21-uart";
283 reg = <0x02038000 0x4000>;
250 interrupts = <0 29 0x04>;
284 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clks IMX6SL_CLK_UART>,
252 <&clks IMX6SL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per";
254 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
255 dma-names = "rx", "tx";
256 status = "disabled";
257 };
258 };
259
260 pwm1: pwm@02080000 {
261 #pwm-cells = <2>;
262 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
263 reg = <0x02080000 0x4000>;
285 clocks = <&clks IMX6SL_CLK_UART>,
286 <&clks IMX6SL_CLK_UART_SERIAL>;
287 clock-names = "ipg", "per";
288 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
289 dma-names = "rx", "tx";
290 status = "disabled";
291 };
292 };
293
294 pwm1: pwm@02080000 {
295 #pwm-cells = <2>;
296 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
297 reg = <0x02080000 0x4000>;
264 interrupts = <0 83 0x04>;
298 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
265 clocks = <&clks IMX6SL_CLK_PWM1>,
266 <&clks IMX6SL_CLK_PWM1>;
267 clock-names = "ipg", "per";
268 };
269
270 pwm2: pwm@02084000 {
271 #pwm-cells = <2>;
272 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
273 reg = <0x02084000 0x4000>;
299 clocks = <&clks IMX6SL_CLK_PWM1>,
300 <&clks IMX6SL_CLK_PWM1>;
301 clock-names = "ipg", "per";
302 };
303
304 pwm2: pwm@02084000 {
305 #pwm-cells = <2>;
306 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
307 reg = <0x02084000 0x4000>;
274 interrupts = <0 84 0x04>;
308 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&clks IMX6SL_CLK_PWM2>,
276 <&clks IMX6SL_CLK_PWM2>;
277 clock-names = "ipg", "per";
278 };
279
280 pwm3: pwm@02088000 {
281 #pwm-cells = <2>;
282 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
283 reg = <0x02088000 0x4000>;
309 clocks = <&clks IMX6SL_CLK_PWM2>,
310 <&clks IMX6SL_CLK_PWM2>;
311 clock-names = "ipg", "per";
312 };
313
314 pwm3: pwm@02088000 {
315 #pwm-cells = <2>;
316 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
317 reg = <0x02088000 0x4000>;
284 interrupts = <0 85 0x04>;
318 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks IMX6SL_CLK_PWM3>,
286 <&clks IMX6SL_CLK_PWM3>;
287 clock-names = "ipg", "per";
288 };
289
290 pwm4: pwm@0208c000 {
291 #pwm-cells = <2>;
292 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
293 reg = <0x0208c000 0x4000>;
319 clocks = <&clks IMX6SL_CLK_PWM3>,
320 <&clks IMX6SL_CLK_PWM3>;
321 clock-names = "ipg", "per";
322 };
323
324 pwm4: pwm@0208c000 {
325 #pwm-cells = <2>;
326 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
327 reg = <0x0208c000 0x4000>;
294 interrupts = <0 86 0x04>;
328 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clks IMX6SL_CLK_PWM4>,
296 <&clks IMX6SL_CLK_PWM4>;
297 clock-names = "ipg", "per";
298 };
299
300 gpt: gpt@02098000 {
301 compatible = "fsl,imx6sl-gpt";
302 reg = <0x02098000 0x4000>;
329 clocks = <&clks IMX6SL_CLK_PWM4>,
330 <&clks IMX6SL_CLK_PWM4>;
331 clock-names = "ipg", "per";
332 };
333
334 gpt: gpt@02098000 {
335 compatible = "fsl,imx6sl-gpt";
336 reg = <0x02098000 0x4000>;
303 interrupts = <0 55 0x04>;
337 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SL_CLK_GPT>,
305 <&clks IMX6SL_CLK_GPT_SERIAL>;
306 clock-names = "ipg", "per";
307 };
308
309 gpio1: gpio@0209c000 {
310 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
311 reg = <0x0209c000 0x4000>;
338 clocks = <&clks IMX6SL_CLK_GPT>,
339 <&clks IMX6SL_CLK_GPT_SERIAL>;
340 clock-names = "ipg", "per";
341 };
342
343 gpio1: gpio@0209c000 {
344 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
345 reg = <0x0209c000 0x4000>;
312 interrupts = <0 66 0x04 0 67 0x04>;
346 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
347 <0 67 IRQ_TYPE_LEVEL_HIGH>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318
319 gpio2: gpio@020a0000 {
320 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
321 reg = <0x020a0000 0x4000>;
348 gpio-controller;
349 #gpio-cells = <2>;
350 interrupt-controller;
351 #interrupt-cells = <2>;
352 };
353
354 gpio2: gpio@020a0000 {
355 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
356 reg = <0x020a0000 0x4000>;
322 interrupts = <0 68 0x04 0 69 0x04>;
357 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
358 <0 69 IRQ_TYPE_LEVEL_HIGH>;
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <2>;
327 };
328
329 gpio3: gpio@020a4000 {
330 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
331 reg = <0x020a4000 0x4000>;
359 gpio-controller;
360 #gpio-cells = <2>;
361 interrupt-controller;
362 #interrupt-cells = <2>;
363 };
364
365 gpio3: gpio@020a4000 {
366 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
367 reg = <0x020a4000 0x4000>;
332 interrupts = <0 70 0x04 0 71 0x04>;
368 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
369 <0 71 IRQ_TYPE_LEVEL_HIGH>;
333 gpio-controller;
334 #gpio-cells = <2>;
335 interrupt-controller;
336 #interrupt-cells = <2>;
337 };
338
339 gpio4: gpio@020a8000 {
340 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
341 reg = <0x020a8000 0x4000>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
374 };
375
376 gpio4: gpio@020a8000 {
377 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
378 reg = <0x020a8000 0x4000>;
342 interrupts = <0 72 0x04 0 73 0x04>;
379 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
380 <0 73 IRQ_TYPE_LEVEL_HIGH>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 interrupt-controller;
346 #interrupt-cells = <2>;
347 };
348
349 gpio5: gpio@020ac000 {
350 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
351 reg = <0x020ac000 0x4000>;
381 gpio-controller;
382 #gpio-cells = <2>;
383 interrupt-controller;
384 #interrupt-cells = <2>;
385 };
386
387 gpio5: gpio@020ac000 {
388 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
389 reg = <0x020ac000 0x4000>;
352 interrupts = <0 74 0x04 0 75 0x04>;
390 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
391 <0 75 IRQ_TYPE_LEVEL_HIGH>;
353 gpio-controller;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 };
358
359 kpp: kpp@020b8000 {
392 gpio-controller;
393 #gpio-cells = <2>;
394 interrupt-controller;
395 #interrupt-cells = <2>;
396 };
397
398 kpp: kpp@020b8000 {
399 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
360 reg = <0x020b8000 0x4000>;
400 reg = <0x020b8000 0x4000>;
361 interrupts = <0 82 0x04>;
401 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
402 clocks = <&clks IMX6SL_CLK_DUMMY>;
403 status = "disabled";
362 };
363
364 wdog1: wdog@020bc000 {
365 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
366 reg = <0x020bc000 0x4000>;
404 };
405
406 wdog1: wdog@020bc000 {
407 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
408 reg = <0x020bc000 0x4000>;
367 interrupts = <0 80 0x04>;
409 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks IMX6SL_CLK_DUMMY>;
369 };
370
371 wdog2: wdog@020c0000 {
372 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
373 reg = <0x020c0000 0x4000>;
410 clocks = <&clks IMX6SL_CLK_DUMMY>;
411 };
412
413 wdog2: wdog@020c0000 {
414 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
415 reg = <0x020c0000 0x4000>;
374 interrupts = <0 81 0x04>;
416 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&clks IMX6SL_CLK_DUMMY>;
376 status = "disabled";
377 };
378
379 clks: ccm@020c4000 {
380 compatible = "fsl,imx6sl-ccm";
381 reg = <0x020c4000 0x4000>;
417 clocks = <&clks IMX6SL_CLK_DUMMY>;
418 status = "disabled";
419 };
420
421 clks: ccm@020c4000 {
422 compatible = "fsl,imx6sl-ccm";
423 reg = <0x020c4000 0x4000>;
382 interrupts = <0 87 0x04 0 88 0x04>;
424 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
425 <0 88 IRQ_TYPE_LEVEL_HIGH>;
383 #clock-cells = <1>;
384 };
385
386 anatop: anatop@020c8000 {
387 compatible = "fsl,imx6sl-anatop",
388 "fsl,imx6q-anatop",
389 "syscon", "simple-bus";
390 reg = <0x020c8000 0x1000>;
426 #clock-cells = <1>;
427 };
428
429 anatop: anatop@020c8000 {
430 compatible = "fsl,imx6sl-anatop",
431 "fsl,imx6q-anatop",
432 "syscon", "simple-bus";
433 reg = <0x020c8000 0x1000>;
391 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
434 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
435 <0 54 IRQ_TYPE_LEVEL_HIGH>,
436 <0 127 IRQ_TYPE_LEVEL_HIGH>;
392
393 regulator-1p1@110 {
394 compatible = "fsl,anatop-regulator";
395 regulator-name = "vdd1p1";
396 regulator-min-microvolt = <800000>;
397 regulator-max-microvolt = <1375000>;
398 regulator-always-on;
399 anatop-reg-offset = <0x110>;

--- 29 unchanged lines hidden (view full) ---

429 anatop-vol-bit-width = <5>;
430 anatop-min-bit-val = <0>;
431 anatop-min-voltage = <2100000>;
432 anatop-max-voltage = <2850000>;
433 };
434
435 reg_arm: regulator-vddcore@140 {
436 compatible = "fsl,anatop-regulator";
437
438 regulator-1p1@110 {
439 compatible = "fsl,anatop-regulator";
440 regulator-name = "vdd1p1";
441 regulator-min-microvolt = <800000>;
442 regulator-max-microvolt = <1375000>;
443 regulator-always-on;
444 anatop-reg-offset = <0x110>;

--- 29 unchanged lines hidden (view full) ---

474 anatop-vol-bit-width = <5>;
475 anatop-min-bit-val = <0>;
476 anatop-min-voltage = <2100000>;
477 anatop-max-voltage = <2850000>;
478 };
479
480 reg_arm: regulator-vddcore@140 {
481 compatible = "fsl,anatop-regulator";
437 regulator-name = "cpu";
482 regulator-name = "vddarm";
438 regulator-min-microvolt = <725000>;
439 regulator-max-microvolt = <1450000>;
440 regulator-always-on;
441 anatop-reg-offset = <0x140>;
442 anatop-vol-bit-shift = <0>;
443 anatop-vol-bit-width = <5>;
444 anatop-delay-reg-offset = <0x170>;
445 anatop-delay-bit-shift = <24>;

--- 36 unchanged lines hidden (view full) ---

482 anatop-min-voltage = <725000>;
483 anatop-max-voltage = <1450000>;
484 };
485 };
486
487 usbphy1: usbphy@020c9000 {
488 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
489 reg = <0x020c9000 0x1000>;
483 regulator-min-microvolt = <725000>;
484 regulator-max-microvolt = <1450000>;
485 regulator-always-on;
486 anatop-reg-offset = <0x140>;
487 anatop-vol-bit-shift = <0>;
488 anatop-vol-bit-width = <5>;
489 anatop-delay-reg-offset = <0x170>;
490 anatop-delay-bit-shift = <24>;

--- 36 unchanged lines hidden (view full) ---

527 anatop-min-voltage = <725000>;
528 anatop-max-voltage = <1450000>;
529 };
530 };
531
532 usbphy1: usbphy@020c9000 {
533 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
534 reg = <0x020c9000 0x1000>;
490 interrupts = <0 44 0x04>;
535 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clks IMX6SL_CLK_USBPHY1>;
536 clocks = <&clks IMX6SL_CLK_USBPHY1>;
537 fsl,anatop = <&anatop>;
492 };
493
494 usbphy2: usbphy@020ca000 {
495 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
496 reg = <0x020ca000 0x1000>;
538 };
539
540 usbphy2: usbphy@020ca000 {
541 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
542 reg = <0x020ca000 0x1000>;
497 interrupts = <0 45 0x04>;
543 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&clks IMX6SL_CLK_USBPHY2>;
544 clocks = <&clks IMX6SL_CLK_USBPHY2>;
545 fsl,anatop = <&anatop>;
499 };
500
501 snvs@020cc000 {
502 compatible = "fsl,sec-v4.0-mon", "simple-bus";
503 #address-cells = <1>;
504 #size-cells = <1>;
505 ranges = <0 0x020cc000 0x4000>;
506
507 snvs-rtc-lp@34 {
508 compatible = "fsl,sec-v4.0-mon-rtc-lp";
509 reg = <0x34 0x58>;
546 };
547
548 snvs@020cc000 {
549 compatible = "fsl,sec-v4.0-mon", "simple-bus";
550 #address-cells = <1>;
551 #size-cells = <1>;
552 ranges = <0 0x020cc000 0x4000>;
553
554 snvs-rtc-lp@34 {
555 compatible = "fsl,sec-v4.0-mon-rtc-lp";
556 reg = <0x34 0x58>;
510 interrupts = <0 19 0x04 0 20 0x04>;
557 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
558 <0 20 IRQ_TYPE_LEVEL_HIGH>;
511 };
512 };
513
514 epit1: epit@020d0000 {
515 reg = <0x020d0000 0x4000>;
559 };
560 };
561
562 epit1: epit@020d0000 {
563 reg = <0x020d0000 0x4000>;
516 interrupts = <0 56 0x04>;
564 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
517 };
518
519 epit2: epit@020d4000 {
520 reg = <0x020d4000 0x4000>;
565 };
566
567 epit2: epit@020d4000 {
568 reg = <0x020d4000 0x4000>;
521 interrupts = <0 57 0x04>;
569 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
522 };
523
524 src: src@020d8000 {
525 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
526 reg = <0x020d8000 0x4000>;
570 };
571
572 src: src@020d8000 {
573 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
574 reg = <0x020d8000 0x4000>;
527 interrupts = <0 91 0x04 0 96 0x04>;
575 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
576 <0 96 IRQ_TYPE_LEVEL_HIGH>;
528 #reset-cells = <1>;
529 };
530
531 gpc: gpc@020dc000 {
532 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
533 reg = <0x020dc000 0x4000>;
577 #reset-cells = <1>;
578 };
579
580 gpc: gpc@020dc000 {
581 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
582 reg = <0x020dc000 0x4000>;
534 interrupts = <0 89 0x04>;
583 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
535 };
536
537 gpr: iomuxc-gpr@020e0000 {
538 compatible = "fsl,imx6sl-iomuxc-gpr",
539 "fsl,imx6q-iomuxc-gpr", "syscon";
540 reg = <0x020e0000 0x38>;
541 };
542
543 iomuxc: iomuxc@020e0000 {
544 compatible = "fsl,imx6sl-iomuxc";
545 reg = <0x020e0000 0x4000>;
584 };
585
586 gpr: iomuxc-gpr@020e0000 {
587 compatible = "fsl,imx6sl-iomuxc-gpr",
588 "fsl,imx6q-iomuxc-gpr", "syscon";
589 reg = <0x020e0000 0x38>;
590 };
591
592 iomuxc: iomuxc@020e0000 {
593 compatible = "fsl,imx6sl-iomuxc";
594 reg = <0x020e0000 0x4000>;
546
547 ecspi1 {
548 pinctrl_ecspi1_1: ecspi1grp-1 {
549 fsl,pins = <
550 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
551 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
552 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
553 >;
554 };
555 };
556
557 fec {
558 pinctrl_fec_1: fecgrp-1 {
559 fsl,pins = <
560 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
561 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
562 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
563 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
564 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
565 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
566 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
567 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
568 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
569 >;
570 };
571 };
572
573 uart1 {
574 pinctrl_uart1_1: uart1grp-1 {
575 fsl,pins = <
576 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
577 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
578 >;
579 };
580 };
581
582 usbotg1 {
583 pinctrl_usbotg1_1: usbotg1grp-1 {
584 fsl,pins = <
585 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
586 >;
587 };
588
589 pinctrl_usbotg1_2: usbotg1grp-2 {
590 fsl,pins = <
591 MX6SL_PAD_FEC_RXD0__USB_OTG1_ID 0x17059
592 >;
593 };
594
595 pinctrl_usbotg1_3: usbotg1grp-3 {
596 fsl,pins = <
597 MX6SL_PAD_LCD_DAT1__USB_OTG1_ID 0x17059
598 >;
599 };
600
601 pinctrl_usbotg1_4: usbotg1grp-4 {
602 fsl,pins = <
603 MX6SL_PAD_REF_CLK_32K__USB_OTG1_ID 0x17059
604 >;
605 };
606
607 pinctrl_usbotg1_5: usbotg1grp-5 {
608 fsl,pins = <
609 MX6SL_PAD_SD3_DAT0__USB_OTG1_ID 0x17059
610 >;
611 };
612 };
613
614 usbotg2 {
615 pinctrl_usbotg2_1: usbotg2grp-1 {
616 fsl,pins = <
617 MX6SL_PAD_ECSPI1_SCLK__USB_OTG2_OC 0x17059
618 >;
619 };
620
621 pinctrl_usbotg2_2: usbotg2grp-2 {
622 fsl,pins = <
623 MX6SL_PAD_ECSPI2_SCLK__USB_OTG2_OC 0x17059
624 >;
625 };
626
627 pinctrl_usbotg2_3: usbotg2grp-3 {
628 fsl,pins = <
629 MX6SL_PAD_KEY_ROW5__USB_OTG2_OC 0x17059
630 >;
631 };
632
633 pinctrl_usbotg2_4: usbotg2grp-4 {
634 fsl,pins = <
635 MX6SL_PAD_SD3_DAT2__USB_OTG2_OC 0x17059
636 >;
637 };
638 };
639
640 usdhc1 {
641 pinctrl_usdhc1_1: usdhc1grp-1 {
642 fsl,pins = <
643 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
644 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
645 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
646 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
647 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
648 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
649 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
650 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
651 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
652 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
653 >;
654 };
655
656 pinctrl_usdhc1_1_100mhz: usdhc1grp-1-100mhz {
657 fsl,pins = <
658 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
659 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
660 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
661 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
662 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
663 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
664 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
665 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
666 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
667 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
668 >;
669 };
670
671 pinctrl_usdhc1_1_200mhz: usdhc1grp-1-200mhz {
672 fsl,pins = <
673 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
674 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
675 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
676 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
677 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
678 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
679 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
680 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
681 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
682 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
683 >;
684 };
685
686
687 };
688
689 usdhc2 {
690 pinctrl_usdhc2_1: usdhc2grp-1 {
691 fsl,pins = <
692 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
693 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
694 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
695 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
696 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
697 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
698 >;
699 };
700
701 pinctrl_usdhc2_1_100mhz: usdhc2grp-1-100mhz {
702 fsl,pins = <
703 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
704 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
705 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
706 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
707 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
708 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
709 >;
710 };
711
712 pinctrl_usdhc2_1_200mhz: usdhc2grp-1-200mhz {
713 fsl,pins = <
714 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
715 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
716 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
717 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
718 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
719 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
720 >;
721 };
722
723 };
724
725 usdhc3 {
726 pinctrl_usdhc3_1: usdhc3grp-1 {
727 fsl,pins = <
728 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
729 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
730 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
731 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
732 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
733 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
734 >;
735 };
736
737 pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
738 fsl,pins = <
739 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
740 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
741 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
742 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
743 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
744 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
745 >;
746 };
747
748 pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
749 fsl,pins = <
750 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
751 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
752 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
753 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
754 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
755 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
756 >;
757 };
758 };
759 };
760
761 csi: csi@020e4000 {
762 reg = <0x020e4000 0x4000>;
595 };
596
597 csi: csi@020e4000 {
598 reg = <0x020e4000 0x4000>;
763 interrupts = <0 7 0x04>;
599 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
764 };
765
766 spdc: spdc@020e8000 {
767 reg = <0x020e8000 0x4000>;
600 };
601
602 spdc: spdc@020e8000 {
603 reg = <0x020e8000 0x4000>;
768 interrupts = <0 6 0x04>;
604 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
769 };
770
771 sdma: sdma@020ec000 {
605 };
606
607 sdma: sdma@020ec000 {
772 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
608 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
773 reg = <0x020ec000 0x4000>;
609 reg = <0x020ec000 0x4000>;
774 interrupts = <0 2 0x04>;
610 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX6SL_CLK_SDMA>,
776 <&clks IMX6SL_CLK_SDMA>;
777 clock-names = "ipg", "ahb";
778 #dma-cells = <3>;
779 /* imx6sl reuses imx6q sdma firmware */
780 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
781 };
782
783 pxp: pxp@020f0000 {
784 reg = <0x020f0000 0x4000>;
611 clocks = <&clks IMX6SL_CLK_SDMA>,
612 <&clks IMX6SL_CLK_SDMA>;
613 clock-names = "ipg", "ahb";
614 #dma-cells = <3>;
615 /* imx6sl reuses imx6q sdma firmware */
616 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
617 };
618
619 pxp: pxp@020f0000 {
620 reg = <0x020f0000 0x4000>;
785 interrupts = <0 98 0x04>;
621 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
786 };
787
788 epdc: epdc@020f4000 {
789 reg = <0x020f4000 0x4000>;
622 };
623
624 epdc: epdc@020f4000 {
625 reg = <0x020f4000 0x4000>;
790 interrupts = <0 97 0x04>;
626 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
791 };
792
793 lcdif: lcdif@020f8000 {
794 reg = <0x020f8000 0x4000>;
627 };
628
629 lcdif: lcdif@020f8000 {
630 reg = <0x020f8000 0x4000>;
795 interrupts = <0 39 0x04>;
631 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
796 };
797
798 dcp: dcp@020fc000 {
799 reg = <0x020fc000 0x4000>;
632 };
633
634 dcp: dcp@020fc000 {
635 reg = <0x020fc000 0x4000>;
800 interrupts = <0 99 0x04>;
636 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
801 };
802 };
803
804 aips2: aips-bus@02100000 {
805 compatible = "fsl,aips-bus", "simple-bus";
806 #address-cells = <1>;
807 #size-cells = <1>;
808 reg = <0x02100000 0x100000>;
809 ranges;
810
811 usbotg1: usb@02184000 {
812 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
813 reg = <0x02184000 0x200>;
637 };
638 };
639
640 aips2: aips-bus@02100000 {
641 compatible = "fsl,aips-bus", "simple-bus";
642 #address-cells = <1>;
643 #size-cells = <1>;
644 reg = <0x02100000 0x100000>;
645 ranges;
646
647 usbotg1: usb@02184000 {
648 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
649 reg = <0x02184000 0x200>;
814 interrupts = <0 43 0x04>;
650 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&clks IMX6SL_CLK_USBOH3>;
816 fsl,usbphy = <&usbphy1>;
817 fsl,usbmisc = <&usbmisc 0>;
818 status = "disabled";
819 };
820
821 usbotg2: usb@02184200 {
822 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
823 reg = <0x02184200 0x200>;
651 clocks = <&clks IMX6SL_CLK_USBOH3>;
652 fsl,usbphy = <&usbphy1>;
653 fsl,usbmisc = <&usbmisc 0>;
654 status = "disabled";
655 };
656
657 usbotg2: usb@02184200 {
658 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
659 reg = <0x02184200 0x200>;
824 interrupts = <0 42 0x04>;
660 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks IMX6SL_CLK_USBOH3>;
826 fsl,usbphy = <&usbphy2>;
827 fsl,usbmisc = <&usbmisc 1>;
828 status = "disabled";
829 };
830
831 usbh: usb@02184400 {
832 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
833 reg = <0x02184400 0x200>;
661 clocks = <&clks IMX6SL_CLK_USBOH3>;
662 fsl,usbphy = <&usbphy2>;
663 fsl,usbmisc = <&usbmisc 1>;
664 status = "disabled";
665 };
666
667 usbh: usb@02184400 {
668 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
669 reg = <0x02184400 0x200>;
834 interrupts = <0 40 0x04>;
670 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks IMX6SL_CLK_USBOH3>;
836 fsl,usbmisc = <&usbmisc 2>;
837 status = "disabled";
838 };
839
840 usbmisc: usbmisc@02184800 {
841 #index-cells = <1>;
842 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
843 reg = <0x02184800 0x200>;
844 clocks = <&clks IMX6SL_CLK_USBOH3>;
845 };
846
847 fec: ethernet@02188000 {
848 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
849 reg = <0x02188000 0x4000>;
671 clocks = <&clks IMX6SL_CLK_USBOH3>;
672 fsl,usbmisc = <&usbmisc 2>;
673 status = "disabled";
674 };
675
676 usbmisc: usbmisc@02184800 {
677 #index-cells = <1>;
678 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
679 reg = <0x02184800 0x200>;
680 clocks = <&clks IMX6SL_CLK_USBOH3>;
681 };
682
683 fec: ethernet@02188000 {
684 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
685 reg = <0x02188000 0x4000>;
850 interrupts = <0 114 0x04>;
851 clocks = <&clks IMX6SL_CLK_ENET_REF>,
686 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&clks IMX6SL_CLK_ENET>,
852 <&clks IMX6SL_CLK_ENET_REF>;
853 clock-names = "ipg", "ahb";
854 status = "disabled";
855 };
856
857 usdhc1: usdhc@02190000 {
858 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
859 reg = <0x02190000 0x4000>;
688 <&clks IMX6SL_CLK_ENET_REF>;
689 clock-names = "ipg", "ahb";
690 status = "disabled";
691 };
692
693 usdhc1: usdhc@02190000 {
694 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
695 reg = <0x02190000 0x4000>;
860 interrupts = <0 22 0x04>;
696 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SL_CLK_USDHC1>,
862 <&clks IMX6SL_CLK_USDHC1>,
863 <&clks IMX6SL_CLK_USDHC1>;
864 clock-names = "ipg", "ahb", "per";
865 bus-width = <4>;
866 status = "disabled";
867 };
868
869 usdhc2: usdhc@02194000 {
870 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
871 reg = <0x02194000 0x4000>;
697 clocks = <&clks IMX6SL_CLK_USDHC1>,
698 <&clks IMX6SL_CLK_USDHC1>,
699 <&clks IMX6SL_CLK_USDHC1>;
700 clock-names = "ipg", "ahb", "per";
701 bus-width = <4>;
702 status = "disabled";
703 };
704
705 usdhc2: usdhc@02194000 {
706 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
707 reg = <0x02194000 0x4000>;
872 interrupts = <0 23 0x04>;
708 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6SL_CLK_USDHC2>,
874 <&clks IMX6SL_CLK_USDHC2>,
875 <&clks IMX6SL_CLK_USDHC2>;
876 clock-names = "ipg", "ahb", "per";
877 bus-width = <4>;
878 status = "disabled";
879 };
880
881 usdhc3: usdhc@02198000 {
882 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
883 reg = <0x02198000 0x4000>;
709 clocks = <&clks IMX6SL_CLK_USDHC2>,
710 <&clks IMX6SL_CLK_USDHC2>,
711 <&clks IMX6SL_CLK_USDHC2>;
712 clock-names = "ipg", "ahb", "per";
713 bus-width = <4>;
714 status = "disabled";
715 };
716
717 usdhc3: usdhc@02198000 {
718 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
719 reg = <0x02198000 0x4000>;
884 interrupts = <0 24 0x04>;
720 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SL_CLK_USDHC3>,
886 <&clks IMX6SL_CLK_USDHC3>,
887 <&clks IMX6SL_CLK_USDHC3>;
888 clock-names = "ipg", "ahb", "per";
889 bus-width = <4>;
890 status = "disabled";
891 };
892
893 usdhc4: usdhc@0219c000 {
894 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
895 reg = <0x0219c000 0x4000>;
721 clocks = <&clks IMX6SL_CLK_USDHC3>,
722 <&clks IMX6SL_CLK_USDHC3>,
723 <&clks IMX6SL_CLK_USDHC3>;
724 clock-names = "ipg", "ahb", "per";
725 bus-width = <4>;
726 status = "disabled";
727 };
728
729 usdhc4: usdhc@0219c000 {
730 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
731 reg = <0x0219c000 0x4000>;
896 interrupts = <0 25 0x04>;
732 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6SL_CLK_USDHC4>,
898 <&clks IMX6SL_CLK_USDHC4>,
899 <&clks IMX6SL_CLK_USDHC4>;
900 clock-names = "ipg", "ahb", "per";
901 bus-width = <4>;
902 status = "disabled";
903 };
904
905 i2c1: i2c@021a0000 {
906 #address-cells = <1>;
907 #size-cells = <0>;
908 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
909 reg = <0x021a0000 0x4000>;
733 clocks = <&clks IMX6SL_CLK_USDHC4>,
734 <&clks IMX6SL_CLK_USDHC4>,
735 <&clks IMX6SL_CLK_USDHC4>;
736 clock-names = "ipg", "ahb", "per";
737 bus-width = <4>;
738 status = "disabled";
739 };
740
741 i2c1: i2c@021a0000 {
742 #address-cells = <1>;
743 #size-cells = <0>;
744 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
745 reg = <0x021a0000 0x4000>;
910 interrupts = <0 36 0x04>;
746 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6SL_CLK_I2C1>;
912 status = "disabled";
913 };
914
915 i2c2: i2c@021a4000 {
916 #address-cells = <1>;
917 #size-cells = <0>;
918 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
919 reg = <0x021a4000 0x4000>;
747 clocks = <&clks IMX6SL_CLK_I2C1>;
748 status = "disabled";
749 };
750
751 i2c2: i2c@021a4000 {
752 #address-cells = <1>;
753 #size-cells = <0>;
754 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
755 reg = <0x021a4000 0x4000>;
920 interrupts = <0 37 0x04>;
756 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6SL_CLK_I2C2>;
922 status = "disabled";
923 };
924
925 i2c3: i2c@021a8000 {
926 #address-cells = <1>;
927 #size-cells = <0>;
928 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
929 reg = <0x021a8000 0x4000>;
757 clocks = <&clks IMX6SL_CLK_I2C2>;
758 status = "disabled";
759 };
760
761 i2c3: i2c@021a8000 {
762 #address-cells = <1>;
763 #size-cells = <0>;
764 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
765 reg = <0x021a8000 0x4000>;
930 interrupts = <0 38 0x04>;
766 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6SL_CLK_I2C3>;
932 status = "disabled";
933 };
934
935 mmdc: mmdc@021b0000 {
936 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
937 reg = <0x021b0000 0x4000>;
938 };
939
940 rngb: rngb@021b4000 {
941 reg = <0x021b4000 0x4000>;
767 clocks = <&clks IMX6SL_CLK_I2C3>;
768 status = "disabled";
769 };
770
771 mmdc: mmdc@021b0000 {
772 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
773 reg = <0x021b0000 0x4000>;
774 };
775
776 rngb: rngb@021b4000 {
777 reg = <0x021b4000 0x4000>;
942 interrupts = <0 5 0x04>;
778 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
943 };
944
945 weim: weim@021b8000 {
946 reg = <0x021b8000 0x4000>;
779 };
780
781 weim: weim@021b8000 {
782 reg = <0x021b8000 0x4000>;
947 interrupts = <0 14 0x04>;
783 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
948 };
949
950 ocotp: ocotp@021bc000 {
951 compatible = "fsl,imx6sl-ocotp";
952 reg = <0x021bc000 0x4000>;
953 };
954
955 audmux: audmux@021d8000 {
956 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
957 reg = <0x021d8000 0x4000>;
958 status = "disabled";
959 };
960 };
961 };
962};
784 };
785
786 ocotp: ocotp@021bc000 {
787 compatible = "fsl,imx6sl-ocotp";
788 reg = <0x021bc000 0x4000>;
789 };
790
791 audmux: audmux@021d8000 {
792 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
793 reg = <0x021d8000 0x4000>;
794 status = "disabled";
795 };
796 };
797 };
798};