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imx6q.dtsi (262573) imx6q.dtsi (270864)
1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/irq.h>
11#include "imx6q-pinfunc.h"
12#include "imx6qdl.dtsi"
13
14/ {
12#include "imx6q-pinfunc.h"
13#include "imx6qdl.dtsi"
14
15/ {
16 aliases {
17 spi4 = &ecspi5;
18 };
19
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
25 /* kHz uV */
26 1200000 1275000
27 996000 1250000
20 cpus {
21 #address-cells = <1>;
22 #size-cells = <0>;
23
24 cpu@0 {
25 compatible = "arm,cortex-a9";
26 device_type = "cpu";
27 reg = <0>;
28 next-level-cache = <&L2>;
29 operating-points = <
30 /* kHz uV */
31 1200000 1275000
32 996000 1250000
33 852000 1250000
28 792000 1150000
34 792000 1150000
29 396000 950000
35 396000 975000
30 >;
36 >;
37 fsl,soc-operating-points = <
38 /* ARM kHz SOC-PU uV */
39 1200000 1275000
40 996000 1250000
41 852000 1250000
42 792000 1175000
43 396000 1175000
44 >;
31 clock-latency = <61036>; /* two CLK32 periods */
45 clock-latency = <61036>; /* two CLK32 periods */
32 clocks = <&clks 104>, <&clks 6>, <&clks 16>,
33 <&clks 17>, <&clks 170>;
46 clocks = <&clks IMX6QDL_CLK_ARM>,
47 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
48 <&clks IMX6QDL_CLK_STEP>,
49 <&clks IMX6QDL_CLK_PLL1_SW>,
50 <&clks IMX6QDL_CLK_PLL1_SYS>;
34 clock-names = "arm", "pll2_pfd2_396m", "step",
35 "pll1_sw", "pll1_sys";
36 arm-supply = <&reg_arm>;
37 pu-supply = <&reg_pu>;
38 soc-supply = <&reg_soc>;
39 };
40
41 cpu@1 {

--- 17 unchanged lines hidden (view full) ---

59 next-level-cache = <&L2>;
60 };
61 };
62
63 soc {
64 ocram: sram@00900000 {
65 compatible = "mmio-sram";
66 reg = <0x00900000 0x40000>;
51 clock-names = "arm", "pll2_pfd2_396m", "step",
52 "pll1_sw", "pll1_sys";
53 arm-supply = <&reg_arm>;
54 pu-supply = <&reg_pu>;
55 soc-supply = <&reg_soc>;
56 };
57
58 cpu@1 {

--- 17 unchanged lines hidden (view full) ---

76 next-level-cache = <&L2>;
77 };
78 };
79
80 soc {
81 ocram: sram@00900000 {
82 compatible = "mmio-sram";
83 reg = <0x00900000 0x40000>;
67 clocks = <&clks 142>;
84 clocks = <&clks IMX6QDL_CLK_OCRAM>;
68 };
69
70 aips-bus@02000000 { /* AIPS1 */
71 spba-bus@02000000 {
72 ecspi5: ecspi@02018000 {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
76 reg = <0x02018000 0x4000>;
85 };
86
87 aips-bus@02000000 { /* AIPS1 */
88 spba-bus@02000000 {
89 ecspi5: ecspi@02018000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
93 reg = <0x02018000 0x4000>;
77 interrupts = <0 35 0x04>;
78 clocks = <&clks 116>, <&clks 116>;
94 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>;
79 clock-names = "ipg", "per";
80 status = "disabled";
81 };
82 };
83
84 iomuxc: iomuxc@020e0000 {
85 compatible = "fsl,imx6q-iomuxc";
86

--- 33 unchanged lines hidden (view full) ---

120 };
121 };
122 };
123 };
124
125 sata: sata@02200000 {
126 compatible = "fsl,imx6q-ahci";
127 reg = <0x02200000 0x4000>;
97 clock-names = "ipg", "per";
98 status = "disabled";
99 };
100 };
101
102 iomuxc: iomuxc@020e0000 {
103 compatible = "fsl,imx6q-iomuxc";
104

--- 33 unchanged lines hidden (view full) ---

138 };
139 };
140 };
141 };
142
143 sata: sata@02200000 {
144 compatible = "fsl,imx6q-ahci";
145 reg = <0x02200000 0x4000>;
128 interrupts = <0 39 0x04>;
129 clocks = <&clks 154>, <&clks 187>, <&clks 105>;
146 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX6QDL_CLK_SATA>,
148 <&clks IMX6QDL_CLK_SATA_REF_100M>,
149 <&clks IMX6QDL_CLK_AHB>;
130 clock-names = "sata", "sata_ref", "ahb";
131 status = "disabled";
132 };
133
134 ipu2: ipu@02800000 {
150 clock-names = "sata", "sata_ref", "ahb";
151 status = "disabled";
152 };
153
154 ipu2: ipu@02800000 {
135 #crtc-cells = <1>;
155 #address-cells = <1>;
156 #size-cells = <0>;
136 compatible = "fsl,imx6q-ipu";
137 reg = <0x02800000 0x400000>;
157 compatible = "fsl,imx6q-ipu";
158 reg = <0x02800000 0x400000>;
138 interrupts = <0 8 0x4 0 7 0x4>;
139 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
159 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
160 <0 7 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&clks IMX6QDL_CLK_IPU2>,
162 <&clks IMX6QDL_CLK_IPU2_DI0>,
163 <&clks IMX6QDL_CLK_IPU2_DI1>;
140 clock-names = "bus", "di0", "di1";
141 resets = <&src 4>;
164 clock-names = "bus", "di0", "di1";
165 resets = <&src 4>;
166
167 ipu2_csi0: port@0 {
168 reg = <0>;
169 };
170
171 ipu2_csi1: port@1 {
172 reg = <1>;
173 };
174
175 ipu2_di0: port@2 {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 reg = <2>;
179
180 ipu2_di0_disp0: endpoint@0 {
181 };
182
183 ipu2_di0_hdmi: endpoint@1 {
184 remote-endpoint = <&hdmi_mux_2>;
185 };
186
187 ipu2_di0_mipi: endpoint@2 {
188 };
189
190 ipu2_di0_lvds0: endpoint@3 {
191 remote-endpoint = <&lvds0_mux_2>;
192 };
193
194 ipu2_di0_lvds1: endpoint@4 {
195 remote-endpoint = <&lvds1_mux_2>;
196 };
197 };
198
199 ipu2_di1: port@3 {
200 #address-cells = <1>;
201 #size-cells = <0>;
202 reg = <3>;
203
204 ipu2_di1_hdmi: endpoint@1 {
205 remote-endpoint = <&hdmi_mux_3>;
206 };
207
208 ipu2_di1_mipi: endpoint@2 {
209 };
210
211 ipu2_di1_lvds0: endpoint@3 {
212 remote-endpoint = <&lvds0_mux_3>;
213 };
214
215 ipu2_di1_lvds1: endpoint@4 {
216 remote-endpoint = <&lvds1_mux_3>;
217 };
218 };
142 };
143 };
219 };
220 };
221
222 display-subsystem {
223 compatible = "fsl,imx-display-subsystem";
224 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
225 };
144};
145
226};
227
228&hdmi {
229 compatible = "fsl,imx6q-hdmi";
230
231 port@2 {
232 reg = <2>;
233
234 hdmi_mux_2: endpoint {
235 remote-endpoint = <&ipu2_di0_hdmi>;
236 };
237 };
238
239 port@3 {
240 reg = <3>;
241
242 hdmi_mux_3: endpoint {
243 remote-endpoint = <&ipu2_di1_hdmi>;
244 };
245 };
246};
247
146&ldb {
248&ldb {
147 clocks = <&clks 33>, <&clks 34>,
148 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
149 <&clks 135>, <&clks 136>;
249 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
250 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
251 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
252 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
150 clock-names = "di0_pll", "di1_pll",
151 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
152 "di0", "di1";
153
154 lvds-channel@0 {
253 clock-names = "di0_pll", "di1_pll",
254 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
255 "di0", "di1";
256
257 lvds-channel@0 {
155 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
258 port@2 {
259 reg = <2>;
260
261 lvds0_mux_2: endpoint {
262 remote-endpoint = <&ipu2_di0_lvds0>;
263 };
264 };
265
266 port@3 {
267 reg = <3>;
268
269 lvds0_mux_3: endpoint {
270 remote-endpoint = <&ipu2_di1_lvds0>;
271 };
272 };
156 };
157
158 lvds-channel@1 {
273 };
274
275 lvds-channel@1 {
159 crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
276 port@2 {
277 reg = <2>;
278
279 lvds1_mux_2: endpoint {
280 remote-endpoint = <&ipu2_di0_lvds1>;
281 };
282 };
283
284 port@3 {
285 reg = <3>;
286
287 lvds1_mux_3: endpoint {
288 remote-endpoint = <&ipu2_di1_lvds1>;
289 };
290 };
160 };
161};
291 };
292};
293
294&mipi_dsi {
295 port@2 {
296 reg = <2>;
297
298 mipi_mux_2: endpoint {
299 remote-endpoint = <&ipu2_di0_mipi>;
300 };
301 };
302
303 port@3 {
304 reg = <3>;
305
306 mipi_mux_3: endpoint {
307 remote-endpoint = <&ipu2_di1_mipi>;
308 };
309 };
310};