1/* 2 * Copyright 2013 Pavel Machek <pavel@denx.de> 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License V2. 6 */ 7 8/dts-v1/; 9#include "imx6q.dtsi" 10 11/ { 12 model = "MicroSys sbc6x board"; 13 compatible = "microsys,sbc6x", "fsl,imx6q"; 14 15 memory { 16 reg = <0x10000000 0x80000000>; 17 }; 18}; 19
| 1/* 2 * Copyright 2013 Pavel Machek <pavel@denx.de> 3 * 4 * The code contained herein is licensed under the GNU General Public 5 * License V2. 6 */ 7 8/dts-v1/; 9#include "imx6q.dtsi" 10 11/ { 12 model = "MicroSys sbc6x board"; 13 compatible = "microsys,sbc6x", "fsl,imx6q"; 14 15 memory { 16 reg = <0x10000000 0x80000000>; 17 }; 18}; 19
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| 20
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20&fec { 21 pinctrl-names = "default";
| 21&fec { 22 pinctrl-names = "default";
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22 pinctrl-0 = <&pinctrl_enet_1>;
| 23 pinctrl-0 = <&pinctrl_enet>;
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23 phy-mode = "rgmii"; 24 status = "okay"; 25}; 26
| 24 phy-mode = "rgmii"; 25 status = "okay"; 26}; 27
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| 28&iomuxc { 29 imx6q-sbc6x { 30 pinctrl_enet: enetgrp { 31 fsl,pins = < 32 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 33 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 34 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 35 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 36 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 37 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 38 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 39 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 40 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 41 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 42 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 43 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 44 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 45 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 46 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 47 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 48 >; 49 }; 50 51 pinctrl_uart1: uart1grp { 52 fsl,pins = < 53 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 54 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 55 >; 56 }; 57 58 pinctrl_usbotg: usbotggrp { 59 fsl,pins = < 60 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 61 >; 62 }; 63 64 pinctrl_usdhc3: usdhc3grp { 65 fsl,pins = < 66 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 67 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 68 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 69 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 70 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 71 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 72 >; 73 }; 74 }; 75}; 76
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27&uart1 { 28 pinctrl-names = "default";
| 77&uart1 { 78 pinctrl-names = "default";
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29 pinctrl-0 = <&pinctrl_uart1_1>;
| 79 pinctrl-0 = <&pinctrl_uart1>;
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30 status = "okay"; 31}; 32 33&usbotg { 34 pinctrl-names = "default";
| 80 status = "okay"; 81}; 82 83&usbotg { 84 pinctrl-names = "default";
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35 pinctrl-0 = <&pinctrl_usbotg_1>;
| 85 pinctrl-0 = <&pinctrl_usbotg>;
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36 disable-over-current; 37 status = "okay"; 38}; 39 40&usdhc3 { 41 pinctrl-names = "default";
| 86 disable-over-current; 87 status = "okay"; 88}; 89 90&usdhc3 { 91 pinctrl-names = "default";
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42 pinctrl-0 = <&pinctrl_usdhc3_2>;
| 92 pinctrl-0 = <&pinctrl_usdhc3>;
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43 status = "okay"; 44};
| 93 status = "okay"; 94};
|