1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
| 1
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 */
10
|
| 11#include <dt-bindings/interrupt-controller/irq.h>
|
11#include "imx6dl-pinfunc.h"
12#include "imx6qdl.dtsi"
13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu@0 {
20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
| 12#include "imx6dl-pinfunc.h"
13#include "imx6qdl.dtsi"
14
15/ {
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "arm,cortex-a9";
22 device_type = "cpu";
23 reg = <0>;
24 next-level-cache = <&L2>;
|
| 25 operating-points = <
26 /* kHz uV */
27 996000 1275000
28 792000 1175000
29 396000 1075000
30 >;
31 fsl,soc-operating-points = <
32 /* ARM kHz SOC-PU uV */
33 996000 1175000
34 792000 1175000
35 396000 1175000
36 >;
37 clock-latency = <61036>; /* two CLK32 periods */
38 clocks = <&clks IMX6QDL_CLK_ARM>,
39 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
40 <&clks IMX6QDL_CLK_STEP>,
41 <&clks IMX6QDL_CLK_PLL1_SW>,
42 <&clks IMX6QDL_CLK_PLL1_SYS>;
43 clock-names = "arm", "pll2_pfd2_396m", "step",
44 "pll1_sw", "pll1_sys";
45 arm-supply = <®_arm>;
46 pu-supply = <®_pu>;
47 soc-supply = <®_soc>;
|
24 };
25
26 cpu@1 {
27 compatible = "arm,cortex-a9";
28 device_type = "cpu";
29 reg = <1>;
30 next-level-cache = <&L2>;
31 };
32 };
33
34 soc {
35 ocram: sram@00900000 {
36 compatible = "mmio-sram";
37 reg = <0x00900000 0x20000>;
| 48 };
49
50 cpu@1 {
51 compatible = "arm,cortex-a9";
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L2>;
55 };
56 };
57
58 soc {
59 ocram: sram@00900000 {
60 compatible = "mmio-sram";
61 reg = <0x00900000 0x20000>;
|
38 clocks = <&clks 142>;
| 62 clocks = <&clks IMX6QDL_CLK_OCRAM>;
|
39 };
40
41 aips1: aips-bus@02000000 {
42 iomuxc: iomuxc@020e0000 {
43 compatible = "fsl,imx6dl-iomuxc";
44 };
45
46 pxp: pxp@020f0000 {
47 reg = <0x020f0000 0x4000>;
| 63 };
64
65 aips1: aips-bus@02000000 {
66 iomuxc: iomuxc@020e0000 {
67 compatible = "fsl,imx6dl-iomuxc";
68 };
69
70 pxp: pxp@020f0000 {
71 reg = <0x020f0000 0x4000>;
|
48 interrupts = <0 98 0x04>;
| 72 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
|
49 };
50
51 epdc: epdc@020f4000 {
52 reg = <0x020f4000 0x4000>;
| 73 };
74
75 epdc: epdc@020f4000 {
76 reg = <0x020f4000 0x4000>;
|
53 interrupts = <0 97 0x04>;
| 77 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
|
54 };
55
56 lcdif: lcdif@020f8000 {
57 reg = <0x020f8000 0x4000>;
| 78 };
79
80 lcdif: lcdif@020f8000 {
81 reg = <0x020f8000 0x4000>;
|
58 interrupts = <0 39 0x04>;
| 82 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
|
59 };
60 };
61
62 aips2: aips-bus@02100000 {
63 i2c4: i2c@021f8000 {
64 #address-cells = <1>;
65 #size-cells = <0>;
| 83 };
84 };
85
86 aips2: aips-bus@02100000 {
87 i2c4: i2c@021f8000 {
88 #address-cells = <1>;
89 #size-cells = <0>;
|
66 compatible = "fsl,imx1-i2c";
| 90 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
|
67 reg = <0x021f8000 0x4000>;
| 91 reg = <0x021f8000 0x4000>;
|
68 interrupts = <0 35 0x04>;
| 92 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&clks IMX6DL_CLK_I2C4>;
|
69 status = "disabled";
70 };
71 };
72 };
| 94 status = "disabled";
95 };
96 };
97 };
|
| 98
99 display-subsystem {
100 compatible = "fsl,imx-display-subsystem";
101 ports = <&ipu1_di0>, <&ipu1_di1>;
102 };
|
73};
74
| 103};
104
|
| 105&hdmi {
106 compatible = "fsl,imx6dl-hdmi";
107};
108
|
75&ldb {
| 109&ldb {
|
76 clocks = <&clks 33>, <&clks 34>,
77 <&clks 39>, <&clks 40>,
78 <&clks 135>, <&clks 136>;
| 110 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
111 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
112 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
|
79 clock-names = "di0_pll", "di1_pll",
80 "di0_sel", "di1_sel",
81 "di0", "di1";
| 113 clock-names = "di0_pll", "di1_pll",
114 "di0_sel", "di1_sel",
115 "di0", "di1";
|
82
83 lvds-channel@0 {
84 crtcs = <&ipu1 0>, <&ipu1 1>;
85 };
86
87 lvds-channel@1 {
88 crtcs = <&ipu1 0>, <&ipu1 1>;
89 };
| |
90};
| 116};
|