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at91sam9g45.dtsi (262573) at91sam9g45.dtsi (270864)
1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/dma/at91.h>
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/dma/at91.h>
14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
17
18/ {
19 model = "Atmel AT91SAM9G45 family SoC";
20 compatible = "atmel,at91sam9g45";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
35 tcb1 = &tcb1;
36 i2c0 = &i2c0;
37 i2c1 = &i2c1;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
40 pwm0 = &pwm0;
41 };
42 cpus {
43 #address-cells = <0>;
44 #size-cells = <0>;
45
46 cpu {
47 compatible = "arm,arm926ej-s";
48 device_type = "cpu";
49 };
50 };
51
52 memory {
53 reg = <0x70000000 0x10000000>;
54 };
55
18
19/ {
20 model = "Atmel AT91SAM9G45 family SoC";
21 compatible = "atmel,at91sam9g45";
22 interrupt-parent = <&aic>;
23
24 aliases {
25 serial0 = &dbgu;
26 serial1 = &usart0;
27 serial2 = &usart1;
28 serial3 = &usart2;
29 serial4 = &usart3;
30 gpio0 = &pioA;
31 gpio1 = &pioB;
32 gpio2 = &pioC;
33 gpio3 = &pioD;
34 gpio4 = &pioE;
35 tcb0 = &tcb0;
36 tcb1 = &tcb1;
37 i2c0 = &i2c0;
38 i2c1 = &i2c1;
39 ssc0 = &ssc0;
40 ssc1 = &ssc1;
41 pwm0 = &pwm0;
42 };
43 cpus {
44 #address-cells = <0>;
45 #size-cells = <0>;
46
47 cpu {
48 compatible = "arm,arm926ej-s";
49 device_type = "cpu";
50 };
51 };
52
53 memory {
54 reg = <0x70000000 0x10000000>;
55 };
56
57 clocks {
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 main_xtal: main_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 adc_op_clk: adc_op_clk{
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <300000>;
74 };
75 };
76
56 ahb {
57 compatible = "simple-bus";
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61
62 apb {
63 compatible = "simple-bus";
64 #address-cells = <1>;
65 #size-cells = <1>;
66 ranges;
67
68 aic: interrupt-controller@fffff000 {
69 #interrupt-cells = <3>;
70 compatible = "atmel,at91rm9200-aic";
71 interrupt-controller;
72 reg = <0xfffff000 0x200>;
73 atmel,external-irqs = <31>;
74 };
75
76 ramc0: ramc@ffffe400 {
77 compatible = "atmel,at91sam9g45-ddramc";
78 reg = <0xffffe400 0x200
79 0xffffe600 0x200>;
77 ahb {
78 compatible = "simple-bus";
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
82
83 apb {
84 compatible = "simple-bus";
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges;
88
89 aic: interrupt-controller@fffff000 {
90 #interrupt-cells = <3>;
91 compatible = "atmel,at91rm9200-aic";
92 interrupt-controller;
93 reg = <0xfffff000 0x200>;
94 atmel,external-irqs = <31>;
95 };
96
97 ramc0: ramc@ffffe400 {
98 compatible = "atmel,at91sam9g45-ddramc";
99 reg = <0xffffe400 0x200
100 0xffffe600 0x200>;
101 clocks = <&ddrck>;
102 clock-names = "ddrck";
80 };
81
82 pmc: pmc@fffffc00 {
103 };
104
105 pmc: pmc@fffffc00 {
83 compatible = "atmel,at91rm9200-pmc";
106 compatible = "atmel,at91sam9g45-pmc";
84 reg = <0xfffffc00 0x100>;
107 reg = <0xfffffc00 0x100>;
108 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
109 interrupt-controller;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 #interrupt-cells = <1>;
113
114 main_osc: main_osc {
115 compatible = "atmel,at91rm9200-clk-main-osc";
116 #clock-cells = <0>;
117 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
118 clocks = <&main_xtal>;
119 };
120
121 main: mainck {
122 compatible = "atmel,at91rm9200-clk-main";
123 #clock-cells = <0>;
124 clocks = <&main_osc>;
125 };
126
127 plla: pllack {
128 compatible = "atmel,at91rm9200-clk-pll";
129 #clock-cells = <0>;
130 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
131 clocks = <&main>;
132 reg = <0>;
133 atmel,clk-input-range = <2000000 32000000>;
134 #atmel,pll-clk-output-range-cells = <4>;
135 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
136 695000000 750000000 1 0
137 645000000 700000000 2 0
138 595000000 650000000 3 0
139 545000000 600000000 0 1
140 495000000 555000000 1 1
141 445000000 500000000 2 1
142 400000000 450000000 3 1>;
143 };
144
145 plladiv: plladivck {
146 compatible = "atmel,at91sam9x5-clk-plldiv";
147 #clock-cells = <0>;
148 clocks = <&plla>;
149 };
150
151 utmi: utmick {
152 compatible = "atmel,at91sam9x5-clk-utmi";
153 #clock-cells = <0>;
154 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
155 clocks = <&main>;
156 };
157
158 mck: masterck {
159 compatible = "atmel,at91rm9200-clk-master";
160 #clock-cells = <0>;
161 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
162 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
163 atmel,clk-output-range = <0 133333333>;
164 atmel,clk-divisors = <1 2 4 3>;
165 };
166
167 usb: usbck {
168 compatible = "atmel,at91sam9x5-clk-usb";
169 #clock-cells = <0>;
170 clocks = <&plladiv>, <&utmi>;
171 };
172
173 prog: progck {
174 compatible = "atmel,at91sam9g45-clk-programmable";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 interrupt-parent = <&pmc>;
178 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
179
180 prog0: prog0 {
181 #clock-cells = <0>;
182 reg = <0>;
183 interrupts = <AT91_PMC_PCKRDY(0)>;
184 };
185
186 prog1: prog1 {
187 #clock-cells = <0>;
188 reg = <1>;
189 interrupts = <AT91_PMC_PCKRDY(1)>;
190 };
191 };
192
193 systemck {
194 compatible = "atmel,at91rm9200-clk-system";
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 ddrck: ddrck {
199 #clock-cells = <0>;
200 reg = <2>;
201 clocks = <&mck>;
202 };
203
204 uhpck: uhpck {
205 #clock-cells = <0>;
206 reg = <6>;
207 clocks = <&usb>;
208 };
209
210 pck0: pck0 {
211 #clock-cells = <0>;
212 reg = <8>;
213 clocks = <&prog0>;
214 };
215
216 pck1: pck1 {
217 #clock-cells = <0>;
218 reg = <9>;
219 clocks = <&prog1>;
220 };
221 };
222
223 periphck {
224 compatible = "atmel,at91rm9200-clk-peripheral";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 clocks = <&mck>;
228
229 pioA_clk: pioA_clk {
230 #clock-cells = <0>;
231 reg = <2>;
232 };
233
234 pioB_clk: pioB_clk {
235 #clock-cells = <0>;
236 reg = <3>;
237 };
238
239 pioC_clk: pioC_clk {
240 #clock-cells = <0>;
241 reg = <4>;
242 };
243
244 pioDE_clk: pioDE_clk {
245 #clock-cells = <0>;
246 reg = <5>;
247 };
248
249 trng_clk: trng_clk {
250 #clock-cells = <0>;
251 reg = <6>;
252 };
253
254 usart0_clk: usart0_clk {
255 #clock-cells = <0>;
256 reg = <7>;
257 };
258
259 usart1_clk: usart1_clk {
260 #clock-cells = <0>;
261 reg = <8>;
262 };
263
264 usart2_clk: usart2_clk {
265 #clock-cells = <0>;
266 reg = <9>;
267 };
268
269 usart3_clk: usart3_clk {
270 #clock-cells = <0>;
271 reg = <10>;
272 };
273
274 mci0_clk: mci0_clk {
275 #clock-cells = <0>;
276 reg = <11>;
277 };
278
279 twi0_clk: twi0_clk {
280 #clock-cells = <0>;
281 reg = <12>;
282 };
283
284 twi1_clk: twi1_clk {
285 #clock-cells = <0>;
286 reg = <13>;
287 };
288
289 spi0_clk: spi0_clk {
290 #clock-cells = <0>;
291 reg = <14>;
292 };
293
294 spi1_clk: spi1_clk {
295 #clock-cells = <0>;
296 reg = <15>;
297 };
298
299 ssc0_clk: ssc0_clk {
300 #clock-cells = <0>;
301 reg = <16>;
302 };
303
304 ssc1_clk: ssc1_clk {
305 #clock-cells = <0>;
306 reg = <17>;
307 };
308
309 tcb0_clk: tcb0_clk {
310 #clock-cells = <0>;
311 reg = <18>;
312 };
313
314 pwm_clk: pwm_clk {
315 #clock-cells = <0>;
316 reg = <19>;
317 };
318
319 adc_clk: adc_clk {
320 #clock-cells = <0>;
321 reg = <20>;
322 };
323
324 dma0_clk: dma0_clk {
325 #clock-cells = <0>;
326 reg = <21>;
327 };
328
329 uhphs_clk: uhphs_clk {
330 #clock-cells = <0>;
331 reg = <22>;
332 };
333
334 lcd_clk: lcd_clk {
335 #clock-cells = <0>;
336 reg = <23>;
337 };
338
339 ac97_clk: ac97_clk {
340 #clock-cells = <0>;
341 reg = <24>;
342 };
343
344 macb0_clk: macb0_clk {
345 #clock-cells = <0>;
346 reg = <25>;
347 };
348
349 isi_clk: isi_clk {
350 #clock-cells = <0>;
351 reg = <26>;
352 };
353
354 udphs_clk: udphs_clk {
355 #clock-cells = <0>;
356 reg = <27>;
357 };
358
359 aestdessha_clk: aestdessha_clk {
360 #clock-cells = <0>;
361 reg = <28>;
362 };
363
364 mci1_clk: mci1_clk {
365 #clock-cells = <0>;
366 reg = <29>;
367 };
368
369 vdec_clk: vdec_clk {
370 #clock-cells = <0>;
371 reg = <30>;
372 };
373 };
85 };
86
87 rstc@fffffd00 {
88 compatible = "atmel,at91sam9g45-rstc";
89 reg = <0xfffffd00 0x10>;
90 };
91
92 pit: timer@fffffd30 {
93 compatible = "atmel,at91sam9260-pit";
94 reg = <0xfffffd30 0xf>;
95 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
374 };
375
376 rstc@fffffd00 {
377 compatible = "atmel,at91sam9g45-rstc";
378 reg = <0xfffffd00 0x10>;
379 };
380
381 pit: timer@fffffd30 {
382 compatible = "atmel,at91sam9260-pit";
383 reg = <0xfffffd30 0xf>;
384 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
385 clocks = <&mck>;
96 };
97
98
99 shdwc@fffffd10 {
100 compatible = "atmel,at91sam9rl-shdwc";
101 reg = <0xfffffd10 0x10>;
102 };
103
104 tcb0: timer@fff7c000 {
105 compatible = "atmel,at91rm9200-tcb";
106 reg = <0xfff7c000 0x100>;
107 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
386 };
387
388
389 shdwc@fffffd10 {
390 compatible = "atmel,at91sam9rl-shdwc";
391 reg = <0xfffffd10 0x10>;
392 };
393
394 tcb0: timer@fff7c000 {
395 compatible = "atmel,at91rm9200-tcb";
396 reg = <0xfff7c000 0x100>;
397 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
398 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
399 clock-names = "t0_clk", "t1_clk", "t2_clk";
108 };
109
110 tcb1: timer@fffd4000 {
111 compatible = "atmel,at91rm9200-tcb";
112 reg = <0xfffd4000 0x100>;
113 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
400 };
401
402 tcb1: timer@fffd4000 {
403 compatible = "atmel,at91rm9200-tcb";
404 reg = <0xfffd4000 0x100>;
405 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
406 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
407 clock-names = "t0_clk", "t1_clk", "t2_clk";
114 };
115
116 dma: dma-controller@ffffec00 {
117 compatible = "atmel,at91sam9g45-dma";
118 reg = <0xffffec00 0x200>;
119 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
120 #dma-cells = <2>;
408 };
409
410 dma: dma-controller@ffffec00 {
411 compatible = "atmel,at91sam9g45-dma";
412 reg = <0xffffec00 0x200>;
413 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
414 #dma-cells = <2>;
415 clocks = <&dma0_clk>;
416 clock-names = "dma_clk";
121 };
122
123 pinctrl@fffff200 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
127 ranges = <0xfffff200 0xfffff200 0xa00>;
128
129 atmel,mux-mask = <
130 /* A B */
131 0xffffffff 0xffc003ff /* pioA */
132 0xffffffff 0x800f8f00 /* pioB */
133 0xffffffff 0x00000e00 /* pioC */
134 0xffffffff 0xff0c1381 /* pioD */
135 0xffffffff 0x81ffff81 /* pioE */
136 >;
137
138 /* shared pinctrl settings */
417 };
418
419 pinctrl@fffff200 {
420 #address-cells = <1>;
421 #size-cells = <1>;
422 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
423 ranges = <0xfffff200 0xfffff200 0xa00>;
424
425 atmel,mux-mask = <
426 /* A B */
427 0xffffffff 0xffc003ff /* pioA */
428 0xffffffff 0x800f8f00 /* pioB */
429 0xffffffff 0x00000e00 /* pioC */
430 0xffffffff 0xff0c1381 /* pioD */
431 0xffffffff 0x81ffff81 /* pioE */
432 >;
433
434 /* shared pinctrl settings */
435 adc0 {
436 pinctrl_adc0_adtrg: adc0_adtrg {
437 atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
438 };
439 pinctrl_adc0_ad0: adc0_ad0 {
440 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
441 };
442 pinctrl_adc0_ad1: adc0_ad1 {
443 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
444 };
445 pinctrl_adc0_ad2: adc0_ad2 {
446 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
447 };
448 pinctrl_adc0_ad3: adc0_ad3 {
449 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
450 };
451 pinctrl_adc0_ad4: adc0_ad4 {
452 atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
453 };
454 pinctrl_adc0_ad5: adc0_ad5 {
455 atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
456 };
457 pinctrl_adc0_ad6: adc0_ad6 {
458 atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
459 };
460 pinctrl_adc0_ad7: adc0_ad7 {
461 atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
462 };
463 };
464
139 dbgu {
140 pinctrl_dbgu: dbgu-0 {
141 atmel,pins =
142 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
143 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
144 };
145 };
146
147 i2c0 {
148 pinctrl_i2c0: i2c0-0 {
149 atmel,pins =
150 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
151 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
152 };
153 };
154
155 i2c1 {
156 pinctrl_i2c1: i2c1-0 {
157 atmel,pins =
158 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
159 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
160 };
161 };
162
163 usart0 {
164 pinctrl_usart0: usart0-0 {
165 atmel,pins =
166 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
167 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
168 };
169
170 pinctrl_usart0_rts: usart0_rts-0 {
171 atmel,pins =
172 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
173 };
174
175 pinctrl_usart0_cts: usart0_cts-0 {
176 atmel,pins =
177 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
178 };
179 };
180
181 uart1 {
182 pinctrl_usart1: usart1-0 {
183 atmel,pins =
184 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
185 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
186 };
187
188 pinctrl_usart1_rts: usart1_rts-0 {
189 atmel,pins =
190 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
191 };
192
193 pinctrl_usart1_cts: usart1_cts-0 {
194 atmel,pins =
195 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
196 };
197 };
198
199 usart2 {
200 pinctrl_usart2: usart2-0 {
201 atmel,pins =
202 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
203 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
204 };
205
206 pinctrl_usart2_rts: usart2_rts-0 {
207 atmel,pins =
208 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
209 };
210
211 pinctrl_usart2_cts: usart2_cts-0 {
212 atmel,pins =
213 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
214 };
215 };
216
217 usart3 {
218 pinctrl_usart3: usart3-0 {
219 atmel,pins =
220 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
221 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
222 };
223
224 pinctrl_usart3_rts: usart3_rts-0 {
225 atmel,pins =
226 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
227 };
228
229 pinctrl_usart3_cts: usart3_cts-0 {
230 atmel,pins =
231 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
232 };
233 };
234
235 nand {
236 pinctrl_nand: nand-0 {
237 atmel,pins =
238 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
239 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
240 };
241 };
242
243 macb {
244 pinctrl_macb_rmii: macb_rmii-0 {
245 atmel,pins =
246 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
247 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
248 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
249 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
250 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
251 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
252 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
253 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
254 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
255 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
256 };
257
258 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
259 atmel,pins =
260 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
261 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
262 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
263 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
264 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
265 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
266 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
267 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
268 };
269 };
270
271 mmc0 {
272 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
273 atmel,pins =
274 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
275 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
276 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
277 };
278
279 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
280 atmel,pins =
281 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
282 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
283 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
284 };
285
286 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
287 atmel,pins =
288 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
289 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
290 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
291 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
292 };
293 };
294
295 mmc1 {
296 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
297 atmel,pins =
298 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
299 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
300 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
301 };
302
303 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
304 atmel,pins =
305 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
306 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
307 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
308 };
309
310 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
311 atmel,pins =
312 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
313 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
314 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
315 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
316 };
317 };
318
319 ssc0 {
320 pinctrl_ssc0_tx: ssc0_tx-0 {
321 atmel,pins =
322 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
323 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
324 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
325 };
326
327 pinctrl_ssc0_rx: ssc0_rx-0 {
328 atmel,pins =
329 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
330 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
331 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
332 };
333 };
334
335 ssc1 {
336 pinctrl_ssc1_tx: ssc1_tx-0 {
337 atmel,pins =
338 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
339 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
340 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
341 };
342
343 pinctrl_ssc1_rx: ssc1_rx-0 {
344 atmel,pins =
345 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
346 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
347 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
348 };
349 };
350
351 spi0 {
352 pinctrl_spi0: spi0-0 {
353 atmel,pins =
354 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
355 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
356 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
357 };
358 };
359
360 spi1 {
361 pinctrl_spi1: spi1-0 {
362 atmel,pins =
363 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
364 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
365 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
366 };
367 };
368
369 tcb0 {
370 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
371 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
372 };
373
374 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
375 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
376 };
377
378 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
379 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
380 };
381
382 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
383 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
384 };
385
386 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
387 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
388 };
389
390 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
391 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
392 };
393
394 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
395 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
396 };
397
398 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
399 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
400 };
401
402 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
403 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
404 };
405 };
406
407 tcb1 {
408 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
409 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
410 };
411
412 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
413 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
414 };
415
416 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
417 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
418 };
419
420 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
421 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
422 };
423
424 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
425 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
426 };
427
428 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
429 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
430 };
431
432 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
433 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
434 };
435
436 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
437 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
438 };
439
440 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
441 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
442 };
443 };
444
445 fb {
446 pinctrl_fb: fb-0 {
447 atmel,pins =
448 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
449 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
450 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
451 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
452 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
453 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
454 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
455 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
456 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
457 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
458 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
459 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
460 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
461 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
462 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
463 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
464 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
465 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
466 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
467 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
468 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
469 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
470 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
471 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
472 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
473 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
474 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
475 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
476 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
477 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
478 };
479 };
480
481 pioA: gpio@fffff200 {
482 compatible = "atmel,at91rm9200-gpio";
483 reg = <0xfffff200 0x200>;
484 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
485 #gpio-cells = <2>;
486 gpio-controller;
487 interrupt-controller;
488 #interrupt-cells = <2>;
465 dbgu {
466 pinctrl_dbgu: dbgu-0 {
467 atmel,pins =
468 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */
469 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB13 periph A */
470 };
471 };
472
473 i2c0 {
474 pinctrl_i2c0: i2c0-0 {
475 atmel,pins =
476 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */
477 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */
478 };
479 };
480
481 i2c1 {
482 pinctrl_i2c1: i2c1-0 {
483 atmel,pins =
484 <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */
485 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */
486 };
487 };
488
489 usart0 {
490 pinctrl_usart0: usart0-0 {
491 atmel,pins =
492 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A with pullup */
493 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */
494 };
495
496 pinctrl_usart0_rts: usart0_rts-0 {
497 atmel,pins =
498 <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB17 periph B */
499 };
500
501 pinctrl_usart0_cts: usart0_cts-0 {
502 atmel,pins =
503 <AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB15 periph B */
504 };
505 };
506
507 uart1 {
508 pinctrl_usart1: usart1-0 {
509 atmel,pins =
510 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB4 periph A with pullup */
511 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */
512 };
513
514 pinctrl_usart1_rts: usart1_rts-0 {
515 atmel,pins =
516 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A */
517 };
518
519 pinctrl_usart1_cts: usart1_cts-0 {
520 atmel,pins =
521 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD17 periph A */
522 };
523 };
524
525 usart2 {
526 pinctrl_usart2: usart2-0 {
527 atmel,pins =
528 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB6 periph A with pullup */
529 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB7 periph A */
530 };
531
532 pinctrl_usart2_rts: usart2_rts-0 {
533 atmel,pins =
534 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC9 periph B */
535 };
536
537 pinctrl_usart2_cts: usart2_cts-0 {
538 atmel,pins =
539 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC11 periph B */
540 };
541 };
542
543 usart3 {
544 pinctrl_usart3: usart3-0 {
545 atmel,pins =
546 <AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB9 periph A with pullup */
547 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
548 };
549
550 pinctrl_usart3_rts: usart3_rts-0 {
551 atmel,pins =
552 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA23 periph B */
553 };
554
555 pinctrl_usart3_cts: usart3_cts-0 {
556 atmel,pins =
557 <AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA24 periph B */
558 };
559 };
560
561 nand {
562 pinctrl_nand: nand-0 {
563 atmel,pins =
564 <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC8 gpio RDY pin pull_up*/
565 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PC14 gpio enable pin pull_up */
566 };
567 };
568
569 macb {
570 pinctrl_macb_rmii: macb_rmii-0 {
571 atmel,pins =
572 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */
573 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */
574 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */
575 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */
576 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */
577 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */
578 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA16 periph A */
579 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA17 periph A */
580 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA18 periph A */
581 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA19 periph A */
582 };
583
584 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
585 atmel,pins =
586 <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA6 periph B */
587 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA7 periph B */
588 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA8 periph B */
589 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA9 periph B */
590 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA27 periph B */
591 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA28 periph B */
592 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA29 periph B */
593 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */
594 };
595 };
596
597 mmc0 {
598 pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
599 atmel,pins =
600 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A */
601 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
602 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA2 periph A with pullup */
603 };
604
605 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
606 atmel,pins =
607 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
608 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
609 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
610 };
611
612 pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
613 atmel,pins =
614 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA6 periph A with pullup */
615 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
616 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA8 periph A with pullup */
617 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA9 periph A with pullup */
618 };
619 };
620
621 mmc1 {
622 pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
623 atmel,pins =
624 <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA31 periph A */
625 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA22 periph A with pullup */
626 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA23 periph A with pullup */
627 };
628
629 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
630 atmel,pins =
631 <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
632 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA25 periph A with pullup */
633 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA26 periph A with pullup */
634 };
635
636 pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
637 atmel,pins =
638 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA27 periph A with pullup */
639 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */
640 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA29 periph A with pullup */
641 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA30 periph A with pullup */
642 };
643 };
644
645 ssc0 {
646 pinctrl_ssc0_tx: ssc0_tx-0 {
647 atmel,pins =
648 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD0 periph A */
649 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD1 periph A */
650 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD2 periph A */
651 };
652
653 pinctrl_ssc0_rx: ssc0_rx-0 {
654 atmel,pins =
655 <AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD3 periph A */
656 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD4 periph A */
657 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD5 periph A */
658 };
659 };
660
661 ssc1 {
662 pinctrl_ssc1_tx: ssc1_tx-0 {
663 atmel,pins =
664 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A */
665 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A */
666 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A */
667 };
668
669 pinctrl_ssc1_rx: ssc1_rx-0 {
670 atmel,pins =
671 <AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD13 periph A */
672 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD14 periph A */
673 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD15 periph A */
674 };
675 };
676
677 spi0 {
678 pinctrl_spi0: spi0-0 {
679 atmel,pins =
680 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A SPI0_MISO pin */
681 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A SPI0_MOSI pin */
682 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A SPI0_SPCK pin */
683 };
684 };
685
686 spi1 {
687 pinctrl_spi1: spi1-0 {
688 atmel,pins =
689 <AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A SPI1_MISO pin */
690 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A SPI1_MOSI pin */
691 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB16 periph A SPI1_SPCK pin */
692 };
693 };
694
695 tcb0 {
696 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
697 atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
698 };
699
700 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
701 atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
702 };
703
704 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
705 atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
706 };
707
708 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
709 atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
710 };
711
712 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
713 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
714 };
715
716 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
717 atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
718 };
719
720 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
721 atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
722 };
723
724 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
725 atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
726 };
727
728 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
729 atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
730 };
731 };
732
733 tcb1 {
734 pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
735 atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
736 };
737
738 pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
739 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
740 };
741
742 pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
743 atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
744 };
745
746 pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
747 atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
748 };
749
750 pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
751 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
752 };
753
754 pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
755 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
756 };
757
758 pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
759 atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
760 };
761
762 pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
763 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
764 };
765
766 pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
767 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
768 };
769 };
770
771 fb {
772 pinctrl_fb: fb-0 {
773 atmel,pins =
774 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */
775 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */
776 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */
777 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */
778 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */
779 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */
780 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */
781 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */
782 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */
783 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */
784 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */
785 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */
786 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */
787 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */
788 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */
789 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */
790 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */
791 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */
792 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */
793 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */
794 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
795 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */
796 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
797 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
798 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
799 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
800 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
801 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
802 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
803 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
804 };
805 };
806
807 pioA: gpio@fffff200 {
808 compatible = "atmel,at91rm9200-gpio";
809 reg = <0xfffff200 0x200>;
810 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
811 #gpio-cells = <2>;
812 gpio-controller;
813 interrupt-controller;
814 #interrupt-cells = <2>;
815 clocks = <&pioA_clk>;
489 };
490
491 pioB: gpio@fffff400 {
492 compatible = "atmel,at91rm9200-gpio";
493 reg = <0xfffff400 0x200>;
494 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
495 #gpio-cells = <2>;
496 gpio-controller;
497 interrupt-controller;
498 #interrupt-cells = <2>;
816 };
817
818 pioB: gpio@fffff400 {
819 compatible = "atmel,at91rm9200-gpio";
820 reg = <0xfffff400 0x200>;
821 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
822 #gpio-cells = <2>;
823 gpio-controller;
824 interrupt-controller;
825 #interrupt-cells = <2>;
826 clocks = <&pioB_clk>;
499 };
500
501 pioC: gpio@fffff600 {
502 compatible = "atmel,at91rm9200-gpio";
503 reg = <0xfffff600 0x200>;
504 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
505 #gpio-cells = <2>;
506 gpio-controller;
507 interrupt-controller;
508 #interrupt-cells = <2>;
827 };
828
829 pioC: gpio@fffff600 {
830 compatible = "atmel,at91rm9200-gpio";
831 reg = <0xfffff600 0x200>;
832 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
833 #gpio-cells = <2>;
834 gpio-controller;
835 interrupt-controller;
836 #interrupt-cells = <2>;
837 clocks = <&pioC_clk>;
509 };
510
511 pioD: gpio@fffff800 {
512 compatible = "atmel,at91rm9200-gpio";
513 reg = <0xfffff800 0x200>;
514 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
515 #gpio-cells = <2>;
516 gpio-controller;
517 interrupt-controller;
518 #interrupt-cells = <2>;
838 };
839
840 pioD: gpio@fffff800 {
841 compatible = "atmel,at91rm9200-gpio";
842 reg = <0xfffff800 0x200>;
843 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
844 #gpio-cells = <2>;
845 gpio-controller;
846 interrupt-controller;
847 #interrupt-cells = <2>;
848 clocks = <&pioDE_clk>;
519 };
520
521 pioE: gpio@fffffa00 {
522 compatible = "atmel,at91rm9200-gpio";
523 reg = <0xfffffa00 0x200>;
524 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
525 #gpio-cells = <2>;
526 gpio-controller;
527 interrupt-controller;
528 #interrupt-cells = <2>;
849 };
850
851 pioE: gpio@fffffa00 {
852 compatible = "atmel,at91rm9200-gpio";
853 reg = <0xfffffa00 0x200>;
854 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
855 #gpio-cells = <2>;
856 gpio-controller;
857 interrupt-controller;
858 #interrupt-cells = <2>;
859 clocks = <&pioDE_clk>;
529 };
530 };
531
532 dbgu: serial@ffffee00 {
533 compatible = "atmel,at91sam9260-usart";
534 reg = <0xffffee00 0x200>;
535 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_dbgu>;
860 };
861 };
862
863 dbgu: serial@ffffee00 {
864 compatible = "atmel,at91sam9260-usart";
865 reg = <0xffffee00 0x200>;
866 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
867 pinctrl-names = "default";
868 pinctrl-0 = <&pinctrl_dbgu>;
869 clocks = <&mck>;
870 clock-names = "usart";
538 status = "disabled";
539 };
540
541 usart0: serial@fff8c000 {
542 compatible = "atmel,at91sam9260-usart";
543 reg = <0xfff8c000 0x200>;
544 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
545 atmel,use-dma-rx;
546 atmel,use-dma-tx;
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_usart0>;
871 status = "disabled";
872 };
873
874 usart0: serial@fff8c000 {
875 compatible = "atmel,at91sam9260-usart";
876 reg = <0xfff8c000 0x200>;
877 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
878 atmel,use-dma-rx;
879 atmel,use-dma-tx;
880 pinctrl-names = "default";
881 pinctrl-0 = <&pinctrl_usart0>;
882 clocks = <&usart0_clk>;
883 clock-names = "usart";
549 status = "disabled";
550 };
551
552 usart1: serial@fff90000 {
553 compatible = "atmel,at91sam9260-usart";
554 reg = <0xfff90000 0x200>;
555 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
556 atmel,use-dma-rx;
557 atmel,use-dma-tx;
558 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_usart1>;
884 status = "disabled";
885 };
886
887 usart1: serial@fff90000 {
888 compatible = "atmel,at91sam9260-usart";
889 reg = <0xfff90000 0x200>;
890 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
891 atmel,use-dma-rx;
892 atmel,use-dma-tx;
893 pinctrl-names = "default";
894 pinctrl-0 = <&pinctrl_usart1>;
895 clocks = <&usart1_clk>;
896 clock-names = "usart";
560 status = "disabled";
561 };
562
563 usart2: serial@fff94000 {
564 compatible = "atmel,at91sam9260-usart";
565 reg = <0xfff94000 0x200>;
566 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
567 atmel,use-dma-rx;
568 atmel,use-dma-tx;
569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_usart2>;
897 status = "disabled";
898 };
899
900 usart2: serial@fff94000 {
901 compatible = "atmel,at91sam9260-usart";
902 reg = <0xfff94000 0x200>;
903 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
904 atmel,use-dma-rx;
905 atmel,use-dma-tx;
906 pinctrl-names = "default";
907 pinctrl-0 = <&pinctrl_usart2>;
908 clocks = <&usart2_clk>;
909 clock-names = "usart";
571 status = "disabled";
572 };
573
574 usart3: serial@fff98000 {
575 compatible = "atmel,at91sam9260-usart";
576 reg = <0xfff98000 0x200>;
577 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
578 atmel,use-dma-rx;
579 atmel,use-dma-tx;
580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_usart3>;
910 status = "disabled";
911 };
912
913 usart3: serial@fff98000 {
914 compatible = "atmel,at91sam9260-usart";
915 reg = <0xfff98000 0x200>;
916 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
917 atmel,use-dma-rx;
918 atmel,use-dma-tx;
919 pinctrl-names = "default";
920 pinctrl-0 = <&pinctrl_usart3>;
921 clocks = <&usart3_clk>;
922 clock-names = "usart";
582 status = "disabled";
583 };
584
585 macb0: ethernet@fffbc000 {
586 compatible = "cdns,at32ap7000-macb", "cdns,macb";
587 reg = <0xfffbc000 0x100>;
588 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_macb_rmii>;
923 status = "disabled";
924 };
925
926 macb0: ethernet@fffbc000 {
927 compatible = "cdns,at32ap7000-macb", "cdns,macb";
928 reg = <0xfffbc000 0x100>;
929 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
930 pinctrl-names = "default";
931 pinctrl-0 = <&pinctrl_macb_rmii>;
932 clocks = <&macb0_clk>, <&macb0_clk>;
933 clock-names = "hclk", "pclk";
591 status = "disabled";
592 };
593
594 i2c0: i2c@fff84000 {
595 compatible = "atmel,at91sam9g10-i2c";
596 reg = <0xfff84000 0x100>;
597 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&pinctrl_i2c0>;
600 #address-cells = <1>;
601 #size-cells = <0>;
934 status = "disabled";
935 };
936
937 i2c0: i2c@fff84000 {
938 compatible = "atmel,at91sam9g10-i2c";
939 reg = <0xfff84000 0x100>;
940 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
941 pinctrl-names = "default";
942 pinctrl-0 = <&pinctrl_i2c0>;
943 #address-cells = <1>;
944 #size-cells = <0>;
945 clocks = <&twi0_clk>;
602 status = "disabled";
603 };
604
605 i2c1: i2c@fff88000 {
606 compatible = "atmel,at91sam9g10-i2c";
607 reg = <0xfff88000 0x100>;
608 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_i2c1>;
611 #address-cells = <1>;
612 #size-cells = <0>;
946 status = "disabled";
947 };
948
949 i2c1: i2c@fff88000 {
950 compatible = "atmel,at91sam9g10-i2c";
951 reg = <0xfff88000 0x100>;
952 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
953 pinctrl-names = "default";
954 pinctrl-0 = <&pinctrl_i2c1>;
955 #address-cells = <1>;
956 #size-cells = <0>;
957 clocks = <&twi1_clk>;
613 status = "disabled";
614 };
615
616 ssc0: ssc@fff9c000 {
617 compatible = "atmel,at91sam9g45-ssc";
618 reg = <0xfff9c000 0x4000>;
619 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
620 pinctrl-names = "default";
621 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
958 status = "disabled";
959 };
960
961 ssc0: ssc@fff9c000 {
962 compatible = "atmel,at91sam9g45-ssc";
963 reg = <0xfff9c000 0x4000>;
964 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
965 pinctrl-names = "default";
966 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
967 clocks = <&ssc0_clk>;
968 clock-names = "pclk";
622 status = "disabled";
623 };
624
625 ssc1: ssc@fffa0000 {
626 compatible = "atmel,at91sam9g45-ssc";
627 reg = <0xfffa0000 0x4000>;
628 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
969 status = "disabled";
970 };
971
972 ssc1: ssc@fffa0000 {
973 compatible = "atmel,at91sam9g45-ssc";
974 reg = <0xfffa0000 0x4000>;
975 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
976 pinctrl-names = "default";
977 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
978 clocks = <&ssc1_clk>;
979 clock-names = "pclk";
631 status = "disabled";
632 };
633
634 adc0: adc@fffb0000 {
980 status = "disabled";
981 };
982
983 adc0: adc@fffb0000 {
635 compatible = "atmel,at91sam9260-adc";
984 #address-cells = <1>;
985 #size-cells = <0>;
986 compatible = "atmel,at91sam9g45-adc";
636 reg = <0xfffb0000 0x100>;
637 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
987 reg = <0xfffb0000 0x100>;
988 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
638 atmel,adc-use-external-triggers;
989 clocks = <&adc_clk>, <&adc_op_clk>;
990 clock-names = "adc_clk", "adc_op_clk";
639 atmel,adc-channels-used = <0xff>;
640 atmel,adc-vref = <3300>;
991 atmel,adc-channels-used = <0xff>;
992 atmel,adc-vref = <3300>;
641 atmel,adc-num-channels = <8>;
642 atmel,adc-startup-time = <40>;
993 atmel,adc-startup-time = <40>;
643 atmel,adc-channel-base = <0x30>;
644 atmel,adc-drdy-mask = <0x10000>;
645 atmel,adc-status-register = <0x1c>;
646 atmel,adc-trigger-register = <0x08>;
647 atmel,adc-res = <8 10>;
648 atmel,adc-res-names = "lowres", "highres";
649 atmel,adc-use-res = "highres";
650
651 trigger@0 {
994 atmel,adc-res = <8 10>;
995 atmel,adc-res-names = "lowres", "highres";
996 atmel,adc-use-res = "highres";
997
998 trigger@0 {
999 reg = <0>;
652 trigger-name = "external-rising";
653 trigger-value = <0x1>;
654 trigger-external;
655 };
656 trigger@1 {
1000 trigger-name = "external-rising";
1001 trigger-value = <0x1>;
1002 trigger-external;
1003 };
1004 trigger@1 {
1005 reg = <1>;
657 trigger-name = "external-falling";
658 trigger-value = <0x2>;
659 trigger-external;
660 };
661
662 trigger@2 {
1006 trigger-name = "external-falling";
1007 trigger-value = <0x2>;
1008 trigger-external;
1009 };
1010
1011 trigger@2 {
1012 reg = <2>;
663 trigger-name = "external-any";
664 trigger-value = <0x3>;
665 trigger-external;
666 };
667
668 trigger@3 {
1013 trigger-name = "external-any";
1014 trigger-value = <0x3>;
1015 trigger-external;
1016 };
1017
1018 trigger@3 {
1019 reg = <3>;
669 trigger-name = "continuous";
670 trigger-value = <0x6>;
671 };
672 };
673
674 pwm0: pwm@fffb8000 {
675 compatible = "atmel,at91sam9rl-pwm";
676 reg = <0xfffb8000 0x300>;
677 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
678 #pwm-cells = <3>;
1020 trigger-name = "continuous";
1021 trigger-value = <0x6>;
1022 };
1023 };
1024
1025 pwm0: pwm@fffb8000 {
1026 compatible = "atmel,at91sam9rl-pwm";
1027 reg = <0xfffb8000 0x300>;
1028 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
1029 #pwm-cells = <3>;
1030 clocks = <&pwm_clk>;
679 status = "disabled";
680 };
681
682 mmc0: mmc@fff80000 {
683 compatible = "atmel,hsmci";
684 reg = <0xfff80000 0x600>;
685 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
686 pinctrl-names = "default";
687 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
688 dma-names = "rxtx";
689 #address-cells = <1>;
690 #size-cells = <0>;
1031 status = "disabled";
1032 };
1033
1034 mmc0: mmc@fff80000 {
1035 compatible = "atmel,hsmci";
1036 reg = <0xfff80000 0x600>;
1037 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1038 pinctrl-names = "default";
1039 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1040 dma-names = "rxtx";
1041 #address-cells = <1>;
1042 #size-cells = <0>;
1043 clocks = <&mci0_clk>;
1044 clock-names = "mci_clk";
691 status = "disabled";
692 };
693
694 mmc1: mmc@fffd0000 {
695 compatible = "atmel,hsmci";
696 reg = <0xfffd0000 0x600>;
697 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
698 pinctrl-names = "default";
699 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
700 dma-names = "rxtx";
701 #address-cells = <1>;
702 #size-cells = <0>;
1045 status = "disabled";
1046 };
1047
1048 mmc1: mmc@fffd0000 {
1049 compatible = "atmel,hsmci";
1050 reg = <0xfffd0000 0x600>;
1051 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1052 pinctrl-names = "default";
1053 dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
1054 dma-names = "rxtx";
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 clocks = <&mci1_clk>;
1058 clock-names = "mci_clk";
703 status = "disabled";
704 };
705
706 watchdog@fffffd40 {
707 compatible = "atmel,at91sam9260-wdt";
708 reg = <0xfffffd40 0x10>;
709 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
710 atmel,watchdog-type = "hardware";
711 atmel,reset-type = "all";
712 atmel,dbg-halt;
713 atmel,idle-halt;
714 status = "disabled";
715 };
716
717 spi0: spi@fffa4000 {
718 #address-cells = <1>;
719 #size-cells = <0>;
720 compatible = "atmel,at91rm9200-spi";
721 reg = <0xfffa4000 0x200>;
722 interrupts = <14 4 3>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_spi0>;
1059 status = "disabled";
1060 };
1061
1062 watchdog@fffffd40 {
1063 compatible = "atmel,at91sam9260-wdt";
1064 reg = <0xfffffd40 0x10>;
1065 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1066 atmel,watchdog-type = "hardware";
1067 atmel,reset-type = "all";
1068 atmel,dbg-halt;
1069 atmel,idle-halt;
1070 status = "disabled";
1071 };
1072
1073 spi0: spi@fffa4000 {
1074 #address-cells = <1>;
1075 #size-cells = <0>;
1076 compatible = "atmel,at91rm9200-spi";
1077 reg = <0xfffa4000 0x200>;
1078 interrupts = <14 4 3>;
1079 pinctrl-names = "default";
1080 pinctrl-0 = <&pinctrl_spi0>;
1081 clocks = <&spi0_clk>;
1082 clock-names = "spi_clk";
725 status = "disabled";
726 };
727
728 spi1: spi@fffa8000 {
729 #address-cells = <1>;
730 #size-cells = <0>;
731 compatible = "atmel,at91rm9200-spi";
732 reg = <0xfffa8000 0x200>;
733 interrupts = <15 4 3>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_spi1>;
1083 status = "disabled";
1084 };
1085
1086 spi1: spi@fffa8000 {
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1089 compatible = "atmel,at91rm9200-spi";
1090 reg = <0xfffa8000 0x200>;
1091 interrupts = <15 4 3>;
1092 pinctrl-names = "default";
1093 pinctrl-0 = <&pinctrl_spi1>;
1094 clocks = <&spi1_clk>;
1095 clock-names = "spi_clk";
736 status = "disabled";
737 };
738
739 usb2: gadget@fff78000 {
740 #address-cells = <1>;
741 #size-cells = <0>;
742 compatible = "atmel,at91sam9rl-udc";
743 reg = <0x00600000 0x80000
744 0xfff78000 0x400>;
745 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1096 status = "disabled";
1097 };
1098
1099 usb2: gadget@fff78000 {
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102 compatible = "atmel,at91sam9rl-udc";
1103 reg = <0x00600000 0x80000
1104 0xfff78000 0x400>;
1105 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1106 clocks = <&udphs_clk>, <&utmi>;
1107 clock-names = "pclk", "hclk";
746 status = "disabled";
747
748 ep0 {
749 reg = <0>;
750 atmel,fifo-size = <64>;
751 atmel,nb-banks = <1>;
752 };
753
754 ep1 {
755 reg = <1>;
756 atmel,fifo-size = <1024>;
757 atmel,nb-banks = <2>;
758 atmel,can-dma;
759 atmel,can-isoc;
760 };
761
762 ep2 {
763 reg = <2>;
764 atmel,fifo-size = <1024>;
765 atmel,nb-banks = <2>;
766 atmel,can-dma;
767 atmel,can-isoc;
768 };
769
770 ep3 {
771 reg = <3>;
772 atmel,fifo-size = <1024>;
773 atmel,nb-banks = <3>;
774 atmel,can-dma;
775 };
776
777 ep4 {
778 reg = <4>;
779 atmel,fifo-size = <1024>;
780 atmel,nb-banks = <3>;
781 atmel,can-dma;
782 };
783
784 ep5 {
785 reg = <5>;
786 atmel,fifo-size = <1024>;
787 atmel,nb-banks = <3>;
788 atmel,can-dma;
789 atmel,can-isoc;
790 };
791
792 ep6 {
793 reg = <6>;
794 atmel,fifo-size = <1024>;
795 atmel,nb-banks = <3>;
796 atmel,can-dma;
797 atmel,can-isoc;
798 };
799 };
800 };
801
802 fb0: fb@0x00500000 {
803 compatible = "atmel,at91sam9g45-lcdc";
804 reg = <0x00500000 0x1000>;
805 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
806 pinctrl-names = "default";
807 pinctrl-0 = <&pinctrl_fb>;
1108 status = "disabled";
1109
1110 ep0 {
1111 reg = <0>;
1112 atmel,fifo-size = <64>;
1113 atmel,nb-banks = <1>;
1114 };
1115
1116 ep1 {
1117 reg = <1>;
1118 atmel,fifo-size = <1024>;
1119 atmel,nb-banks = <2>;
1120 atmel,can-dma;
1121 atmel,can-isoc;
1122 };
1123
1124 ep2 {
1125 reg = <2>;
1126 atmel,fifo-size = <1024>;
1127 atmel,nb-banks = <2>;
1128 atmel,can-dma;
1129 atmel,can-isoc;
1130 };
1131
1132 ep3 {
1133 reg = <3>;
1134 atmel,fifo-size = <1024>;
1135 atmel,nb-banks = <3>;
1136 atmel,can-dma;
1137 };
1138
1139 ep4 {
1140 reg = <4>;
1141 atmel,fifo-size = <1024>;
1142 atmel,nb-banks = <3>;
1143 atmel,can-dma;
1144 };
1145
1146 ep5 {
1147 reg = <5>;
1148 atmel,fifo-size = <1024>;
1149 atmel,nb-banks = <3>;
1150 atmel,can-dma;
1151 atmel,can-isoc;
1152 };
1153
1154 ep6 {
1155 reg = <6>;
1156 atmel,fifo-size = <1024>;
1157 atmel,nb-banks = <3>;
1158 atmel,can-dma;
1159 atmel,can-isoc;
1160 };
1161 };
1162 };
1163
1164 fb0: fb@0x00500000 {
1165 compatible = "atmel,at91sam9g45-lcdc";
1166 reg = <0x00500000 0x1000>;
1167 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
1168 pinctrl-names = "default";
1169 pinctrl-0 = <&pinctrl_fb>;
1170 clocks = <&lcd_clk>, <&lcd_clk>;
1171 clock-names = "hclk", "lcdc_clk";
808 status = "disabled";
809 };
810
811 nand0: nand@40000000 {
812 compatible = "atmel,at91rm9200-nand";
813 #address-cells = <1>;
814 #size-cells = <1>;
815 reg = <0x40000000 0x10000000
816 0xffffe200 0x200
817 >;
818 atmel,nand-addr-offset = <21>;
819 atmel,nand-cmd-offset = <22>;
1172 status = "disabled";
1173 };
1174
1175 nand0: nand@40000000 {
1176 compatible = "atmel,at91rm9200-nand";
1177 #address-cells = <1>;
1178 #size-cells = <1>;
1179 reg = <0x40000000 0x10000000
1180 0xffffe200 0x200
1181 >;
1182 atmel,nand-addr-offset = <21>;
1183 atmel,nand-cmd-offset = <22>;
1184 atmel,nand-has-dma;
820 pinctrl-names = "default";
821 pinctrl-0 = <&pinctrl_nand>;
822 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
823 &pioC 14 GPIO_ACTIVE_HIGH
824 0
825 >;
826 status = "disabled";
827 };
828
829 usb0: ohci@00700000 {
830 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
831 reg = <0x00700000 0x100000>;
832 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1185 pinctrl-names = "default";
1186 pinctrl-0 = <&pinctrl_nand>;
1187 gpios = <&pioC 8 GPIO_ACTIVE_HIGH
1188 &pioC 14 GPIO_ACTIVE_HIGH
1189 0
1190 >;
1191 status = "disabled";
1192 };
1193
1194 usb0: ohci@00700000 {
1195 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1196 reg = <0x00700000 0x100000>;
1197 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1198 //TODO
1199 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1200 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
833 status = "disabled";
834 };
835
836 usb1: ehci@00800000 {
837 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
838 reg = <0x00800000 0x100000>;
839 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1201 status = "disabled";
1202 };
1203
1204 usb1: ehci@00800000 {
1205 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1206 reg = <0x00800000 0x100000>;
1207 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1208 //TODO
1209 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1210 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
840 status = "disabled";
841 };
842 };
843
844 i2c@0 {
845 compatible = "i2c-gpio";
846 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
847 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
848 >;
849 i2c-gpio,sda-open-drain;
850 i2c-gpio,scl-open-drain;
851 i2c-gpio,delay-us = <5>; /* ~100 kHz */
852 #address-cells = <1>;
853 #size-cells = <0>;
854 status = "disabled";
855 };
856};
1211 status = "disabled";
1212 };
1213 };
1214
1215 i2c@0 {
1216 compatible = "i2c-gpio";
1217 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
1218 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1219 >;
1220 i2c-gpio,sda-open-drain;
1221 i2c-gpio,scl-open-drain;
1222 i2c-gpio,delay-us = <5>; /* ~100 kHz */
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1225 status = "disabled";
1226 };
1227};