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at91sam9g20.dtsi (262573) at91sam9g20.dtsi (270864)
1/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8

--- 11 unchanged lines hidden (view full) ---

20 apb {
21 i2c0: i2c@fffac000 {
22 compatible = "atmel,at91sam9g20-i2c";
23 };
24
25 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>;
27 };
1/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2.
7 */
8

--- 11 unchanged lines hidden (view full) ---

20 apb {
21 i2c0: i2c@fffac000 {
22 compatible = "atmel,at91sam9g20-i2c";
23 };
24
25 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>;
27 };
28
29 pmc: pmc@fffffc00 {
30 plla: pllack {
31 atmel,clk-input-range = <2000000 32000000>;
32 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
33 <695000000 750000000 1 0>,
34 <645000000 700000000 2 0>,
35 <595000000 650000000 3 0>,
36 <545000000 600000000 0 1>,
37 <495000000 550000000 1 1>,
38 <445000000 500000000 2 1>,
39 <400000000 450000000 3 1>;
40 };
41
42 pllb: pllbck {
43 atmel,clk-input-range = <2000000 32000000>;
44 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
45 };
46
47 mck: masterck {
48 atmel,clk-output-range = <0 133000000>;
49 atmel,clk-divisors = <1 2 4 6>;
50 };
51 };
28 };
29 };
30};
52 };
53 };
54};