35
36/*
37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44/*
45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that
46 * combines a tri-speed ethernet MAC and PHY, with the following
47 * features:
48 *
49 * o Jumbo frame support up to 16K
50 * o Transmit and receive flow control
51 * o IPv4 checksum offload
52 * o VLAN tag insertion and stripping
53 * o TCP large send
54 * o 64-bit multicast hash table filter
55 * o 64 entry CAM filter
56 * o 16K RX FIFO and 48K TX FIFO memory
57 * o Interrupt moderation
58 *
59 * The VT6122 supports up to four transmit DMA queues. The descriptors
60 * in the transmit ring can address up to 7 data fragments; frames which
61 * span more than 7 data buffers must be coalesced, but in general the
62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
63 * long. The receive descriptors address only a single buffer.
64 *
65 * There are two peculiar design issues with the VT6122. One is that
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
68 * systems, but on architectures that generate unaligned access traps, we
69 * have to do some copying.
70 *
71 * The other issue has to do with the way 64-bit addresses are handled.
72 * The DMA descriptors only allow you to specify 48 bits of addressing
73 * information. The remaining 16 bits are specified using one of the
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
76 * memory, you must have to make sure your network data buffers reside
77 * in the same 48-bit 'segment.'
78 *
79 * Special thanks to Ryan Fu at VIA Networking for providing documentation
80 * and sample NICs for testing.
81 */
82
83#include <sys/param.h>
84#include <sys/endian.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/module.h>
90#include <sys/kernel.h>
91#include <sys/socket.h>
92#include <sys/taskqueue.h>
93
94#include <net/if.h>
95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99#include <net/if_types.h>
100#include <net/if_vlan_var.h>
101
102#include <net/bpf.h>
103
104#include <machine/bus.h>
105#include <machine/resource.h>
106#include <sys/bus.h>
107#include <sys/rman.h>
108
109#include <dev/mii/mii.h>
110#include <dev/mii/miivar.h>
111
112#include <dev/pci/pcireg.h>
113#include <dev/pci/pcivar.h>
114
115MODULE_DEPEND(vge, pci, 1, 1, 1);
116MODULE_DEPEND(vge, ether, 1, 1, 1);
117MODULE_DEPEND(vge, miibus, 1, 1, 1);
118
119/* "controller miibus0" required. See GENERIC if you get errors here. */
120#include "miibus_if.h"
121
122#include <dev/vge/if_vgereg.h>
123#include <dev/vge/if_vgevar.h>
124
125#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
126
127/*
128 * Various supported device vendors/types and their names.
129 */
130static struct vge_type vge_devs[] = {
131 { VIA_VENDORID, VIA_DEVICEID_61XX,
132 "VIA Networking Gigabit Ethernet" },
133 { 0, 0, NULL }
134};
135
136static int vge_probe (device_t);
137static int vge_attach (device_t);
138static int vge_detach (device_t);
139
140static int vge_encap (struct vge_softc *, struct mbuf *, int);
141
142static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int);
143static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int,
144 bus_size_t, int);
145static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int,
146 bus_size_t, int);
147static int vge_allocmem (device_t, struct vge_softc *);
148static int vge_newbuf (struct vge_softc *, int, struct mbuf *);
149static int vge_rx_list_init (struct vge_softc *);
150static int vge_tx_list_init (struct vge_softc *);
151#ifdef VGE_FIXUP_RX
152static __inline void vge_fixup_rx
153 (struct mbuf *);
154#endif
155static void vge_rxeof (struct vge_softc *);
156static void vge_txeof (struct vge_softc *);
157static void vge_intr (void *);
158static void vge_tick (void *);
159static void vge_tx_task (void *, int);
160static void vge_start (struct ifnet *);
161static int vge_ioctl (struct ifnet *, u_long, caddr_t);
162static void vge_init (void *);
163static void vge_stop (struct vge_softc *);
164static void vge_watchdog (struct ifnet *);
165static int vge_suspend (device_t);
166static int vge_resume (device_t);
167static void vge_shutdown (device_t);
168static int vge_ifmedia_upd (struct ifnet *);
169static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
170
171#ifdef VGE_EEPROM
172static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *);
173#endif
174static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int);
175
176static void vge_miipoll_start (struct vge_softc *);
177static void vge_miipoll_stop (struct vge_softc *);
178static int vge_miibus_readreg (device_t, int, int);
179static int vge_miibus_writereg (device_t, int, int, int);
180static void vge_miibus_statchg (device_t);
181
182static void vge_cam_clear (struct vge_softc *);
183static int vge_cam_set (struct vge_softc *, uint8_t *);
184#if __FreeBSD_version < 502113
185static uint32_t vge_mchash (uint8_t *);
186#endif
187static void vge_setmulti (struct vge_softc *);
188static void vge_reset (struct vge_softc *);
189
190#define VGE_PCI_LOIO 0x10
191#define VGE_PCI_LOMEM 0x14
192
193static device_method_t vge_methods[] = {
194 /* Device interface */
195 DEVMETHOD(device_probe, vge_probe),
196 DEVMETHOD(device_attach, vge_attach),
197 DEVMETHOD(device_detach, vge_detach),
198 DEVMETHOD(device_suspend, vge_suspend),
199 DEVMETHOD(device_resume, vge_resume),
200 DEVMETHOD(device_shutdown, vge_shutdown),
201
202 /* bus interface */
203 DEVMETHOD(bus_print_child, bus_generic_print_child),
204 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205
206 /* MII interface */
207 DEVMETHOD(miibus_readreg, vge_miibus_readreg),
208 DEVMETHOD(miibus_writereg, vge_miibus_writereg),
209 DEVMETHOD(miibus_statchg, vge_miibus_statchg),
210
211 { 0, 0 }
212};
213
214static driver_t vge_driver = {
215 "vge",
216 vge_methods,
217 sizeof(struct vge_softc)
218};
219
220static devclass_t vge_devclass;
221
222DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0);
223DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0);
224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0);
225
226#ifdef VGE_EEPROM
227/*
228 * Read a word of data stored in the EEPROM at address 'addr.'
229 */
230static void
231vge_eeprom_getword(sc, addr, dest)
232 struct vge_softc *sc;
233 int addr;
234 u_int16_t *dest;
235{
236 register int i;
237 u_int16_t word = 0;
238
239 /*
240 * Enter EEPROM embedded programming mode. In order to
241 * access the EEPROM at all, we first have to set the
242 * EELOAD bit in the CHIPCFG2 register.
243 */
244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
246
247 /* Select the address of the word we want to read */
248 CSR_WRITE_1(sc, VGE_EEADDR, addr);
249
250 /* Issue read command */
251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
252
253 /* Wait for the done bit to be set. */
254 for (i = 0; i < VGE_TIMEOUT; i++) {
255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
256 break;
257 }
258
259 if (i == VGE_TIMEOUT) {
260 device_printf(sc->vge_dev, "EEPROM read timed out\n");
261 *dest = 0;
262 return;
263 }
264
265 /* Read the result */
266 word = CSR_READ_2(sc, VGE_EERDDAT);
267
268 /* Turn off EEPROM access mode. */
269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
271
272 *dest = word;
273
274 return;
275}
276#endif
277
278/*
279 * Read a sequence of words from the EEPROM.
280 */
281static void
282vge_read_eeprom(sc, dest, off, cnt, swap)
283 struct vge_softc *sc;
284 caddr_t dest;
285 int off;
286 int cnt;
287 int swap;
288{
289 int i;
290#ifdef VGE_EEPROM
291 u_int16_t word = 0, *ptr;
292
293 for (i = 0; i < cnt; i++) {
294 vge_eeprom_getword(sc, off + i, &word);
295 ptr = (u_int16_t *)(dest + (i * 2));
296 if (swap)
297 *ptr = ntohs(word);
298 else
299 *ptr = word;
300 }
301#else
302 for (i = 0; i < ETHER_ADDR_LEN; i++)
303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
304#endif
305}
306
307static void
308vge_miipoll_stop(sc)
309 struct vge_softc *sc;
310{
311 int i;
312
313 CSR_WRITE_1(sc, VGE_MIICMD, 0);
314
315 for (i = 0; i < VGE_TIMEOUT; i++) {
316 DELAY(1);
317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
318 break;
319 }
320
321 if (i == VGE_TIMEOUT)
322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
323
324 return;
325}
326
327static void
328vge_miipoll_start(sc)
329 struct vge_softc *sc;
330{
331 int i;
332
333 /* First, make sure we're idle. */
334
335 CSR_WRITE_1(sc, VGE_MIICMD, 0);
336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
337
338 for (i = 0; i < VGE_TIMEOUT; i++) {
339 DELAY(1);
340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
341 break;
342 }
343
344 if (i == VGE_TIMEOUT) {
345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
346 return;
347 }
348
349 /* Now enable auto poll mode. */
350
351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
352
353 /* And make sure it started. */
354
355 for (i = 0; i < VGE_TIMEOUT; i++) {
356 DELAY(1);
357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
358 break;
359 }
360
361 if (i == VGE_TIMEOUT)
362 device_printf(sc->vge_dev, "failed to start MII autopoll\n");
363
364 return;
365}
366
367static int
368vge_miibus_readreg(dev, phy, reg)
369 device_t dev;
370 int phy, reg;
371{
372 struct vge_softc *sc;
373 int i;
374 u_int16_t rval = 0;
375
376 sc = device_get_softc(dev);
377
378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
379 return(0);
380
381 VGE_LOCK(sc);
382 vge_miipoll_stop(sc);
383
384 /* Specify the register we want to read. */
385 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
386
387 /* Issue read command. */
388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
389
390 /* Wait for the read command bit to self-clear. */
391 for (i = 0; i < VGE_TIMEOUT; i++) {
392 DELAY(1);
393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
394 break;
395 }
396
397 if (i == VGE_TIMEOUT)
398 device_printf(sc->vge_dev, "MII read timed out\n");
399 else
400 rval = CSR_READ_2(sc, VGE_MIIDATA);
401
402 vge_miipoll_start(sc);
403 VGE_UNLOCK(sc);
404
405 return (rval);
406}
407
408static int
409vge_miibus_writereg(dev, phy, reg, data)
410 device_t dev;
411 int phy, reg, data;
412{
413 struct vge_softc *sc;
414 int i, rval = 0;
415
416 sc = device_get_softc(dev);
417
418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
419 return(0);
420
421 VGE_LOCK(sc);
422 vge_miipoll_stop(sc);
423
424 /* Specify the register we want to write. */
425 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
426
427 /* Specify the data we want to write. */
428 CSR_WRITE_2(sc, VGE_MIIDATA, data);
429
430 /* Issue write command. */
431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
432
433 /* Wait for the write command bit to self-clear. */
434 for (i = 0; i < VGE_TIMEOUT; i++) {
435 DELAY(1);
436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
437 break;
438 }
439
440 if (i == VGE_TIMEOUT) {
441 device_printf(sc->vge_dev, "MII write timed out\n");
442 rval = EIO;
443 }
444
445 vge_miipoll_start(sc);
446 VGE_UNLOCK(sc);
447
448 return (rval);
449}
450
451static void
452vge_cam_clear(sc)
453 struct vge_softc *sc;
454{
455 int i;
456
457 /*
458 * Turn off all the mask bits. This tells the chip
459 * that none of the entries in the CAM filter are valid.
460 * desired entries will be enabled as we fill the filter in.
461 */
462
463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
466 for (i = 0; i < 8; i++)
467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
468
469 /* Clear the VLAN filter too. */
470
471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
472 for (i = 0; i < 8; i++)
473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
474
475 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
478
479 sc->vge_camidx = 0;
480
481 return;
482}
483
484static int
485vge_cam_set(sc, addr)
486 struct vge_softc *sc;
487 uint8_t *addr;
488{
489 int i, error = 0;
490
491 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
492 return(ENOSPC);
493
494 /* Select the CAM data page. */
495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
497
498 /* Set the filter entry we want to update and enable writing. */
499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
500
501 /* Write the address to the CAM registers */
502 for (i = 0; i < ETHER_ADDR_LEN; i++)
503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
504
505 /* Issue a write command. */
506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
507
508 /* Wake for it to clear. */
509 for (i = 0; i < VGE_TIMEOUT; i++) {
510 DELAY(1);
511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
512 break;
513 }
514
515 if (i == VGE_TIMEOUT) {
516 device_printf(sc->vge_dev, "setting CAM filter failed\n");
517 error = EIO;
518 goto fail;
519 }
520
521 /* Select the CAM mask page. */
522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
524
525 /* Set the mask bit that enables this filter. */
526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
527 1<<(sc->vge_camidx & 7));
528
529 sc->vge_camidx++;
530
531fail:
532 /* Turn off access to CAM. */
533 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
536
537 return (error);
538}
539
540#if __FreeBSD_version < 502113
541static uint32_t
542vge_mchash(addr)
543 uint8_t *addr;
544{
545 uint32_t crc, carry;
546 int idx, bit;
547 uint8_t data;
548
549 /* Compute CRC for the address value. */
550 crc = 0xFFFFFFFF; /* initial value */
551
552 for (idx = 0; idx < 6; idx++) {
553 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
554 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
555 crc <<= 1;
556 if (carry)
557 crc = (crc ^ 0x04c11db6) | carry;
558 }
559 }
560
561 return(crc);
562}
563#endif
564
565/*
566 * Program the multicast filter. We use the 64-entry CAM filter
567 * for perfect filtering. If there's more than 64 multicast addresses,
568 * we use the hash filter insted.
569 */
570static void
571vge_setmulti(sc)
572 struct vge_softc *sc;
573{
574 struct ifnet *ifp;
575 int error = 0/*, h = 0*/;
576 struct ifmultiaddr *ifma;
577 u_int32_t h, hashes[2] = { 0, 0 };
578
579 ifp = sc->vge_ifp;
580
581 /* First, zot all the multicast entries. */
582 vge_cam_clear(sc);
583 CSR_WRITE_4(sc, VGE_MAR0, 0);
584 CSR_WRITE_4(sc, VGE_MAR1, 0);
585
586 /*
587 * If the user wants allmulti or promisc mode, enable reception
588 * of all multicast frames.
589 */
590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
591 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
592 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
593 return;
594 }
595
596 /* Now program new ones */
| 35
36/*
37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver.
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44/*
45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that
46 * combines a tri-speed ethernet MAC and PHY, with the following
47 * features:
48 *
49 * o Jumbo frame support up to 16K
50 * o Transmit and receive flow control
51 * o IPv4 checksum offload
52 * o VLAN tag insertion and stripping
53 * o TCP large send
54 * o 64-bit multicast hash table filter
55 * o 64 entry CAM filter
56 * o 16K RX FIFO and 48K TX FIFO memory
57 * o Interrupt moderation
58 *
59 * The VT6122 supports up to four transmit DMA queues. The descriptors
60 * in the transmit ring can address up to 7 data fragments; frames which
61 * span more than 7 data buffers must be coalesced, but in general the
62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments
63 * long. The receive descriptors address only a single buffer.
64 *
65 * There are two peculiar design issues with the VT6122. One is that
66 * receive data buffers must be aligned on a 32-bit boundary. This is
67 * not a problem where the VT6122 is used as a LOM device in x86-based
68 * systems, but on architectures that generate unaligned access traps, we
69 * have to do some copying.
70 *
71 * The other issue has to do with the way 64-bit addresses are handled.
72 * The DMA descriptors only allow you to specify 48 bits of addressing
73 * information. The remaining 16 bits are specified using one of the
74 * I/O registers. If you only have a 32-bit system, then this isn't
75 * an issue, but if you have a 64-bit system and more than 4GB of
76 * memory, you must have to make sure your network data buffers reside
77 * in the same 48-bit 'segment.'
78 *
79 * Special thanks to Ryan Fu at VIA Networking for providing documentation
80 * and sample NICs for testing.
81 */
82
83#include <sys/param.h>
84#include <sys/endian.h>
85#include <sys/systm.h>
86#include <sys/sockio.h>
87#include <sys/mbuf.h>
88#include <sys/malloc.h>
89#include <sys/module.h>
90#include <sys/kernel.h>
91#include <sys/socket.h>
92#include <sys/taskqueue.h>
93
94#include <net/if.h>
95#include <net/if_arp.h>
96#include <net/ethernet.h>
97#include <net/if_dl.h>
98#include <net/if_media.h>
99#include <net/if_types.h>
100#include <net/if_vlan_var.h>
101
102#include <net/bpf.h>
103
104#include <machine/bus.h>
105#include <machine/resource.h>
106#include <sys/bus.h>
107#include <sys/rman.h>
108
109#include <dev/mii/mii.h>
110#include <dev/mii/miivar.h>
111
112#include <dev/pci/pcireg.h>
113#include <dev/pci/pcivar.h>
114
115MODULE_DEPEND(vge, pci, 1, 1, 1);
116MODULE_DEPEND(vge, ether, 1, 1, 1);
117MODULE_DEPEND(vge, miibus, 1, 1, 1);
118
119/* "controller miibus0" required. See GENERIC if you get errors here. */
120#include "miibus_if.h"
121
122#include <dev/vge/if_vgereg.h>
123#include <dev/vge/if_vgevar.h>
124
125#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
126
127/*
128 * Various supported device vendors/types and their names.
129 */
130static struct vge_type vge_devs[] = {
131 { VIA_VENDORID, VIA_DEVICEID_61XX,
132 "VIA Networking Gigabit Ethernet" },
133 { 0, 0, NULL }
134};
135
136static int vge_probe (device_t);
137static int vge_attach (device_t);
138static int vge_detach (device_t);
139
140static int vge_encap (struct vge_softc *, struct mbuf *, int);
141
142static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int);
143static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int,
144 bus_size_t, int);
145static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int,
146 bus_size_t, int);
147static int vge_allocmem (device_t, struct vge_softc *);
148static int vge_newbuf (struct vge_softc *, int, struct mbuf *);
149static int vge_rx_list_init (struct vge_softc *);
150static int vge_tx_list_init (struct vge_softc *);
151#ifdef VGE_FIXUP_RX
152static __inline void vge_fixup_rx
153 (struct mbuf *);
154#endif
155static void vge_rxeof (struct vge_softc *);
156static void vge_txeof (struct vge_softc *);
157static void vge_intr (void *);
158static void vge_tick (void *);
159static void vge_tx_task (void *, int);
160static void vge_start (struct ifnet *);
161static int vge_ioctl (struct ifnet *, u_long, caddr_t);
162static void vge_init (void *);
163static void vge_stop (struct vge_softc *);
164static void vge_watchdog (struct ifnet *);
165static int vge_suspend (device_t);
166static int vge_resume (device_t);
167static void vge_shutdown (device_t);
168static int vge_ifmedia_upd (struct ifnet *);
169static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *);
170
171#ifdef VGE_EEPROM
172static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *);
173#endif
174static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int);
175
176static void vge_miipoll_start (struct vge_softc *);
177static void vge_miipoll_stop (struct vge_softc *);
178static int vge_miibus_readreg (device_t, int, int);
179static int vge_miibus_writereg (device_t, int, int, int);
180static void vge_miibus_statchg (device_t);
181
182static void vge_cam_clear (struct vge_softc *);
183static int vge_cam_set (struct vge_softc *, uint8_t *);
184#if __FreeBSD_version < 502113
185static uint32_t vge_mchash (uint8_t *);
186#endif
187static void vge_setmulti (struct vge_softc *);
188static void vge_reset (struct vge_softc *);
189
190#define VGE_PCI_LOIO 0x10
191#define VGE_PCI_LOMEM 0x14
192
193static device_method_t vge_methods[] = {
194 /* Device interface */
195 DEVMETHOD(device_probe, vge_probe),
196 DEVMETHOD(device_attach, vge_attach),
197 DEVMETHOD(device_detach, vge_detach),
198 DEVMETHOD(device_suspend, vge_suspend),
199 DEVMETHOD(device_resume, vge_resume),
200 DEVMETHOD(device_shutdown, vge_shutdown),
201
202 /* bus interface */
203 DEVMETHOD(bus_print_child, bus_generic_print_child),
204 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
205
206 /* MII interface */
207 DEVMETHOD(miibus_readreg, vge_miibus_readreg),
208 DEVMETHOD(miibus_writereg, vge_miibus_writereg),
209 DEVMETHOD(miibus_statchg, vge_miibus_statchg),
210
211 { 0, 0 }
212};
213
214static driver_t vge_driver = {
215 "vge",
216 vge_methods,
217 sizeof(struct vge_softc)
218};
219
220static devclass_t vge_devclass;
221
222DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0);
223DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0);
224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0);
225
226#ifdef VGE_EEPROM
227/*
228 * Read a word of data stored in the EEPROM at address 'addr.'
229 */
230static void
231vge_eeprom_getword(sc, addr, dest)
232 struct vge_softc *sc;
233 int addr;
234 u_int16_t *dest;
235{
236 register int i;
237 u_int16_t word = 0;
238
239 /*
240 * Enter EEPROM embedded programming mode. In order to
241 * access the EEPROM at all, we first have to set the
242 * EELOAD bit in the CHIPCFG2 register.
243 */
244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
246
247 /* Select the address of the word we want to read */
248 CSR_WRITE_1(sc, VGE_EEADDR, addr);
249
250 /* Issue read command */
251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD);
252
253 /* Wait for the done bit to be set. */
254 for (i = 0; i < VGE_TIMEOUT; i++) {
255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE)
256 break;
257 }
258
259 if (i == VGE_TIMEOUT) {
260 device_printf(sc->vge_dev, "EEPROM read timed out\n");
261 *dest = 0;
262 return;
263 }
264
265 /* Read the result */
266 word = CSR_READ_2(sc, VGE_EERDDAT);
267
268 /* Turn off EEPROM access mode. */
269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/);
270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD);
271
272 *dest = word;
273
274 return;
275}
276#endif
277
278/*
279 * Read a sequence of words from the EEPROM.
280 */
281static void
282vge_read_eeprom(sc, dest, off, cnt, swap)
283 struct vge_softc *sc;
284 caddr_t dest;
285 int off;
286 int cnt;
287 int swap;
288{
289 int i;
290#ifdef VGE_EEPROM
291 u_int16_t word = 0, *ptr;
292
293 for (i = 0; i < cnt; i++) {
294 vge_eeprom_getword(sc, off + i, &word);
295 ptr = (u_int16_t *)(dest + (i * 2));
296 if (swap)
297 *ptr = ntohs(word);
298 else
299 *ptr = word;
300 }
301#else
302 for (i = 0; i < ETHER_ADDR_LEN; i++)
303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i);
304#endif
305}
306
307static void
308vge_miipoll_stop(sc)
309 struct vge_softc *sc;
310{
311 int i;
312
313 CSR_WRITE_1(sc, VGE_MIICMD, 0);
314
315 for (i = 0; i < VGE_TIMEOUT; i++) {
316 DELAY(1);
317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
318 break;
319 }
320
321 if (i == VGE_TIMEOUT)
322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
323
324 return;
325}
326
327static void
328vge_miipoll_start(sc)
329 struct vge_softc *sc;
330{
331 int i;
332
333 /* First, make sure we're idle. */
334
335 CSR_WRITE_1(sc, VGE_MIICMD, 0);
336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL);
337
338 for (i = 0; i < VGE_TIMEOUT; i++) {
339 DELAY(1);
340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL)
341 break;
342 }
343
344 if (i == VGE_TIMEOUT) {
345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n");
346 return;
347 }
348
349 /* Now enable auto poll mode. */
350
351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO);
352
353 /* And make sure it started. */
354
355 for (i = 0; i < VGE_TIMEOUT; i++) {
356 DELAY(1);
357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0)
358 break;
359 }
360
361 if (i == VGE_TIMEOUT)
362 device_printf(sc->vge_dev, "failed to start MII autopoll\n");
363
364 return;
365}
366
367static int
368vge_miibus_readreg(dev, phy, reg)
369 device_t dev;
370 int phy, reg;
371{
372 struct vge_softc *sc;
373 int i;
374 u_int16_t rval = 0;
375
376 sc = device_get_softc(dev);
377
378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
379 return(0);
380
381 VGE_LOCK(sc);
382 vge_miipoll_stop(sc);
383
384 /* Specify the register we want to read. */
385 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
386
387 /* Issue read command. */
388 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD);
389
390 /* Wait for the read command bit to self-clear. */
391 for (i = 0; i < VGE_TIMEOUT; i++) {
392 DELAY(1);
393 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0)
394 break;
395 }
396
397 if (i == VGE_TIMEOUT)
398 device_printf(sc->vge_dev, "MII read timed out\n");
399 else
400 rval = CSR_READ_2(sc, VGE_MIIDATA);
401
402 vge_miipoll_start(sc);
403 VGE_UNLOCK(sc);
404
405 return (rval);
406}
407
408static int
409vge_miibus_writereg(dev, phy, reg, data)
410 device_t dev;
411 int phy, reg, data;
412{
413 struct vge_softc *sc;
414 int i, rval = 0;
415
416 sc = device_get_softc(dev);
417
418 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F))
419 return(0);
420
421 VGE_LOCK(sc);
422 vge_miipoll_stop(sc);
423
424 /* Specify the register we want to write. */
425 CSR_WRITE_1(sc, VGE_MIIADDR, reg);
426
427 /* Specify the data we want to write. */
428 CSR_WRITE_2(sc, VGE_MIIDATA, data);
429
430 /* Issue write command. */
431 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD);
432
433 /* Wait for the write command bit to self-clear. */
434 for (i = 0; i < VGE_TIMEOUT; i++) {
435 DELAY(1);
436 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0)
437 break;
438 }
439
440 if (i == VGE_TIMEOUT) {
441 device_printf(sc->vge_dev, "MII write timed out\n");
442 rval = EIO;
443 }
444
445 vge_miipoll_start(sc);
446 VGE_UNLOCK(sc);
447
448 return (rval);
449}
450
451static void
452vge_cam_clear(sc)
453 struct vge_softc *sc;
454{
455 int i;
456
457 /*
458 * Turn off all the mask bits. This tells the chip
459 * that none of the entries in the CAM filter are valid.
460 * desired entries will be enabled as we fill the filter in.
461 */
462
463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
465 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE);
466 for (i = 0; i < 8; i++)
467 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
468
469 /* Clear the VLAN filter too. */
470
471 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0);
472 for (i = 0; i < 8; i++)
473 CSR_WRITE_1(sc, VGE_CAM0 + i, 0);
474
475 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
476 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
478
479 sc->vge_camidx = 0;
480
481 return;
482}
483
484static int
485vge_cam_set(sc, addr)
486 struct vge_softc *sc;
487 uint8_t *addr;
488{
489 int i, error = 0;
490
491 if (sc->vge_camidx == VGE_CAM_MAXADDRS)
492 return(ENOSPC);
493
494 /* Select the CAM data page. */
495 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
496 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA);
497
498 /* Set the filter entry we want to update and enable writing. */
499 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx);
500
501 /* Write the address to the CAM registers */
502 for (i = 0; i < ETHER_ADDR_LEN; i++)
503 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]);
504
505 /* Issue a write command. */
506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE);
507
508 /* Wake for it to clear. */
509 for (i = 0; i < VGE_TIMEOUT; i++) {
510 DELAY(1);
511 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0)
512 break;
513 }
514
515 if (i == VGE_TIMEOUT) {
516 device_printf(sc->vge_dev, "setting CAM filter failed\n");
517 error = EIO;
518 goto fail;
519 }
520
521 /* Select the CAM mask page. */
522 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
523 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK);
524
525 /* Set the mask bit that enables this filter. */
526 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8),
527 1<<(sc->vge_camidx & 7));
528
529 sc->vge_camidx++;
530
531fail:
532 /* Turn off access to CAM. */
533 CSR_WRITE_1(sc, VGE_CAMADDR, 0);
534 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
535 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
536
537 return (error);
538}
539
540#if __FreeBSD_version < 502113
541static uint32_t
542vge_mchash(addr)
543 uint8_t *addr;
544{
545 uint32_t crc, carry;
546 int idx, bit;
547 uint8_t data;
548
549 /* Compute CRC for the address value. */
550 crc = 0xFFFFFFFF; /* initial value */
551
552 for (idx = 0; idx < 6; idx++) {
553 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) {
554 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
555 crc <<= 1;
556 if (carry)
557 crc = (crc ^ 0x04c11db6) | carry;
558 }
559 }
560
561 return(crc);
562}
563#endif
564
565/*
566 * Program the multicast filter. We use the 64-entry CAM filter
567 * for perfect filtering. If there's more than 64 multicast addresses,
568 * we use the hash filter insted.
569 */
570static void
571vge_setmulti(sc)
572 struct vge_softc *sc;
573{
574 struct ifnet *ifp;
575 int error = 0/*, h = 0*/;
576 struct ifmultiaddr *ifma;
577 u_int32_t h, hashes[2] = { 0, 0 };
578
579 ifp = sc->vge_ifp;
580
581 /* First, zot all the multicast entries. */
582 vge_cam_clear(sc);
583 CSR_WRITE_4(sc, VGE_MAR0, 0);
584 CSR_WRITE_4(sc, VGE_MAR1, 0);
585
586 /*
587 * If the user wants allmulti or promisc mode, enable reception
588 * of all multicast frames.
589 */
590 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
591 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF);
592 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF);
593 return;
594 }
595
596 /* Now program new ones */
|
629
630 return;
631}
632
633static void
634vge_reset(sc)
635 struct vge_softc *sc;
636{
637 register int i;
638
639 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
640
641 for (i = 0; i < VGE_TIMEOUT; i++) {
642 DELAY(5);
643 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
644 break;
645 }
646
647 if (i == VGE_TIMEOUT) {
648 device_printf(sc->vge_dev, "soft reset timed out");
649 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
650 DELAY(2000);
651 }
652
653 DELAY(5000);
654
655 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
656
657 for (i = 0; i < VGE_TIMEOUT; i++) {
658 DELAY(5);
659 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
660 break;
661 }
662
663 if (i == VGE_TIMEOUT) {
664 device_printf(sc->vge_dev, "EEPROM reload timed out\n");
665 return;
666 }
667
668 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
669
670 return;
671}
672
673/*
674 * Probe for a VIA gigabit chip. Check the PCI vendor and device
675 * IDs against our list and return a device name if we find a match.
676 */
677static int
678vge_probe(dev)
679 device_t dev;
680{
681 struct vge_type *t;
682 struct vge_softc *sc;
683
684 t = vge_devs;
685 sc = device_get_softc(dev);
686
687 while (t->vge_name != NULL) {
688 if ((pci_get_vendor(dev) == t->vge_vid) &&
689 (pci_get_device(dev) == t->vge_did)) {
690 device_set_desc(dev, t->vge_name);
691 return (BUS_PROBE_DEFAULT);
692 }
693 t++;
694 }
695
696 return (ENXIO);
697}
698
699static void
700vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error)
701 void *arg;
702 bus_dma_segment_t *segs;
703 int nseg;
704 bus_size_t mapsize;
705 int error;
706{
707
708 struct vge_dmaload_arg *ctx;
709 struct vge_rx_desc *d = NULL;
710
711 if (error)
712 return;
713
714 ctx = arg;
715
716 /* Signal error to caller if there's too many segments */
717 if (nseg > ctx->vge_maxsegs) {
718 ctx->vge_maxsegs = 0;
719 return;
720 }
721
722 /*
723 * Map the segment array into descriptors.
724 */
725
726 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx];
727
728 /* If this descriptor is still owned by the chip, bail. */
729
730 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) {
731 device_printf(ctx->sc->vge_dev,
732 "tried to map busy descriptor\n");
733 ctx->vge_maxsegs = 0;
734 return;
735 }
736
737 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I);
738 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
739 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF);
740 d->vge_sts = 0;
741 d->vge_ctl = 0;
742
743 ctx->vge_maxsegs = 1;
744
745 return;
746}
747
748static void
749vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error)
750 void *arg;
751 bus_dma_segment_t *segs;
752 int nseg;
753 bus_size_t mapsize;
754 int error;
755{
756 struct vge_dmaload_arg *ctx;
757 struct vge_tx_desc *d = NULL;
758 struct vge_tx_frag *f;
759 int i = 0;
760
761 if (error)
762 return;
763
764 ctx = arg;
765
766 /* Signal error to caller if there's too many segments */
767 if (nseg > ctx->vge_maxsegs) {
768 ctx->vge_maxsegs = 0;
769 return;
770 }
771
772 /* Map the segment array into descriptors. */
773
774 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx];
775
776 /* If this descriptor is still owned by the chip, bail. */
777
778 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) {
779 ctx->vge_maxsegs = 0;
780 return;
781 }
782
783 for (i = 0; i < nseg; i++) {
784 f = &d->vge_frag[i];
785 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len));
786 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr));
787 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF);
788 }
789
790 /* Argh. This chip does not autopad short frames */
791
792 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) {
793 f = &d->vge_frag[i];
794 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN -
795 ctx->vge_m0->m_pkthdr.len));
796 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
797 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF);
798 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN;
799 i++;
800 }
801
802 /*
803 * When telling the chip how many segments there are, we
804 * must use nsegs + 1 instead of just nsegs. Darned if I
805 * know why.
806 */
807 i++;
808
809 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16;
810 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM;
811
812 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN)
813 d->vge_ctl |= VGE_TDCTL_JUMBO;
814
815 ctx->vge_maxsegs = nseg;
816
817 return;
818}
819
820/*
821 * Map a single buffer address.
822 */
823
824static void
825vge_dma_map_addr(arg, segs, nseg, error)
826 void *arg;
827 bus_dma_segment_t *segs;
828 int nseg;
829 int error;
830{
831 bus_addr_t *addr;
832
833 if (error)
834 return;
835
836 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
837 addr = arg;
838 *addr = segs->ds_addr;
839
840 return;
841}
842
843static int
844vge_allocmem(dev, sc)
845 device_t dev;
846 struct vge_softc *sc;
847{
848 int error;
849 int nseg;
850 int i;
851
852 /*
853 * Allocate map for RX mbufs.
854 */
855 nseg = 32;
856 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0,
857 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
858 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
859 NULL, NULL, &sc->vge_ldata.vge_mtag);
860 if (error) {
861 device_printf(dev, "could not allocate dma tag\n");
862 return (ENOMEM);
863 }
864
865 /*
866 * Allocate map for TX descriptor list.
867 */
868 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN,
869 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
870 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
871 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag);
872 if (error) {
873 device_printf(dev, "could not allocate dma tag\n");
874 return (ENOMEM);
875 }
876
877 /* Allocate DMA'able memory for the TX ring */
878
879 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag,
880 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
881 &sc->vge_ldata.vge_tx_list_map);
882 if (error)
883 return (ENOMEM);
884
885 /* Load the map for the TX ring. */
886
887 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag,
888 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list,
889 VGE_TX_LIST_SZ, vge_dma_map_addr,
890 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT);
891
892 /* Create DMA maps for TX buffers */
893
894 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
895 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0,
896 &sc->vge_ldata.vge_tx_dmamap[i]);
897 if (error) {
898 device_printf(dev, "can't create DMA map for TX\n");
899 return (ENOMEM);
900 }
901 }
902
903 /*
904 * Allocate map for RX descriptor list.
905 */
906 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN,
907 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
908 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
909 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag);
910 if (error) {
911 device_printf(dev, "could not allocate dma tag\n");
912 return (ENOMEM);
913 }
914
915 /* Allocate DMA'able memory for the RX ring */
916
917 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag,
918 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
919 &sc->vge_ldata.vge_rx_list_map);
920 if (error)
921 return (ENOMEM);
922
923 /* Load the map for the RX ring. */
924
925 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag,
926 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list,
927 VGE_TX_LIST_SZ, vge_dma_map_addr,
928 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT);
929
930 /* Create DMA maps for RX buffers */
931
932 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
933 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0,
934 &sc->vge_ldata.vge_rx_dmamap[i]);
935 if (error) {
936 device_printf(dev, "can't create DMA map for RX\n");
937 return (ENOMEM);
938 }
939 }
940
941 return (0);
942}
943
944/*
945 * Attach the interface. Allocate softc structures, do ifmedia
946 * setup and ethernet/BPF attach.
947 */
948static int
949vge_attach(dev)
950 device_t dev;
951{
952 u_char eaddr[ETHER_ADDR_LEN];
953 struct vge_softc *sc;
954 struct ifnet *ifp;
955 int unit, error = 0, rid;
956
957 sc = device_get_softc(dev);
958 unit = device_get_unit(dev);
959 sc->vge_dev = dev;
960
961 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
962 MTX_DEF | MTX_RECURSE);
963 /*
964 * Map control/status registers.
965 */
966 pci_enable_busmaster(dev);
967
968 rid = VGE_PCI_LOMEM;
969 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
970 0, ~0, 1, RF_ACTIVE);
971
972 if (sc->vge_res == NULL) {
973 printf ("vge%d: couldn't map ports/memory\n", unit);
974 error = ENXIO;
975 goto fail;
976 }
977
978 sc->vge_btag = rman_get_bustag(sc->vge_res);
979 sc->vge_bhandle = rman_get_bushandle(sc->vge_res);
980
981 /* Allocate interrupt */
982 rid = 0;
983 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
984 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
985
986 if (sc->vge_irq == NULL) {
987 printf("vge%d: couldn't map interrupt\n", unit);
988 error = ENXIO;
989 goto fail;
990 }
991
992 /* Reset the adapter. */
993 vge_reset(sc);
994
995 /*
996 * Get station address from the EEPROM.
997 */
998 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0);
999
1000 sc->vge_unit = unit;
1001
1002#if __FreeBSD_version < 502113
1003 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":");
1004#endif
1005
1006 /*
1007 * Allocate the parent bus DMA tag appropriate for PCI.
1008 */
1009#define VGE_NSEG_NEW 32
1010 error = bus_dma_tag_create(NULL, /* parent */
1011 1, 0, /* alignment, boundary */
1012 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1013 BUS_SPACE_MAXADDR, /* highaddr */
1014 NULL, NULL, /* filter, filterarg */
1015 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */
1016 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1017 BUS_DMA_ALLOCNOW, /* flags */
1018 NULL, NULL, /* lockfunc, lockarg */
1019 &sc->vge_parent_tag);
1020 if (error)
1021 goto fail;
1022
1023 error = vge_allocmem(dev, sc);
1024
1025 if (error)
1026 goto fail;
1027
1028 ifp = sc->vge_ifp = if_alloc(IFT_ETHER);
1029 if (ifp == NULL) {
1030 printf("vge%d: can not if_alloc()\n", sc->vge_unit);
1031 error = ENOSPC;
1032 goto fail;
1033 }
1034
1035 /* Do MII setup */
1036 if (mii_phy_probe(dev, &sc->vge_miibus,
1037 vge_ifmedia_upd, vge_ifmedia_sts)) {
1038 printf("vge%d: MII without any phy!\n", sc->vge_unit);
1039 error = ENXIO;
1040 goto fail;
1041 }
1042
1043 ifp->if_softc = sc;
1044 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1045 ifp->if_mtu = ETHERMTU;
1046 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1047 ifp->if_ioctl = vge_ioctl;
1048 ifp->if_capabilities = IFCAP_VLAN_MTU;
1049 ifp->if_start = vge_start;
1050 ifp->if_hwassist = VGE_CSUM_FEATURES;
1051 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1052#ifdef DEVICE_POLLING
1053#ifdef IFCAP_POLLING
1054 ifp->if_capabilities |= IFCAP_POLLING;
1055#endif
1056#endif
1057 ifp->if_watchdog = vge_watchdog;
1058 ifp->if_init = vge_init;
1059 ifp->if_baudrate = 1000000000;
1060 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN;
1061 ifp->if_capenable = ifp->if_capabilities;
1062
1063 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp);
1064
1065 /*
1066 * Call MI attach routine.
1067 */
1068 ether_ifattach(ifp, eaddr);
1069
1070 /* Hook interrupt last to avoid having to lock softc */
1071 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE,
1072 vge_intr, sc, &sc->vge_intrhand);
1073
1074 if (error) {
1075 printf("vge%d: couldn't set up irq\n", unit);
1076 ether_ifdetach(ifp);
1077 goto fail;
1078 }
1079
1080fail:
1081 if (error)
1082 vge_detach(dev);
1083
1084 return (error);
1085}
1086
1087/*
1088 * Shutdown hardware and free up resources. This can be called any
1089 * time after the mutex has been initialized. It is called in both
1090 * the error case in attach and the normal detach case so it needs
1091 * to be careful about only freeing resources that have actually been
1092 * allocated.
1093 */
1094static int
1095vge_detach(dev)
1096 device_t dev;
1097{
1098 struct vge_softc *sc;
1099 struct ifnet *ifp;
1100 int i;
1101
1102 sc = device_get_softc(dev);
1103 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized"));
1104 ifp = sc->vge_ifp;
1105
1106 /* These should only be active if attach succeeded */
1107 if (device_is_attached(dev)) {
1108 vge_stop(sc);
1109 /*
1110 * Force off the IFF_UP flag here, in case someone
1111 * still had a BPF descriptor attached to this
1112 * interface. If they do, ether_ifattach() will cause
1113 * the BPF code to try and clear the promisc mode
1114 * flag, which will bubble down to vge_ioctl(),
1115 * which will try to call vge_init() again. This will
1116 * turn the NIC back on and restart the MII ticker,
1117 * which will panic the system when the kernel tries
1118 * to invoke the vge_tick() function that isn't there
1119 * anymore.
1120 */
1121 ifp->if_flags &= ~IFF_UP;
1122 ether_ifdetach(ifp);
1123 if_free(ifp);
1124 }
1125 if (sc->vge_miibus)
1126 device_delete_child(dev, sc->vge_miibus);
1127 bus_generic_detach(dev);
1128
1129 if (sc->vge_intrhand)
1130 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand);
1131 if (sc->vge_irq)
1132 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq);
1133 if (sc->vge_res)
1134 bus_release_resource(dev, SYS_RES_MEMORY,
1135 VGE_PCI_LOMEM, sc->vge_res);
1136
1137 /* Unload and free the RX DMA ring memory and map */
1138
1139 if (sc->vge_ldata.vge_rx_list_tag) {
1140 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag,
1141 sc->vge_ldata.vge_rx_list_map);
1142 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag,
1143 sc->vge_ldata.vge_rx_list,
1144 sc->vge_ldata.vge_rx_list_map);
1145 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag);
1146 }
1147
1148 /* Unload and free the TX DMA ring memory and map */
1149
1150 if (sc->vge_ldata.vge_tx_list_tag) {
1151 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag,
1152 sc->vge_ldata.vge_tx_list_map);
1153 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag,
1154 sc->vge_ldata.vge_tx_list,
1155 sc->vge_ldata.vge_tx_list_map);
1156 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag);
1157 }
1158
1159 /* Destroy all the RX and TX buffer maps */
1160
1161 if (sc->vge_ldata.vge_mtag) {
1162 for (i = 0; i < VGE_TX_DESC_CNT; i++)
1163 bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
1164 sc->vge_ldata.vge_tx_dmamap[i]);
1165 for (i = 0; i < VGE_RX_DESC_CNT; i++)
1166 bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
1167 sc->vge_ldata.vge_rx_dmamap[i]);
1168 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag);
1169 }
1170
1171 if (sc->vge_parent_tag)
1172 bus_dma_tag_destroy(sc->vge_parent_tag);
1173
1174 mtx_destroy(&sc->vge_mtx);
1175
1176 return (0);
1177}
1178
1179static int
1180vge_newbuf(sc, idx, m)
1181 struct vge_softc *sc;
1182 int idx;
1183 struct mbuf *m;
1184{
1185 struct vge_dmaload_arg arg;
1186 struct mbuf *n = NULL;
1187 int i, error;
1188
1189 if (m == NULL) {
1190 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1191 if (n == NULL)
1192 return (ENOBUFS);
1193 m = n;
1194 } else
1195 m->m_data = m->m_ext.ext_buf;
1196
1197
1198#ifdef VGE_FIXUP_RX
1199 /*
1200 * This is part of an evil trick to deal with non-x86 platforms.
1201 * The VIA chip requires RX buffers to be aligned on 32-bit
1202 * boundaries, but that will hose non-x86 machines. To get around
1203 * this, we leave some empty space at the start of each buffer
1204 * and for non-x86 hosts, we copy the buffer back two bytes
1205 * to achieve word alignment. This is slightly more efficient
1206 * than allocating a new buffer, copying the contents, and
1207 * discarding the old buffer.
1208 */
1209 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN;
1210 m_adj(m, VGE_ETHER_ALIGN);
1211#else
1212 m->m_len = m->m_pkthdr.len = MCLBYTES;
1213#endif
1214
1215 arg.sc = sc;
1216 arg.vge_idx = idx;
1217 arg.vge_maxsegs = 1;
1218 arg.vge_flags = 0;
1219
1220 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag,
1221 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc,
1222 &arg, BUS_DMA_NOWAIT);
1223 if (error || arg.vge_maxsegs != 1) {
1224 if (n != NULL)
1225 m_freem(n);
1226 return (ENOMEM);
1227 }
1228
1229 /*
1230 * Note: the manual fails to document the fact that for
1231 * proper opration, the driver needs to replentish the RX
1232 * DMA ring 4 descriptors at a time (rather than one at a
1233 * time, like most chips). We can allocate the new buffers
1234 * but we should not set the OWN bits until we're ready
1235 * to hand back 4 of them in one shot.
1236 */
1237
1238#define VGE_RXCHUNK 4
1239 sc->vge_rx_consumed++;
1240 if (sc->vge_rx_consumed == VGE_RXCHUNK) {
1241 for (i = idx; i != idx - sc->vge_rx_consumed; i--)
1242 sc->vge_ldata.vge_rx_list[i].vge_sts |=
1243 htole32(VGE_RDSTS_OWN);
1244 sc->vge_rx_consumed = 0;
1245 }
1246
1247 sc->vge_ldata.vge_rx_mbuf[idx] = m;
1248
1249 bus_dmamap_sync(sc->vge_ldata.vge_mtag,
1250 sc->vge_ldata.vge_rx_dmamap[idx],
1251 BUS_DMASYNC_PREREAD);
1252
1253 return (0);
1254}
1255
1256static int
1257vge_tx_list_init(sc)
1258 struct vge_softc *sc;
1259{
1260 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ);
1261 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf,
1262 (VGE_TX_DESC_CNT * sizeof(struct mbuf *)));
1263
1264 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1265 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE);
1266 sc->vge_ldata.vge_tx_prodidx = 0;
1267 sc->vge_ldata.vge_tx_considx = 0;
1268 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT;
1269
1270 return (0);
1271}
1272
1273static int
1274vge_rx_list_init(sc)
1275 struct vge_softc *sc;
1276{
1277 int i;
1278
1279 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ);
1280 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf,
1281 (VGE_RX_DESC_CNT * sizeof(struct mbuf *)));
1282
1283 sc->vge_rx_consumed = 0;
1284
1285 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
1286 if (vge_newbuf(sc, i, NULL) == ENOBUFS)
1287 return (ENOBUFS);
1288 }
1289
1290 /* Flush the RX descriptors */
1291
1292 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1293 sc->vge_ldata.vge_rx_list_map,
1294 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1295
1296 sc->vge_ldata.vge_rx_prodidx = 0;
1297 sc->vge_rx_consumed = 0;
1298 sc->vge_head = sc->vge_tail = NULL;
1299
1300 return (0);
1301}
1302
1303#ifdef VGE_FIXUP_RX
1304static __inline void
1305vge_fixup_rx(m)
1306 struct mbuf *m;
1307{
1308 int i;
1309 uint16_t *src, *dst;
1310
1311 src = mtod(m, uint16_t *);
1312 dst = src - 1;
1313
1314 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1315 *dst++ = *src++;
1316
1317 m->m_data -= ETHER_ALIGN;
1318
1319 return;
1320}
1321#endif
1322
1323/*
1324 * RX handler. We support the reception of jumbo frames that have
1325 * been fragmented across multiple 2K mbuf cluster buffers.
1326 */
1327static void
1328vge_rxeof(sc)
1329 struct vge_softc *sc;
1330{
1331 struct mbuf *m;
1332 struct ifnet *ifp;
1333 int i, total_len;
1334 int lim = 0;
1335 struct vge_rx_desc *cur_rx;
1336 u_int32_t rxstat, rxctl;
1337
1338 VGE_LOCK_ASSERT(sc);
1339 ifp = sc->vge_ifp;
1340 i = sc->vge_ldata.vge_rx_prodidx;
1341
1342 /* Invalidate the descriptor memory */
1343
1344 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1345 sc->vge_ldata.vge_rx_list_map,
1346 BUS_DMASYNC_POSTREAD);
1347
1348 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) {
1349
1350#ifdef DEVICE_POLLING
1351 if (ifp->if_flags & IFF_POLLING) {
1352 if (sc->rxcycles <= 0)
1353 break;
1354 sc->rxcycles--;
1355 }
1356#endif /* DEVICE_POLLING */
1357
1358 cur_rx = &sc->vge_ldata.vge_rx_list[i];
1359 m = sc->vge_ldata.vge_rx_mbuf[i];
1360 total_len = VGE_RXBYTES(cur_rx);
1361 rxstat = le32toh(cur_rx->vge_sts);
1362 rxctl = le32toh(cur_rx->vge_ctl);
1363
1364 /* Invalidate the RX mbuf and unload its map */
1365
1366 bus_dmamap_sync(sc->vge_ldata.vge_mtag,
1367 sc->vge_ldata.vge_rx_dmamap[i],
1368 BUS_DMASYNC_POSTWRITE);
1369 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
1370 sc->vge_ldata.vge_rx_dmamap[i]);
1371
1372 /*
1373 * If the 'start of frame' bit is set, this indicates
1374 * either the first fragment in a multi-fragment receive,
1375 * or an intermediate fragment. Either way, we want to
1376 * accumulate the buffers.
1377 */
1378 if (rxstat & VGE_RXPKT_SOF) {
1379 m->m_len = MCLBYTES - VGE_ETHER_ALIGN;
1380 if (sc->vge_head == NULL)
1381 sc->vge_head = sc->vge_tail = m;
1382 else {
1383 m->m_flags &= ~M_PKTHDR;
1384 sc->vge_tail->m_next = m;
1385 sc->vge_tail = m;
1386 }
1387 vge_newbuf(sc, i, NULL);
1388 VGE_RX_DESC_INC(i);
1389 continue;
1390 }
1391
1392 /*
1393 * Bad/error frames will have the RXOK bit cleared.
1394 * However, there's one error case we want to allow:
1395 * if a VLAN tagged frame arrives and the chip can't
1396 * match it against the CAM filter, it considers this
1397 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1398 * We don't want to drop the frame though: our VLAN
1399 * filtering is done in software.
1400 */
1401 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM)
1402 && !(rxstat & VGE_RDSTS_CSUMERR)) {
1403 ifp->if_ierrors++;
1404 /*
1405 * If this is part of a multi-fragment packet,
1406 * discard all the pieces.
1407 */
1408 if (sc->vge_head != NULL) {
1409 m_freem(sc->vge_head);
1410 sc->vge_head = sc->vge_tail = NULL;
1411 }
1412 vge_newbuf(sc, i, m);
1413 VGE_RX_DESC_INC(i);
1414 continue;
1415 }
1416
1417 /*
1418 * If allocating a replacement mbuf fails,
1419 * reload the current one.
1420 */
1421
1422 if (vge_newbuf(sc, i, NULL)) {
1423 ifp->if_ierrors++;
1424 if (sc->vge_head != NULL) {
1425 m_freem(sc->vge_head);
1426 sc->vge_head = sc->vge_tail = NULL;
1427 }
1428 vge_newbuf(sc, i, m);
1429 VGE_RX_DESC_INC(i);
1430 continue;
1431 }
1432
1433 VGE_RX_DESC_INC(i);
1434
1435 if (sc->vge_head != NULL) {
1436 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN);
1437 /*
1438 * Special case: if there's 4 bytes or less
1439 * in this buffer, the mbuf can be discarded:
1440 * the last 4 bytes is the CRC, which we don't
1441 * care about anyway.
1442 */
1443 if (m->m_len <= ETHER_CRC_LEN) {
1444 sc->vge_tail->m_len -=
1445 (ETHER_CRC_LEN - m->m_len);
1446 m_freem(m);
1447 } else {
1448 m->m_len -= ETHER_CRC_LEN;
1449 m->m_flags &= ~M_PKTHDR;
1450 sc->vge_tail->m_next = m;
1451 }
1452 m = sc->vge_head;
1453 sc->vge_head = sc->vge_tail = NULL;
1454 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1455 } else
1456 m->m_pkthdr.len = m->m_len =
1457 (total_len - ETHER_CRC_LEN);
1458
1459#ifdef VGE_FIXUP_RX
1460 vge_fixup_rx(m);
1461#endif
1462 ifp->if_ipackets++;
1463 m->m_pkthdr.rcvif = ifp;
1464
1465 /* Do RX checksumming if enabled */
1466 if (ifp->if_capenable & IFCAP_RXCSUM) {
1467
1468 /* Check IP header checksum */
1469 if (rxctl & VGE_RDCTL_IPPKT)
1470 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1471 if (rxctl & VGE_RDCTL_IPCSUMOK)
1472 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1473
1474 /* Check TCP/UDP checksum */
1475 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) &&
1476 rxctl & VGE_RDCTL_PROTOCSUMOK) {
1477 m->m_pkthdr.csum_flags |=
1478 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1479 m->m_pkthdr.csum_data = 0xffff;
1480 }
1481 }
1482
1483 if (rxstat & VGE_RDSTS_VTAG)
1484 VLAN_INPUT_TAG(ifp, m,
1485 ntohs((rxctl & VGE_RDCTL_VLANID)), continue);
1486
1487 VGE_UNLOCK(sc);
1488 (*ifp->if_input)(ifp, m);
1489 VGE_LOCK(sc);
1490
1491 lim++;
1492 if (lim == VGE_RX_DESC_CNT)
1493 break;
1494
1495 }
1496
1497 /* Flush the RX DMA ring */
1498
1499 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1500 sc->vge_ldata.vge_rx_list_map,
1501 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1502
1503 sc->vge_ldata.vge_rx_prodidx = i;
1504 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1505
1506
1507 return;
1508}
1509
1510static void
1511vge_txeof(sc)
1512 struct vge_softc *sc;
1513{
1514 struct ifnet *ifp;
1515 u_int32_t txstat;
1516 int idx;
1517
1518 ifp = sc->vge_ifp;
1519 idx = sc->vge_ldata.vge_tx_considx;
1520
1521 /* Invalidate the TX descriptor list */
1522
1523 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1524 sc->vge_ldata.vge_tx_list_map,
1525 BUS_DMASYNC_POSTREAD);
1526
1527 while (idx != sc->vge_ldata.vge_tx_prodidx) {
1528
1529 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts);
1530 if (txstat & VGE_TDSTS_OWN)
1531 break;
1532
1533 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]);
1534 sc->vge_ldata.vge_tx_mbuf[idx] = NULL;
1535 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
1536 sc->vge_ldata.vge_tx_dmamap[idx]);
1537 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL))
1538 ifp->if_collisions++;
1539 if (txstat & VGE_TDSTS_TXERR)
1540 ifp->if_oerrors++;
1541 else
1542 ifp->if_opackets++;
1543
1544 sc->vge_ldata.vge_tx_free++;
1545 VGE_TX_DESC_INC(idx);
1546 }
1547
1548 /* No changes made to the TX ring, so no flush needed */
1549
1550 if (idx != sc->vge_ldata.vge_tx_considx) {
1551 sc->vge_ldata.vge_tx_considx = idx;
1552 ifp->if_flags &= ~IFF_OACTIVE;
1553 ifp->if_timer = 0;
1554 }
1555
1556 /*
1557 * If not all descriptors have been released reaped yet,
1558 * reload the timer so that we will eventually get another
1559 * interrupt that will cause us to re-enter this routine.
1560 * This is done in case the transmitter has gone idle.
1561 */
1562 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) {
1563 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1564 }
1565
1566 return;
1567}
1568
1569static void
1570vge_tick(xsc)
1571 void *xsc;
1572{
1573 struct vge_softc *sc;
1574 struct ifnet *ifp;
1575 struct mii_data *mii;
1576
1577 sc = xsc;
1578 ifp = sc->vge_ifp;
1579 VGE_LOCK(sc);
1580 mii = device_get_softc(sc->vge_miibus);
1581
1582 mii_tick(mii);
1583 if (sc->vge_link) {
1584 if (!(mii->mii_media_status & IFM_ACTIVE)) {
1585 sc->vge_link = 0;
1586 if_link_state_change(sc->vge_ifp,
1587 LINK_STATE_DOWN);
1588 }
1589 } else {
1590 if (mii->mii_media_status & IFM_ACTIVE &&
1591 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1592 sc->vge_link = 1;
1593 if_link_state_change(sc->vge_ifp,
1594 LINK_STATE_UP);
1595#if __FreeBSD_version < 502114
1596 if (ifp->if_snd.ifq_head != NULL)
1597#else
1598 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1599#endif
1600 taskqueue_enqueue(taskqueue_swi,
1601 &sc->vge_txtask);
1602 }
1603 }
1604
1605 VGE_UNLOCK(sc);
1606
1607 return;
1608}
1609
1610#ifdef DEVICE_POLLING
1611static void
1612vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1613{
1614 struct vge_softc *sc = ifp->if_softc;
1615
1616 VGE_LOCK(sc);
1617#ifdef IFCAP_POLLING
1618 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1619 ether_poll_deregister(ifp);
1620 cmd = POLL_DEREGISTER;
1621 }
1622#endif
1623 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1624 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
1625 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
1626 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1627 goto done;
1628 }
1629
1630 sc->rxcycles = count;
1631 vge_rxeof(sc);
1632 vge_txeof(sc);
1633
1634#if __FreeBSD_version < 502114
1635 if (ifp->if_snd.ifq_head != NULL)
1636#else
1637 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1638#endif
1639 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask);
1640
1641 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1642 u_int32_t status;
1643 status = CSR_READ_4(sc, VGE_ISR);
1644 if (status == 0xFFFFFFFF)
1645 goto done;
1646 if (status)
1647 CSR_WRITE_4(sc, VGE_ISR, status);
1648
1649 /*
1650 * XXX check behaviour on receiver stalls.
1651 */
1652
1653 if (status & VGE_ISR_TXDMA_STALL ||
1654 status & VGE_ISR_RXDMA_STALL)
1655 vge_init(sc);
1656
1657 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1658 vge_rxeof(sc);
1659 ifp->if_ierrors++;
1660 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1661 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1662 }
1663 }
1664done:
1665 VGE_UNLOCK(sc);
1666}
1667#endif /* DEVICE_POLLING */
1668
1669static void
1670vge_intr(arg)
1671 void *arg;
1672{
1673 struct vge_softc *sc;
1674 struct ifnet *ifp;
1675 u_int32_t status;
1676
1677 sc = arg;
1678
1679 if (sc->suspended) {
1680 return;
1681 }
1682
1683 VGE_LOCK(sc);
1684 ifp = sc->vge_ifp;
1685
1686 if (!(ifp->if_flags & IFF_UP)) {
1687 VGE_UNLOCK(sc);
1688 return;
1689 }
1690
1691#ifdef DEVICE_POLLING
1692 if (ifp->if_flags & IFF_POLLING)
1693 goto done;
1694 if (
1695#ifdef IFCAP_POLLING
1696 (ifp->if_capenable & IFCAP_POLLING) &&
1697#endif
1698 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */
1699 CSR_WRITE_4(sc, VGE_IMR, 0);
1700 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1701 vge_poll(ifp, 0, 1);
1702 goto done;
1703 }
1704
1705#endif /* DEVICE_POLLING */
1706
1707 /* Disable interrupts */
1708 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1709
1710 for (;;) {
1711
1712 status = CSR_READ_4(sc, VGE_ISR);
1713 /* If the card has gone away the read returns 0xffff. */
1714 if (status == 0xFFFFFFFF)
1715 break;
1716
1717 if (status)
1718 CSR_WRITE_4(sc, VGE_ISR, status);
1719
1720 if ((status & VGE_INTRS) == 0)
1721 break;
1722
1723 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO))
1724 vge_rxeof(sc);
1725
1726 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1727 vge_rxeof(sc);
1728 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1729 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1730 }
1731
1732 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0))
1733 vge_txeof(sc);
1734
1735 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL))
1736 vge_init(sc);
1737
1738 if (status & VGE_ISR_LINKSTS)
1739 vge_tick(sc);
1740 }
1741
1742 /* Re-enable interrupts */
1743 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1744
1745#ifdef DEVICE_POLLING
1746done:
1747#endif
1748 VGE_UNLOCK(sc);
1749
1750#if __FreeBSD_version < 502114
1751 if (ifp->if_snd.ifq_head != NULL)
1752#else
1753 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1754#endif
1755 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask);
1756
1757 return;
1758}
1759
1760static int
1761vge_encap(sc, m_head, idx)
1762 struct vge_softc *sc;
1763 struct mbuf *m_head;
1764 int idx;
1765{
1766 struct mbuf *m_new = NULL;
1767 struct vge_dmaload_arg arg;
1768 bus_dmamap_t map;
1769 int error;
1770 struct m_tag *mtag;
1771
1772 if (sc->vge_ldata.vge_tx_free <= 2)
1773 return (EFBIG);
1774
1775 arg.vge_flags = 0;
1776
1777 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1778 arg.vge_flags |= VGE_TDCTL_IPCSUM;
1779 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1780 arg.vge_flags |= VGE_TDCTL_TCPCSUM;
1781 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1782 arg.vge_flags |= VGE_TDCTL_UDPCSUM;
1783
1784 arg.sc = sc;
1785 arg.vge_idx = idx;
1786 arg.vge_m0 = m_head;
1787 arg.vge_maxsegs = VGE_TX_FRAGS;
1788
1789 map = sc->vge_ldata.vge_tx_dmamap[idx];
1790 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map,
1791 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT);
1792
1793 if (error && error != EFBIG) {
1794 printf("vge%d: can't map mbuf (error %d)\n",
1795 sc->vge_unit, error);
1796 return (ENOBUFS);
1797 }
1798
1799 /* Too many segments to map, coalesce into a single mbuf */
1800
1801 if (error || arg.vge_maxsegs == 0) {
1802 m_new = m_defrag(m_head, M_DONTWAIT);
1803 if (m_new == NULL)
1804 return (1);
1805 else
1806 m_head = m_new;
1807
1808 arg.sc = sc;
1809 arg.vge_m0 = m_head;
1810 arg.vge_idx = idx;
1811 arg.vge_maxsegs = 1;
1812
1813 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map,
1814 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT);
1815 if (error) {
1816 printf("vge%d: can't map mbuf (error %d)\n",
1817 sc->vge_unit, error);
1818 return (EFBIG);
1819 }
1820 }
1821
1822 sc->vge_ldata.vge_tx_mbuf[idx] = m_head;
1823 sc->vge_ldata.vge_tx_free--;
1824
1825 /*
1826 * Set up hardware VLAN tagging.
1827 */
1828
1829 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head);
1830 if (mtag != NULL)
1831 sc->vge_ldata.vge_tx_list[idx].vge_ctl |=
1832 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG);
1833
1834 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN);
1835
1836 return (0);
1837}
1838
1839static void
1840vge_tx_task(arg, npending)
1841 void *arg;
1842 int npending;
1843{
1844 struct ifnet *ifp;
1845
1846 ifp = arg;
1847 vge_start(ifp);
1848
1849 return;
1850}
1851
1852/*
1853 * Main transmit routine.
1854 */
1855
1856static void
1857vge_start(ifp)
1858 struct ifnet *ifp;
1859{
1860 struct vge_softc *sc;
1861 struct mbuf *m_head = NULL;
1862 int idx, pidx = 0;
1863
1864 sc = ifp->if_softc;
1865 VGE_LOCK(sc);
1866
1867 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) {
1868 VGE_UNLOCK(sc);
1869 return;
1870 }
1871
1872#if __FreeBSD_version < 502114
1873 if (ifp->if_snd.ifq_head == NULL) {
1874#else
1875 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
1876#endif
1877 VGE_UNLOCK(sc);
1878 return;
1879 }
1880
1881 idx = sc->vge_ldata.vge_tx_prodidx;
1882
1883 pidx = idx - 1;
1884 if (pidx < 0)
1885 pidx = VGE_TX_DESC_CNT - 1;
1886
1887
1888 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) {
1889#if __FreeBSD_version < 502114
1890 IF_DEQUEUE(&ifp->if_snd, m_head);
1891#else
1892 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1893#endif
1894 if (m_head == NULL)
1895 break;
1896
1897 if (vge_encap(sc, m_head, idx)) {
1898#if __FreeBSD_version >= 502114
1899 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1900#else
1901 IF_PREPEND(&ifp->if_snd, m_head);
1902#endif
1903 ifp->if_flags |= IFF_OACTIVE;
1904 break;
1905 }
1906
1907 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |=
1908 htole16(VGE_TXDESC_Q);
1909
1910 pidx = idx;
1911 VGE_TX_DESC_INC(idx);
1912
1913 /*
1914 * If there's a BPF listener, bounce a copy of this frame
1915 * to him.
1916 */
1917 BPF_MTAP(ifp, m_head);
1918 }
1919
1920 if (idx == sc->vge_ldata.vge_tx_prodidx) {
1921 VGE_UNLOCK(sc);
1922 return;
1923 }
1924
1925 /* Flush the TX descriptors */
1926
1927 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1928 sc->vge_ldata.vge_tx_list_map,
1929 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1930
1931 /* Issue a transmit command. */
1932 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1933
1934 sc->vge_ldata.vge_tx_prodidx = idx;
1935
1936 /*
1937 * Use the countdown timer for interrupt moderation.
1938 * 'TX done' interrupts are disabled. Instead, we reset the
1939 * countdown timer, which will begin counting until it hits
1940 * the value in the SSTIMER register, and then trigger an
1941 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1942 * the timer count is reloaded. Only when the transmitter
1943 * is idle will the timer hit 0 and an interrupt fire.
1944 */
1945 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1946
1947 VGE_UNLOCK(sc);
1948
1949 /*
1950 * Set a timeout in case the chip goes out to lunch.
1951 */
1952 ifp->if_timer = 5;
1953
1954 return;
1955}
1956
1957static void
1958vge_init(xsc)
1959 void *xsc;
1960{
1961 struct vge_softc *sc = xsc;
1962 struct ifnet *ifp = sc->vge_ifp;
1963 struct mii_data *mii;
1964 int i;
1965
1966 VGE_LOCK(sc);
1967 mii = device_get_softc(sc->vge_miibus);
1968
1969 /*
1970 * Cancel pending I/O and free all RX/TX buffers.
1971 */
1972 vge_stop(sc);
1973 vge_reset(sc);
1974
1975 /*
1976 * Initialize the RX and TX descriptors and mbufs.
1977 */
1978
1979 vge_rx_list_init(sc);
1980 vge_tx_list_init(sc);
1981
1982 /* Set our station address */
1983 for (i = 0; i < ETHER_ADDR_LEN; i++)
1984 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]);
1985
1986 /*
1987 * Set receive FIFO threshold. Also allow transmission and
1988 * reception of VLAN tagged frames.
1989 */
1990 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT);
1991 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2);
1992
1993 /* Set DMA burst length */
1994 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
1995 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
1996
1997 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
1998
1999 /* Set collision backoff algorithm */
2000 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
2001 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT);
2002 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2003
2004 /* Disable LPSEL field in priority resolution */
2005 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2006
2007 /*
2008 * Load the addresses of the DMA queues into the chip.
2009 * Note that we only use one transmit queue.
2010 */
2011
2012 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
2013 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr));
2014 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
2015
2016 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
2017 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr));
2018 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
2019 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
2020
2021 /* Enable and wake up the RX descriptor queue */
2022 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
2023 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
2024
2025 /* Enable the TX descriptor queue */
2026 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
2027
2028 /* Set up the receive filter -- allow large frames for VLANs. */
2029 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT);
2030
2031 /* If we want promiscuous mode, set the allframes bit. */
2032 if (ifp->if_flags & IFF_PROMISC) {
2033 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
2034 }
2035
2036 /* Set capture broadcast bit to capture broadcast frames. */
2037 if (ifp->if_flags & IFF_BROADCAST) {
2038 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
2039 }
2040
2041 /* Set multicast bit to capture multicast frames. */
2042 if (ifp->if_flags & IFF_MULTICAST) {
2043 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
2044 }
2045
2046 /* Init the cam filter. */
2047 vge_cam_clear(sc);
2048
2049 /* Init the multicast filter. */
2050 vge_setmulti(sc);
2051
2052 /* Enable flow control */
2053
2054 CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
2055
2056 /* Enable jumbo frame reception (if desired) */
2057
2058 /* Start the MAC. */
2059 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
2060 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
2061 CSR_WRITE_1(sc, VGE_CRS0,
2062 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START);
2063
2064 /*
2065 * Configure one-shot timer for microsecond
2066 * resulution and load it for 500 usecs.
2067 */
2068 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
2069 CSR_WRITE_2(sc, VGE_SSTIMER, 400);
2070
2071 /*
2072 * Configure interrupt moderation for receive. Enable
2073 * the holdoff counter and load it, and set the RX
2074 * suppression count to the number of descriptors we
2075 * want to allow before triggering an interrupt.
2076 * The holdoff timer is in units of 20 usecs.
2077 */
2078
2079#ifdef notyet
2080 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
2081 /* Select the interrupt holdoff timer page. */
2082 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
2083 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
2084 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
2085
2086 /* Enable use of the holdoff timer. */
2087 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
2088 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
2089
2090 /* Select the RX suppression threshold page. */
2091 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
2092 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
2093 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
2094
2095 /* Restore the page select bits. */
2096 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
2097 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
2098#endif
2099
2100#ifdef DEVICE_POLLING
2101 /*
2102 * Disable interrupts if we are polling.
2103 */
2104 if (ifp->if_flags & IFF_POLLING) {
2105 CSR_WRITE_4(sc, VGE_IMR, 0);
2106 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2107 } else /* otherwise ... */
2108#endif /* DEVICE_POLLING */
2109 {
2110 /*
2111 * Enable interrupts.
2112 */
2113 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2114 CSR_WRITE_4(sc, VGE_ISR, 0);
2115 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2116 }
2117
2118 mii_mediachg(mii);
2119
2120 ifp->if_flags |= IFF_RUNNING;
2121 ifp->if_flags &= ~IFF_OACTIVE;
2122
2123 sc->vge_if_flags = 0;
2124 sc->vge_link = 0;
2125
2126 VGE_UNLOCK(sc);
2127
2128 return;
2129}
2130
2131/*
2132 * Set media options.
2133 */
2134static int
2135vge_ifmedia_upd(ifp)
2136 struct ifnet *ifp;
2137{
2138 struct vge_softc *sc;
2139 struct mii_data *mii;
2140
2141 sc = ifp->if_softc;
2142 mii = device_get_softc(sc->vge_miibus);
2143 mii_mediachg(mii);
2144
2145 return (0);
2146}
2147
2148/*
2149 * Report current media status.
2150 */
2151static void
2152vge_ifmedia_sts(ifp, ifmr)
2153 struct ifnet *ifp;
2154 struct ifmediareq *ifmr;
2155{
2156 struct vge_softc *sc;
2157 struct mii_data *mii;
2158
2159 sc = ifp->if_softc;
2160 mii = device_get_softc(sc->vge_miibus);
2161
2162 mii_pollstat(mii);
2163 ifmr->ifm_active = mii->mii_media_active;
2164 ifmr->ifm_status = mii->mii_media_status;
2165
2166 return;
2167}
2168
2169static void
2170vge_miibus_statchg(dev)
2171 device_t dev;
2172{
2173 struct vge_softc *sc;
2174 struct mii_data *mii;
2175 struct ifmedia_entry *ife;
2176
2177 sc = device_get_softc(dev);
2178 mii = device_get_softc(sc->vge_miibus);
2179 ife = mii->mii_media.ifm_cur;
2180
2181 /*
2182 * If the user manually selects a media mode, we need to turn
2183 * on the forced MAC mode bit in the DIAGCTL register. If the
2184 * user happens to choose a full duplex mode, we also need to
2185 * set the 'force full duplex' bit. This applies only to
2186 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
2187 * mode is disabled, and in 1000baseT mode, full duplex is
2188 * always implied, so we turn on the forced mode bit but leave
2189 * the FDX bit cleared.
2190 */
2191
2192 switch (IFM_SUBTYPE(ife->ifm_media)) {
2193 case IFM_AUTO:
2194 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2195 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2196 break;
2197 case IFM_1000_T:
2198 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2199 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2200 break;
2201 case IFM_100_TX:
2202 case IFM_10_T:
2203 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2204 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
2205 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2206 } else {
2207 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2208 }
2209 break;
2210 default:
2211 device_printf(dev, "unknown media type: %x\n",
2212 IFM_SUBTYPE(ife->ifm_media));
2213 break;
2214 }
2215
2216 return;
2217}
2218
2219static int
2220vge_ioctl(ifp, command, data)
2221 struct ifnet *ifp;
2222 u_long command;
2223 caddr_t data;
2224{
2225 struct vge_softc *sc = ifp->if_softc;
2226 struct ifreq *ifr = (struct ifreq *) data;
2227 struct mii_data *mii;
2228 int error = 0;
2229
2230 switch (command) {
2231 case SIOCSIFMTU:
2232 if (ifr->ifr_mtu > VGE_JUMBO_MTU)
2233 error = EINVAL;
2234 ifp->if_mtu = ifr->ifr_mtu;
2235 break;
2236 case SIOCSIFFLAGS:
2237 if (ifp->if_flags & IFF_UP) {
2238 if (ifp->if_flags & IFF_RUNNING &&
2239 ifp->if_flags & IFF_PROMISC &&
2240 !(sc->vge_if_flags & IFF_PROMISC)) {
2241 CSR_SETBIT_1(sc, VGE_RXCTL,
2242 VGE_RXCTL_RX_PROMISC);
2243 vge_setmulti(sc);
2244 } else if (ifp->if_flags & IFF_RUNNING &&
2245 !(ifp->if_flags & IFF_PROMISC) &&
2246 sc->vge_if_flags & IFF_PROMISC) {
2247 CSR_CLRBIT_1(sc, VGE_RXCTL,
2248 VGE_RXCTL_RX_PROMISC);
2249 vge_setmulti(sc);
2250 } else
2251 vge_init(sc);
2252 } else {
2253 if (ifp->if_flags & IFF_RUNNING)
2254 vge_stop(sc);
2255 }
2256 sc->vge_if_flags = ifp->if_flags;
2257 break;
2258 case SIOCADDMULTI:
2259 case SIOCDELMULTI:
2260 vge_setmulti(sc);
2261 break;
2262 case SIOCGIFMEDIA:
2263 case SIOCSIFMEDIA:
2264 mii = device_get_softc(sc->vge_miibus);
2265 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2266 break;
2267 case SIOCSIFCAP:
2268#ifdef IFCAP_POLLING
2269 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2270#else
2271 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2272#endif
2273 ifp->if_capenable |=
2274#ifdef IFCAP_POLLING
2275 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2276#else
2277 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2278#endif
2279 if (ifp->if_capenable & IFCAP_TXCSUM)
2280 ifp->if_hwassist = VGE_CSUM_FEATURES;
2281 else
2282 ifp->if_hwassist = 0;
2283 if (ifp->if_flags & IFF_RUNNING)
2284 vge_init(sc);
2285 break;
2286 default:
2287 error = ether_ioctl(ifp, command, data);
2288 break;
2289 }
2290
2291 return (error);
2292}
2293
2294static void
2295vge_watchdog(ifp)
2296 struct ifnet *ifp;
2297{
2298 struct vge_softc *sc;
2299
2300 sc = ifp->if_softc;
2301 VGE_LOCK(sc);
2302 printf("vge%d: watchdog timeout\n", sc->vge_unit);
2303 ifp->if_oerrors++;
2304
2305 vge_txeof(sc);
2306 vge_rxeof(sc);
2307
2308 vge_init(sc);
2309
2310 VGE_UNLOCK(sc);
2311
2312 return;
2313}
2314
2315/*
2316 * Stop the adapter and free any mbufs allocated to the
2317 * RX and TX lists.
2318 */
2319static void
2320vge_stop(sc)
2321 struct vge_softc *sc;
2322{
2323 register int i;
2324 struct ifnet *ifp;
2325
2326 VGE_LOCK(sc);
2327 ifp = sc->vge_ifp;
2328 ifp->if_timer = 0;
2329
2330 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2331#ifdef DEVICE_POLLING
2332 ether_poll_deregister(ifp);
2333#endif /* DEVICE_POLLING */
2334
2335 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2336 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2337 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2338 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2339 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2340 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2341
2342 if (sc->vge_head != NULL) {
2343 m_freem(sc->vge_head);
2344 sc->vge_head = sc->vge_tail = NULL;
2345 }
2346
2347 /* Free the TX list buffers. */
2348
2349 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
2350 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) {
2351 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
2352 sc->vge_ldata.vge_tx_dmamap[i]);
2353 m_freem(sc->vge_ldata.vge_tx_mbuf[i]);
2354 sc->vge_ldata.vge_tx_mbuf[i] = NULL;
2355 }
2356 }
2357
2358 /* Free the RX list buffers. */
2359
2360 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
2361 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) {
2362 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
2363 sc->vge_ldata.vge_rx_dmamap[i]);
2364 m_freem(sc->vge_ldata.vge_rx_mbuf[i]);
2365 sc->vge_ldata.vge_rx_mbuf[i] = NULL;
2366 }
2367 }
2368
2369 VGE_UNLOCK(sc);
2370
2371 return;
2372}
2373
2374/*
2375 * Device suspend routine. Stop the interface and save some PCI
2376 * settings in case the BIOS doesn't restore them properly on
2377 * resume.
2378 */
2379static int
2380vge_suspend(dev)
2381 device_t dev;
2382{
2383 struct vge_softc *sc;
2384
2385 sc = device_get_softc(dev);
2386
2387 vge_stop(sc);
2388
2389 sc->suspended = 1;
2390
2391 return (0);
2392}
2393
2394/*
2395 * Device resume routine. Restore some PCI settings in case the BIOS
2396 * doesn't, re-enable busmastering, and restart the interface if
2397 * appropriate.
2398 */
2399static int
2400vge_resume(dev)
2401 device_t dev;
2402{
2403 struct vge_softc *sc;
2404 struct ifnet *ifp;
2405
2406 sc = device_get_softc(dev);
2407 ifp = sc->vge_ifp;
2408
2409 /* reenable busmastering */
2410 pci_enable_busmaster(dev);
2411 pci_enable_io(dev, SYS_RES_MEMORY);
2412
2413 /* reinitialize interface if necessary */
2414 if (ifp->if_flags & IFF_UP)
2415 vge_init(sc);
2416
2417 sc->suspended = 0;
2418
2419 return (0);
2420}
2421
2422/*
2423 * Stop all chip I/O so that the kernel's probe routines don't
2424 * get confused by errant DMAs when rebooting.
2425 */
2426static void
2427vge_shutdown(dev)
2428 device_t dev;
2429{
2430 struct vge_softc *sc;
2431
2432 sc = device_get_softc(dev);
2433
2434 vge_stop(sc);
2435}
| 631
632 return;
633}
634
635static void
636vge_reset(sc)
637 struct vge_softc *sc;
638{
639 register int i;
640
641 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET);
642
643 for (i = 0; i < VGE_TIMEOUT; i++) {
644 DELAY(5);
645 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0)
646 break;
647 }
648
649 if (i == VGE_TIMEOUT) {
650 device_printf(sc->vge_dev, "soft reset timed out");
651 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE);
652 DELAY(2000);
653 }
654
655 DELAY(5000);
656
657 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD);
658
659 for (i = 0; i < VGE_TIMEOUT; i++) {
660 DELAY(5);
661 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0)
662 break;
663 }
664
665 if (i == VGE_TIMEOUT) {
666 device_printf(sc->vge_dev, "EEPROM reload timed out\n");
667 return;
668 }
669
670 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI);
671
672 return;
673}
674
675/*
676 * Probe for a VIA gigabit chip. Check the PCI vendor and device
677 * IDs against our list and return a device name if we find a match.
678 */
679static int
680vge_probe(dev)
681 device_t dev;
682{
683 struct vge_type *t;
684 struct vge_softc *sc;
685
686 t = vge_devs;
687 sc = device_get_softc(dev);
688
689 while (t->vge_name != NULL) {
690 if ((pci_get_vendor(dev) == t->vge_vid) &&
691 (pci_get_device(dev) == t->vge_did)) {
692 device_set_desc(dev, t->vge_name);
693 return (BUS_PROBE_DEFAULT);
694 }
695 t++;
696 }
697
698 return (ENXIO);
699}
700
701static void
702vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error)
703 void *arg;
704 bus_dma_segment_t *segs;
705 int nseg;
706 bus_size_t mapsize;
707 int error;
708{
709
710 struct vge_dmaload_arg *ctx;
711 struct vge_rx_desc *d = NULL;
712
713 if (error)
714 return;
715
716 ctx = arg;
717
718 /* Signal error to caller if there's too many segments */
719 if (nseg > ctx->vge_maxsegs) {
720 ctx->vge_maxsegs = 0;
721 return;
722 }
723
724 /*
725 * Map the segment array into descriptors.
726 */
727
728 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx];
729
730 /* If this descriptor is still owned by the chip, bail. */
731
732 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) {
733 device_printf(ctx->sc->vge_dev,
734 "tried to map busy descriptor\n");
735 ctx->vge_maxsegs = 0;
736 return;
737 }
738
739 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I);
740 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
741 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF);
742 d->vge_sts = 0;
743 d->vge_ctl = 0;
744
745 ctx->vge_maxsegs = 1;
746
747 return;
748}
749
750static void
751vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error)
752 void *arg;
753 bus_dma_segment_t *segs;
754 int nseg;
755 bus_size_t mapsize;
756 int error;
757{
758 struct vge_dmaload_arg *ctx;
759 struct vge_tx_desc *d = NULL;
760 struct vge_tx_frag *f;
761 int i = 0;
762
763 if (error)
764 return;
765
766 ctx = arg;
767
768 /* Signal error to caller if there's too many segments */
769 if (nseg > ctx->vge_maxsegs) {
770 ctx->vge_maxsegs = 0;
771 return;
772 }
773
774 /* Map the segment array into descriptors. */
775
776 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx];
777
778 /* If this descriptor is still owned by the chip, bail. */
779
780 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) {
781 ctx->vge_maxsegs = 0;
782 return;
783 }
784
785 for (i = 0; i < nseg; i++) {
786 f = &d->vge_frag[i];
787 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len));
788 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr));
789 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF);
790 }
791
792 /* Argh. This chip does not autopad short frames */
793
794 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) {
795 f = &d->vge_frag[i];
796 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN -
797 ctx->vge_m0->m_pkthdr.len));
798 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr));
799 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF);
800 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN;
801 i++;
802 }
803
804 /*
805 * When telling the chip how many segments there are, we
806 * must use nsegs + 1 instead of just nsegs. Darned if I
807 * know why.
808 */
809 i++;
810
811 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16;
812 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM;
813
814 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN)
815 d->vge_ctl |= VGE_TDCTL_JUMBO;
816
817 ctx->vge_maxsegs = nseg;
818
819 return;
820}
821
822/*
823 * Map a single buffer address.
824 */
825
826static void
827vge_dma_map_addr(arg, segs, nseg, error)
828 void *arg;
829 bus_dma_segment_t *segs;
830 int nseg;
831 int error;
832{
833 bus_addr_t *addr;
834
835 if (error)
836 return;
837
838 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
839 addr = arg;
840 *addr = segs->ds_addr;
841
842 return;
843}
844
845static int
846vge_allocmem(dev, sc)
847 device_t dev;
848 struct vge_softc *sc;
849{
850 int error;
851 int nseg;
852 int i;
853
854 /*
855 * Allocate map for RX mbufs.
856 */
857 nseg = 32;
858 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0,
859 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
860 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW,
861 NULL, NULL, &sc->vge_ldata.vge_mtag);
862 if (error) {
863 device_printf(dev, "could not allocate dma tag\n");
864 return (ENOMEM);
865 }
866
867 /*
868 * Allocate map for TX descriptor list.
869 */
870 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN,
871 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
872 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
873 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag);
874 if (error) {
875 device_printf(dev, "could not allocate dma tag\n");
876 return (ENOMEM);
877 }
878
879 /* Allocate DMA'able memory for the TX ring */
880
881 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag,
882 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
883 &sc->vge_ldata.vge_tx_list_map);
884 if (error)
885 return (ENOMEM);
886
887 /* Load the map for the TX ring. */
888
889 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag,
890 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list,
891 VGE_TX_LIST_SZ, vge_dma_map_addr,
892 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT);
893
894 /* Create DMA maps for TX buffers */
895
896 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
897 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0,
898 &sc->vge_ldata.vge_tx_dmamap[i]);
899 if (error) {
900 device_printf(dev, "can't create DMA map for TX\n");
901 return (ENOMEM);
902 }
903 }
904
905 /*
906 * Allocate map for RX descriptor list.
907 */
908 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN,
909 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL,
910 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW,
911 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag);
912 if (error) {
913 device_printf(dev, "could not allocate dma tag\n");
914 return (ENOMEM);
915 }
916
917 /* Allocate DMA'able memory for the RX ring */
918
919 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag,
920 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO,
921 &sc->vge_ldata.vge_rx_list_map);
922 if (error)
923 return (ENOMEM);
924
925 /* Load the map for the RX ring. */
926
927 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag,
928 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list,
929 VGE_TX_LIST_SZ, vge_dma_map_addr,
930 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT);
931
932 /* Create DMA maps for RX buffers */
933
934 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
935 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0,
936 &sc->vge_ldata.vge_rx_dmamap[i]);
937 if (error) {
938 device_printf(dev, "can't create DMA map for RX\n");
939 return (ENOMEM);
940 }
941 }
942
943 return (0);
944}
945
946/*
947 * Attach the interface. Allocate softc structures, do ifmedia
948 * setup and ethernet/BPF attach.
949 */
950static int
951vge_attach(dev)
952 device_t dev;
953{
954 u_char eaddr[ETHER_ADDR_LEN];
955 struct vge_softc *sc;
956 struct ifnet *ifp;
957 int unit, error = 0, rid;
958
959 sc = device_get_softc(dev);
960 unit = device_get_unit(dev);
961 sc->vge_dev = dev;
962
963 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
964 MTX_DEF | MTX_RECURSE);
965 /*
966 * Map control/status registers.
967 */
968 pci_enable_busmaster(dev);
969
970 rid = VGE_PCI_LOMEM;
971 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
972 0, ~0, 1, RF_ACTIVE);
973
974 if (sc->vge_res == NULL) {
975 printf ("vge%d: couldn't map ports/memory\n", unit);
976 error = ENXIO;
977 goto fail;
978 }
979
980 sc->vge_btag = rman_get_bustag(sc->vge_res);
981 sc->vge_bhandle = rman_get_bushandle(sc->vge_res);
982
983 /* Allocate interrupt */
984 rid = 0;
985 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
986 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
987
988 if (sc->vge_irq == NULL) {
989 printf("vge%d: couldn't map interrupt\n", unit);
990 error = ENXIO;
991 goto fail;
992 }
993
994 /* Reset the adapter. */
995 vge_reset(sc);
996
997 /*
998 * Get station address from the EEPROM.
999 */
1000 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0);
1001
1002 sc->vge_unit = unit;
1003
1004#if __FreeBSD_version < 502113
1005 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":");
1006#endif
1007
1008 /*
1009 * Allocate the parent bus DMA tag appropriate for PCI.
1010 */
1011#define VGE_NSEG_NEW 32
1012 error = bus_dma_tag_create(NULL, /* parent */
1013 1, 0, /* alignment, boundary */
1014 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1015 BUS_SPACE_MAXADDR, /* highaddr */
1016 NULL, NULL, /* filter, filterarg */
1017 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */
1018 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1019 BUS_DMA_ALLOCNOW, /* flags */
1020 NULL, NULL, /* lockfunc, lockarg */
1021 &sc->vge_parent_tag);
1022 if (error)
1023 goto fail;
1024
1025 error = vge_allocmem(dev, sc);
1026
1027 if (error)
1028 goto fail;
1029
1030 ifp = sc->vge_ifp = if_alloc(IFT_ETHER);
1031 if (ifp == NULL) {
1032 printf("vge%d: can not if_alloc()\n", sc->vge_unit);
1033 error = ENOSPC;
1034 goto fail;
1035 }
1036
1037 /* Do MII setup */
1038 if (mii_phy_probe(dev, &sc->vge_miibus,
1039 vge_ifmedia_upd, vge_ifmedia_sts)) {
1040 printf("vge%d: MII without any phy!\n", sc->vge_unit);
1041 error = ENXIO;
1042 goto fail;
1043 }
1044
1045 ifp->if_softc = sc;
1046 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1047 ifp->if_mtu = ETHERMTU;
1048 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1049 ifp->if_ioctl = vge_ioctl;
1050 ifp->if_capabilities = IFCAP_VLAN_MTU;
1051 ifp->if_start = vge_start;
1052 ifp->if_hwassist = VGE_CSUM_FEATURES;
1053 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1054#ifdef DEVICE_POLLING
1055#ifdef IFCAP_POLLING
1056 ifp->if_capabilities |= IFCAP_POLLING;
1057#endif
1058#endif
1059 ifp->if_watchdog = vge_watchdog;
1060 ifp->if_init = vge_init;
1061 ifp->if_baudrate = 1000000000;
1062 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN;
1063 ifp->if_capenable = ifp->if_capabilities;
1064
1065 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp);
1066
1067 /*
1068 * Call MI attach routine.
1069 */
1070 ether_ifattach(ifp, eaddr);
1071
1072 /* Hook interrupt last to avoid having to lock softc */
1073 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE,
1074 vge_intr, sc, &sc->vge_intrhand);
1075
1076 if (error) {
1077 printf("vge%d: couldn't set up irq\n", unit);
1078 ether_ifdetach(ifp);
1079 goto fail;
1080 }
1081
1082fail:
1083 if (error)
1084 vge_detach(dev);
1085
1086 return (error);
1087}
1088
1089/*
1090 * Shutdown hardware and free up resources. This can be called any
1091 * time after the mutex has been initialized. It is called in both
1092 * the error case in attach and the normal detach case so it needs
1093 * to be careful about only freeing resources that have actually been
1094 * allocated.
1095 */
1096static int
1097vge_detach(dev)
1098 device_t dev;
1099{
1100 struct vge_softc *sc;
1101 struct ifnet *ifp;
1102 int i;
1103
1104 sc = device_get_softc(dev);
1105 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized"));
1106 ifp = sc->vge_ifp;
1107
1108 /* These should only be active if attach succeeded */
1109 if (device_is_attached(dev)) {
1110 vge_stop(sc);
1111 /*
1112 * Force off the IFF_UP flag here, in case someone
1113 * still had a BPF descriptor attached to this
1114 * interface. If they do, ether_ifattach() will cause
1115 * the BPF code to try and clear the promisc mode
1116 * flag, which will bubble down to vge_ioctl(),
1117 * which will try to call vge_init() again. This will
1118 * turn the NIC back on and restart the MII ticker,
1119 * which will panic the system when the kernel tries
1120 * to invoke the vge_tick() function that isn't there
1121 * anymore.
1122 */
1123 ifp->if_flags &= ~IFF_UP;
1124 ether_ifdetach(ifp);
1125 if_free(ifp);
1126 }
1127 if (sc->vge_miibus)
1128 device_delete_child(dev, sc->vge_miibus);
1129 bus_generic_detach(dev);
1130
1131 if (sc->vge_intrhand)
1132 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand);
1133 if (sc->vge_irq)
1134 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq);
1135 if (sc->vge_res)
1136 bus_release_resource(dev, SYS_RES_MEMORY,
1137 VGE_PCI_LOMEM, sc->vge_res);
1138
1139 /* Unload and free the RX DMA ring memory and map */
1140
1141 if (sc->vge_ldata.vge_rx_list_tag) {
1142 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag,
1143 sc->vge_ldata.vge_rx_list_map);
1144 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag,
1145 sc->vge_ldata.vge_rx_list,
1146 sc->vge_ldata.vge_rx_list_map);
1147 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag);
1148 }
1149
1150 /* Unload and free the TX DMA ring memory and map */
1151
1152 if (sc->vge_ldata.vge_tx_list_tag) {
1153 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag,
1154 sc->vge_ldata.vge_tx_list_map);
1155 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag,
1156 sc->vge_ldata.vge_tx_list,
1157 sc->vge_ldata.vge_tx_list_map);
1158 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag);
1159 }
1160
1161 /* Destroy all the RX and TX buffer maps */
1162
1163 if (sc->vge_ldata.vge_mtag) {
1164 for (i = 0; i < VGE_TX_DESC_CNT; i++)
1165 bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
1166 sc->vge_ldata.vge_tx_dmamap[i]);
1167 for (i = 0; i < VGE_RX_DESC_CNT; i++)
1168 bus_dmamap_destroy(sc->vge_ldata.vge_mtag,
1169 sc->vge_ldata.vge_rx_dmamap[i]);
1170 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag);
1171 }
1172
1173 if (sc->vge_parent_tag)
1174 bus_dma_tag_destroy(sc->vge_parent_tag);
1175
1176 mtx_destroy(&sc->vge_mtx);
1177
1178 return (0);
1179}
1180
1181static int
1182vge_newbuf(sc, idx, m)
1183 struct vge_softc *sc;
1184 int idx;
1185 struct mbuf *m;
1186{
1187 struct vge_dmaload_arg arg;
1188 struct mbuf *n = NULL;
1189 int i, error;
1190
1191 if (m == NULL) {
1192 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1193 if (n == NULL)
1194 return (ENOBUFS);
1195 m = n;
1196 } else
1197 m->m_data = m->m_ext.ext_buf;
1198
1199
1200#ifdef VGE_FIXUP_RX
1201 /*
1202 * This is part of an evil trick to deal with non-x86 platforms.
1203 * The VIA chip requires RX buffers to be aligned on 32-bit
1204 * boundaries, but that will hose non-x86 machines. To get around
1205 * this, we leave some empty space at the start of each buffer
1206 * and for non-x86 hosts, we copy the buffer back two bytes
1207 * to achieve word alignment. This is slightly more efficient
1208 * than allocating a new buffer, copying the contents, and
1209 * discarding the old buffer.
1210 */
1211 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN;
1212 m_adj(m, VGE_ETHER_ALIGN);
1213#else
1214 m->m_len = m->m_pkthdr.len = MCLBYTES;
1215#endif
1216
1217 arg.sc = sc;
1218 arg.vge_idx = idx;
1219 arg.vge_maxsegs = 1;
1220 arg.vge_flags = 0;
1221
1222 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag,
1223 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc,
1224 &arg, BUS_DMA_NOWAIT);
1225 if (error || arg.vge_maxsegs != 1) {
1226 if (n != NULL)
1227 m_freem(n);
1228 return (ENOMEM);
1229 }
1230
1231 /*
1232 * Note: the manual fails to document the fact that for
1233 * proper opration, the driver needs to replentish the RX
1234 * DMA ring 4 descriptors at a time (rather than one at a
1235 * time, like most chips). We can allocate the new buffers
1236 * but we should not set the OWN bits until we're ready
1237 * to hand back 4 of them in one shot.
1238 */
1239
1240#define VGE_RXCHUNK 4
1241 sc->vge_rx_consumed++;
1242 if (sc->vge_rx_consumed == VGE_RXCHUNK) {
1243 for (i = idx; i != idx - sc->vge_rx_consumed; i--)
1244 sc->vge_ldata.vge_rx_list[i].vge_sts |=
1245 htole32(VGE_RDSTS_OWN);
1246 sc->vge_rx_consumed = 0;
1247 }
1248
1249 sc->vge_ldata.vge_rx_mbuf[idx] = m;
1250
1251 bus_dmamap_sync(sc->vge_ldata.vge_mtag,
1252 sc->vge_ldata.vge_rx_dmamap[idx],
1253 BUS_DMASYNC_PREREAD);
1254
1255 return (0);
1256}
1257
1258static int
1259vge_tx_list_init(sc)
1260 struct vge_softc *sc;
1261{
1262 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ);
1263 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf,
1264 (VGE_TX_DESC_CNT * sizeof(struct mbuf *)));
1265
1266 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1267 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE);
1268 sc->vge_ldata.vge_tx_prodidx = 0;
1269 sc->vge_ldata.vge_tx_considx = 0;
1270 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT;
1271
1272 return (0);
1273}
1274
1275static int
1276vge_rx_list_init(sc)
1277 struct vge_softc *sc;
1278{
1279 int i;
1280
1281 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ);
1282 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf,
1283 (VGE_RX_DESC_CNT * sizeof(struct mbuf *)));
1284
1285 sc->vge_rx_consumed = 0;
1286
1287 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
1288 if (vge_newbuf(sc, i, NULL) == ENOBUFS)
1289 return (ENOBUFS);
1290 }
1291
1292 /* Flush the RX descriptors */
1293
1294 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1295 sc->vge_ldata.vge_rx_list_map,
1296 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1297
1298 sc->vge_ldata.vge_rx_prodidx = 0;
1299 sc->vge_rx_consumed = 0;
1300 sc->vge_head = sc->vge_tail = NULL;
1301
1302 return (0);
1303}
1304
1305#ifdef VGE_FIXUP_RX
1306static __inline void
1307vge_fixup_rx(m)
1308 struct mbuf *m;
1309{
1310 int i;
1311 uint16_t *src, *dst;
1312
1313 src = mtod(m, uint16_t *);
1314 dst = src - 1;
1315
1316 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1317 *dst++ = *src++;
1318
1319 m->m_data -= ETHER_ALIGN;
1320
1321 return;
1322}
1323#endif
1324
1325/*
1326 * RX handler. We support the reception of jumbo frames that have
1327 * been fragmented across multiple 2K mbuf cluster buffers.
1328 */
1329static void
1330vge_rxeof(sc)
1331 struct vge_softc *sc;
1332{
1333 struct mbuf *m;
1334 struct ifnet *ifp;
1335 int i, total_len;
1336 int lim = 0;
1337 struct vge_rx_desc *cur_rx;
1338 u_int32_t rxstat, rxctl;
1339
1340 VGE_LOCK_ASSERT(sc);
1341 ifp = sc->vge_ifp;
1342 i = sc->vge_ldata.vge_rx_prodidx;
1343
1344 /* Invalidate the descriptor memory */
1345
1346 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1347 sc->vge_ldata.vge_rx_list_map,
1348 BUS_DMASYNC_POSTREAD);
1349
1350 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) {
1351
1352#ifdef DEVICE_POLLING
1353 if (ifp->if_flags & IFF_POLLING) {
1354 if (sc->rxcycles <= 0)
1355 break;
1356 sc->rxcycles--;
1357 }
1358#endif /* DEVICE_POLLING */
1359
1360 cur_rx = &sc->vge_ldata.vge_rx_list[i];
1361 m = sc->vge_ldata.vge_rx_mbuf[i];
1362 total_len = VGE_RXBYTES(cur_rx);
1363 rxstat = le32toh(cur_rx->vge_sts);
1364 rxctl = le32toh(cur_rx->vge_ctl);
1365
1366 /* Invalidate the RX mbuf and unload its map */
1367
1368 bus_dmamap_sync(sc->vge_ldata.vge_mtag,
1369 sc->vge_ldata.vge_rx_dmamap[i],
1370 BUS_DMASYNC_POSTWRITE);
1371 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
1372 sc->vge_ldata.vge_rx_dmamap[i]);
1373
1374 /*
1375 * If the 'start of frame' bit is set, this indicates
1376 * either the first fragment in a multi-fragment receive,
1377 * or an intermediate fragment. Either way, we want to
1378 * accumulate the buffers.
1379 */
1380 if (rxstat & VGE_RXPKT_SOF) {
1381 m->m_len = MCLBYTES - VGE_ETHER_ALIGN;
1382 if (sc->vge_head == NULL)
1383 sc->vge_head = sc->vge_tail = m;
1384 else {
1385 m->m_flags &= ~M_PKTHDR;
1386 sc->vge_tail->m_next = m;
1387 sc->vge_tail = m;
1388 }
1389 vge_newbuf(sc, i, NULL);
1390 VGE_RX_DESC_INC(i);
1391 continue;
1392 }
1393
1394 /*
1395 * Bad/error frames will have the RXOK bit cleared.
1396 * However, there's one error case we want to allow:
1397 * if a VLAN tagged frame arrives and the chip can't
1398 * match it against the CAM filter, it considers this
1399 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit.
1400 * We don't want to drop the frame though: our VLAN
1401 * filtering is done in software.
1402 */
1403 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM)
1404 && !(rxstat & VGE_RDSTS_CSUMERR)) {
1405 ifp->if_ierrors++;
1406 /*
1407 * If this is part of a multi-fragment packet,
1408 * discard all the pieces.
1409 */
1410 if (sc->vge_head != NULL) {
1411 m_freem(sc->vge_head);
1412 sc->vge_head = sc->vge_tail = NULL;
1413 }
1414 vge_newbuf(sc, i, m);
1415 VGE_RX_DESC_INC(i);
1416 continue;
1417 }
1418
1419 /*
1420 * If allocating a replacement mbuf fails,
1421 * reload the current one.
1422 */
1423
1424 if (vge_newbuf(sc, i, NULL)) {
1425 ifp->if_ierrors++;
1426 if (sc->vge_head != NULL) {
1427 m_freem(sc->vge_head);
1428 sc->vge_head = sc->vge_tail = NULL;
1429 }
1430 vge_newbuf(sc, i, m);
1431 VGE_RX_DESC_INC(i);
1432 continue;
1433 }
1434
1435 VGE_RX_DESC_INC(i);
1436
1437 if (sc->vge_head != NULL) {
1438 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN);
1439 /*
1440 * Special case: if there's 4 bytes or less
1441 * in this buffer, the mbuf can be discarded:
1442 * the last 4 bytes is the CRC, which we don't
1443 * care about anyway.
1444 */
1445 if (m->m_len <= ETHER_CRC_LEN) {
1446 sc->vge_tail->m_len -=
1447 (ETHER_CRC_LEN - m->m_len);
1448 m_freem(m);
1449 } else {
1450 m->m_len -= ETHER_CRC_LEN;
1451 m->m_flags &= ~M_PKTHDR;
1452 sc->vge_tail->m_next = m;
1453 }
1454 m = sc->vge_head;
1455 sc->vge_head = sc->vge_tail = NULL;
1456 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1457 } else
1458 m->m_pkthdr.len = m->m_len =
1459 (total_len - ETHER_CRC_LEN);
1460
1461#ifdef VGE_FIXUP_RX
1462 vge_fixup_rx(m);
1463#endif
1464 ifp->if_ipackets++;
1465 m->m_pkthdr.rcvif = ifp;
1466
1467 /* Do RX checksumming if enabled */
1468 if (ifp->if_capenable & IFCAP_RXCSUM) {
1469
1470 /* Check IP header checksum */
1471 if (rxctl & VGE_RDCTL_IPPKT)
1472 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1473 if (rxctl & VGE_RDCTL_IPCSUMOK)
1474 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1475
1476 /* Check TCP/UDP checksum */
1477 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) &&
1478 rxctl & VGE_RDCTL_PROTOCSUMOK) {
1479 m->m_pkthdr.csum_flags |=
1480 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1481 m->m_pkthdr.csum_data = 0xffff;
1482 }
1483 }
1484
1485 if (rxstat & VGE_RDSTS_VTAG)
1486 VLAN_INPUT_TAG(ifp, m,
1487 ntohs((rxctl & VGE_RDCTL_VLANID)), continue);
1488
1489 VGE_UNLOCK(sc);
1490 (*ifp->if_input)(ifp, m);
1491 VGE_LOCK(sc);
1492
1493 lim++;
1494 if (lim == VGE_RX_DESC_CNT)
1495 break;
1496
1497 }
1498
1499 /* Flush the RX DMA ring */
1500
1501 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag,
1502 sc->vge_ldata.vge_rx_list_map,
1503 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1504
1505 sc->vge_ldata.vge_rx_prodidx = i;
1506 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim);
1507
1508
1509 return;
1510}
1511
1512static void
1513vge_txeof(sc)
1514 struct vge_softc *sc;
1515{
1516 struct ifnet *ifp;
1517 u_int32_t txstat;
1518 int idx;
1519
1520 ifp = sc->vge_ifp;
1521 idx = sc->vge_ldata.vge_tx_considx;
1522
1523 /* Invalidate the TX descriptor list */
1524
1525 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1526 sc->vge_ldata.vge_tx_list_map,
1527 BUS_DMASYNC_POSTREAD);
1528
1529 while (idx != sc->vge_ldata.vge_tx_prodidx) {
1530
1531 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts);
1532 if (txstat & VGE_TDSTS_OWN)
1533 break;
1534
1535 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]);
1536 sc->vge_ldata.vge_tx_mbuf[idx] = NULL;
1537 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
1538 sc->vge_ldata.vge_tx_dmamap[idx]);
1539 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL))
1540 ifp->if_collisions++;
1541 if (txstat & VGE_TDSTS_TXERR)
1542 ifp->if_oerrors++;
1543 else
1544 ifp->if_opackets++;
1545
1546 sc->vge_ldata.vge_tx_free++;
1547 VGE_TX_DESC_INC(idx);
1548 }
1549
1550 /* No changes made to the TX ring, so no flush needed */
1551
1552 if (idx != sc->vge_ldata.vge_tx_considx) {
1553 sc->vge_ldata.vge_tx_considx = idx;
1554 ifp->if_flags &= ~IFF_OACTIVE;
1555 ifp->if_timer = 0;
1556 }
1557
1558 /*
1559 * If not all descriptors have been released reaped yet,
1560 * reload the timer so that we will eventually get another
1561 * interrupt that will cause us to re-enter this routine.
1562 * This is done in case the transmitter has gone idle.
1563 */
1564 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) {
1565 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1566 }
1567
1568 return;
1569}
1570
1571static void
1572vge_tick(xsc)
1573 void *xsc;
1574{
1575 struct vge_softc *sc;
1576 struct ifnet *ifp;
1577 struct mii_data *mii;
1578
1579 sc = xsc;
1580 ifp = sc->vge_ifp;
1581 VGE_LOCK(sc);
1582 mii = device_get_softc(sc->vge_miibus);
1583
1584 mii_tick(mii);
1585 if (sc->vge_link) {
1586 if (!(mii->mii_media_status & IFM_ACTIVE)) {
1587 sc->vge_link = 0;
1588 if_link_state_change(sc->vge_ifp,
1589 LINK_STATE_DOWN);
1590 }
1591 } else {
1592 if (mii->mii_media_status & IFM_ACTIVE &&
1593 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1594 sc->vge_link = 1;
1595 if_link_state_change(sc->vge_ifp,
1596 LINK_STATE_UP);
1597#if __FreeBSD_version < 502114
1598 if (ifp->if_snd.ifq_head != NULL)
1599#else
1600 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1601#endif
1602 taskqueue_enqueue(taskqueue_swi,
1603 &sc->vge_txtask);
1604 }
1605 }
1606
1607 VGE_UNLOCK(sc);
1608
1609 return;
1610}
1611
1612#ifdef DEVICE_POLLING
1613static void
1614vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1615{
1616 struct vge_softc *sc = ifp->if_softc;
1617
1618 VGE_LOCK(sc);
1619#ifdef IFCAP_POLLING
1620 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1621 ether_poll_deregister(ifp);
1622 cmd = POLL_DEREGISTER;
1623 }
1624#endif
1625 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1626 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
1627 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
1628 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1629 goto done;
1630 }
1631
1632 sc->rxcycles = count;
1633 vge_rxeof(sc);
1634 vge_txeof(sc);
1635
1636#if __FreeBSD_version < 502114
1637 if (ifp->if_snd.ifq_head != NULL)
1638#else
1639 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1640#endif
1641 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask);
1642
1643 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1644 u_int32_t status;
1645 status = CSR_READ_4(sc, VGE_ISR);
1646 if (status == 0xFFFFFFFF)
1647 goto done;
1648 if (status)
1649 CSR_WRITE_4(sc, VGE_ISR, status);
1650
1651 /*
1652 * XXX check behaviour on receiver stalls.
1653 */
1654
1655 if (status & VGE_ISR_TXDMA_STALL ||
1656 status & VGE_ISR_RXDMA_STALL)
1657 vge_init(sc);
1658
1659 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1660 vge_rxeof(sc);
1661 ifp->if_ierrors++;
1662 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1663 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1664 }
1665 }
1666done:
1667 VGE_UNLOCK(sc);
1668}
1669#endif /* DEVICE_POLLING */
1670
1671static void
1672vge_intr(arg)
1673 void *arg;
1674{
1675 struct vge_softc *sc;
1676 struct ifnet *ifp;
1677 u_int32_t status;
1678
1679 sc = arg;
1680
1681 if (sc->suspended) {
1682 return;
1683 }
1684
1685 VGE_LOCK(sc);
1686 ifp = sc->vge_ifp;
1687
1688 if (!(ifp->if_flags & IFF_UP)) {
1689 VGE_UNLOCK(sc);
1690 return;
1691 }
1692
1693#ifdef DEVICE_POLLING
1694 if (ifp->if_flags & IFF_POLLING)
1695 goto done;
1696 if (
1697#ifdef IFCAP_POLLING
1698 (ifp->if_capenable & IFCAP_POLLING) &&
1699#endif
1700 ether_poll_register(vge_poll, ifp)) { /* ok, disable interrupts */
1701 CSR_WRITE_4(sc, VGE_IMR, 0);
1702 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1703 vge_poll(ifp, 0, 1);
1704 goto done;
1705 }
1706
1707#endif /* DEVICE_POLLING */
1708
1709 /* Disable interrupts */
1710 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
1711
1712 for (;;) {
1713
1714 status = CSR_READ_4(sc, VGE_ISR);
1715 /* If the card has gone away the read returns 0xffff. */
1716 if (status == 0xFFFFFFFF)
1717 break;
1718
1719 if (status)
1720 CSR_WRITE_4(sc, VGE_ISR, status);
1721
1722 if ((status & VGE_INTRS) == 0)
1723 break;
1724
1725 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO))
1726 vge_rxeof(sc);
1727
1728 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) {
1729 vge_rxeof(sc);
1730 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
1731 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
1732 }
1733
1734 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0))
1735 vge_txeof(sc);
1736
1737 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL))
1738 vge_init(sc);
1739
1740 if (status & VGE_ISR_LINKSTS)
1741 vge_tick(sc);
1742 }
1743
1744 /* Re-enable interrupts */
1745 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
1746
1747#ifdef DEVICE_POLLING
1748done:
1749#endif
1750 VGE_UNLOCK(sc);
1751
1752#if __FreeBSD_version < 502114
1753 if (ifp->if_snd.ifq_head != NULL)
1754#else
1755 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1756#endif
1757 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask);
1758
1759 return;
1760}
1761
1762static int
1763vge_encap(sc, m_head, idx)
1764 struct vge_softc *sc;
1765 struct mbuf *m_head;
1766 int idx;
1767{
1768 struct mbuf *m_new = NULL;
1769 struct vge_dmaload_arg arg;
1770 bus_dmamap_t map;
1771 int error;
1772 struct m_tag *mtag;
1773
1774 if (sc->vge_ldata.vge_tx_free <= 2)
1775 return (EFBIG);
1776
1777 arg.vge_flags = 0;
1778
1779 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1780 arg.vge_flags |= VGE_TDCTL_IPCSUM;
1781 if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1782 arg.vge_flags |= VGE_TDCTL_TCPCSUM;
1783 if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1784 arg.vge_flags |= VGE_TDCTL_UDPCSUM;
1785
1786 arg.sc = sc;
1787 arg.vge_idx = idx;
1788 arg.vge_m0 = m_head;
1789 arg.vge_maxsegs = VGE_TX_FRAGS;
1790
1791 map = sc->vge_ldata.vge_tx_dmamap[idx];
1792 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map,
1793 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT);
1794
1795 if (error && error != EFBIG) {
1796 printf("vge%d: can't map mbuf (error %d)\n",
1797 sc->vge_unit, error);
1798 return (ENOBUFS);
1799 }
1800
1801 /* Too many segments to map, coalesce into a single mbuf */
1802
1803 if (error || arg.vge_maxsegs == 0) {
1804 m_new = m_defrag(m_head, M_DONTWAIT);
1805 if (m_new == NULL)
1806 return (1);
1807 else
1808 m_head = m_new;
1809
1810 arg.sc = sc;
1811 arg.vge_m0 = m_head;
1812 arg.vge_idx = idx;
1813 arg.vge_maxsegs = 1;
1814
1815 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map,
1816 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT);
1817 if (error) {
1818 printf("vge%d: can't map mbuf (error %d)\n",
1819 sc->vge_unit, error);
1820 return (EFBIG);
1821 }
1822 }
1823
1824 sc->vge_ldata.vge_tx_mbuf[idx] = m_head;
1825 sc->vge_ldata.vge_tx_free--;
1826
1827 /*
1828 * Set up hardware VLAN tagging.
1829 */
1830
1831 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head);
1832 if (mtag != NULL)
1833 sc->vge_ldata.vge_tx_list[idx].vge_ctl |=
1834 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG);
1835
1836 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN);
1837
1838 return (0);
1839}
1840
1841static void
1842vge_tx_task(arg, npending)
1843 void *arg;
1844 int npending;
1845{
1846 struct ifnet *ifp;
1847
1848 ifp = arg;
1849 vge_start(ifp);
1850
1851 return;
1852}
1853
1854/*
1855 * Main transmit routine.
1856 */
1857
1858static void
1859vge_start(ifp)
1860 struct ifnet *ifp;
1861{
1862 struct vge_softc *sc;
1863 struct mbuf *m_head = NULL;
1864 int idx, pidx = 0;
1865
1866 sc = ifp->if_softc;
1867 VGE_LOCK(sc);
1868
1869 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) {
1870 VGE_UNLOCK(sc);
1871 return;
1872 }
1873
1874#if __FreeBSD_version < 502114
1875 if (ifp->if_snd.ifq_head == NULL) {
1876#else
1877 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
1878#endif
1879 VGE_UNLOCK(sc);
1880 return;
1881 }
1882
1883 idx = sc->vge_ldata.vge_tx_prodidx;
1884
1885 pidx = idx - 1;
1886 if (pidx < 0)
1887 pidx = VGE_TX_DESC_CNT - 1;
1888
1889
1890 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) {
1891#if __FreeBSD_version < 502114
1892 IF_DEQUEUE(&ifp->if_snd, m_head);
1893#else
1894 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1895#endif
1896 if (m_head == NULL)
1897 break;
1898
1899 if (vge_encap(sc, m_head, idx)) {
1900#if __FreeBSD_version >= 502114
1901 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1902#else
1903 IF_PREPEND(&ifp->if_snd, m_head);
1904#endif
1905 ifp->if_flags |= IFF_OACTIVE;
1906 break;
1907 }
1908
1909 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |=
1910 htole16(VGE_TXDESC_Q);
1911
1912 pidx = idx;
1913 VGE_TX_DESC_INC(idx);
1914
1915 /*
1916 * If there's a BPF listener, bounce a copy of this frame
1917 * to him.
1918 */
1919 BPF_MTAP(ifp, m_head);
1920 }
1921
1922 if (idx == sc->vge_ldata.vge_tx_prodidx) {
1923 VGE_UNLOCK(sc);
1924 return;
1925 }
1926
1927 /* Flush the TX descriptors */
1928
1929 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag,
1930 sc->vge_ldata.vge_tx_list_map,
1931 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1932
1933 /* Issue a transmit command. */
1934 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
1935
1936 sc->vge_ldata.vge_tx_prodidx = idx;
1937
1938 /*
1939 * Use the countdown timer for interrupt moderation.
1940 * 'TX done' interrupts are disabled. Instead, we reset the
1941 * countdown timer, which will begin counting until it hits
1942 * the value in the SSTIMER register, and then trigger an
1943 * interrupt. Each time we set the TIMER0_ENABLE bit, the
1944 * the timer count is reloaded. Only when the transmitter
1945 * is idle will the timer hit 0 and an interrupt fire.
1946 */
1947 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE);
1948
1949 VGE_UNLOCK(sc);
1950
1951 /*
1952 * Set a timeout in case the chip goes out to lunch.
1953 */
1954 ifp->if_timer = 5;
1955
1956 return;
1957}
1958
1959static void
1960vge_init(xsc)
1961 void *xsc;
1962{
1963 struct vge_softc *sc = xsc;
1964 struct ifnet *ifp = sc->vge_ifp;
1965 struct mii_data *mii;
1966 int i;
1967
1968 VGE_LOCK(sc);
1969 mii = device_get_softc(sc->vge_miibus);
1970
1971 /*
1972 * Cancel pending I/O and free all RX/TX buffers.
1973 */
1974 vge_stop(sc);
1975 vge_reset(sc);
1976
1977 /*
1978 * Initialize the RX and TX descriptors and mbufs.
1979 */
1980
1981 vge_rx_list_init(sc);
1982 vge_tx_list_init(sc);
1983
1984 /* Set our station address */
1985 for (i = 0; i < ETHER_ADDR_LEN; i++)
1986 CSR_WRITE_1(sc, VGE_PAR0 + i, IFP2ENADDR(sc->vge_ifp)[i]);
1987
1988 /*
1989 * Set receive FIFO threshold. Also allow transmission and
1990 * reception of VLAN tagged frames.
1991 */
1992 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT);
1993 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2);
1994
1995 /* Set DMA burst length */
1996 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN);
1997 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128);
1998
1999 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK);
2000
2001 /* Set collision backoff algorithm */
2002 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM|
2003 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT);
2004 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET);
2005
2006 /* Disable LPSEL field in priority resolution */
2007 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS);
2008
2009 /*
2010 * Load the addresses of the DMA queues into the chip.
2011 * Note that we only use one transmit queue.
2012 */
2013
2014 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0,
2015 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr));
2016 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
2017
2018 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO,
2019 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr));
2020 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
2021 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
2022
2023 /* Enable and wake up the RX descriptor queue */
2024 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN);
2025 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK);
2026
2027 /* Enable the TX descriptor queue */
2028 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
2029
2030 /* Set up the receive filter -- allow large frames for VLANs. */
2031 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT);
2032
2033 /* If we want promiscuous mode, set the allframes bit. */
2034 if (ifp->if_flags & IFF_PROMISC) {
2035 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC);
2036 }
2037
2038 /* Set capture broadcast bit to capture broadcast frames. */
2039 if (ifp->if_flags & IFF_BROADCAST) {
2040 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST);
2041 }
2042
2043 /* Set multicast bit to capture multicast frames. */
2044 if (ifp->if_flags & IFF_MULTICAST) {
2045 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST);
2046 }
2047
2048 /* Init the cam filter. */
2049 vge_cam_clear(sc);
2050
2051 /* Init the multicast filter. */
2052 vge_setmulti(sc);
2053
2054 /* Enable flow control */
2055
2056 CSR_WRITE_1(sc, VGE_CRS2, 0x8B);
2057
2058 /* Enable jumbo frame reception (if desired) */
2059
2060 /* Start the MAC. */
2061 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP);
2062 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL);
2063 CSR_WRITE_1(sc, VGE_CRS0,
2064 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START);
2065
2066 /*
2067 * Configure one-shot timer for microsecond
2068 * resulution and load it for 500 usecs.
2069 */
2070 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES);
2071 CSR_WRITE_2(sc, VGE_SSTIMER, 400);
2072
2073 /*
2074 * Configure interrupt moderation for receive. Enable
2075 * the holdoff counter and load it, and set the RX
2076 * suppression count to the number of descriptors we
2077 * want to allow before triggering an interrupt.
2078 * The holdoff timer is in units of 20 usecs.
2079 */
2080
2081#ifdef notyet
2082 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE);
2083 /* Select the interrupt holdoff timer page. */
2084 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
2085 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF);
2086 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */
2087
2088 /* Enable use of the holdoff timer. */
2089 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF);
2090 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD);
2091
2092 /* Select the RX suppression threshold page. */
2093 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
2094 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR);
2095 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */
2096
2097 /* Restore the page select bits. */
2098 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL);
2099 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR);
2100#endif
2101
2102#ifdef DEVICE_POLLING
2103 /*
2104 * Disable interrupts if we are polling.
2105 */
2106 if (ifp->if_flags & IFF_POLLING) {
2107 CSR_WRITE_4(sc, VGE_IMR, 0);
2108 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2109 } else /* otherwise ... */
2110#endif /* DEVICE_POLLING */
2111 {
2112 /*
2113 * Enable interrupts.
2114 */
2115 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS);
2116 CSR_WRITE_4(sc, VGE_ISR, 0);
2117 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK);
2118 }
2119
2120 mii_mediachg(mii);
2121
2122 ifp->if_flags |= IFF_RUNNING;
2123 ifp->if_flags &= ~IFF_OACTIVE;
2124
2125 sc->vge_if_flags = 0;
2126 sc->vge_link = 0;
2127
2128 VGE_UNLOCK(sc);
2129
2130 return;
2131}
2132
2133/*
2134 * Set media options.
2135 */
2136static int
2137vge_ifmedia_upd(ifp)
2138 struct ifnet *ifp;
2139{
2140 struct vge_softc *sc;
2141 struct mii_data *mii;
2142
2143 sc = ifp->if_softc;
2144 mii = device_get_softc(sc->vge_miibus);
2145 mii_mediachg(mii);
2146
2147 return (0);
2148}
2149
2150/*
2151 * Report current media status.
2152 */
2153static void
2154vge_ifmedia_sts(ifp, ifmr)
2155 struct ifnet *ifp;
2156 struct ifmediareq *ifmr;
2157{
2158 struct vge_softc *sc;
2159 struct mii_data *mii;
2160
2161 sc = ifp->if_softc;
2162 mii = device_get_softc(sc->vge_miibus);
2163
2164 mii_pollstat(mii);
2165 ifmr->ifm_active = mii->mii_media_active;
2166 ifmr->ifm_status = mii->mii_media_status;
2167
2168 return;
2169}
2170
2171static void
2172vge_miibus_statchg(dev)
2173 device_t dev;
2174{
2175 struct vge_softc *sc;
2176 struct mii_data *mii;
2177 struct ifmedia_entry *ife;
2178
2179 sc = device_get_softc(dev);
2180 mii = device_get_softc(sc->vge_miibus);
2181 ife = mii->mii_media.ifm_cur;
2182
2183 /*
2184 * If the user manually selects a media mode, we need to turn
2185 * on the forced MAC mode bit in the DIAGCTL register. If the
2186 * user happens to choose a full duplex mode, we also need to
2187 * set the 'force full duplex' bit. This applies only to
2188 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC
2189 * mode is disabled, and in 1000baseT mode, full duplex is
2190 * always implied, so we turn on the forced mode bit but leave
2191 * the FDX bit cleared.
2192 */
2193
2194 switch (IFM_SUBTYPE(ife->ifm_media)) {
2195 case IFM_AUTO:
2196 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2197 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2198 break;
2199 case IFM_1000_T:
2200 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2201 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2202 break;
2203 case IFM_100_TX:
2204 case IFM_10_T:
2205 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE);
2206 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
2207 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2208 } else {
2209 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE);
2210 }
2211 break;
2212 default:
2213 device_printf(dev, "unknown media type: %x\n",
2214 IFM_SUBTYPE(ife->ifm_media));
2215 break;
2216 }
2217
2218 return;
2219}
2220
2221static int
2222vge_ioctl(ifp, command, data)
2223 struct ifnet *ifp;
2224 u_long command;
2225 caddr_t data;
2226{
2227 struct vge_softc *sc = ifp->if_softc;
2228 struct ifreq *ifr = (struct ifreq *) data;
2229 struct mii_data *mii;
2230 int error = 0;
2231
2232 switch (command) {
2233 case SIOCSIFMTU:
2234 if (ifr->ifr_mtu > VGE_JUMBO_MTU)
2235 error = EINVAL;
2236 ifp->if_mtu = ifr->ifr_mtu;
2237 break;
2238 case SIOCSIFFLAGS:
2239 if (ifp->if_flags & IFF_UP) {
2240 if (ifp->if_flags & IFF_RUNNING &&
2241 ifp->if_flags & IFF_PROMISC &&
2242 !(sc->vge_if_flags & IFF_PROMISC)) {
2243 CSR_SETBIT_1(sc, VGE_RXCTL,
2244 VGE_RXCTL_RX_PROMISC);
2245 vge_setmulti(sc);
2246 } else if (ifp->if_flags & IFF_RUNNING &&
2247 !(ifp->if_flags & IFF_PROMISC) &&
2248 sc->vge_if_flags & IFF_PROMISC) {
2249 CSR_CLRBIT_1(sc, VGE_RXCTL,
2250 VGE_RXCTL_RX_PROMISC);
2251 vge_setmulti(sc);
2252 } else
2253 vge_init(sc);
2254 } else {
2255 if (ifp->if_flags & IFF_RUNNING)
2256 vge_stop(sc);
2257 }
2258 sc->vge_if_flags = ifp->if_flags;
2259 break;
2260 case SIOCADDMULTI:
2261 case SIOCDELMULTI:
2262 vge_setmulti(sc);
2263 break;
2264 case SIOCGIFMEDIA:
2265 case SIOCSIFMEDIA:
2266 mii = device_get_softc(sc->vge_miibus);
2267 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2268 break;
2269 case SIOCSIFCAP:
2270#ifdef IFCAP_POLLING
2271 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_POLLING);
2272#else
2273 ifp->if_capenable &= ~(IFCAP_HWCSUM);
2274#endif
2275 ifp->if_capenable |=
2276#ifdef IFCAP_POLLING
2277 ifr->ifr_reqcap & (IFCAP_HWCSUM | IFCAP_POLLING);
2278#else
2279 ifr->ifr_reqcap & (IFCAP_HWCSUM);
2280#endif
2281 if (ifp->if_capenable & IFCAP_TXCSUM)
2282 ifp->if_hwassist = VGE_CSUM_FEATURES;
2283 else
2284 ifp->if_hwassist = 0;
2285 if (ifp->if_flags & IFF_RUNNING)
2286 vge_init(sc);
2287 break;
2288 default:
2289 error = ether_ioctl(ifp, command, data);
2290 break;
2291 }
2292
2293 return (error);
2294}
2295
2296static void
2297vge_watchdog(ifp)
2298 struct ifnet *ifp;
2299{
2300 struct vge_softc *sc;
2301
2302 sc = ifp->if_softc;
2303 VGE_LOCK(sc);
2304 printf("vge%d: watchdog timeout\n", sc->vge_unit);
2305 ifp->if_oerrors++;
2306
2307 vge_txeof(sc);
2308 vge_rxeof(sc);
2309
2310 vge_init(sc);
2311
2312 VGE_UNLOCK(sc);
2313
2314 return;
2315}
2316
2317/*
2318 * Stop the adapter and free any mbufs allocated to the
2319 * RX and TX lists.
2320 */
2321static void
2322vge_stop(sc)
2323 struct vge_softc *sc;
2324{
2325 register int i;
2326 struct ifnet *ifp;
2327
2328 VGE_LOCK(sc);
2329 ifp = sc->vge_ifp;
2330 ifp->if_timer = 0;
2331
2332 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2333#ifdef DEVICE_POLLING
2334 ether_poll_deregister(ifp);
2335#endif /* DEVICE_POLLING */
2336
2337 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK);
2338 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP);
2339 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF);
2340 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
2341 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF);
2342 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0);
2343
2344 if (sc->vge_head != NULL) {
2345 m_freem(sc->vge_head);
2346 sc->vge_head = sc->vge_tail = NULL;
2347 }
2348
2349 /* Free the TX list buffers. */
2350
2351 for (i = 0; i < VGE_TX_DESC_CNT; i++) {
2352 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) {
2353 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
2354 sc->vge_ldata.vge_tx_dmamap[i]);
2355 m_freem(sc->vge_ldata.vge_tx_mbuf[i]);
2356 sc->vge_ldata.vge_tx_mbuf[i] = NULL;
2357 }
2358 }
2359
2360 /* Free the RX list buffers. */
2361
2362 for (i = 0; i < VGE_RX_DESC_CNT; i++) {
2363 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) {
2364 bus_dmamap_unload(sc->vge_ldata.vge_mtag,
2365 sc->vge_ldata.vge_rx_dmamap[i]);
2366 m_freem(sc->vge_ldata.vge_rx_mbuf[i]);
2367 sc->vge_ldata.vge_rx_mbuf[i] = NULL;
2368 }
2369 }
2370
2371 VGE_UNLOCK(sc);
2372
2373 return;
2374}
2375
2376/*
2377 * Device suspend routine. Stop the interface and save some PCI
2378 * settings in case the BIOS doesn't restore them properly on
2379 * resume.
2380 */
2381static int
2382vge_suspend(dev)
2383 device_t dev;
2384{
2385 struct vge_softc *sc;
2386
2387 sc = device_get_softc(dev);
2388
2389 vge_stop(sc);
2390
2391 sc->suspended = 1;
2392
2393 return (0);
2394}
2395
2396/*
2397 * Device resume routine. Restore some PCI settings in case the BIOS
2398 * doesn't, re-enable busmastering, and restart the interface if
2399 * appropriate.
2400 */
2401static int
2402vge_resume(dev)
2403 device_t dev;
2404{
2405 struct vge_softc *sc;
2406 struct ifnet *ifp;
2407
2408 sc = device_get_softc(dev);
2409 ifp = sc->vge_ifp;
2410
2411 /* reenable busmastering */
2412 pci_enable_busmaster(dev);
2413 pci_enable_io(dev, SYS_RES_MEMORY);
2414
2415 /* reinitialize interface if necessary */
2416 if (ifp->if_flags & IFF_UP)
2417 vge_init(sc);
2418
2419 sc->suspended = 0;
2420
2421 return (0);
2422}
2423
2424/*
2425 * Stop all chip I/O so that the kernel's probe routines don't
2426 * get confused by errant DMAs when rebooting.
2427 */
2428static void
2429vge_shutdown(dev)
2430 device_t dev;
2431{
2432 struct vge_softc *sc;
2433
2434 sc = device_get_softc(dev);
2435
2436 vge_stop(sc);
2437}
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