102static void ehci_dump_regs(ehci_softc_t *sc);
103static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
104
105#endif
106
107#define EHCI_INTR_ENDPT 1
108
109extern struct usb_bus_methods ehci_bus_methods;
110extern struct usb_pipe_methods ehci_device_bulk_methods;
111extern struct usb_pipe_methods ehci_device_ctrl_methods;
112extern struct usb_pipe_methods ehci_device_intr_methods;
113extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
114extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
115
116static void ehci_do_poll(struct usb_bus *);
117static void ehci_device_done(struct usb_xfer *, usb_error_t);
118static uint8_t ehci_check_transfer(struct usb_xfer *);
119static void ehci_timeout(void *);
120static void ehci_poll_timeout(void *);
121
122static void ehci_root_intr(ehci_softc_t *sc);
123
124struct ehci_std_temp {
125 ehci_softc_t *sc;
126 struct usb_page_cache *pc;
127 ehci_qtd_t *td;
128 ehci_qtd_t *td_next;
129 uint32_t average;
130 uint32_t qtd_status;
131 uint32_t len;
132 uint16_t max_frame_size;
133 uint8_t shortpkt;
134 uint8_t auto_data_toggle;
135 uint8_t setup_alt_next;
136 uint8_t last_frame;
137 uint8_t can_use_next;
138};
139
140void
141ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
142{
143 ehci_softc_t *sc = EHCI_BUS2SC(bus);
144 uint32_t i;
145
146 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
147 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
148
149 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
150 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
151
152 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
153 cb(bus, sc->sc_hw.intr_start_pc + i,
154 sc->sc_hw.intr_start_pg + i,
155 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
156 }
157
158 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
159 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
160 sc->sc_hw.isoc_hs_start_pg + i,
161 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
162 }
163
164 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
165 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
166 sc->sc_hw.isoc_fs_start_pg + i,
167 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
168 }
169}
170
171usb_error_t
172ehci_reset(ehci_softc_t *sc)
173{
174 uint32_t hcr;
175 int i;
176
177 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
178 for (i = 0; i < 100; i++) {
179 usb_pause_mtx(NULL, hz / 1000);
180 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
181 if (!hcr) {
182 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
183 /*
184 * Force USBMODE as requested. Controllers
185 * may have multiple operating modes.
186 */
187 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
188 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
189 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
190 device_printf(sc->sc_bus.bdev,
191 "set host controller mode\n");
192 }
193 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
194 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
195 device_printf(sc->sc_bus.bdev,
196 "set big-endian mode\n");
197 }
198 EOWRITE4(sc, EHCI_USBMODE, usbmode);
199 }
200 return (0);
201 }
202 }
203 device_printf(sc->sc_bus.bdev, "reset timeout\n");
204 return (USB_ERR_IOERROR);
205}
206
207static usb_error_t
208ehci_hcreset(ehci_softc_t *sc)
209{
210 uint32_t hcr;
211 int i;
212
213 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
214 for (i = 0; i < 100; i++) {
215 usb_pause_mtx(NULL, hz / 1000);
216 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
217 if (hcr)
218 break;
219 }
220 if (!hcr)
221 /*
222 * Fall through and try reset anyway even though
223 * Table 2-9 in the EHCI spec says this will result
224 * in undefined behavior.
225 */
226 device_printf(sc->sc_bus.bdev, "stop timeout\n");
227
228 return ehci_reset(sc);
229}
230
231usb_error_t
232ehci_init(ehci_softc_t *sc)
233{
234 struct usb_page_search buf_res;
235 uint32_t version;
236 uint32_t sparams;
237 uint32_t cparams;
238 uint32_t hcr;
239 uint16_t i;
240 uint16_t x;
241 uint16_t y;
242 uint16_t bit;
243 usb_error_t err = 0;
244
245 DPRINTF("start\n");
246
247 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
248 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
249
250#if USB_DEBUG
251 if (ehcidebug > 2) {
252 ehci_dump_regs(sc);
253 }
254#endif
255
256 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
257
258 version = EREAD2(sc, EHCI_HCIVERSION);
259 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
260 version >> 8, version & 0xff);
261
262 sparams = EREAD4(sc, EHCI_HCSPARAMS);
263 DPRINTF("sparams=0x%x\n", sparams);
264
265 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
266 cparams = EREAD4(sc, EHCI_HCCPARAMS);
267 DPRINTF("cparams=0x%x\n", cparams);
268
269 if (EHCI_HCC_64BIT(cparams)) {
270 DPRINTF("HCC uses 64-bit structures\n");
271
272 /* MUST clear segment register if 64 bit capable */
273 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
274 }
275 sc->sc_bus.usbrev = USB_REV_2_0;
276
277 /* Reset the controller */
278 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
279
280 err = ehci_hcreset(sc);
281 if (err) {
282 device_printf(sc->sc_bus.bdev, "reset timeout\n");
283 return (err);
284 }
285 /*
286 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
287 * bytes 2: 256*4 bytes 3: unknown
288 */
289 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
290 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
291 return (USB_ERR_IOERROR);
292 }
293 /* set up the bus struct */
294 sc->sc_bus.methods = &ehci_bus_methods;
295
296 sc->sc_eintrs = EHCI_NORMAL_INTRS;
297
298 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
299 ehci_qh_t *qh;
300
301 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
302
303 qh = buf_res.buffer;
304
305 /* initialize page cache pointer */
306
307 qh->page_cache = sc->sc_hw.intr_start_pc + i;
308
309 /* store a pointer to queue head */
310
311 sc->sc_intr_p_last[i] = qh;
312
313 qh->qh_self =
314 htohc32(sc, buf_res.physaddr) |
315 htohc32(sc, EHCI_LINK_QH);
316
317 qh->qh_endp =
318 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
319 qh->qh_endphub =
320 htohc32(sc, EHCI_QH_SET_MULT(1));
321 qh->qh_curqtd = 0;
322
323 qh->qh_qtd.qtd_next =
324 htohc32(sc, EHCI_LINK_TERMINATE);
325 qh->qh_qtd.qtd_altnext =
326 htohc32(sc, EHCI_LINK_TERMINATE);
327 qh->qh_qtd.qtd_status =
328 htohc32(sc, EHCI_QTD_HALTED);
329 }
330
331 /*
332 * the QHs are arranged to give poll intervals that are
333 * powers of 2 times 1ms
334 */
335 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
336 while (bit) {
337 x = bit;
338 while (x & bit) {
339 ehci_qh_t *qh_x;
340 ehci_qh_t *qh_y;
341
342 y = (x ^ bit) | (bit / 2);
343
344 qh_x = sc->sc_intr_p_last[x];
345 qh_y = sc->sc_intr_p_last[y];
346
347 /*
348 * the next QH has half the poll interval
349 */
350 qh_x->qh_link = qh_y->qh_self;
351
352 x++;
353 }
354 bit >>= 1;
355 }
356
357 if (1) {
358 ehci_qh_t *qh;
359
360 qh = sc->sc_intr_p_last[0];
361
362 /* the last (1ms) QH terminates */
363 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
364 }
365 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
366 ehci_sitd_t *sitd;
367 ehci_itd_t *itd;
368
369 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
370
371 sitd = buf_res.buffer;
372
373 /* initialize page cache pointer */
374
375 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
376
377 /* store a pointer to the transfer descriptor */
378
379 sc->sc_isoc_fs_p_last[i] = sitd;
380
381 /* initialize full speed isochronous */
382
383 sitd->sitd_self =
384 htohc32(sc, buf_res.physaddr) |
385 htohc32(sc, EHCI_LINK_SITD);
386
387 sitd->sitd_back =
388 htohc32(sc, EHCI_LINK_TERMINATE);
389
390 sitd->sitd_next =
391 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
392
393
394 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
395
396 itd = buf_res.buffer;
397
398 /* initialize page cache pointer */
399
400 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
401
402 /* store a pointer to the transfer descriptor */
403
404 sc->sc_isoc_hs_p_last[i] = itd;
405
406 /* initialize high speed isochronous */
407
408 itd->itd_self =
409 htohc32(sc, buf_res.physaddr) |
410 htohc32(sc, EHCI_LINK_ITD);
411
412 itd->itd_next =
413 sitd->sitd_self;
414 }
415
416 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
417
418 if (1) {
419 uint32_t *pframes;
420
421 pframes = buf_res.buffer;
422
423 /*
424 * execution order:
425 * pframes -> high speed isochronous ->
426 * full speed isochronous -> interrupt QH's
427 */
428 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
429 pframes[i] = sc->sc_isoc_hs_p_last
430 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
431 }
432 }
433 /* setup sync list pointer */
434 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
435
436 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
437
438 if (1) {
439
440 ehci_qh_t *qh;
441
442 qh = buf_res.buffer;
443
444 /* initialize page cache pointer */
445
446 qh->page_cache = &sc->sc_hw.async_start_pc;
447
448 /* store a pointer to the queue head */
449
450 sc->sc_async_p_last = qh;
451
452 /* init dummy QH that starts the async list */
453
454 qh->qh_self =
455 htohc32(sc, buf_res.physaddr) |
456 htohc32(sc, EHCI_LINK_QH);
457
458 /* fill the QH */
459 qh->qh_endp =
460 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
461 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
462 qh->qh_link = qh->qh_self;
463 qh->qh_curqtd = 0;
464
465 /* fill the overlay qTD */
466 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
467 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
468 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
469 }
470 /* flush all cache into memory */
471
472 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
473
474#if USB_DEBUG
475 if (ehcidebug) {
476 ehci_dump_sqh(sc, sc->sc_async_p_last);
477 }
478#endif
479
480 /* setup async list pointer */
481 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
482
483
484 /* enable interrupts */
485 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
486
487 /* turn on controller */
488 EOWRITE4(sc, EHCI_USBCMD,
489 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
490 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
491 EHCI_CMD_ASE |
492 EHCI_CMD_PSE |
493 EHCI_CMD_RS);
494
495 /* Take over port ownership */
496 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
497
498 for (i = 0; i < 100; i++) {
499 usb_pause_mtx(NULL, hz / 1000);
500 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
501 if (!hcr) {
502 break;
503 }
504 }
505 if (hcr) {
506 device_printf(sc->sc_bus.bdev, "run timeout\n");
507 return (USB_ERR_IOERROR);
508 }
509
510 if (!err) {
511 /* catch any lost interrupts */
512 ehci_do_poll(&sc->sc_bus);
513 }
514 return (err);
515}
516
517/*
518 * shut down the controller when the system is going down
519 */
520void
521ehci_detach(ehci_softc_t *sc)
522{
523 USB_BUS_LOCK(&sc->sc_bus);
524
525 usb_callout_stop(&sc->sc_tmo_pcd);
526 usb_callout_stop(&sc->sc_tmo_poll);
527
528 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
529 USB_BUS_UNLOCK(&sc->sc_bus);
530
531 if (ehci_hcreset(sc)) {
532 DPRINTF("reset failed!\n");
533 }
534
535 /* XXX let stray task complete */
536 usb_pause_mtx(NULL, hz / 20);
537
538 usb_callout_drain(&sc->sc_tmo_pcd);
539 usb_callout_drain(&sc->sc_tmo_poll);
540}
541
542void
543ehci_suspend(ehci_softc_t *sc)
544{
545 uint32_t cmd;
546 uint32_t hcr;
547 uint8_t i;
548
549 USB_BUS_LOCK(&sc->sc_bus);
550
551 for (i = 1; i <= sc->sc_noport; i++) {
552 cmd = EOREAD4(sc, EHCI_PORTSC(i));
553 if (((cmd & EHCI_PS_PO) == 0) &&
554 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
555 EOWRITE4(sc, EHCI_PORTSC(i),
556 cmd | EHCI_PS_SUSP);
557 }
558 }
559
560 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
561
562 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
563 EOWRITE4(sc, EHCI_USBCMD, cmd);
564
565 for (i = 0; i < 100; i++) {
566 hcr = EOREAD4(sc, EHCI_USBSTS) &
567 (EHCI_STS_ASS | EHCI_STS_PSS);
568
569 if (hcr == 0) {
570 break;
571 }
572 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
573 }
574
575 if (hcr != 0) {
576 device_printf(sc->sc_bus.bdev, "reset timeout\n");
577 }
578 cmd &= ~EHCI_CMD_RS;
579 EOWRITE4(sc, EHCI_USBCMD, cmd);
580
581 for (i = 0; i < 100; i++) {
582 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
583 if (hcr == EHCI_STS_HCH) {
584 break;
585 }
586 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
587 }
588
589 if (hcr != EHCI_STS_HCH) {
590 device_printf(sc->sc_bus.bdev,
591 "config timeout\n");
592 }
593 USB_BUS_UNLOCK(&sc->sc_bus);
594}
595
596void
597ehci_resume(ehci_softc_t *sc)
598{
599 struct usb_page_search buf_res;
600 uint32_t cmd;
601 uint32_t hcr;
602 uint8_t i;
603
604 USB_BUS_LOCK(&sc->sc_bus);
605
606 /* restore things in case the bios doesn't */
607 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
608
609 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
610 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
611
612 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
613 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
614
615 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
616
617 hcr = 0;
618 for (i = 1; i <= sc->sc_noport; i++) {
619 cmd = EOREAD4(sc, EHCI_PORTSC(i));
620 if (((cmd & EHCI_PS_PO) == 0) &&
621 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
622 EOWRITE4(sc, EHCI_PORTSC(i),
623 cmd | EHCI_PS_FPR);
624 hcr = 1;
625 }
626 }
627
628 if (hcr) {
629 usb_pause_mtx(&sc->sc_bus.bus_mtx,
630 USB_MS_TO_TICKS(USB_RESUME_WAIT));
631
632 for (i = 1; i <= sc->sc_noport; i++) {
633 cmd = EOREAD4(sc, EHCI_PORTSC(i));
634 if (((cmd & EHCI_PS_PO) == 0) &&
635 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
636 EOWRITE4(sc, EHCI_PORTSC(i),
637 cmd & ~EHCI_PS_FPR);
638 }
639 }
640 }
641 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
642
643 for (i = 0; i < 100; i++) {
644 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
645 if (hcr != EHCI_STS_HCH) {
646 break;
647 }
648 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
649 }
650 if (hcr == EHCI_STS_HCH) {
651 device_printf(sc->sc_bus.bdev, "config timeout\n");
652 }
653
654 USB_BUS_UNLOCK(&sc->sc_bus);
655
656 usb_pause_mtx(NULL,
657 USB_MS_TO_TICKS(USB_RESUME_WAIT));
658
659 /* catch any lost interrupts */
660 ehci_do_poll(&sc->sc_bus);
661}
662
663void
664ehci_shutdown(ehci_softc_t *sc)
665{
666 DPRINTF("stopping the HC\n");
667
668 if (ehci_hcreset(sc)) {
669 DPRINTF("reset failed!\n");
670 }
671}
672
673#if USB_DEBUG
674static void
675ehci_dump_regs(ehci_softc_t *sc)
676{
677 uint32_t i;
678
679 i = EOREAD4(sc, EHCI_USBCMD);
680 printf("cmd=0x%08x\n", i);
681
682 if (i & EHCI_CMD_ITC_1)
683 printf(" EHCI_CMD_ITC_1\n");
684 if (i & EHCI_CMD_ITC_2)
685 printf(" EHCI_CMD_ITC_2\n");
686 if (i & EHCI_CMD_ITC_4)
687 printf(" EHCI_CMD_ITC_4\n");
688 if (i & EHCI_CMD_ITC_8)
689 printf(" EHCI_CMD_ITC_8\n");
690 if (i & EHCI_CMD_ITC_16)
691 printf(" EHCI_CMD_ITC_16\n");
692 if (i & EHCI_CMD_ITC_32)
693 printf(" EHCI_CMD_ITC_32\n");
694 if (i & EHCI_CMD_ITC_64)
695 printf(" EHCI_CMD_ITC_64\n");
696 if (i & EHCI_CMD_ASPME)
697 printf(" EHCI_CMD_ASPME\n");
698 if (i & EHCI_CMD_ASPMC)
699 printf(" EHCI_CMD_ASPMC\n");
700 if (i & EHCI_CMD_LHCR)
701 printf(" EHCI_CMD_LHCR\n");
702 if (i & EHCI_CMD_IAAD)
703 printf(" EHCI_CMD_IAAD\n");
704 if (i & EHCI_CMD_ASE)
705 printf(" EHCI_CMD_ASE\n");
706 if (i & EHCI_CMD_PSE)
707 printf(" EHCI_CMD_PSE\n");
708 if (i & EHCI_CMD_FLS_M)
709 printf(" EHCI_CMD_FLS_M\n");
710 if (i & EHCI_CMD_HCRESET)
711 printf(" EHCI_CMD_HCRESET\n");
712 if (i & EHCI_CMD_RS)
713 printf(" EHCI_CMD_RS\n");
714
715 i = EOREAD4(sc, EHCI_USBSTS);
716
717 printf("sts=0x%08x\n", i);
718
719 if (i & EHCI_STS_ASS)
720 printf(" EHCI_STS_ASS\n");
721 if (i & EHCI_STS_PSS)
722 printf(" EHCI_STS_PSS\n");
723 if (i & EHCI_STS_REC)
724 printf(" EHCI_STS_REC\n");
725 if (i & EHCI_STS_HCH)
726 printf(" EHCI_STS_HCH\n");
727 if (i & EHCI_STS_IAA)
728 printf(" EHCI_STS_IAA\n");
729 if (i & EHCI_STS_HSE)
730 printf(" EHCI_STS_HSE\n");
731 if (i & EHCI_STS_FLR)
732 printf(" EHCI_STS_FLR\n");
733 if (i & EHCI_STS_PCD)
734 printf(" EHCI_STS_PCD\n");
735 if (i & EHCI_STS_ERRINT)
736 printf(" EHCI_STS_ERRINT\n");
737 if (i & EHCI_STS_INT)
738 printf(" EHCI_STS_INT\n");
739
740 printf("ien=0x%08x\n",
741 EOREAD4(sc, EHCI_USBINTR));
742 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
743 EOREAD4(sc, EHCI_FRINDEX),
744 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
745 EOREAD4(sc, EHCI_PERIODICLISTBASE),
746 EOREAD4(sc, EHCI_ASYNCLISTADDR));
747 for (i = 1; i <= sc->sc_noport; i++) {
748 printf("port %d status=0x%08x\n", i,
749 EOREAD4(sc, EHCI_PORTSC(i)));
750 }
751}
752
753static void
754ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
755{
756 link = hc32toh(sc, link);
757 printf("0x%08x", link);
758 if (link & EHCI_LINK_TERMINATE)
759 printf("<T>");
760 else {
761 printf("<");
762 if (type) {
763 switch (EHCI_LINK_TYPE(link)) {
764 case EHCI_LINK_ITD:
765 printf("ITD");
766 break;
767 case EHCI_LINK_QH:
768 printf("QH");
769 break;
770 case EHCI_LINK_SITD:
771 printf("SITD");
772 break;
773 case EHCI_LINK_FSTN:
774 printf("FSTN");
775 break;
776 }
777 }
778 printf(">");
779 }
780}
781
782static void
783ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
784{
785 uint32_t s;
786
787 printf(" next=");
788 ehci_dump_link(sc, qtd->qtd_next, 0);
789 printf(" altnext=");
790 ehci_dump_link(sc, qtd->qtd_altnext, 0);
791 printf("\n");
792 s = hc32toh(sc, qtd->qtd_status);
793 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
794 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
795 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
796 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
797 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
798 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
799 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
800 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
801 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
802 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
803 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
804 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
805 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
806
807 for (s = 0; s < 5; s++) {
808 printf(" buffer[%d]=0x%08x\n", s,
809 hc32toh(sc, qtd->qtd_buffer[s]));
810 }
811 for (s = 0; s < 5; s++) {
812 printf(" buffer_hi[%d]=0x%08x\n", s,
813 hc32toh(sc, qtd->qtd_buffer_hi[s]));
814 }
815}
816
817static uint8_t
818ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
819{
820 uint8_t temp;
821
822 usb_pc_cpu_invalidate(sqtd->page_cache);
823 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
824 ehci_dump_qtd(sc, sqtd);
825 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
826 return (temp);
827}
828
829static void
830ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
831{
832 uint16_t i;
833 uint8_t stop;
834
835 stop = 0;
836 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
837 stop = ehci_dump_sqtd(sc, sqtd);
838 }
839 if (sqtd) {
840 printf("dump aborted, too many TDs\n");
841 }
842}
843
844static void
845ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
846{
847 uint32_t endp;
848 uint32_t endphub;
849
850 usb_pc_cpu_invalidate(qh->page_cache);
851 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
852 printf(" link=");
853 ehci_dump_link(sc, qh->qh_link, 1);
854 printf("\n");
855 endp = hc32toh(sc, qh->qh_endp);
856 printf(" endp=0x%08x\n", endp);
857 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
858 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
859 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
860 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
861 printf(" mpl=0x%x ctl=%d nrl=%d\n",
862 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
863 EHCI_QH_GET_NRL(endp));
864 endphub = hc32toh(sc, qh->qh_endphub);
865 printf(" endphub=0x%08x\n", endphub);
866 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
867 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
868 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
869 EHCI_QH_GET_MULT(endphub));
870 printf(" curqtd=");
871 ehci_dump_link(sc, qh->qh_curqtd, 0);
872 printf("\n");
873 printf("Overlay qTD:\n");
874 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
875}
876
877static void
878ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
879{
880 usb_pc_cpu_invalidate(sitd->page_cache);
881 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
882 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
883 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
884 hc32toh(sc, sitd->sitd_portaddr),
885 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
886 ? "in" : "out",
887 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
888 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
889 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
890 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
891 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
892 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
893 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
894 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
895 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
896 hc32toh(sc, sitd->sitd_back),
897 hc32toh(sc, sitd->sitd_bp[0]),
898 hc32toh(sc, sitd->sitd_bp[1]),
899 hc32toh(sc, sitd->sitd_bp_hi[0]),
900 hc32toh(sc, sitd->sitd_bp_hi[1]));
901}
902
903static void
904ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
905{
906 usb_pc_cpu_invalidate(itd->page_cache);
907 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
908 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
909 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
910 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
911 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
912 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
913 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
914 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
915 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
916 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
917 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
918 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
919 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
920 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
921 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
922 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
923 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
924 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
925 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
926 printf(" addr=0x%02x; endpt=0x%01x\n",
927 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
928 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
929 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
930 printf(" dir=%s; mpl=0x%02x\n",
931 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
932 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
933 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
934 hc32toh(sc, itd->itd_bp[2]),
935 hc32toh(sc, itd->itd_bp[3]),
936 hc32toh(sc, itd->itd_bp[4]),
937 hc32toh(sc, itd->itd_bp[5]),
938 hc32toh(sc, itd->itd_bp[6]));
939 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
940 " 0x%08x,0x%08x,0x%08x\n",
941 hc32toh(sc, itd->itd_bp_hi[0]),
942 hc32toh(sc, itd->itd_bp_hi[1]),
943 hc32toh(sc, itd->itd_bp_hi[2]),
944 hc32toh(sc, itd->itd_bp_hi[3]),
945 hc32toh(sc, itd->itd_bp_hi[4]),
946 hc32toh(sc, itd->itd_bp_hi[5]),
947 hc32toh(sc, itd->itd_bp_hi[6]));
948}
949
950static void
951ehci_dump_isoc(ehci_softc_t *sc)
952{
953 ehci_itd_t *itd;
954 ehci_sitd_t *sitd;
955 uint16_t max = 1000;
956 uint16_t pos;
957
958 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
959 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
960
961 printf("%s: isochronous dump from frame 0x%03x:\n",
962 __FUNCTION__, pos);
963
964 itd = sc->sc_isoc_hs_p_last[pos];
965 sitd = sc->sc_isoc_fs_p_last[pos];
966
967 while (itd && max && max--) {
968 ehci_dump_itd(sc, itd);
969 itd = itd->prev;
970 }
971
972 while (sitd && max && max--) {
973 ehci_dump_sitd(sc, sitd);
974 sitd = sitd->prev;
975 }
976}
977
978#endif
979
980static void
981ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
982{
983 /* check for early completion */
984 if (ehci_check_transfer(xfer)) {
985 return;
986 }
987 /* put transfer on interrupt queue */
988 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
989
990 /* start timeout, if any */
991 if (xfer->timeout != 0) {
992 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
993 }
994}
995
996#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
997static ehci_sitd_t *
998_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
999{
1000 DPRINTFN(11, "%p to %p\n", std, last);
1001
1002 /* (sc->sc_bus.mtx) must be locked */
1003
1004 std->next = last->next;
1005 std->sitd_next = last->sitd_next;
1006
1007 std->prev = last;
1008
1009 usb_pc_cpu_flush(std->page_cache);
1010
1011 /*
1012 * the last->next->prev is never followed: std->next->prev = std;
1013 */
1014 last->next = std;
1015 last->sitd_next = std->sitd_self;
1016
1017 usb_pc_cpu_flush(last->page_cache);
1018
1019 return (std);
1020}
1021
1022#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
1023static ehci_itd_t *
1024_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1025{
1026 DPRINTFN(11, "%p to %p\n", std, last);
1027
1028 /* (sc->sc_bus.mtx) must be locked */
1029
1030 std->next = last->next;
1031 std->itd_next = last->itd_next;
1032
1033 std->prev = last;
1034
1035 usb_pc_cpu_flush(std->page_cache);
1036
1037 /*
1038 * the last->next->prev is never followed: std->next->prev = std;
1039 */
1040 last->next = std;
1041 last->itd_next = std->itd_self;
1042
1043 usb_pc_cpu_flush(last->page_cache);
1044
1045 return (std);
1046}
1047
1048#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1049static ehci_qh_t *
1050_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1051{
1052 DPRINTFN(11, "%p to %p\n", sqh, last);
1053
1054 if (sqh->prev != NULL) {
1055 /* should not happen */
1056 DPRINTFN(0, "QH already linked!\n");
1057 return (last);
1058 }
1059 /* (sc->sc_bus.mtx) must be locked */
1060
1061 sqh->next = last->next;
1062 sqh->qh_link = last->qh_link;
1063
1064 sqh->prev = last;
1065
1066 usb_pc_cpu_flush(sqh->page_cache);
1067
1068 /*
1069 * the last->next->prev is never followed: sqh->next->prev = sqh;
1070 */
1071
1072 last->next = sqh;
1073 last->qh_link = sqh->qh_self;
1074
1075 usb_pc_cpu_flush(last->page_cache);
1076
1077 return (sqh);
1078}
1079
1080#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1081static ehci_sitd_t *
1082_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1083{
1084 DPRINTFN(11, "%p from %p\n", std, last);
1085
1086 /* (sc->sc_bus.mtx) must be locked */
1087
1088 std->prev->next = std->next;
1089 std->prev->sitd_next = std->sitd_next;
1090
1091 usb_pc_cpu_flush(std->prev->page_cache);
1092
1093 if (std->next) {
1094 std->next->prev = std->prev;
1095 usb_pc_cpu_flush(std->next->page_cache);
1096 }
1097 return ((last == std) ? std->prev : last);
1098}
1099
1100#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1101static ehci_itd_t *
1102_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1103{
1104 DPRINTFN(11, "%p from %p\n", std, last);
1105
1106 /* (sc->sc_bus.mtx) must be locked */
1107
1108 std->prev->next = std->next;
1109 std->prev->itd_next = std->itd_next;
1110
1111 usb_pc_cpu_flush(std->prev->page_cache);
1112
1113 if (std->next) {
1114 std->next->prev = std->prev;
1115 usb_pc_cpu_flush(std->next->page_cache);
1116 }
1117 return ((last == std) ? std->prev : last);
1118}
1119
1120#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1121static ehci_qh_t *
1122_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1123{
1124 DPRINTFN(11, "%p from %p\n", sqh, last);
1125
1126 /* (sc->sc_bus.mtx) must be locked */
1127
1128 /* only remove if not removed from a queue */
1129 if (sqh->prev) {
1130
1131 sqh->prev->next = sqh->next;
1132 sqh->prev->qh_link = sqh->qh_link;
1133
1134 usb_pc_cpu_flush(sqh->prev->page_cache);
1135
1136 if (sqh->next) {
1137 sqh->next->prev = sqh->prev;
1138 usb_pc_cpu_flush(sqh->next->page_cache);
1139 }
1140 last = ((last == sqh) ? sqh->prev : last);
1141
1142 sqh->prev = 0;
1143
1144 usb_pc_cpu_flush(sqh->page_cache);
1145 }
1146 return (last);
1147}
1148
1149static usb_error_t
1150ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1151{
1152 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1153 ehci_qtd_t *td;
1154 ehci_qtd_t *td_alt_next;
1155 uint32_t status;
1156 uint16_t len;
1157
1158 td = xfer->td_transfer_cache;
1159 td_alt_next = td->alt_next;
1160
1161 if (xfer->aframes != xfer->nframes) {
1162 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1163 }
1164 while (1) {
1165
1166 usb_pc_cpu_invalidate(td->page_cache);
1167 status = hc32toh(sc, td->qtd_status);
1168
1169 len = EHCI_QTD_GET_BYTES(status);
1170
1171 /*
1172 * Verify the status length and
1173 * add the length to "frlengths[]":
1174 */
1175 if (len > td->len) {
1176 /* should not happen */
1177 DPRINTF("Invalid status length, "
1178 "0x%04x/0x%04x bytes\n", len, td->len);
1179 status |= EHCI_QTD_HALTED;
1180 } else if (xfer->aframes != xfer->nframes) {
1181 xfer->frlengths[xfer->aframes] += td->len - len;
1182 }
1183 /* Check for last transfer */
1184 if (((void *)td) == xfer->td_transfer_last) {
1185 td = NULL;
1186 break;
1187 }
1188 /* Check for transfer error */
1189 if (status & EHCI_QTD_HALTED) {
1190 /* the transfer is finished */
1191 td = NULL;
1192 break;
1193 }
1194 /* Check for short transfer */
1195 if (len > 0) {
1196 if (xfer->flags_int.short_frames_ok) {
1197 /* follow alt next */
1198 td = td->alt_next;
1199 } else {
1200 /* the transfer is finished */
1201 td = NULL;
1202 }
1203 break;
1204 }
1205 td = td->obj_next;
1206
1207 if (td->alt_next != td_alt_next) {
1208 /* this USB frame is complete */
1209 break;
1210 }
1211 }
1212
1213 /* update transfer cache */
1214
1215 xfer->td_transfer_cache = td;
1216
1217#if USB_DEBUG
1218 if (status & EHCI_QTD_STATERRS) {
1219 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1220 "status=%s%s%s%s%s%s%s%s\n",
1221 xfer->address, xfer->endpointno, xfer->aframes,
1222 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1223 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1224 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1225 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1226 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1227 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1228 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1229 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1230 }
1231#endif
1232
1233 return ((status & EHCI_QTD_HALTED) ?
1234 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1235}
1236
1237static void
1238ehci_non_isoc_done(struct usb_xfer *xfer)
1239{
1240 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1241 ehci_qh_t *qh;
1242 uint32_t status;
1243 usb_error_t err = 0;
1244
1245 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1246 xfer, xfer->endpoint);
1247
1248#if USB_DEBUG
1249 if (ehcidebug > 10) {
1250 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1251
1252 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1253 }
1254#endif
1255
1256 /* extract data toggle directly from the QH's overlay area */
1257
1258 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1259
1260 usb_pc_cpu_invalidate(qh->page_cache);
1261
1262 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1263
1264 xfer->endpoint->toggle_next =
1265 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0;
1266
1267 /* reset scanner */
1268
1269 xfer->td_transfer_cache = xfer->td_transfer_first;
1270
1271 if (xfer->flags_int.control_xfr) {
1272
1273 if (xfer->flags_int.control_hdr) {
1274
1275 err = ehci_non_isoc_done_sub(xfer);
1276 }
1277 xfer->aframes = 1;
1278
1279 if (xfer->td_transfer_cache == NULL) {
1280 goto done;
1281 }
1282 }
1283 while (xfer->aframes != xfer->nframes) {
1284
1285 err = ehci_non_isoc_done_sub(xfer);
1286 xfer->aframes++;
1287
1288 if (xfer->td_transfer_cache == NULL) {
1289 goto done;
1290 }
1291 }
1292
1293 if (xfer->flags_int.control_xfr &&
1294 !xfer->flags_int.control_act) {
1295
1296 err = ehci_non_isoc_done_sub(xfer);
1297 }
1298done:
1299 ehci_device_done(xfer, err);
1300}
1301
1302/*------------------------------------------------------------------------*
1303 * ehci_check_transfer
1304 *
1305 * Return values:
1306 * 0: USB transfer is not finished
1307 * Else: USB transfer is finished
1308 *------------------------------------------------------------------------*/
1309static uint8_t
1310ehci_check_transfer(struct usb_xfer *xfer)
1311{
1312 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1313 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1314
1315 uint32_t status;
1316
1317 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1318
1319 if (methods == &ehci_device_isoc_fs_methods) {
1320 ehci_sitd_t *td;
1321
1322 /* isochronous full speed transfer */
1323
1324 td = xfer->td_transfer_last;
1325 usb_pc_cpu_invalidate(td->page_cache);
1326 status = hc32toh(sc, td->sitd_status);
1327
1328 /* also check if first is complete */
1329
1330 td = xfer->td_transfer_first;
1331 usb_pc_cpu_invalidate(td->page_cache);
1332 status |= hc32toh(sc, td->sitd_status);
1333
1334 if (!(status & EHCI_SITD_ACTIVE)) {
1335 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1336 goto transferred;
1337 }
1338 } else if (methods == &ehci_device_isoc_hs_methods) {
1339 ehci_itd_t *td;
1340
1341 /* isochronous high speed transfer */
1342
1343 td = xfer->td_transfer_last;
1344 usb_pc_cpu_invalidate(td->page_cache);
1345 status =
1346 td->itd_status[0] | td->itd_status[1] |
1347 td->itd_status[2] | td->itd_status[3] |
1348 td->itd_status[4] | td->itd_status[5] |
1349 td->itd_status[6] | td->itd_status[7];
1350
1351 /* also check first transfer */
1352 td = xfer->td_transfer_first;
1353 usb_pc_cpu_invalidate(td->page_cache);
1354 status |=
1355 td->itd_status[0] | td->itd_status[1] |
1356 td->itd_status[2] | td->itd_status[3] |
1357 td->itd_status[4] | td->itd_status[5] |
1358 td->itd_status[6] | td->itd_status[7];
1359
1360 /* if no transactions are active we continue */
1361 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1362 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1363 goto transferred;
1364 }
1365 } else {
1366 ehci_qtd_t *td;
1367 ehci_qh_t *qh;
1368
1369 /* non-isochronous transfer */
1370
1371 /*
1372 * check whether there is an error somewhere in the middle,
1373 * or whether there was a short packet (SPD and not ACTIVE)
1374 */
1375 td = xfer->td_transfer_cache;
1376
1377 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1378
1379 usb_pc_cpu_invalidate(qh->page_cache);
1380
1381 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1382 if (status & EHCI_QTD_ACTIVE) {
1383 /* transfer is pending */
1384 goto done;
1385 }
1386
1387 while (1) {
1388 usb_pc_cpu_invalidate(td->page_cache);
1389 status = hc32toh(sc, td->qtd_status);
1390
1391 /*
1392 * Check if there is an active TD which
1393 * indicates that the transfer isn't done.
1394 */
1395 if (status & EHCI_QTD_ACTIVE) {
1396 /* update cache */
1397 if (xfer->td_transfer_cache != td) {
1398 xfer->td_transfer_cache = td;
1399 if (qh->qh_qtd.qtd_next &
1400 htohc32(sc, EHCI_LINK_TERMINATE)) {
1401 /* XXX - manually advance to next frame */
1402 qh->qh_qtd.qtd_next = td->qtd_self;
1403 usb_pc_cpu_flush(td->page_cache);
1404 }
1405 }
1406 goto done;
1407 }
1408 /*
1409 * last transfer descriptor makes the transfer done
1410 */
1411 if (((void *)td) == xfer->td_transfer_last) {
1412 break;
1413 }
1414 /*
1415 * any kind of error makes the transfer done
1416 */
1417 if (status & EHCI_QTD_HALTED) {
1418 break;
1419 }
1420 /*
1421 * if there is no alternate next transfer, a short
1422 * packet also makes the transfer done
1423 */
1424 if (EHCI_QTD_GET_BYTES(status)) {
1425 if (xfer->flags_int.short_frames_ok) {
1426 /* follow alt next */
1427 if (td->alt_next) {
1428 td = td->alt_next;
1429 continue;
1430 }
1431 }
1432 /* transfer is done */
1433 break;
1434 }
1435 td = td->obj_next;
1436 }
1437 ehci_non_isoc_done(xfer);
1438 goto transferred;
1439 }
1440
1441done:
1442 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1443 return (0);
1444
1445transferred:
1446 return (1);
1447}
1448
1449static void
1450ehci_pcd_enable(ehci_softc_t *sc)
1451{
1452 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1453
1454 sc->sc_eintrs |= EHCI_STS_PCD;
1455 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1456
1457 /* acknowledge any PCD interrupt */
1458 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1459
1460 ehci_root_intr(sc);
1461}
1462
1463static void
1464ehci_interrupt_poll(ehci_softc_t *sc)
1465{
1466 struct usb_xfer *xfer;
1467
1468repeat:
1469 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1470 /*
1471 * check if transfer is transferred
1472 */
1473 if (ehci_check_transfer(xfer)) {
1474 /* queue has been modified */
1475 goto repeat;
1476 }
1477 }
1478}
1479
1480/*
1481 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1482 * writing back the qTD status, or miss signalling occasionally under
1483 * heavy load. If the host machine is too fast, we can miss
1484 * transaction completion - when we scan the active list the
1485 * transaction still seems to be active. This generally exhibits
1486 * itself as a umass stall that never recovers.
1487 *
1488 * We work around this behaviour by setting up this callback after any
1489 * softintr that completes with transactions still pending, giving us
1490 * another chance to check for completion after the writeback has
1491 * taken place.
1492 */
1493static void
1494ehci_poll_timeout(void *arg)
1495{
1496 ehci_softc_t *sc = arg;
1497
1498 DPRINTFN(3, "\n");
1499 ehci_interrupt_poll(sc);
1500}
1501
1502/*------------------------------------------------------------------------*
1503 * ehci_interrupt - EHCI interrupt handler
1504 *
1505 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1506 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1507 * is present !
1508 *------------------------------------------------------------------------*/
1509void
1510ehci_interrupt(ehci_softc_t *sc)
1511{
1512 uint32_t status;
1513
1514 USB_BUS_LOCK(&sc->sc_bus);
1515
1516 DPRINTFN(16, "real interrupt\n");
1517
1518#if USB_DEBUG
1519 if (ehcidebug > 15) {
1520 ehci_dump_regs(sc);
1521 }
1522#endif
1523
1524 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1525 if (status == 0) {
1526 /* the interrupt was not for us */
1527 goto done;
1528 }
1529 if (!(status & sc->sc_eintrs)) {
1530 goto done;
1531 }
1532 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1533
1534 status &= sc->sc_eintrs;
1535
1536 if (status & EHCI_STS_HSE) {
1537 printf("%s: unrecoverable error, "
1538 "controller halted\n", __FUNCTION__);
1539#if USB_DEBUG
1540 ehci_dump_regs(sc);
1541 ehci_dump_isoc(sc);
1542#endif
1543 }
1544 if (status & EHCI_STS_PCD) {
1545 /*
1546 * Disable PCD interrupt for now, because it will be
1547 * on until the port has been reset.
1548 */
1549 sc->sc_eintrs &= ~EHCI_STS_PCD;
1550 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1551
1552 ehci_root_intr(sc);
1553
1554 /* do not allow RHSC interrupts > 1 per second */
1555 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1556 (void *)&ehci_pcd_enable, sc);
1557 }
1558 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1559
1560 if (status != 0) {
1561 /* block unprocessed interrupts */
1562 sc->sc_eintrs &= ~status;
1563 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1564 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1565 }
1566 /* poll all the USB transfers */
1567 ehci_interrupt_poll(sc);
1568
1569 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1570 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1571 (void *)&ehci_poll_timeout, sc);
1572 }
1573
1574done:
1575 USB_BUS_UNLOCK(&sc->sc_bus);
1576}
1577
1578/*
1579 * called when a request does not complete
1580 */
1581static void
1582ehci_timeout(void *arg)
1583{
1584 struct usb_xfer *xfer = arg;
1585
1586 DPRINTF("xfer=%p\n", xfer);
1587
1588 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1589
1590 /* transfer is transferred */
1591 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1592}
1593
1594static void
1595ehci_do_poll(struct usb_bus *bus)
1596{
1597 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1598
1599 USB_BUS_LOCK(&sc->sc_bus);
1600 ehci_interrupt_poll(sc);
1601 USB_BUS_UNLOCK(&sc->sc_bus);
1602}
1603
1604static void
1605ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1606{
1607 struct usb_page_search buf_res;
1608 ehci_qtd_t *td;
1609 ehci_qtd_t *td_next;
1610 ehci_qtd_t *td_alt_next;
1611 uint32_t buf_offset;
1612 uint32_t average;
1613 uint32_t len_old;
1614 uint32_t terminate;
1615 uint8_t shortpkt_old;
1616 uint8_t precompute;
1617
1618 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE);
1619 td_alt_next = NULL;
1620 buf_offset = 0;
1621 shortpkt_old = temp->shortpkt;
1622 len_old = temp->len;
1623 precompute = 1;
1624
1625restart:
1626
1627 td = temp->td;
1628 td_next = temp->td_next;
1629
1630 while (1) {
1631
1632 if (temp->len == 0) {
1633
1634 if (temp->shortpkt) {
1635 break;
1636 }
1637 /* send a Zero Length Packet, ZLP, last */
1638
1639 temp->shortpkt = 1;
1640 average = 0;
1641
1642 } else {
1643
1644 average = temp->average;
1645
1646 if (temp->len < average) {
1647 if (temp->len % temp->max_frame_size) {
1648 temp->shortpkt = 1;
1649 }
1650 average = temp->len;
1651 }
1652 }
1653
1654 if (td_next == NULL) {
1655 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1656 }
1657 /* get next TD */
1658
1659 td = td_next;
1660 td_next = td->obj_next;
1661
1662 /* check if we are pre-computing */
1663
1664 if (precompute) {
1665
1666 /* update remaining length */
1667
1668 temp->len -= average;
1669
1670 continue;
1671 }
1672 /* fill out current TD */
1673
1674 td->qtd_status =
1675 temp->qtd_status |
1676 htohc32(temp->sc, EHCI_QTD_IOC |
1677 EHCI_QTD_SET_BYTES(average));
1678
1679 if (average == 0) {
1680
1681 if (temp->auto_data_toggle == 0) {
1682
1683 /* update data toggle, ZLP case */
1684
1685 temp->qtd_status ^=
1686 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1687 }
1688 td->len = 0;
1689
1690 td->qtd_buffer[0] = 0;
1691 td->qtd_buffer_hi[0] = 0;
1692
1693 td->qtd_buffer[1] = 0;
1694 td->qtd_buffer_hi[1] = 0;
1695
1696 } else {
1697
1698 uint8_t x;
1699
1700 if (temp->auto_data_toggle == 0) {
1701
1702 /* update data toggle */
1703
1704 if (((average + temp->max_frame_size - 1) /
1705 temp->max_frame_size) & 1) {
1706 temp->qtd_status ^=
1707 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1708 }
1709 }
1710 td->len = average;
1711
1712 /* update remaining length */
1713
1714 temp->len -= average;
1715
1716 /* fill out buffer pointers */
1717
1718 usbd_get_page(temp->pc, buf_offset, &buf_res);
1719 td->qtd_buffer[0] =
1720 htohc32(temp->sc, buf_res.physaddr);
1721 td->qtd_buffer_hi[0] = 0;
1722
1723 x = 1;
1724
1725 while (average > EHCI_PAGE_SIZE) {
1726 average -= EHCI_PAGE_SIZE;
1727 buf_offset += EHCI_PAGE_SIZE;
1728 usbd_get_page(temp->pc, buf_offset, &buf_res);
1729 td->qtd_buffer[x] =
1730 htohc32(temp->sc,
1731 buf_res.physaddr & (~0xFFF));
1732 td->qtd_buffer_hi[x] = 0;
1733 x++;
1734 }
1735
1736 /*
1737 * NOTE: The "average" variable is never zero after
1738 * exiting the loop above !
1739 *
1740 * NOTE: We have to subtract one from the offset to
1741 * ensure that we are computing the physical address
1742 * of a valid page !
1743 */
1744 buf_offset += average;
1745 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1746 td->qtd_buffer[x] =
1747 htohc32(temp->sc,
1748 buf_res.physaddr & (~0xFFF));
1749 td->qtd_buffer_hi[x] = 0;
1750 }
1751
1752 if (temp->can_use_next) {
1753 if (td_next) {
1754 /* link the current TD with the next one */
1755 td->qtd_next = td_next->qtd_self;
1756 }
1757 } else {
1758 /*
1759 * BUG WARNING: The EHCI HW can use the
1760 * qtd_next field instead of qtd_altnext when
1761 * a short packet is received! We work this
1762 * around in software by not queueing more
1763 * than one job/TD at a time!
1764 */
1765 td->qtd_next = terminate;
1766 }
1767
1768 td->qtd_altnext = terminate;
1769 td->alt_next = td_alt_next;
1770
1771 usb_pc_cpu_flush(td->page_cache);
1772 }
1773
1774 if (precompute) {
1775 precompute = 0;
1776
1777 /* setup alt next pointer, if any */
1778 if (temp->last_frame) {
1779 td_alt_next = NULL;
1780 } else {
1781 /* we use this field internally */
1782 td_alt_next = td_next;
1783 }
1784
1785 /* restore */
1786 temp->shortpkt = shortpkt_old;
1787 temp->len = len_old;
1788 goto restart;
1789 }
1790 temp->td = td;
1791 temp->td_next = td_next;
1792}
1793
1794static void
1795ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1796{
1797 struct ehci_std_temp temp;
1798 struct usb_pipe_methods *methods;
1799 ehci_qh_t *qh;
1800 ehci_qtd_t *td;
1801 uint32_t qh_endp;
1802 uint32_t qh_endphub;
1803 uint32_t x;
1804
1805 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1806 xfer->address, UE_GET_ADDR(xfer->endpointno),
1807 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1808
1809 temp.average = xfer->max_hc_frame_size;
1810 temp.max_frame_size = xfer->max_frame_size;
1811 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1812
1813 /* toggle the DMA set we are using */
1814 xfer->flags_int.curr_dma_set ^= 1;
1815
1816 /* get next DMA set */
1817 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1818
1819 xfer->td_transfer_first = td;
1820 xfer->td_transfer_cache = td;
1821
1822 temp.td = NULL;
1823 temp.td_next = td;
1824 temp.qtd_status = 0;
1825 temp.last_frame = 0;
1826 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1827 temp.can_use_next = (xfer->flags_int.control_xfr ||
1828 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT));
1829
1830 if (xfer->flags_int.control_xfr) {
1831 if (xfer->endpoint->toggle_next) {
1832 /* DATA1 is next */
1833 temp.qtd_status |=
1834 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1835 }
1836 temp.auto_data_toggle = 0;
1837 } else {
1838 temp.auto_data_toggle = 1;
1839 }
1840
1841 if (usbd_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) {
1842 /* max 3 retries */
1843 temp.qtd_status |=
1844 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1845 }
1846 /* check if we should prepend a setup message */
1847
1848 if (xfer->flags_int.control_xfr) {
1849 if (xfer->flags_int.control_hdr) {
1850
1851 temp.qtd_status &=
1852 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1853 temp.qtd_status |= htohc32(temp.sc,
1854 EHCI_QTD_ACTIVE |
1855 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1856 EHCI_QTD_SET_TOGGLE(0));
1857
1858 temp.len = xfer->frlengths[0];
1859 temp.pc = xfer->frbuffers + 0;
1860 temp.shortpkt = temp.len ? 1 : 0;
1861 /* check for last frame */
1862 if (xfer->nframes == 1) {
1863 /* no STATUS stage yet, SETUP is last */
1864 if (xfer->flags_int.control_act) {
1865 temp.last_frame = 1;
1866 temp.setup_alt_next = 0;
1867 }
1868 }
1869 ehci_setup_standard_chain_sub(&temp);
1870 }
1871 x = 1;
1872 } else {
1873 x = 0;
1874 }
1875
1876 while (x != xfer->nframes) {
1877
1878 /* DATA0 / DATA1 message */
1879
1880 temp.len = xfer->frlengths[x];
1881 temp.pc = xfer->frbuffers + x;
1882
1883 x++;
1884
1885 if (x == xfer->nframes) {
1886 if (xfer->flags_int.control_xfr) {
1887 /* no STATUS stage yet, DATA is last */
1888 if (xfer->flags_int.control_act) {
1889 temp.last_frame = 1;
1890 temp.setup_alt_next = 0;
1891 }
1892 } else {
1893 temp.last_frame = 1;
1894 temp.setup_alt_next = 0;
1895 }
1896 }
1897 /* keep previous data toggle and error count */
1898
1899 temp.qtd_status &=
1900 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1901 EHCI_QTD_SET_TOGGLE(1));
1902
1903 if (temp.len == 0) {
1904
1905 /* make sure that we send an USB packet */
1906
1907 temp.shortpkt = 0;
1908
1909 } else {
1910
1911 /* regular data transfer */
1912
1913 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1914 }
1915
1916 /* set endpoint direction */
1917
1918 temp.qtd_status |=
1919 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1920 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1921 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1922 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1923 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1924
1925 ehci_setup_standard_chain_sub(&temp);
1926 }
1927
1928 /* check if we should append a status stage */
1929
1930 if (xfer->flags_int.control_xfr &&
1931 !xfer->flags_int.control_act) {
1932
1933 /*
1934 * Send a DATA1 message and invert the current endpoint
1935 * direction.
1936 */
1937
1938 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1939 EHCI_QTD_SET_TOGGLE(1));
1940 temp.qtd_status |=
1941 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1942 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1943 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1944 EHCI_QTD_SET_TOGGLE(1)) :
1945 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1946 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1947 EHCI_QTD_SET_TOGGLE(1));
1948
1949 temp.len = 0;
1950 temp.pc = NULL;
1951 temp.shortpkt = 0;
1952 temp.last_frame = 1;
1953 temp.setup_alt_next = 0;
1954
1955 ehci_setup_standard_chain_sub(&temp);
1956 }
1957 td = temp.td;
1958
1959 /* the last TD terminates the transfer: */
1960 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1961 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1962
1963 usb_pc_cpu_flush(td->page_cache);
1964
1965 /* must have at least one frame! */
1966
1967 xfer->td_transfer_last = td;
1968
1969#if USB_DEBUG
1970 if (ehcidebug > 8) {
1971 DPRINTF("nexttog=%d; data before transfer:\n",
1972 xfer->endpoint->toggle_next);
1973 ehci_dump_sqtds(temp.sc,
1974 xfer->td_transfer_first);
1975 }
1976#endif
1977
1978 methods = xfer->endpoint->methods;
1979
1980 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1981
1982 /* the "qh_link" field is filled when the QH is added */
1983
1984 qh_endp =
1985 (EHCI_QH_SET_ADDR(xfer->address) |
1986 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1987 EHCI_QH_SET_MPL(xfer->max_packet_size));
1988
1989 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1990 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1991 if (methods != &ehci_device_intr_methods)
1992 qh_endp |= EHCI_QH_SET_NRL(8);
1993 } else {
1994
1995 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1996 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
1997 } else {
1998 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
1999 }
2000
2001 if (methods == &ehci_device_ctrl_methods) {
2002 qh_endp |= EHCI_QH_CTL;
2003 }
2004 if (methods != &ehci_device_intr_methods) {
2005 /* Only try one time per microframe! */
2006 qh_endp |= EHCI_QH_SET_NRL(1);
2007 }
2008 }
2009
2010 if (temp.auto_data_toggle == 0) {
2011 /* software computes the data toggle */
2012 qh_endp |= EHCI_QH_DTC;
2013 }
2014
2015 qh->qh_endp = htohc32(temp.sc, qh_endp);
2016
2017 qh_endphub =
2018 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
2019 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
2020 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
2021 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2022 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2023
2024 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2025 qh->qh_curqtd = 0;
2026
2027 /* fill the overlay qTD */
2028
2029 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2030 /* DATA1 is next */
2031 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2032 } else {
2033 qh->qh_qtd.qtd_status = 0;
2034 }
2035
2036 td = xfer->td_transfer_first;
2037
2038 qh->qh_qtd.qtd_next = td->qtd_self;
2039 qh->qh_qtd.qtd_altnext =
2040 htohc32(temp.sc, EHCI_LINK_TERMINATE);
2041
2042 usb_pc_cpu_flush(qh->page_cache);
2043
2044 if (xfer->xroot->udev->flags.self_suspended == 0) {
2045 EHCI_APPEND_QH(qh, *qh_last);
2046 }
2047}
2048
2049static void
2050ehci_root_intr(ehci_softc_t *sc)
2051{
2052 uint16_t i;
2053 uint16_t m;
2054
2055 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2056
2057 /* clear any old interrupt data */
2058 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2059
2060 /* set bits */
2061 m = (sc->sc_noport + 1);
2062 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2063 m = (8 * sizeof(sc->sc_hub_idata));
2064 }
2065 for (i = 1; i < m; i++) {
2066 /* pick out CHANGE bits from the status register */
2067 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2068 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2069 DPRINTF("port %d changed\n", i);
2070 }
2071 }
2072 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2073 sizeof(sc->sc_hub_idata));
2074}
2075
2076static void
2077ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2078{
2079 uint32_t nframes = xfer->nframes;
2080 uint32_t status;
2081 uint32_t *plen = xfer->frlengths;
2082 uint16_t len = 0;
2083 ehci_sitd_t *td = xfer->td_transfer_first;
2084 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2085
2086 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2087 xfer, xfer->endpoint);
2088
2089 while (nframes--) {
2090 if (td == NULL) {
2091 panic("%s:%d: out of TD's\n",
2092 __FUNCTION__, __LINE__);
2093 }
2094 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2095 pp_last = &sc->sc_isoc_fs_p_last[0];
2096 }
2097#if USB_DEBUG
2098 if (ehcidebug > 15) {
2099 DPRINTF("isoc FS-TD\n");
2100 ehci_dump_sitd(sc, td);
2101 }
2102#endif
2103 usb_pc_cpu_invalidate(td->page_cache);
2104 status = hc32toh(sc, td->sitd_status);
2105
2106 len = EHCI_SITD_GET_LEN(status);
2107
2108 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2109
2110 if (*plen >= len) {
2111 len = *plen - len;
2112 } else {
2113 len = 0;
2114 }
2115
2116 *plen = len;
2117
2118 /* remove FS-TD from schedule */
2119 EHCI_REMOVE_FS_TD(td, *pp_last);
2120
2121 pp_last++;
2122 plen++;
2123 td = td->obj_next;
2124 }
2125
2126 xfer->aframes = xfer->nframes;
2127}
2128
2129static void
2130ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2131{
2132 uint32_t nframes = xfer->nframes;
2133 uint32_t status;
2134 uint32_t *plen = xfer->frlengths;
2135 uint16_t len = 0;
2136 uint8_t td_no = 0;
2137 ehci_itd_t *td = xfer->td_transfer_first;
2138 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2139
2140 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2141 xfer, xfer->endpoint);
2142
2143 while (nframes) {
2144 if (td == NULL) {
2145 panic("%s:%d: out of TD's\n",
2146 __FUNCTION__, __LINE__);
2147 }
2148 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2149 pp_last = &sc->sc_isoc_hs_p_last[0];
2150 }
2151#if USB_DEBUG
2152 if (ehcidebug > 15) {
2153 DPRINTF("isoc HS-TD\n");
2154 ehci_dump_itd(sc, td);
2155 }
2156#endif
2157
2158 usb_pc_cpu_invalidate(td->page_cache);
2159 status = hc32toh(sc, td->itd_status[td_no]);
2160
2161 len = EHCI_ITD_GET_LEN(status);
2162
2163 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2164
2165 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2166
2167 if (*plen >= len) {
2168 /*
2169 * The length is valid. NOTE: The
2170 * complete length is written back
2171 * into the status field, and not the
2172 * remainder like with other transfer
2173 * descriptor types.
2174 */
2175 } else {
2176 /* Invalid length - truncate */
2177 len = 0;
2178 }
2179
2180 *plen = len;
2181 plen++;
2182 nframes--;
2183 }
2184
2185 td_no++;
2186
2187 if ((td_no == 8) || (nframes == 0)) {
2188 /* remove HS-TD from schedule */
2189 EHCI_REMOVE_HS_TD(td, *pp_last);
2190 pp_last++;
2191
2192 td_no = 0;
2193 td = td->obj_next;
2194 }
2195 }
2196 xfer->aframes = xfer->nframes;
2197}
2198
2199/* NOTE: "done" can be run two times in a row,
2200 * from close and from interrupt
2201 */
2202static void
2203ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2204{
2205 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2206 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2207
2208 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2209
2210 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2211 xfer, xfer->endpoint, error);
2212
2213 if ((methods == &ehci_device_bulk_methods) ||
2214 (methods == &ehci_device_ctrl_methods)) {
2215#if USB_DEBUG
2216 if (ehcidebug > 8) {
2217 DPRINTF("nexttog=%d; data after transfer:\n",
2218 xfer->endpoint->toggle_next);
2219 ehci_dump_sqtds(sc,
2220 xfer->td_transfer_first);
2221 }
2222#endif
2223
2224 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2225 sc->sc_async_p_last);
2226 }
2227 if (methods == &ehci_device_intr_methods) {
2228 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2229 sc->sc_intr_p_last[xfer->qh_pos]);
2230 }
2231 /*
2232 * Only finish isochronous transfers once which will update
2233 * "xfer->frlengths".
2234 */
2235 if (xfer->td_transfer_first &&
2236 xfer->td_transfer_last) {
2237 if (methods == &ehci_device_isoc_fs_methods) {
2238 ehci_isoc_fs_done(sc, xfer);
2239 }
2240 if (methods == &ehci_device_isoc_hs_methods) {
2241 ehci_isoc_hs_done(sc, xfer);
2242 }
2243 xfer->td_transfer_first = NULL;
2244 xfer->td_transfer_last = NULL;
2245 }
2246 /* dequeue transfer and start next transfer */
2247 usbd_transfer_done(xfer, error);
2248}
2249
2250/*------------------------------------------------------------------------*
2251 * ehci bulk support
2252 *------------------------------------------------------------------------*/
2253static void
2254ehci_device_bulk_open(struct usb_xfer *xfer)
2255{
2256 return;
2257}
2258
2259static void
2260ehci_device_bulk_close(struct usb_xfer *xfer)
2261{
2262 ehci_device_done(xfer, USB_ERR_CANCELLED);
2263}
2264
2265static void
2266ehci_device_bulk_enter(struct usb_xfer *xfer)
2267{
2268 return;
2269}
2270
2271static void
2272ehci_device_bulk_start(struct usb_xfer *xfer)
2273{
2274 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2275 uint32_t temp;
2276
2277 /* setup TD's and QH */
2278 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2279
2280 /* put transfer on interrupt queue */
2281 ehci_transfer_intr_enqueue(xfer);
2282
2283 /* XXX Performance quirk: Some Host Controllers have a too low
2284 * interrupt rate. Issue an IAAD to stimulate the Host
2285 * Controller after queueing the BULK transfer.
2286 */
2287 temp = EOREAD4(sc, EHCI_USBCMD);
2288 if (!(temp & EHCI_CMD_IAAD))
2289 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2290}
2291
2292struct usb_pipe_methods ehci_device_bulk_methods =
2293{
2294 .open = ehci_device_bulk_open,
2295 .close = ehci_device_bulk_close,
2296 .enter = ehci_device_bulk_enter,
2297 .start = ehci_device_bulk_start,
2298};
2299
2300/*------------------------------------------------------------------------*
2301 * ehci control support
2302 *------------------------------------------------------------------------*/
2303static void
2304ehci_device_ctrl_open(struct usb_xfer *xfer)
2305{
2306 return;
2307}
2308
2309static void
2310ehci_device_ctrl_close(struct usb_xfer *xfer)
2311{
2312 ehci_device_done(xfer, USB_ERR_CANCELLED);
2313}
2314
2315static void
2316ehci_device_ctrl_enter(struct usb_xfer *xfer)
2317{
2318 return;
2319}
2320
2321static void
2322ehci_device_ctrl_start(struct usb_xfer *xfer)
2323{
2324 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2325
2326 /* setup TD's and QH */
2327 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2328
2329 /* put transfer on interrupt queue */
2330 ehci_transfer_intr_enqueue(xfer);
2331}
2332
2333struct usb_pipe_methods ehci_device_ctrl_methods =
2334{
2335 .open = ehci_device_ctrl_open,
2336 .close = ehci_device_ctrl_close,
2337 .enter = ehci_device_ctrl_enter,
2338 .start = ehci_device_ctrl_start,
2339};
2340
2341/*------------------------------------------------------------------------*
2342 * ehci interrupt support
2343 *------------------------------------------------------------------------*/
2344static void
2345ehci_device_intr_open(struct usb_xfer *xfer)
2346{
2347 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2348 uint16_t best;
2349 uint16_t bit;
2350 uint16_t x;
2351
2352 usb_hs_bandwidth_alloc(xfer);
2353
2354 /*
2355 * Find the best QH position corresponding to the given interval:
2356 */
2357
2358 best = 0;
2359 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2360 while (bit) {
2361 if (xfer->interval >= bit) {
2362 x = bit;
2363 best = bit;
2364 while (x & bit) {
2365 if (sc->sc_intr_stat[x] <
2366 sc->sc_intr_stat[best]) {
2367 best = x;
2368 }
2369 x++;
2370 }
2371 break;
2372 }
2373 bit >>= 1;
2374 }
2375
2376 sc->sc_intr_stat[best]++;
2377 xfer->qh_pos = best;
2378
2379 DPRINTFN(3, "best=%d interval=%d\n",
2380 best, xfer->interval);
2381}
2382
2383static void
2384ehci_device_intr_close(struct usb_xfer *xfer)
2385{
2386 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2387
2388 sc->sc_intr_stat[xfer->qh_pos]--;
2389
2390 ehci_device_done(xfer, USB_ERR_CANCELLED);
2391
2392 /* bandwidth must be freed after device done */
2393 usb_hs_bandwidth_free(xfer);
2394}
2395
2396static void
2397ehci_device_intr_enter(struct usb_xfer *xfer)
2398{
2399 return;
2400}
2401
2402static void
2403ehci_device_intr_start(struct usb_xfer *xfer)
2404{
2405 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2406
2407 /* setup TD's and QH */
2408 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2409
2410 /* put transfer on interrupt queue */
2411 ehci_transfer_intr_enqueue(xfer);
2412}
2413
2414struct usb_pipe_methods ehci_device_intr_methods =
2415{
2416 .open = ehci_device_intr_open,
2417 .close = ehci_device_intr_close,
2418 .enter = ehci_device_intr_enter,
2419 .start = ehci_device_intr_start,
2420};
2421
2422/*------------------------------------------------------------------------*
2423 * ehci full speed isochronous support
2424 *------------------------------------------------------------------------*/
2425static void
2426ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2427{
2428 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2429 ehci_sitd_t *td;
2430 uint32_t sitd_portaddr;
2431 uint8_t ds;
2432
2433 sitd_portaddr =
2434 EHCI_SITD_SET_ADDR(xfer->address) |
2435 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2436 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2437 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2438
2439 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2440 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2441 }
2442 sitd_portaddr = htohc32(sc, sitd_portaddr);
2443
2444 /* initialize all TD's */
2445
2446 for (ds = 0; ds != 2; ds++) {
2447
2448 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2449
2450 td->sitd_portaddr = sitd_portaddr;
2451
2452 /*
2453 * TODO: make some kind of automatic
2454 * SMASK/CMASK selection based on micro-frame
2455 * usage
2456 *
2457 * micro-frame usage (8 microframes per 1ms)
2458 */
2459 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2460
2461 usb_pc_cpu_flush(td->page_cache);
2462 }
2463 }
2464}
2465
2466static void
2467ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2468{
2469 ehci_device_done(xfer, USB_ERR_CANCELLED);
2470}
2471
2472static void
2473ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2474{
2475 struct usb_page_search buf_res;
2476 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2477 struct usb_fs_isoc_schedule *fss_start;
2478 struct usb_fs_isoc_schedule *fss_end;
2479 struct usb_fs_isoc_schedule *fss;
2480 ehci_sitd_t *td;
2481 ehci_sitd_t *td_last = NULL;
2482 ehci_sitd_t **pp_last;
2483 uint32_t *plen;
2484 uint32_t buf_offset;
2485 uint32_t nframes;
2486 uint32_t temp;
2487 uint32_t sitd_mask;
2488 uint16_t tlen;
2489 uint8_t sa;
2490 uint8_t sb;
2491 uint8_t error;
2492
2493#if USB_DEBUG
2494 uint8_t once = 1;
2495
2496#endif
2497
2498 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2499 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2500
2501 /* get the current frame index */
2502
2503 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2504
2505 /*
2506 * check if the frame index is within the window where the frames
2507 * will be inserted
2508 */
2509 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2510 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2511
2512 if ((xfer->endpoint->is_synced == 0) ||
2513 (buf_offset < xfer->nframes)) {
2514 /*
2515 * If there is data underflow or the pipe queue is empty we
2516 * schedule the transfer a few frames ahead of the current
2517 * frame position. Else two isochronous transfers might
2518 * overlap.
2519 */
2520 xfer->endpoint->isoc_next = (nframes + 3) &
2521 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2522 xfer->endpoint->is_synced = 1;
2523 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2524 }
2525 /*
2526 * compute how many milliseconds the insertion is ahead of the
2527 * current frame position:
2528 */
2529 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2530 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2531
2532 /*
2533 * pre-compute when the isochronous transfer will be finished:
2534 */
2535 xfer->isoc_time_complete =
2536 usbd_fs_isoc_schedule_isoc_time_expand
2537 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2538 xfer->nframes;
2539
2540 /* get the real number of frames */
2541
2542 nframes = xfer->nframes;
2543
2544 buf_offset = 0;
2545
2546 plen = xfer->frlengths;
2547
2548 /* toggle the DMA set we are using */
2549 xfer->flags_int.curr_dma_set ^= 1;
2550
2551 /* get next DMA set */
2552 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2553 xfer->td_transfer_first = td;
2554
2555 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2556
2557 /* store starting position */
2558
2559 xfer->qh_pos = xfer->endpoint->isoc_next;
2560
2561 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2562
2563 while (nframes--) {
2564 if (td == NULL) {
2565 panic("%s:%d: out of TD's\n",
2566 __FUNCTION__, __LINE__);
2567 }
2568 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2569 pp_last = &sc->sc_isoc_fs_p_last[0];
2570 }
2571 if (fss >= fss_end) {
2572 fss = fss_start;
2573 }
2574 /* reuse sitd_portaddr and sitd_back from last transfer */
2575
2576 if (*plen > xfer->max_frame_size) {
2577#if USB_DEBUG
2578 if (once) {
2579 once = 0;
2580 printf("%s: frame length(%d) exceeds %d "
2581 "bytes (frame truncated)\n",
2582 __FUNCTION__, *plen,
2583 xfer->max_frame_size);
2584 }
2585#endif
2586 *plen = xfer->max_frame_size;
2587 }
2588 /*
2589 * We currently don't care if the ISOCHRONOUS schedule is
2590 * full!
2591 */
2592 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen);
2593 if (error) {
2594 /*
2595 * The FULL speed schedule is FULL! Set length
2596 * to zero.
2597 */
2598 *plen = 0;
2599 }
2600 if (*plen) {
2601 /*
2602 * only call "usbd_get_page()" when we have a
2603 * non-zero length
2604 */
2605 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2606 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2607 buf_offset += *plen;
2608 /*
2609 * NOTE: We need to subtract one from the offset so
2610 * that we are on a valid page!
2611 */
2612 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2613 &buf_res);
2614 temp = buf_res.physaddr & ~0xFFF;
2615 } else {
2616 td->sitd_bp[0] = 0;
2617 temp = 0;
2618 }
2619
2620 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2621 tlen = *plen;
2622 if (tlen <= 188) {
2623 temp |= 1; /* T-count = 1, TP = ALL */
2624 tlen = 1;
2625 } else {
2626 tlen += 187;
2627 tlen /= 188;
2628 temp |= tlen; /* T-count = [1..6] */
2629 temp |= 8; /* TP = Begin */
2630 }
2631
2632 tlen += sa;
2633
2634 if (tlen >= 8) {
2635 sb = 0;
2636 } else {
2637 sb = (1 << tlen);
2638 }
2639
2640 sa = (1 << sa);
2641 sa = (sb - sa) & 0x3F;
2642 sb = 0;
2643 } else {
2644 sb = (-(4 << sa)) & 0xFE;
2645 sa = (1 << sa) & 0x3F;
2646 }
2647
2648 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2649 EHCI_SITD_SET_CMASK(sb));
2650
2651 td->sitd_bp[1] = htohc32(sc, temp);
2652
2653 td->sitd_mask = htohc32(sc, sitd_mask);
2654
2655 if (nframes == 0) {
2656 td->sitd_status = htohc32(sc,
2657 EHCI_SITD_IOC |
2658 EHCI_SITD_ACTIVE |
2659 EHCI_SITD_SET_LEN(*plen));
2660 } else {
2661 td->sitd_status = htohc32(sc,
2662 EHCI_SITD_ACTIVE |
2663 EHCI_SITD_SET_LEN(*plen));
2664 }
2665 usb_pc_cpu_flush(td->page_cache);
2666
2667#if USB_DEBUG
2668 if (ehcidebug > 15) {
2669 DPRINTF("FS-TD %d\n", nframes);
2670 ehci_dump_sitd(sc, td);
2671 }
2672#endif
2673 /* insert TD into schedule */
2674 EHCI_APPEND_FS_TD(td, *pp_last);
2675 pp_last++;
2676
2677 plen++;
2678 fss++;
2679 td_last = td;
2680 td = td->obj_next;
2681 }
2682
2683 xfer->td_transfer_last = td_last;
2684
2685 /* update isoc_next */
2686 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2687 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2688}
2689
2690static void
2691ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2692{
2693 /* put transfer on interrupt queue */
2694 ehci_transfer_intr_enqueue(xfer);
2695}
2696
2697struct usb_pipe_methods ehci_device_isoc_fs_methods =
2698{
2699 .open = ehci_device_isoc_fs_open,
2700 .close = ehci_device_isoc_fs_close,
2701 .enter = ehci_device_isoc_fs_enter,
2702 .start = ehci_device_isoc_fs_start,
2703};
2704
2705/*------------------------------------------------------------------------*
2706 * ehci high speed isochronous support
2707 *------------------------------------------------------------------------*/
2708static void
2709ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2710{
2711 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2712 ehci_itd_t *td;
2713 uint32_t temp;
2714 uint8_t ds;
2715
2716 usb_hs_bandwidth_alloc(xfer);
2717
2718 /* initialize all TD's */
2719
2720 for (ds = 0; ds != 2; ds++) {
2721
2722 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2723
2724 /* set TD inactive */
2725 td->itd_status[0] = 0;
2726 td->itd_status[1] = 0;
2727 td->itd_status[2] = 0;
2728 td->itd_status[3] = 0;
2729 td->itd_status[4] = 0;
2730 td->itd_status[5] = 0;
2731 td->itd_status[6] = 0;
2732 td->itd_status[7] = 0;
2733
2734 /* set endpoint and address */
2735 td->itd_bp[0] = htohc32(sc,
2736 EHCI_ITD_SET_ADDR(xfer->address) |
2737 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2738
2739 temp =
2740 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2741
2742 /* set direction */
2743 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2744 temp |= EHCI_ITD_SET_DIR_IN;
2745 }
2746 /* set maximum packet size */
2747 td->itd_bp[1] = htohc32(sc, temp);
2748
2749 /* set transfer multiplier */
2750 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2751
2752 usb_pc_cpu_flush(td->page_cache);
2753 }
2754 }
2755}
2756
2757static void
2758ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2759{
2760 ehci_device_done(xfer, USB_ERR_CANCELLED);
2761
2762 /* bandwidth must be freed after device done */
2763 usb_hs_bandwidth_free(xfer);
2764}
2765
2766static void
2767ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2768{
2769 struct usb_page_search buf_res;
2770 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2771 ehci_itd_t *td;
2772 ehci_itd_t *td_last = NULL;
2773 ehci_itd_t **pp_last;
2774 bus_size_t page_addr;
2775 uint32_t *plen;
2776 uint32_t status;
2777 uint32_t buf_offset;
2778 uint32_t nframes;
2779 uint32_t itd_offset[8 + 1];
2780 uint8_t x;
2781 uint8_t td_no;
2782 uint8_t page_no;
2783
2784#if USB_DEBUG
2785 uint8_t once = 1;
2786
2787#endif
2788
2789 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2790 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2791
2792 /* get the current frame index */
2793
2794 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2795
2796 /*
2797 * check if the frame index is within the window where the frames
2798 * will be inserted
2799 */
2800 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2801 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2802
2803 if ((xfer->endpoint->is_synced == 0) ||
2804 (buf_offset < ((xfer->nframes + 7) / 8))) {
2805 /*
2806 * If there is data underflow or the pipe queue is empty we
2807 * schedule the transfer a few frames ahead of the current
2808 * frame position. Else two isochronous transfers might
2809 * overlap.
2810 */
2811 xfer->endpoint->isoc_next = (nframes + 3) &
2812 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2813 xfer->endpoint->is_synced = 1;
2814 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2815 }
2816 /*
2817 * compute how many milliseconds the insertion is ahead of the
2818 * current frame position:
2819 */
2820 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2821 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2822
2823 /*
2824 * pre-compute when the isochronous transfer will be finished:
2825 */
2826 xfer->isoc_time_complete =
2827 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2828 ((xfer->nframes + 7) / 8);
2829
2830 /* get the real number of frames */
2831
2832 nframes = xfer->nframes;
2833
2834 buf_offset = 0;
2835 td_no = 0;
2836
2837 plen = xfer->frlengths;
2838
2839 /* toggle the DMA set we are using */
2840 xfer->flags_int.curr_dma_set ^= 1;
2841
2842 /* get next DMA set */
2843 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2844 xfer->td_transfer_first = td;
2845
2846 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2847
2848 /* store starting position */
2849
2850 xfer->qh_pos = xfer->endpoint->isoc_next;
2851
2852 while (nframes) {
2853 if (td == NULL) {
2854 panic("%s:%d: out of TD's\n",
2855 __FUNCTION__, __LINE__);
2856 }
2857 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2858 pp_last = &sc->sc_isoc_hs_p_last[0];
2859 }
2860 /* range check */
2861 if (*plen > xfer->max_frame_size) {
2862#if USB_DEBUG
2863 if (once) {
2864 once = 0;
2865 printf("%s: frame length(%d) exceeds %d bytes "
2866 "(frame truncated)\n",
2867 __FUNCTION__, *plen, xfer->max_frame_size);
2868 }
2869#endif
2870 *plen = xfer->max_frame_size;
2871 }
2872
2873 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2874 status = (EHCI_ITD_SET_LEN(*plen) |
2875 EHCI_ITD_ACTIVE |
2876 EHCI_ITD_SET_PG(0));
2877 td->itd_status[td_no] = htohc32(sc, status);
2878 itd_offset[td_no] = buf_offset;
2879 buf_offset += *plen;
2880 plen++;
2881 nframes --;
2882 } else {
2883 td->itd_status[td_no] = 0; /* not active */
2884 itd_offset[td_no] = buf_offset;
2885 }
2886
2887 td_no++;
2888
2889 if ((td_no == 8) || (nframes == 0)) {
2890
2891 /* the rest of the transfers are not active, if any */
2892 for (x = td_no; x != 8; x++) {
2893 td->itd_status[x] = 0; /* not active */
2894 }
2895
2896 /* check if there is any data to be transferred */
2897 if (itd_offset[0] != buf_offset) {
2898 page_no = 0;
2899 itd_offset[td_no] = buf_offset;
2900
2901 /* get first page offset */
2902 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2903 /* get page address */
2904 page_addr = buf_res.physaddr & ~0xFFF;
2905 /* update page address */
2906 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2907 td->itd_bp[0] |= htohc32(sc, page_addr);
2908
2909 for (x = 0; x != td_no; x++) {
2910 /* set page number and page offset */
2911 status = (EHCI_ITD_SET_PG(page_no) |
2912 (buf_res.physaddr & 0xFFF));
2913 td->itd_status[x] |= htohc32(sc, status);
2914
2915 /* get next page offset */
2916 if (itd_offset[x + 1] == buf_offset) {
2917 /*
2918 * We subtract one so that
2919 * we don't go off the last
2920 * page!
2921 */
2922 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2923 } else {
2924 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2925 }
2926
2927 /* check if we need a new page */
2928 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2929 /* new page needed */
2930 page_addr = buf_res.physaddr & ~0xFFF;
2931 if (page_no == 6) {
2932 panic("%s: too many pages\n", __FUNCTION__);
2933 }
2934 page_no++;
2935 /* update page address */
2936 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2937 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2938 }
2939 }
2940 }
2941 /* set IOC bit if we are complete */
2942 if (nframes == 0) {
2943 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2944 }
2945 usb_pc_cpu_flush(td->page_cache);
2946#if USB_DEBUG
2947 if (ehcidebug > 15) {
2948 DPRINTF("HS-TD %d\n", nframes);
2949 ehci_dump_itd(sc, td);
2950 }
2951#endif
2952 /* insert TD into schedule */
2953 EHCI_APPEND_HS_TD(td, *pp_last);
2954 pp_last++;
2955
2956 td_no = 0;
2957 td_last = td;
2958 td = td->obj_next;
2959 }
2960 }
2961
2962 xfer->td_transfer_last = td_last;
2963
2964 /* update isoc_next */
2965 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2966 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2967}
2968
2969static void
2970ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2971{
2972 /* put transfer on interrupt queue */
2973 ehci_transfer_intr_enqueue(xfer);
2974}
2975
2976struct usb_pipe_methods ehci_device_isoc_hs_methods =
2977{
2978 .open = ehci_device_isoc_hs_open,
2979 .close = ehci_device_isoc_hs_close,
2980 .enter = ehci_device_isoc_hs_enter,
2981 .start = ehci_device_isoc_hs_start,
2982};
2983
2984/*------------------------------------------------------------------------*
2985 * ehci root control support
2986 *------------------------------------------------------------------------*
2987 * Simulate a hardware hub by handling all the necessary requests.
2988 *------------------------------------------------------------------------*/
2989
2990static const
2991struct usb_device_descriptor ehci_devd =
2992{
2993 sizeof(struct usb_device_descriptor),
2994 UDESC_DEVICE, /* type */
2995 {0x00, 0x02}, /* USB version */
2996 UDCLASS_HUB, /* class */
2997 UDSUBCLASS_HUB, /* subclass */
2998 UDPROTO_HSHUBSTT, /* protocol */
2999 64, /* max packet */
3000 {0}, {0}, {0x00, 0x01}, /* device id */
3001 1, 2, 0, /* string indicies */
3002 1 /* # of configurations */
3003};
3004
3005static const
3006struct usb_device_qualifier ehci_odevd =
3007{
3008 sizeof(struct usb_device_qualifier),
3009 UDESC_DEVICE_QUALIFIER, /* type */
3010 {0x00, 0x02}, /* USB version */
3011 UDCLASS_HUB, /* class */
3012 UDSUBCLASS_HUB, /* subclass */
3013 UDPROTO_FSHUB, /* protocol */
3014 0, /* max packet */
3015 0, /* # of configurations */
3016 0
3017};
3018
3019static const struct ehci_config_desc ehci_confd = {
3020 .confd = {
3021 .bLength = sizeof(struct usb_config_descriptor),
3022 .bDescriptorType = UDESC_CONFIG,
3023 .wTotalLength[0] = sizeof(ehci_confd),
3024 .bNumInterface = 1,
3025 .bConfigurationValue = 1,
3026 .iConfiguration = 0,
3027 .bmAttributes = UC_SELF_POWERED,
3028 .bMaxPower = 0 /* max power */
3029 },
3030 .ifcd = {
3031 .bLength = sizeof(struct usb_interface_descriptor),
3032 .bDescriptorType = UDESC_INTERFACE,
3033 .bNumEndpoints = 1,
3034 .bInterfaceClass = UICLASS_HUB,
3035 .bInterfaceSubClass = UISUBCLASS_HUB,
3036 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
3037 0
3038 },
3039 .endpd = {
3040 .bLength = sizeof(struct usb_endpoint_descriptor),
3041 .bDescriptorType = UDESC_ENDPOINT,
3042 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3043 .bmAttributes = UE_INTERRUPT,
3044 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3045 .bInterval = 255,
3046 },
3047};
3048
3049static const
3050struct usb_hub_descriptor ehci_hubd =
3051{
3052 0, /* dynamic length */
3053 UDESC_HUB,
3054 0,
3055 {0, 0},
3056 0,
3057 0,
3058 {0},
3059};
3060
3061static void
3062ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3063{
3064 uint32_t port;
3065 uint32_t v;
3066
3067 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3068
3069 port = EHCI_PORTSC(index);
3070 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3071 EOWRITE4(sc, port, v | EHCI_PS_PO);
3072}
3073
3074static usb_error_t
3075ehci_roothub_exec(struct usb_device *udev,
3076 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3077{
3078 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3079 const char *str_ptr;
3080 const void *ptr;
3081 uint32_t port;
3082 uint32_t v;
3083 uint16_t len;
3084 uint16_t i;
3085 uint16_t value;
3086 uint16_t index;
3087 uint8_t l;
3088 usb_error_t err;
3089
3090 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3091
3092 /* buffer reset */
3093 ptr = (const void *)&sc->sc_hub_desc;
3094 len = 0;
3095 err = 0;
3096
3097 value = UGETW(req->wValue);
3098 index = UGETW(req->wIndex);
3099
3100 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3101 "wValue=0x%04x wIndex=0x%04x\n",
3102 req->bmRequestType, req->bRequest,
3103 UGETW(req->wLength), value, index);
3104
3105#define C(x,y) ((x) | ((y) << 8))
3106 switch (C(req->bRequest, req->bmRequestType)) {
3107 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3108 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3109 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3110 /*
3111 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3112 * for the integrated root hub.
3113 */
3114 break;
3115 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3116 len = 1;
3117 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3118 break;
3119 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3120 switch (value >> 8) {
3121 case UDESC_DEVICE:
3122 if ((value & 0xff) != 0) {
3123 err = USB_ERR_IOERROR;
3124 goto done;
3125 }
3126 len = sizeof(ehci_devd);
3127 ptr = (const void *)&ehci_devd;
3128 break;
3129 /*
3130 * We can't really operate at another speed,
3131 * but the specification says we need this
3132 * descriptor:
3133 */
3134 case UDESC_DEVICE_QUALIFIER:
3135 if ((value & 0xff) != 0) {
3136 err = USB_ERR_IOERROR;
3137 goto done;
3138 }
3139 len = sizeof(ehci_odevd);
3140 ptr = (const void *)&ehci_odevd;
3141 break;
3142
3143 case UDESC_CONFIG:
3144 if ((value & 0xff) != 0) {
3145 err = USB_ERR_IOERROR;
3146 goto done;
3147 }
3148 len = sizeof(ehci_confd);
3149 ptr = (const void *)&ehci_confd;
3150 break;
3151
3152 case UDESC_STRING:
3153 switch (value & 0xff) {
3154 case 0: /* Language table */
3155 str_ptr = "\001";
3156 break;
3157
3158 case 1: /* Vendor */
3159 str_ptr = sc->sc_vendor;
3160 break;
3161
3162 case 2: /* Product */
3163 str_ptr = "EHCI root HUB";
3164 break;
3165
3166 default:
3167 str_ptr = "";
3168 break;
3169 }
3170
3171 len = usb_make_str_desc(
3172 sc->sc_hub_desc.temp,
3173 sizeof(sc->sc_hub_desc.temp),
3174 str_ptr);
3175 break;
3176 default:
3177 err = USB_ERR_IOERROR;
3178 goto done;
3179 }
3180 break;
3181 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3182 len = 1;
3183 sc->sc_hub_desc.temp[0] = 0;
3184 break;
3185 case C(UR_GET_STATUS, UT_READ_DEVICE):
3186 len = 2;
3187 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3188 break;
3189 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3190 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3191 len = 2;
3192 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3193 break;
3194 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3195 if (value >= EHCI_MAX_DEVICES) {
3196 err = USB_ERR_IOERROR;
3197 goto done;
3198 }
3199 sc->sc_addr = value;
3200 break;
3201 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3202 if ((value != 0) && (value != 1)) {
3203 err = USB_ERR_IOERROR;
3204 goto done;
3205 }
3206 sc->sc_conf = value;
3207 break;
3208 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3209 break;
3210 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3211 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3212 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3213 err = USB_ERR_IOERROR;
3214 goto done;
3215 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3216 break;
3217 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3218 break;
3219 /* Hub requests */
3220 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3221 break;
3222 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3223 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3224
3225 if ((index < 1) ||
3226 (index > sc->sc_noport)) {
3227 err = USB_ERR_IOERROR;
3228 goto done;
3229 }
3230 port = EHCI_PORTSC(index);
3231 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3232 switch (value) {
3233 case UHF_PORT_ENABLE:
3234 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3235 break;
3236 case UHF_PORT_SUSPEND:
3237 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3238
3239 /*
3240 * waking up a High Speed device is rather
3241 * complicated if
3242 */
3243 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3244 }
3245 /* wait 20ms for resume sequence to complete */
3246 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3247
3248 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3249 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3250
3251 /* 4ms settle time */
3252 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3253 break;
3254 case UHF_PORT_POWER:
3255 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3256 break;
3257 case UHF_PORT_TEST:
3258 DPRINTFN(3, "clear port test "
3259 "%d\n", index);
3260 break;
3261 case UHF_PORT_INDICATOR:
3262 DPRINTFN(3, "clear port ind "
3263 "%d\n", index);
3264 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3265 break;
3266 case UHF_C_PORT_CONNECTION:
3267 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3268 break;
3269 case UHF_C_PORT_ENABLE:
3270 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3271 break;
3272 case UHF_C_PORT_SUSPEND:
3273 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3274 break;
3275 case UHF_C_PORT_OVER_CURRENT:
3276 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3277 break;
3278 case UHF_C_PORT_RESET:
3279 sc->sc_isreset = 0;
3280 break;
3281 default:
3282 err = USB_ERR_IOERROR;
3283 goto done;
3284 }
3285 break;
3286 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3287 if ((value & 0xff) != 0) {
3288 err = USB_ERR_IOERROR;
3289 goto done;
3290 }
3291 v = EOREAD4(sc, EHCI_HCSPARAMS);
3292
3293 sc->sc_hub_desc.hubd = ehci_hubd;
3294 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3295 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics,
3296 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
3297 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ?
3298 UHD_PORT_IND : 0));
3299 /* XXX can't find out? */
3300 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3301 for (l = 0; l < sc->sc_noport; l++) {
3302 /* XXX can't find out? */
3303 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8));
3304 }
3305 sc->sc_hub_desc.hubd.bDescLength =
3306 8 + ((sc->sc_noport + 7) / 8);
3307 len = sc->sc_hub_desc.hubd.bDescLength;
3308 break;
3309 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3310 len = 16;
3311 bzero(sc->sc_hub_desc.temp, 16);
3312 break;
3313 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3314 DPRINTFN(9, "get port status i=%d\n",
3315 index);
3316 if ((index < 1) ||
3317 (index > sc->sc_noport)) {
3318 err = USB_ERR_IOERROR;
3319 goto done;
3320 }
3321 v = EOREAD4(sc, EHCI_PORTSC(index));
3322 DPRINTFN(9, "port status=0x%04x\n", v);
3323 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3324 if ((v & 0xc000000) == 0x8000000)
3325 i = UPS_HIGH_SPEED;
3326 else if ((v & 0xc000000) == 0x4000000)
3327 i = UPS_LOW_SPEED;
3328 else
3329 i = 0;
3330 } else {
3331 i = UPS_HIGH_SPEED;
3332 }
3333 if (v & EHCI_PS_CS)
3334 i |= UPS_CURRENT_CONNECT_STATUS;
3335 if (v & EHCI_PS_PE)
3336 i |= UPS_PORT_ENABLED;
3337 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3338 i |= UPS_SUSPEND;
3339 if (v & EHCI_PS_OCA)
3340 i |= UPS_OVERCURRENT_INDICATOR;
3341 if (v & EHCI_PS_PR)
3342 i |= UPS_RESET;
3343 if (v & EHCI_PS_PP)
3344 i |= UPS_PORT_POWER;
3345 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3346 i = 0;
3347 if (v & EHCI_PS_CSC)
3348 i |= UPS_C_CONNECT_STATUS;
3349 if (v & EHCI_PS_PEC)
3350 i |= UPS_C_PORT_ENABLED;
3351 if (v & EHCI_PS_OCC)
3352 i |= UPS_C_OVERCURRENT_INDICATOR;
3353 if (v & EHCI_PS_FPR)
3354 i |= UPS_C_SUSPEND;
3355 if (sc->sc_isreset)
3356 i |= UPS_C_PORT_RESET;
3357 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3358 len = sizeof(sc->sc_hub_desc.ps);
3359 break;
3360 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3361 err = USB_ERR_IOERROR;
3362 goto done;
3363 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3364 break;
3365 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3366 if ((index < 1) ||
3367 (index > sc->sc_noport)) {
3368 err = USB_ERR_IOERROR;
3369 goto done;
3370 }
3371 port = EHCI_PORTSC(index);
3372 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3373 switch (value) {
3374 case UHF_PORT_ENABLE:
3375 EOWRITE4(sc, port, v | EHCI_PS_PE);
3376 break;
3377 case UHF_PORT_SUSPEND:
3378 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3379 break;
3380 case UHF_PORT_RESET:
3381 DPRINTFN(6, "reset port %d\n", index);
3382#if USB_DEBUG
3383 if (ehcinohighspeed) {
3384 /*
3385 * Connect USB device to companion
3386 * controller.
3387 */
3388 ehci_disown(sc, index, 1);
3389 break;
3390 }
3391#endif
3392 if (EHCI_PS_IS_LOWSPEED(v) &&
3393 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3394 /* Low speed device, give up ownership. */
3395 ehci_disown(sc, index, 1);
3396 break;
3397 }
3398 /* Start reset sequence. */
3399 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3400 EOWRITE4(sc, port, v | EHCI_PS_PR);
3401
3402 /* Wait for reset to complete. */
3403 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3404 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3405
3406 /* Terminate reset sequence. */
3407 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3408 EOWRITE4(sc, port, v);
3409
3410 /* Wait for HC to complete reset. */
3411 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3412 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3413
3414 v = EOREAD4(sc, port);
3415 DPRINTF("ehci after reset, status=0x%08x\n", v);
3416 if (v & EHCI_PS_PR) {
3417 device_printf(sc->sc_bus.bdev,
3418 "port reset timeout\n");
3419 err = USB_ERR_TIMEOUT;
3420 goto done;
3421 }
3422 if (!(v & EHCI_PS_PE) &&
3423 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3424 /* Not a high speed device, give up ownership.*/
3425 ehci_disown(sc, index, 0);
3426 break;
3427 }
3428 sc->sc_isreset = 1;
3429 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3430 index, v);
3431 break;
3432
3433 case UHF_PORT_POWER:
3434 DPRINTFN(3, "set port power %d\n", index);
3435 EOWRITE4(sc, port, v | EHCI_PS_PP);
3436 break;
3437
3438 case UHF_PORT_TEST:
3439 DPRINTFN(3, "set port test %d\n", index);
3440 break;
3441
3442 case UHF_PORT_INDICATOR:
3443 DPRINTFN(3, "set port ind %d\n", index);
3444 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3445 break;
3446
3447 default:
3448 err = USB_ERR_IOERROR;
3449 goto done;
3450 }
3451 break;
3452 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3453 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3454 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3455 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3456 break;
3457 default:
3458 err = USB_ERR_IOERROR;
3459 goto done;
3460 }
3461done:
3462 *plength = len;
3463 *pptr = ptr;
3464 return (err);
3465}
3466
3467static void
3468ehci_xfer_setup(struct usb_setup_params *parm)
3469{
3470 struct usb_page_search page_info;
3471 struct usb_page_cache *pc;
3472 ehci_softc_t *sc;
3473 struct usb_xfer *xfer;
3474 void *last_obj;
3475 uint32_t nqtd;
3476 uint32_t nqh;
3477 uint32_t nsitd;
3478 uint32_t nitd;
3479 uint32_t n;
3480
3481 sc = EHCI_BUS2SC(parm->udev->bus);
3482 xfer = parm->curr_xfer;
3483
3484 nqtd = 0;
3485 nqh = 0;
3486 nsitd = 0;
3487 nitd = 0;
3488
3489 /*
3490 * compute maximum number of some structures
3491 */
3492 if (parm->methods == &ehci_device_ctrl_methods) {
3493
3494 /*
3495 * The proof for the "nqtd" formula is illustrated like
3496 * this:
3497 *
3498 * +------------------------------------+
3499 * | |
3500 * | |remainder -> |
3501 * | +-----+---+ |
3502 * | | xxx | x | frm 0 |
3503 * | +-----+---++ |
3504 * | | xxx | xx | frm 1 |
3505 * | +-----+----+ |
3506 * | ... |
3507 * +------------------------------------+
3508 *
3509 * "xxx" means a completely full USB transfer descriptor
3510 *
3511 * "x" and "xx" means a short USB packet
3512 *
3513 * For the remainder of an USB transfer modulo
3514 * "max_data_length" we need two USB transfer descriptors.
3515 * One to transfer the remaining data and one to finalise
3516 * with a zero length packet in case the "force_short_xfer"
3517 * flag is set. We only need two USB transfer descriptors in
3518 * the case where the transfer length of the first one is a
3519 * factor of "max_frame_size". The rest of the needed USB
3520 * transfer descriptors is given by the buffer size divided
3521 * by the maximum data payload.
3522 */
3523 parm->hc_max_packet_size = 0x400;
3524 parm->hc_max_packet_count = 1;
3525 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3526 xfer->flags_int.bdma_enable = 1;
3527
3528 usbd_transfer_setup_sub(parm);
3529
3530 nqh = 1;
3531 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3532 + (xfer->max_data_length / xfer->max_hc_frame_size));
3533
3534 } else if (parm->methods == &ehci_device_bulk_methods) {
3535
3536 parm->hc_max_packet_size = 0x400;
3537 parm->hc_max_packet_count = 1;
3538 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3539 xfer->flags_int.bdma_enable = 1;
3540
3541 usbd_transfer_setup_sub(parm);
3542
3543 nqh = 1;
3544 nqtd = ((2 * xfer->nframes)
3545 + (xfer->max_data_length / xfer->max_hc_frame_size));
3546
3547 } else if (parm->methods == &ehci_device_intr_methods) {
3548
3549 if (parm->speed == USB_SPEED_HIGH) {
3550 parm->hc_max_packet_size = 0x400;
3551 parm->hc_max_packet_count = 3;
3552 } else if (parm->speed == USB_SPEED_FULL) {
3553 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3554 parm->hc_max_packet_count = 1;
3555 } else {
3556 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3557 parm->hc_max_packet_count = 1;
3558 }
3559
3560 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3561 xfer->flags_int.bdma_enable = 1;
3562
3563 usbd_transfer_setup_sub(parm);
3564
3565 nqh = 1;
3566 nqtd = ((2 * xfer->nframes)
3567 + (xfer->max_data_length / xfer->max_hc_frame_size));
3568
3569 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3570
3571 parm->hc_max_packet_size = 0x3FF;
3572 parm->hc_max_packet_count = 1;
3573 parm->hc_max_frame_size = 0x3FF;
3574 xfer->flags_int.bdma_enable = 1;
3575
3576 usbd_transfer_setup_sub(parm);
3577
3578 nsitd = xfer->nframes;
3579
3580 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3581
3582 parm->hc_max_packet_size = 0x400;
3583 parm->hc_max_packet_count = 3;
3584 parm->hc_max_frame_size = 0xC00;
3585 xfer->flags_int.bdma_enable = 1;
3586
3587 usbd_transfer_setup_sub(parm);
3588
3589 nitd = ((xfer->nframes + 7) / 8) <<
3590 usbd_xfer_get_fps_shift(xfer);
3591
3592 } else {
3593
3594 parm->hc_max_packet_size = 0x400;
3595 parm->hc_max_packet_count = 1;
3596 parm->hc_max_frame_size = 0x400;
3597
3598 usbd_transfer_setup_sub(parm);
3599 }
3600
3601alloc_dma_set:
3602
3603 if (parm->err) {
3604 return;
3605 }
3606 /*
3607 * Allocate queue heads and transfer descriptors
3608 */
3609 last_obj = NULL;
3610
3611 if (usbd_transfer_setup_sub_malloc(
3612 parm, &pc, sizeof(ehci_itd_t),
3613 EHCI_ITD_ALIGN, nitd)) {
3614 parm->err = USB_ERR_NOMEM;
3615 return;
3616 }
3617 if (parm->buf) {
3618 for (n = 0; n != nitd; n++) {
3619 ehci_itd_t *td;
3620
3621 usbd_get_page(pc + n, 0, &page_info);
3622
3623 td = page_info.buffer;
3624
3625 /* init TD */
3626 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3627 td->obj_next = last_obj;
3628 td->page_cache = pc + n;
3629
3630 last_obj = td;
3631
3632 usb_pc_cpu_flush(pc + n);
3633 }
3634 }
3635 if (usbd_transfer_setup_sub_malloc(
3636 parm, &pc, sizeof(ehci_sitd_t),
3637 EHCI_SITD_ALIGN, nsitd)) {
3638 parm->err = USB_ERR_NOMEM;
3639 return;
3640 }
3641 if (parm->buf) {
3642 for (n = 0; n != nsitd; n++) {
3643 ehci_sitd_t *td;
3644
3645 usbd_get_page(pc + n, 0, &page_info);
3646
3647 td = page_info.buffer;
3648
3649 /* init TD */
3650 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3651 td->obj_next = last_obj;
3652 td->page_cache = pc + n;
3653
3654 last_obj = td;
3655
3656 usb_pc_cpu_flush(pc + n);
3657 }
3658 }
3659 if (usbd_transfer_setup_sub_malloc(
3660 parm, &pc, sizeof(ehci_qtd_t),
3661 EHCI_QTD_ALIGN, nqtd)) {
3662 parm->err = USB_ERR_NOMEM;
3663 return;
3664 }
3665 if (parm->buf) {
3666 for (n = 0; n != nqtd; n++) {
3667 ehci_qtd_t *qtd;
3668
3669 usbd_get_page(pc + n, 0, &page_info);
3670
3671 qtd = page_info.buffer;
3672
3673 /* init TD */
3674 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3675 qtd->obj_next = last_obj;
3676 qtd->page_cache = pc + n;
3677
3678 last_obj = qtd;
3679
3680 usb_pc_cpu_flush(pc + n);
3681 }
3682 }
3683 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3684
3685 last_obj = NULL;
3686
3687 if (usbd_transfer_setup_sub_malloc(
3688 parm, &pc, sizeof(ehci_qh_t),
3689 EHCI_QH_ALIGN, nqh)) {
3690 parm->err = USB_ERR_NOMEM;
3691 return;
3692 }
3693 if (parm->buf) {
3694 for (n = 0; n != nqh; n++) {
3695 ehci_qh_t *qh;
3696
3697 usbd_get_page(pc + n, 0, &page_info);
3698
3699 qh = page_info.buffer;
3700
3701 /* init QH */
3702 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3703 qh->obj_next = last_obj;
3704 qh->page_cache = pc + n;
3705
3706 last_obj = qh;
3707
3708 usb_pc_cpu_flush(pc + n);
3709 }
3710 }
3711 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3712
3713 if (!xfer->flags_int.curr_dma_set) {
3714 xfer->flags_int.curr_dma_set = 1;
3715 goto alloc_dma_set;
3716 }
3717}
3718
3719static void
3720ehci_xfer_unsetup(struct usb_xfer *xfer)
3721{
3722 return;
3723}
3724
3725static void
3726ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3727 struct usb_endpoint *ep)
3728{
3729 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3730
3731 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3732 ep, udev->address,
3733 edesc->bEndpointAddress, udev->flags.usb_mode,
3734 sc->sc_addr);
3735
3736 if (udev->flags.usb_mode != USB_MODE_HOST) {
3737 /* not supported */
3738 return;
3739 }
3740 if (udev->device_index != sc->sc_addr) {
3741
3742 if ((udev->speed != USB_SPEED_HIGH) &&
3743 ((udev->hs_hub_addr == 0) ||
3744 (udev->hs_port_no == 0) ||
3745 (udev->parent_hs_hub == NULL) ||
3746 (udev->parent_hs_hub->hub == NULL))) {
3747 /* We need a transaction translator */
3748 goto done;
3749 }
3750 switch (edesc->bmAttributes & UE_XFERTYPE) {
3751 case UE_CONTROL:
3752 ep->methods = &ehci_device_ctrl_methods;
3753 break;
3754 case UE_INTERRUPT:
3755 ep->methods = &ehci_device_intr_methods;
3756 break;
3757 case UE_ISOCHRONOUS:
3758 if (udev->speed == USB_SPEED_HIGH) {
3759 ep->methods = &ehci_device_isoc_hs_methods;
3760 } else if (udev->speed == USB_SPEED_FULL) {
3761 ep->methods = &ehci_device_isoc_fs_methods;
3762 }
3763 break;
3764 case UE_BULK:
3765 if (udev->speed != USB_SPEED_LOW) {
3766 ep->methods = &ehci_device_bulk_methods;
3767 }
3768 break;
3769 default:
3770 /* do nothing */
3771 break;
3772 }
3773 }
3774done:
3775 return;
3776}
3777
3778static void
3779ehci_get_dma_delay(struct usb_bus *bus, uint32_t *pus)
3780{
3781 /*
3782 * Wait until the hardware has finished any possible use of
3783 * the transfer descriptor(s) and QH
3784 */
3785 *pus = (188); /* microseconds */
3786}
3787
3788static void
3789ehci_device_resume(struct usb_device *udev)
3790{
3791 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3792 struct usb_xfer *xfer;
3793 struct usb_pipe_methods *methods;
3794
3795 DPRINTF("\n");
3796
3797 USB_BUS_LOCK(udev->bus);
3798
3799 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3800
3801 if (xfer->xroot->udev == udev) {
3802
3803 methods = xfer->endpoint->methods;
3804
3805 if ((methods == &ehci_device_bulk_methods) ||
3806 (methods == &ehci_device_ctrl_methods)) {
3807 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3808 sc->sc_async_p_last);
3809 }
3810 if (methods == &ehci_device_intr_methods) {
3811 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3812 sc->sc_intr_p_last[xfer->qh_pos]);
3813 }
3814 }
3815 }
3816
3817 USB_BUS_UNLOCK(udev->bus);
3818
3819 return;
3820}
3821
3822static void
3823ehci_device_suspend(struct usb_device *udev)
3824{
3825 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3826 struct usb_xfer *xfer;
3827 struct usb_pipe_methods *methods;
3828
3829 DPRINTF("\n");
3830
3831 USB_BUS_LOCK(udev->bus);
3832
3833 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3834
3835 if (xfer->xroot->udev == udev) {
3836
3837 methods = xfer->endpoint->methods;
3838
3839 if ((methods == &ehci_device_bulk_methods) ||
3840 (methods == &ehci_device_ctrl_methods)) {
3841 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3842 sc->sc_async_p_last);
3843 }
3844 if (methods == &ehci_device_intr_methods) {
3845 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3846 sc->sc_intr_p_last[xfer->qh_pos]);
3847 }
3848 }
3849 }
3850
3851 USB_BUS_UNLOCK(udev->bus);
3852
3853 return;
3854}
3855
3856static void
3857ehci_set_hw_power(struct usb_bus *bus)
3858{
3859 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3860 uint32_t temp;
3861 uint32_t flags;
3862
3863 DPRINTF("\n");
3864
3865 USB_BUS_LOCK(bus);
3866
3867 flags = bus->hw_power_state;
3868
3869 temp = EOREAD4(sc, EHCI_USBCMD);
3870
3871 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3872
3873 if (flags & (USB_HW_POWER_CONTROL |
3874 USB_HW_POWER_BULK)) {
3875 DPRINTF("Async is active\n");
3876 temp |= EHCI_CMD_ASE;
3877 }
3878 if (flags & (USB_HW_POWER_INTERRUPT |
3879 USB_HW_POWER_ISOC)) {
3880 DPRINTF("Periodic is active\n");
3881 temp |= EHCI_CMD_PSE;
3882 }
3883 EOWRITE4(sc, EHCI_USBCMD, temp);
3884
3885 USB_BUS_UNLOCK(bus);
3886
3887 return;
3888}
3889
3890struct usb_bus_methods ehci_bus_methods =
3891{
3892 .endpoint_init = ehci_ep_init,
3893 .xfer_setup = ehci_xfer_setup,
3894 .xfer_unsetup = ehci_xfer_unsetup,
3895 .get_dma_delay = ehci_get_dma_delay,
3896 .device_resume = ehci_device_resume,
3897 .device_suspend = ehci_device_suspend,
3898 .set_hw_power = ehci_set_hw_power,
3899 .roothub_exec = ehci_roothub_exec,
3900 .xfer_poll = ehci_do_poll,
3901};
| 105static void ehci_dump_regs(ehci_softc_t *sc);
106static void ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *sqh);
107
108#endif
109
110#define EHCI_INTR_ENDPT 1
111
112extern struct usb_bus_methods ehci_bus_methods;
113extern struct usb_pipe_methods ehci_device_bulk_methods;
114extern struct usb_pipe_methods ehci_device_ctrl_methods;
115extern struct usb_pipe_methods ehci_device_intr_methods;
116extern struct usb_pipe_methods ehci_device_isoc_fs_methods;
117extern struct usb_pipe_methods ehci_device_isoc_hs_methods;
118
119static void ehci_do_poll(struct usb_bus *);
120static void ehci_device_done(struct usb_xfer *, usb_error_t);
121static uint8_t ehci_check_transfer(struct usb_xfer *);
122static void ehci_timeout(void *);
123static void ehci_poll_timeout(void *);
124
125static void ehci_root_intr(ehci_softc_t *sc);
126
127struct ehci_std_temp {
128 ehci_softc_t *sc;
129 struct usb_page_cache *pc;
130 ehci_qtd_t *td;
131 ehci_qtd_t *td_next;
132 uint32_t average;
133 uint32_t qtd_status;
134 uint32_t len;
135 uint16_t max_frame_size;
136 uint8_t shortpkt;
137 uint8_t auto_data_toggle;
138 uint8_t setup_alt_next;
139 uint8_t last_frame;
140 uint8_t can_use_next;
141};
142
143void
144ehci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
145{
146 ehci_softc_t *sc = EHCI_BUS2SC(bus);
147 uint32_t i;
148
149 cb(bus, &sc->sc_hw.pframes_pc, &sc->sc_hw.pframes_pg,
150 sizeof(uint32_t) * EHCI_FRAMELIST_COUNT, EHCI_FRAMELIST_ALIGN);
151
152 cb(bus, &sc->sc_hw.async_start_pc, &sc->sc_hw.async_start_pg,
153 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
154
155 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
156 cb(bus, sc->sc_hw.intr_start_pc + i,
157 sc->sc_hw.intr_start_pg + i,
158 sizeof(ehci_qh_t), EHCI_QH_ALIGN);
159 }
160
161 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
162 cb(bus, sc->sc_hw.isoc_hs_start_pc + i,
163 sc->sc_hw.isoc_hs_start_pg + i,
164 sizeof(ehci_itd_t), EHCI_ITD_ALIGN);
165 }
166
167 for (i = 0; i != EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
168 cb(bus, sc->sc_hw.isoc_fs_start_pc + i,
169 sc->sc_hw.isoc_fs_start_pg + i,
170 sizeof(ehci_sitd_t), EHCI_SITD_ALIGN);
171 }
172}
173
174usb_error_t
175ehci_reset(ehci_softc_t *sc)
176{
177 uint32_t hcr;
178 int i;
179
180 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
181 for (i = 0; i < 100; i++) {
182 usb_pause_mtx(NULL, hz / 1000);
183 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
184 if (!hcr) {
185 if (sc->sc_flags & (EHCI_SCFLG_SETMODE | EHCI_SCFLG_BIGEMMIO)) {
186 /*
187 * Force USBMODE as requested. Controllers
188 * may have multiple operating modes.
189 */
190 uint32_t usbmode = EOREAD4(sc, EHCI_USBMODE);
191 if (sc->sc_flags & EHCI_SCFLG_SETMODE) {
192 usbmode = (usbmode &~ EHCI_UM_CM) | EHCI_UM_CM_HOST;
193 device_printf(sc->sc_bus.bdev,
194 "set host controller mode\n");
195 }
196 if (sc->sc_flags & EHCI_SCFLG_BIGEMMIO) {
197 usbmode = (usbmode &~ EHCI_UM_ES) | EHCI_UM_ES_BE;
198 device_printf(sc->sc_bus.bdev,
199 "set big-endian mode\n");
200 }
201 EOWRITE4(sc, EHCI_USBMODE, usbmode);
202 }
203 return (0);
204 }
205 }
206 device_printf(sc->sc_bus.bdev, "reset timeout\n");
207 return (USB_ERR_IOERROR);
208}
209
210static usb_error_t
211ehci_hcreset(ehci_softc_t *sc)
212{
213 uint32_t hcr;
214 int i;
215
216 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
217 for (i = 0; i < 100; i++) {
218 usb_pause_mtx(NULL, hz / 1000);
219 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
220 if (hcr)
221 break;
222 }
223 if (!hcr)
224 /*
225 * Fall through and try reset anyway even though
226 * Table 2-9 in the EHCI spec says this will result
227 * in undefined behavior.
228 */
229 device_printf(sc->sc_bus.bdev, "stop timeout\n");
230
231 return ehci_reset(sc);
232}
233
234usb_error_t
235ehci_init(ehci_softc_t *sc)
236{
237 struct usb_page_search buf_res;
238 uint32_t version;
239 uint32_t sparams;
240 uint32_t cparams;
241 uint32_t hcr;
242 uint16_t i;
243 uint16_t x;
244 uint16_t y;
245 uint16_t bit;
246 usb_error_t err = 0;
247
248 DPRINTF("start\n");
249
250 usb_callout_init_mtx(&sc->sc_tmo_pcd, &sc->sc_bus.bus_mtx, 0);
251 usb_callout_init_mtx(&sc->sc_tmo_poll, &sc->sc_bus.bus_mtx, 0);
252
253#if USB_DEBUG
254 if (ehcidebug > 2) {
255 ehci_dump_regs(sc);
256 }
257#endif
258
259 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
260
261 version = EREAD2(sc, EHCI_HCIVERSION);
262 device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
263 version >> 8, version & 0xff);
264
265 sparams = EREAD4(sc, EHCI_HCSPARAMS);
266 DPRINTF("sparams=0x%x\n", sparams);
267
268 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
269 cparams = EREAD4(sc, EHCI_HCCPARAMS);
270 DPRINTF("cparams=0x%x\n", cparams);
271
272 if (EHCI_HCC_64BIT(cparams)) {
273 DPRINTF("HCC uses 64-bit structures\n");
274
275 /* MUST clear segment register if 64 bit capable */
276 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
277 }
278 sc->sc_bus.usbrev = USB_REV_2_0;
279
280 /* Reset the controller */
281 DPRINTF("%s: resetting\n", device_get_nameunit(sc->sc_bus.bdev));
282
283 err = ehci_hcreset(sc);
284 if (err) {
285 device_printf(sc->sc_bus.bdev, "reset timeout\n");
286 return (err);
287 }
288 /*
289 * use current frame-list-size selection 0: 1024*4 bytes 1: 512*4
290 * bytes 2: 256*4 bytes 3: unknown
291 */
292 if (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD)) == 3) {
293 device_printf(sc->sc_bus.bdev, "invalid frame-list-size\n");
294 return (USB_ERR_IOERROR);
295 }
296 /* set up the bus struct */
297 sc->sc_bus.methods = &ehci_bus_methods;
298
299 sc->sc_eintrs = EHCI_NORMAL_INTRS;
300
301 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
302 ehci_qh_t *qh;
303
304 usbd_get_page(sc->sc_hw.intr_start_pc + i, 0, &buf_res);
305
306 qh = buf_res.buffer;
307
308 /* initialize page cache pointer */
309
310 qh->page_cache = sc->sc_hw.intr_start_pc + i;
311
312 /* store a pointer to queue head */
313
314 sc->sc_intr_p_last[i] = qh;
315
316 qh->qh_self =
317 htohc32(sc, buf_res.physaddr) |
318 htohc32(sc, EHCI_LINK_QH);
319
320 qh->qh_endp =
321 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
322 qh->qh_endphub =
323 htohc32(sc, EHCI_QH_SET_MULT(1));
324 qh->qh_curqtd = 0;
325
326 qh->qh_qtd.qtd_next =
327 htohc32(sc, EHCI_LINK_TERMINATE);
328 qh->qh_qtd.qtd_altnext =
329 htohc32(sc, EHCI_LINK_TERMINATE);
330 qh->qh_qtd.qtd_status =
331 htohc32(sc, EHCI_QTD_HALTED);
332 }
333
334 /*
335 * the QHs are arranged to give poll intervals that are
336 * powers of 2 times 1ms
337 */
338 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
339 while (bit) {
340 x = bit;
341 while (x & bit) {
342 ehci_qh_t *qh_x;
343 ehci_qh_t *qh_y;
344
345 y = (x ^ bit) | (bit / 2);
346
347 qh_x = sc->sc_intr_p_last[x];
348 qh_y = sc->sc_intr_p_last[y];
349
350 /*
351 * the next QH has half the poll interval
352 */
353 qh_x->qh_link = qh_y->qh_self;
354
355 x++;
356 }
357 bit >>= 1;
358 }
359
360 if (1) {
361 ehci_qh_t *qh;
362
363 qh = sc->sc_intr_p_last[0];
364
365 /* the last (1ms) QH terminates */
366 qh->qh_link = htohc32(sc, EHCI_LINK_TERMINATE);
367 }
368 for (i = 0; i < EHCI_VIRTUAL_FRAMELIST_COUNT; i++) {
369 ehci_sitd_t *sitd;
370 ehci_itd_t *itd;
371
372 usbd_get_page(sc->sc_hw.isoc_fs_start_pc + i, 0, &buf_res);
373
374 sitd = buf_res.buffer;
375
376 /* initialize page cache pointer */
377
378 sitd->page_cache = sc->sc_hw.isoc_fs_start_pc + i;
379
380 /* store a pointer to the transfer descriptor */
381
382 sc->sc_isoc_fs_p_last[i] = sitd;
383
384 /* initialize full speed isochronous */
385
386 sitd->sitd_self =
387 htohc32(sc, buf_res.physaddr) |
388 htohc32(sc, EHCI_LINK_SITD);
389
390 sitd->sitd_back =
391 htohc32(sc, EHCI_LINK_TERMINATE);
392
393 sitd->sitd_next =
394 sc->sc_intr_p_last[i | (EHCI_VIRTUAL_FRAMELIST_COUNT / 2)]->qh_self;
395
396
397 usbd_get_page(sc->sc_hw.isoc_hs_start_pc + i, 0, &buf_res);
398
399 itd = buf_res.buffer;
400
401 /* initialize page cache pointer */
402
403 itd->page_cache = sc->sc_hw.isoc_hs_start_pc + i;
404
405 /* store a pointer to the transfer descriptor */
406
407 sc->sc_isoc_hs_p_last[i] = itd;
408
409 /* initialize high speed isochronous */
410
411 itd->itd_self =
412 htohc32(sc, buf_res.physaddr) |
413 htohc32(sc, EHCI_LINK_ITD);
414
415 itd->itd_next =
416 sitd->sitd_self;
417 }
418
419 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
420
421 if (1) {
422 uint32_t *pframes;
423
424 pframes = buf_res.buffer;
425
426 /*
427 * execution order:
428 * pframes -> high speed isochronous ->
429 * full speed isochronous -> interrupt QH's
430 */
431 for (i = 0; i < EHCI_FRAMELIST_COUNT; i++) {
432 pframes[i] = sc->sc_isoc_hs_p_last
433 [i & (EHCI_VIRTUAL_FRAMELIST_COUNT - 1)]->itd_self;
434 }
435 }
436 /* setup sync list pointer */
437 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
438
439 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
440
441 if (1) {
442
443 ehci_qh_t *qh;
444
445 qh = buf_res.buffer;
446
447 /* initialize page cache pointer */
448
449 qh->page_cache = &sc->sc_hw.async_start_pc;
450
451 /* store a pointer to the queue head */
452
453 sc->sc_async_p_last = qh;
454
455 /* init dummy QH that starts the async list */
456
457 qh->qh_self =
458 htohc32(sc, buf_res.physaddr) |
459 htohc32(sc, EHCI_LINK_QH);
460
461 /* fill the QH */
462 qh->qh_endp =
463 htohc32(sc, EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
464 qh->qh_endphub = htohc32(sc, EHCI_QH_SET_MULT(1));
465 qh->qh_link = qh->qh_self;
466 qh->qh_curqtd = 0;
467
468 /* fill the overlay qTD */
469 qh->qh_qtd.qtd_next = htohc32(sc, EHCI_LINK_TERMINATE);
470 qh->qh_qtd.qtd_altnext = htohc32(sc, EHCI_LINK_TERMINATE);
471 qh->qh_qtd.qtd_status = htohc32(sc, EHCI_QTD_HALTED);
472 }
473 /* flush all cache into memory */
474
475 usb_bus_mem_flush_all(&sc->sc_bus, &ehci_iterate_hw_softc);
476
477#if USB_DEBUG
478 if (ehcidebug) {
479 ehci_dump_sqh(sc, sc->sc_async_p_last);
480 }
481#endif
482
483 /* setup async list pointer */
484 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
485
486
487 /* enable interrupts */
488 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
489
490 /* turn on controller */
491 EOWRITE4(sc, EHCI_USBCMD,
492 EHCI_CMD_ITC_1 | /* 1 microframes interrupt delay */
493 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
494 EHCI_CMD_ASE |
495 EHCI_CMD_PSE |
496 EHCI_CMD_RS);
497
498 /* Take over port ownership */
499 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
500
501 for (i = 0; i < 100; i++) {
502 usb_pause_mtx(NULL, hz / 1000);
503 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
504 if (!hcr) {
505 break;
506 }
507 }
508 if (hcr) {
509 device_printf(sc->sc_bus.bdev, "run timeout\n");
510 return (USB_ERR_IOERROR);
511 }
512
513 if (!err) {
514 /* catch any lost interrupts */
515 ehci_do_poll(&sc->sc_bus);
516 }
517 return (err);
518}
519
520/*
521 * shut down the controller when the system is going down
522 */
523void
524ehci_detach(ehci_softc_t *sc)
525{
526 USB_BUS_LOCK(&sc->sc_bus);
527
528 usb_callout_stop(&sc->sc_tmo_pcd);
529 usb_callout_stop(&sc->sc_tmo_poll);
530
531 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
532 USB_BUS_UNLOCK(&sc->sc_bus);
533
534 if (ehci_hcreset(sc)) {
535 DPRINTF("reset failed!\n");
536 }
537
538 /* XXX let stray task complete */
539 usb_pause_mtx(NULL, hz / 20);
540
541 usb_callout_drain(&sc->sc_tmo_pcd);
542 usb_callout_drain(&sc->sc_tmo_poll);
543}
544
545void
546ehci_suspend(ehci_softc_t *sc)
547{
548 uint32_t cmd;
549 uint32_t hcr;
550 uint8_t i;
551
552 USB_BUS_LOCK(&sc->sc_bus);
553
554 for (i = 1; i <= sc->sc_noport; i++) {
555 cmd = EOREAD4(sc, EHCI_PORTSC(i));
556 if (((cmd & EHCI_PS_PO) == 0) &&
557 ((cmd & EHCI_PS_PE) == EHCI_PS_PE)) {
558 EOWRITE4(sc, EHCI_PORTSC(i),
559 cmd | EHCI_PS_SUSP);
560 }
561 }
562
563 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
564
565 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
566 EOWRITE4(sc, EHCI_USBCMD, cmd);
567
568 for (i = 0; i < 100; i++) {
569 hcr = EOREAD4(sc, EHCI_USBSTS) &
570 (EHCI_STS_ASS | EHCI_STS_PSS);
571
572 if (hcr == 0) {
573 break;
574 }
575 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
576 }
577
578 if (hcr != 0) {
579 device_printf(sc->sc_bus.bdev, "reset timeout\n");
580 }
581 cmd &= ~EHCI_CMD_RS;
582 EOWRITE4(sc, EHCI_USBCMD, cmd);
583
584 for (i = 0; i < 100; i++) {
585 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
586 if (hcr == EHCI_STS_HCH) {
587 break;
588 }
589 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
590 }
591
592 if (hcr != EHCI_STS_HCH) {
593 device_printf(sc->sc_bus.bdev,
594 "config timeout\n");
595 }
596 USB_BUS_UNLOCK(&sc->sc_bus);
597}
598
599void
600ehci_resume(ehci_softc_t *sc)
601{
602 struct usb_page_search buf_res;
603 uint32_t cmd;
604 uint32_t hcr;
605 uint8_t i;
606
607 USB_BUS_LOCK(&sc->sc_bus);
608
609 /* restore things in case the bios doesn't */
610 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
611
612 usbd_get_page(&sc->sc_hw.pframes_pc, 0, &buf_res);
613 EOWRITE4(sc, EHCI_PERIODICLISTBASE, buf_res.physaddr);
614
615 usbd_get_page(&sc->sc_hw.async_start_pc, 0, &buf_res);
616 EOWRITE4(sc, EHCI_ASYNCLISTADDR, buf_res.physaddr | EHCI_LINK_QH);
617
618 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
619
620 hcr = 0;
621 for (i = 1; i <= sc->sc_noport; i++) {
622 cmd = EOREAD4(sc, EHCI_PORTSC(i));
623 if (((cmd & EHCI_PS_PO) == 0) &&
624 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
625 EOWRITE4(sc, EHCI_PORTSC(i),
626 cmd | EHCI_PS_FPR);
627 hcr = 1;
628 }
629 }
630
631 if (hcr) {
632 usb_pause_mtx(&sc->sc_bus.bus_mtx,
633 USB_MS_TO_TICKS(USB_RESUME_WAIT));
634
635 for (i = 1; i <= sc->sc_noport; i++) {
636 cmd = EOREAD4(sc, EHCI_PORTSC(i));
637 if (((cmd & EHCI_PS_PO) == 0) &&
638 ((cmd & EHCI_PS_SUSP) == EHCI_PS_SUSP)) {
639 EOWRITE4(sc, EHCI_PORTSC(i),
640 cmd & ~EHCI_PS_FPR);
641 }
642 }
643 }
644 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
645
646 for (i = 0; i < 100; i++) {
647 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
648 if (hcr != EHCI_STS_HCH) {
649 break;
650 }
651 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 1000);
652 }
653 if (hcr == EHCI_STS_HCH) {
654 device_printf(sc->sc_bus.bdev, "config timeout\n");
655 }
656
657 USB_BUS_UNLOCK(&sc->sc_bus);
658
659 usb_pause_mtx(NULL,
660 USB_MS_TO_TICKS(USB_RESUME_WAIT));
661
662 /* catch any lost interrupts */
663 ehci_do_poll(&sc->sc_bus);
664}
665
666void
667ehci_shutdown(ehci_softc_t *sc)
668{
669 DPRINTF("stopping the HC\n");
670
671 if (ehci_hcreset(sc)) {
672 DPRINTF("reset failed!\n");
673 }
674}
675
676#if USB_DEBUG
677static void
678ehci_dump_regs(ehci_softc_t *sc)
679{
680 uint32_t i;
681
682 i = EOREAD4(sc, EHCI_USBCMD);
683 printf("cmd=0x%08x\n", i);
684
685 if (i & EHCI_CMD_ITC_1)
686 printf(" EHCI_CMD_ITC_1\n");
687 if (i & EHCI_CMD_ITC_2)
688 printf(" EHCI_CMD_ITC_2\n");
689 if (i & EHCI_CMD_ITC_4)
690 printf(" EHCI_CMD_ITC_4\n");
691 if (i & EHCI_CMD_ITC_8)
692 printf(" EHCI_CMD_ITC_8\n");
693 if (i & EHCI_CMD_ITC_16)
694 printf(" EHCI_CMD_ITC_16\n");
695 if (i & EHCI_CMD_ITC_32)
696 printf(" EHCI_CMD_ITC_32\n");
697 if (i & EHCI_CMD_ITC_64)
698 printf(" EHCI_CMD_ITC_64\n");
699 if (i & EHCI_CMD_ASPME)
700 printf(" EHCI_CMD_ASPME\n");
701 if (i & EHCI_CMD_ASPMC)
702 printf(" EHCI_CMD_ASPMC\n");
703 if (i & EHCI_CMD_LHCR)
704 printf(" EHCI_CMD_LHCR\n");
705 if (i & EHCI_CMD_IAAD)
706 printf(" EHCI_CMD_IAAD\n");
707 if (i & EHCI_CMD_ASE)
708 printf(" EHCI_CMD_ASE\n");
709 if (i & EHCI_CMD_PSE)
710 printf(" EHCI_CMD_PSE\n");
711 if (i & EHCI_CMD_FLS_M)
712 printf(" EHCI_CMD_FLS_M\n");
713 if (i & EHCI_CMD_HCRESET)
714 printf(" EHCI_CMD_HCRESET\n");
715 if (i & EHCI_CMD_RS)
716 printf(" EHCI_CMD_RS\n");
717
718 i = EOREAD4(sc, EHCI_USBSTS);
719
720 printf("sts=0x%08x\n", i);
721
722 if (i & EHCI_STS_ASS)
723 printf(" EHCI_STS_ASS\n");
724 if (i & EHCI_STS_PSS)
725 printf(" EHCI_STS_PSS\n");
726 if (i & EHCI_STS_REC)
727 printf(" EHCI_STS_REC\n");
728 if (i & EHCI_STS_HCH)
729 printf(" EHCI_STS_HCH\n");
730 if (i & EHCI_STS_IAA)
731 printf(" EHCI_STS_IAA\n");
732 if (i & EHCI_STS_HSE)
733 printf(" EHCI_STS_HSE\n");
734 if (i & EHCI_STS_FLR)
735 printf(" EHCI_STS_FLR\n");
736 if (i & EHCI_STS_PCD)
737 printf(" EHCI_STS_PCD\n");
738 if (i & EHCI_STS_ERRINT)
739 printf(" EHCI_STS_ERRINT\n");
740 if (i & EHCI_STS_INT)
741 printf(" EHCI_STS_INT\n");
742
743 printf("ien=0x%08x\n",
744 EOREAD4(sc, EHCI_USBINTR));
745 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
746 EOREAD4(sc, EHCI_FRINDEX),
747 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
748 EOREAD4(sc, EHCI_PERIODICLISTBASE),
749 EOREAD4(sc, EHCI_ASYNCLISTADDR));
750 for (i = 1; i <= sc->sc_noport; i++) {
751 printf("port %d status=0x%08x\n", i,
752 EOREAD4(sc, EHCI_PORTSC(i)));
753 }
754}
755
756static void
757ehci_dump_link(ehci_softc_t *sc, uint32_t link, int type)
758{
759 link = hc32toh(sc, link);
760 printf("0x%08x", link);
761 if (link & EHCI_LINK_TERMINATE)
762 printf("<T>");
763 else {
764 printf("<");
765 if (type) {
766 switch (EHCI_LINK_TYPE(link)) {
767 case EHCI_LINK_ITD:
768 printf("ITD");
769 break;
770 case EHCI_LINK_QH:
771 printf("QH");
772 break;
773 case EHCI_LINK_SITD:
774 printf("SITD");
775 break;
776 case EHCI_LINK_FSTN:
777 printf("FSTN");
778 break;
779 }
780 }
781 printf(">");
782 }
783}
784
785static void
786ehci_dump_qtd(ehci_softc_t *sc, ehci_qtd_t *qtd)
787{
788 uint32_t s;
789
790 printf(" next=");
791 ehci_dump_link(sc, qtd->qtd_next, 0);
792 printf(" altnext=");
793 ehci_dump_link(sc, qtd->qtd_altnext, 0);
794 printf("\n");
795 s = hc32toh(sc, qtd->qtd_status);
796 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
797 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
798 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
799 printf(" cerr=%d pid=%d stat=%s%s%s%s%s%s%s%s\n",
800 EHCI_QTD_GET_CERR(s), EHCI_QTD_GET_PID(s),
801 (s & EHCI_QTD_ACTIVE) ? "ACTIVE" : "NOT_ACTIVE",
802 (s & EHCI_QTD_HALTED) ? "-HALTED" : "",
803 (s & EHCI_QTD_BUFERR) ? "-BUFERR" : "",
804 (s & EHCI_QTD_BABBLE) ? "-BABBLE" : "",
805 (s & EHCI_QTD_XACTERR) ? "-XACTERR" : "",
806 (s & EHCI_QTD_MISSEDMICRO) ? "-MISSED" : "",
807 (s & EHCI_QTD_SPLITXSTATE) ? "-SPLIT" : "",
808 (s & EHCI_QTD_PINGSTATE) ? "-PING" : "");
809
810 for (s = 0; s < 5; s++) {
811 printf(" buffer[%d]=0x%08x\n", s,
812 hc32toh(sc, qtd->qtd_buffer[s]));
813 }
814 for (s = 0; s < 5; s++) {
815 printf(" buffer_hi[%d]=0x%08x\n", s,
816 hc32toh(sc, qtd->qtd_buffer_hi[s]));
817 }
818}
819
820static uint8_t
821ehci_dump_sqtd(ehci_softc_t *sc, ehci_qtd_t *sqtd)
822{
823 uint8_t temp;
824
825 usb_pc_cpu_invalidate(sqtd->page_cache);
826 printf("QTD(%p) at 0x%08x:\n", sqtd, hc32toh(sc, sqtd->qtd_self));
827 ehci_dump_qtd(sc, sqtd);
828 temp = (sqtd->qtd_next & htohc32(sc, EHCI_LINK_TERMINATE)) ? 1 : 0;
829 return (temp);
830}
831
832static void
833ehci_dump_sqtds(ehci_softc_t *sc, ehci_qtd_t *sqtd)
834{
835 uint16_t i;
836 uint8_t stop;
837
838 stop = 0;
839 for (i = 0; sqtd && (i < 20) && !stop; sqtd = sqtd->obj_next, i++) {
840 stop = ehci_dump_sqtd(sc, sqtd);
841 }
842 if (sqtd) {
843 printf("dump aborted, too many TDs\n");
844 }
845}
846
847static void
848ehci_dump_sqh(ehci_softc_t *sc, ehci_qh_t *qh)
849{
850 uint32_t endp;
851 uint32_t endphub;
852
853 usb_pc_cpu_invalidate(qh->page_cache);
854 printf("QH(%p) at 0x%08x:\n", qh, hc32toh(sc, qh->qh_self) & ~0x1F);
855 printf(" link=");
856 ehci_dump_link(sc, qh->qh_link, 1);
857 printf("\n");
858 endp = hc32toh(sc, qh->qh_endp);
859 printf(" endp=0x%08x\n", endp);
860 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
861 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
862 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
863 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
864 printf(" mpl=0x%x ctl=%d nrl=%d\n",
865 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
866 EHCI_QH_GET_NRL(endp));
867 endphub = hc32toh(sc, qh->qh_endphub);
868 printf(" endphub=0x%08x\n", endphub);
869 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
870 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
871 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
872 EHCI_QH_GET_MULT(endphub));
873 printf(" curqtd=");
874 ehci_dump_link(sc, qh->qh_curqtd, 0);
875 printf("\n");
876 printf("Overlay qTD:\n");
877 ehci_dump_qtd(sc, (void *)&qh->qh_qtd);
878}
879
880static void
881ehci_dump_sitd(ehci_softc_t *sc, ehci_sitd_t *sitd)
882{
883 usb_pc_cpu_invalidate(sitd->page_cache);
884 printf("SITD(%p) at 0x%08x\n", sitd, hc32toh(sc, sitd->sitd_self) & ~0x1F);
885 printf(" next=0x%08x\n", hc32toh(sc, sitd->sitd_next));
886 printf(" portaddr=0x%08x dir=%s addr=%d endpt=0x%x port=0x%x huba=0x%x\n",
887 hc32toh(sc, sitd->sitd_portaddr),
888 (sitd->sitd_portaddr & htohc32(sc, EHCI_SITD_SET_DIR_IN))
889 ? "in" : "out",
890 EHCI_SITD_GET_ADDR(hc32toh(sc, sitd->sitd_portaddr)),
891 EHCI_SITD_GET_ENDPT(hc32toh(sc, sitd->sitd_portaddr)),
892 EHCI_SITD_GET_PORT(hc32toh(sc, sitd->sitd_portaddr)),
893 EHCI_SITD_GET_HUBA(hc32toh(sc, sitd->sitd_portaddr)));
894 printf(" mask=0x%08x\n", hc32toh(sc, sitd->sitd_mask));
895 printf(" status=0x%08x <%s> len=0x%x\n", hc32toh(sc, sitd->sitd_status),
896 (sitd->sitd_status & htohc32(sc, EHCI_SITD_ACTIVE)) ? "ACTIVE" : "",
897 EHCI_SITD_GET_LEN(hc32toh(sc, sitd->sitd_status)));
898 printf(" back=0x%08x, bp=0x%08x,0x%08x,0x%08x,0x%08x\n",
899 hc32toh(sc, sitd->sitd_back),
900 hc32toh(sc, sitd->sitd_bp[0]),
901 hc32toh(sc, sitd->sitd_bp[1]),
902 hc32toh(sc, sitd->sitd_bp_hi[0]),
903 hc32toh(sc, sitd->sitd_bp_hi[1]));
904}
905
906static void
907ehci_dump_itd(ehci_softc_t *sc, ehci_itd_t *itd)
908{
909 usb_pc_cpu_invalidate(itd->page_cache);
910 printf("ITD(%p) at 0x%08x\n", itd, hc32toh(sc, itd->itd_self) & ~0x1F);
911 printf(" next=0x%08x\n", hc32toh(sc, itd->itd_next));
912 printf(" status[0]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[0]),
913 (itd->itd_status[0] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
914 printf(" status[1]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[1]),
915 (itd->itd_status[1] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
916 printf(" status[2]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[2]),
917 (itd->itd_status[2] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
918 printf(" status[3]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[3]),
919 (itd->itd_status[3] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
920 printf(" status[4]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[4]),
921 (itd->itd_status[4] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
922 printf(" status[5]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[5]),
923 (itd->itd_status[5] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
924 printf(" status[6]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[6]),
925 (itd->itd_status[6] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
926 printf(" status[7]=0x%08x; <%s>\n", hc32toh(sc, itd->itd_status[7]),
927 (itd->itd_status[7] & htohc32(sc, EHCI_ITD_ACTIVE)) ? "ACTIVE" : "");
928 printf(" bp[0]=0x%08x\n", hc32toh(sc, itd->itd_bp[0]));
929 printf(" addr=0x%02x; endpt=0x%01x\n",
930 EHCI_ITD_GET_ADDR(hc32toh(sc, itd->itd_bp[0])),
931 EHCI_ITD_GET_ENDPT(hc32toh(sc, itd->itd_bp[0])));
932 printf(" bp[1]=0x%08x\n", hc32toh(sc, itd->itd_bp[1]));
933 printf(" dir=%s; mpl=0x%02x\n",
934 (hc32toh(sc, itd->itd_bp[1]) & EHCI_ITD_SET_DIR_IN) ? "in" : "out",
935 EHCI_ITD_GET_MPL(hc32toh(sc, itd->itd_bp[1])));
936 printf(" bp[2..6]=0x%08x,0x%08x,0x%08x,0x%08x,0x%08x\n",
937 hc32toh(sc, itd->itd_bp[2]),
938 hc32toh(sc, itd->itd_bp[3]),
939 hc32toh(sc, itd->itd_bp[4]),
940 hc32toh(sc, itd->itd_bp[5]),
941 hc32toh(sc, itd->itd_bp[6]));
942 printf(" bp_hi=0x%08x,0x%08x,0x%08x,0x%08x,\n"
943 " 0x%08x,0x%08x,0x%08x\n",
944 hc32toh(sc, itd->itd_bp_hi[0]),
945 hc32toh(sc, itd->itd_bp_hi[1]),
946 hc32toh(sc, itd->itd_bp_hi[2]),
947 hc32toh(sc, itd->itd_bp_hi[3]),
948 hc32toh(sc, itd->itd_bp_hi[4]),
949 hc32toh(sc, itd->itd_bp_hi[5]),
950 hc32toh(sc, itd->itd_bp_hi[6]));
951}
952
953static void
954ehci_dump_isoc(ehci_softc_t *sc)
955{
956 ehci_itd_t *itd;
957 ehci_sitd_t *sitd;
958 uint16_t max = 1000;
959 uint16_t pos;
960
961 pos = (EOREAD4(sc, EHCI_FRINDEX) / 8) &
962 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
963
964 printf("%s: isochronous dump from frame 0x%03x:\n",
965 __FUNCTION__, pos);
966
967 itd = sc->sc_isoc_hs_p_last[pos];
968 sitd = sc->sc_isoc_fs_p_last[pos];
969
970 while (itd && max && max--) {
971 ehci_dump_itd(sc, itd);
972 itd = itd->prev;
973 }
974
975 while (sitd && max && max--) {
976 ehci_dump_sitd(sc, sitd);
977 sitd = sitd->prev;
978 }
979}
980
981#endif
982
983static void
984ehci_transfer_intr_enqueue(struct usb_xfer *xfer)
985{
986 /* check for early completion */
987 if (ehci_check_transfer(xfer)) {
988 return;
989 }
990 /* put transfer on interrupt queue */
991 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
992
993 /* start timeout, if any */
994 if (xfer->timeout != 0) {
995 usbd_transfer_timeout_ms(xfer, &ehci_timeout, xfer->timeout);
996 }
997}
998
999#define EHCI_APPEND_FS_TD(std,last) (last) = _ehci_append_fs_td(std,last)
1000static ehci_sitd_t *
1001_ehci_append_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1002{
1003 DPRINTFN(11, "%p to %p\n", std, last);
1004
1005 /* (sc->sc_bus.mtx) must be locked */
1006
1007 std->next = last->next;
1008 std->sitd_next = last->sitd_next;
1009
1010 std->prev = last;
1011
1012 usb_pc_cpu_flush(std->page_cache);
1013
1014 /*
1015 * the last->next->prev is never followed: std->next->prev = std;
1016 */
1017 last->next = std;
1018 last->sitd_next = std->sitd_self;
1019
1020 usb_pc_cpu_flush(last->page_cache);
1021
1022 return (std);
1023}
1024
1025#define EHCI_APPEND_HS_TD(std,last) (last) = _ehci_append_hs_td(std,last)
1026static ehci_itd_t *
1027_ehci_append_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1028{
1029 DPRINTFN(11, "%p to %p\n", std, last);
1030
1031 /* (sc->sc_bus.mtx) must be locked */
1032
1033 std->next = last->next;
1034 std->itd_next = last->itd_next;
1035
1036 std->prev = last;
1037
1038 usb_pc_cpu_flush(std->page_cache);
1039
1040 /*
1041 * the last->next->prev is never followed: std->next->prev = std;
1042 */
1043 last->next = std;
1044 last->itd_next = std->itd_self;
1045
1046 usb_pc_cpu_flush(last->page_cache);
1047
1048 return (std);
1049}
1050
1051#define EHCI_APPEND_QH(sqh,last) (last) = _ehci_append_qh(sqh,last)
1052static ehci_qh_t *
1053_ehci_append_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1054{
1055 DPRINTFN(11, "%p to %p\n", sqh, last);
1056
1057 if (sqh->prev != NULL) {
1058 /* should not happen */
1059 DPRINTFN(0, "QH already linked!\n");
1060 return (last);
1061 }
1062 /* (sc->sc_bus.mtx) must be locked */
1063
1064 sqh->next = last->next;
1065 sqh->qh_link = last->qh_link;
1066
1067 sqh->prev = last;
1068
1069 usb_pc_cpu_flush(sqh->page_cache);
1070
1071 /*
1072 * the last->next->prev is never followed: sqh->next->prev = sqh;
1073 */
1074
1075 last->next = sqh;
1076 last->qh_link = sqh->qh_self;
1077
1078 usb_pc_cpu_flush(last->page_cache);
1079
1080 return (sqh);
1081}
1082
1083#define EHCI_REMOVE_FS_TD(std,last) (last) = _ehci_remove_fs_td(std,last)
1084static ehci_sitd_t *
1085_ehci_remove_fs_td(ehci_sitd_t *std, ehci_sitd_t *last)
1086{
1087 DPRINTFN(11, "%p from %p\n", std, last);
1088
1089 /* (sc->sc_bus.mtx) must be locked */
1090
1091 std->prev->next = std->next;
1092 std->prev->sitd_next = std->sitd_next;
1093
1094 usb_pc_cpu_flush(std->prev->page_cache);
1095
1096 if (std->next) {
1097 std->next->prev = std->prev;
1098 usb_pc_cpu_flush(std->next->page_cache);
1099 }
1100 return ((last == std) ? std->prev : last);
1101}
1102
1103#define EHCI_REMOVE_HS_TD(std,last) (last) = _ehci_remove_hs_td(std,last)
1104static ehci_itd_t *
1105_ehci_remove_hs_td(ehci_itd_t *std, ehci_itd_t *last)
1106{
1107 DPRINTFN(11, "%p from %p\n", std, last);
1108
1109 /* (sc->sc_bus.mtx) must be locked */
1110
1111 std->prev->next = std->next;
1112 std->prev->itd_next = std->itd_next;
1113
1114 usb_pc_cpu_flush(std->prev->page_cache);
1115
1116 if (std->next) {
1117 std->next->prev = std->prev;
1118 usb_pc_cpu_flush(std->next->page_cache);
1119 }
1120 return ((last == std) ? std->prev : last);
1121}
1122
1123#define EHCI_REMOVE_QH(sqh,last) (last) = _ehci_remove_qh(sqh,last)
1124static ehci_qh_t *
1125_ehci_remove_qh(ehci_qh_t *sqh, ehci_qh_t *last)
1126{
1127 DPRINTFN(11, "%p from %p\n", sqh, last);
1128
1129 /* (sc->sc_bus.mtx) must be locked */
1130
1131 /* only remove if not removed from a queue */
1132 if (sqh->prev) {
1133
1134 sqh->prev->next = sqh->next;
1135 sqh->prev->qh_link = sqh->qh_link;
1136
1137 usb_pc_cpu_flush(sqh->prev->page_cache);
1138
1139 if (sqh->next) {
1140 sqh->next->prev = sqh->prev;
1141 usb_pc_cpu_flush(sqh->next->page_cache);
1142 }
1143 last = ((last == sqh) ? sqh->prev : last);
1144
1145 sqh->prev = 0;
1146
1147 usb_pc_cpu_flush(sqh->page_cache);
1148 }
1149 return (last);
1150}
1151
1152static usb_error_t
1153ehci_non_isoc_done_sub(struct usb_xfer *xfer)
1154{
1155 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1156 ehci_qtd_t *td;
1157 ehci_qtd_t *td_alt_next;
1158 uint32_t status;
1159 uint16_t len;
1160
1161 td = xfer->td_transfer_cache;
1162 td_alt_next = td->alt_next;
1163
1164 if (xfer->aframes != xfer->nframes) {
1165 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
1166 }
1167 while (1) {
1168
1169 usb_pc_cpu_invalidate(td->page_cache);
1170 status = hc32toh(sc, td->qtd_status);
1171
1172 len = EHCI_QTD_GET_BYTES(status);
1173
1174 /*
1175 * Verify the status length and
1176 * add the length to "frlengths[]":
1177 */
1178 if (len > td->len) {
1179 /* should not happen */
1180 DPRINTF("Invalid status length, "
1181 "0x%04x/0x%04x bytes\n", len, td->len);
1182 status |= EHCI_QTD_HALTED;
1183 } else if (xfer->aframes != xfer->nframes) {
1184 xfer->frlengths[xfer->aframes] += td->len - len;
1185 }
1186 /* Check for last transfer */
1187 if (((void *)td) == xfer->td_transfer_last) {
1188 td = NULL;
1189 break;
1190 }
1191 /* Check for transfer error */
1192 if (status & EHCI_QTD_HALTED) {
1193 /* the transfer is finished */
1194 td = NULL;
1195 break;
1196 }
1197 /* Check for short transfer */
1198 if (len > 0) {
1199 if (xfer->flags_int.short_frames_ok) {
1200 /* follow alt next */
1201 td = td->alt_next;
1202 } else {
1203 /* the transfer is finished */
1204 td = NULL;
1205 }
1206 break;
1207 }
1208 td = td->obj_next;
1209
1210 if (td->alt_next != td_alt_next) {
1211 /* this USB frame is complete */
1212 break;
1213 }
1214 }
1215
1216 /* update transfer cache */
1217
1218 xfer->td_transfer_cache = td;
1219
1220#if USB_DEBUG
1221 if (status & EHCI_QTD_STATERRS) {
1222 DPRINTFN(11, "error, addr=%d, endpt=0x%02x, frame=0x%02x"
1223 "status=%s%s%s%s%s%s%s%s\n",
1224 xfer->address, xfer->endpointno, xfer->aframes,
1225 (status & EHCI_QTD_ACTIVE) ? "[ACTIVE]" : "[NOT_ACTIVE]",
1226 (status & EHCI_QTD_HALTED) ? "[HALTED]" : "",
1227 (status & EHCI_QTD_BUFERR) ? "[BUFERR]" : "",
1228 (status & EHCI_QTD_BABBLE) ? "[BABBLE]" : "",
1229 (status & EHCI_QTD_XACTERR) ? "[XACTERR]" : "",
1230 (status & EHCI_QTD_MISSEDMICRO) ? "[MISSED]" : "",
1231 (status & EHCI_QTD_SPLITXSTATE) ? "[SPLIT]" : "",
1232 (status & EHCI_QTD_PINGSTATE) ? "[PING]" : "");
1233 }
1234#endif
1235
1236 return ((status & EHCI_QTD_HALTED) ?
1237 USB_ERR_STALLED : USB_ERR_NORMAL_COMPLETION);
1238}
1239
1240static void
1241ehci_non_isoc_done(struct usb_xfer *xfer)
1242{
1243 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1244 ehci_qh_t *qh;
1245 uint32_t status;
1246 usb_error_t err = 0;
1247
1248 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
1249 xfer, xfer->endpoint);
1250
1251#if USB_DEBUG
1252 if (ehcidebug > 10) {
1253 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1254
1255 ehci_dump_sqtds(sc, xfer->td_transfer_first);
1256 }
1257#endif
1258
1259 /* extract data toggle directly from the QH's overlay area */
1260
1261 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1262
1263 usb_pc_cpu_invalidate(qh->page_cache);
1264
1265 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1266
1267 xfer->endpoint->toggle_next =
1268 (status & EHCI_QTD_TOGGLE_MASK) ? 1 : 0;
1269
1270 /* reset scanner */
1271
1272 xfer->td_transfer_cache = xfer->td_transfer_first;
1273
1274 if (xfer->flags_int.control_xfr) {
1275
1276 if (xfer->flags_int.control_hdr) {
1277
1278 err = ehci_non_isoc_done_sub(xfer);
1279 }
1280 xfer->aframes = 1;
1281
1282 if (xfer->td_transfer_cache == NULL) {
1283 goto done;
1284 }
1285 }
1286 while (xfer->aframes != xfer->nframes) {
1287
1288 err = ehci_non_isoc_done_sub(xfer);
1289 xfer->aframes++;
1290
1291 if (xfer->td_transfer_cache == NULL) {
1292 goto done;
1293 }
1294 }
1295
1296 if (xfer->flags_int.control_xfr &&
1297 !xfer->flags_int.control_act) {
1298
1299 err = ehci_non_isoc_done_sub(xfer);
1300 }
1301done:
1302 ehci_device_done(xfer, err);
1303}
1304
1305/*------------------------------------------------------------------------*
1306 * ehci_check_transfer
1307 *
1308 * Return values:
1309 * 0: USB transfer is not finished
1310 * Else: USB transfer is finished
1311 *------------------------------------------------------------------------*/
1312static uint8_t
1313ehci_check_transfer(struct usb_xfer *xfer)
1314{
1315 struct usb_pipe_methods *methods = xfer->endpoint->methods;
1316 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
1317
1318 uint32_t status;
1319
1320 DPRINTFN(13, "xfer=%p checking transfer\n", xfer);
1321
1322 if (methods == &ehci_device_isoc_fs_methods) {
1323 ehci_sitd_t *td;
1324
1325 /* isochronous full speed transfer */
1326
1327 td = xfer->td_transfer_last;
1328 usb_pc_cpu_invalidate(td->page_cache);
1329 status = hc32toh(sc, td->sitd_status);
1330
1331 /* also check if first is complete */
1332
1333 td = xfer->td_transfer_first;
1334 usb_pc_cpu_invalidate(td->page_cache);
1335 status |= hc32toh(sc, td->sitd_status);
1336
1337 if (!(status & EHCI_SITD_ACTIVE)) {
1338 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1339 goto transferred;
1340 }
1341 } else if (methods == &ehci_device_isoc_hs_methods) {
1342 ehci_itd_t *td;
1343
1344 /* isochronous high speed transfer */
1345
1346 td = xfer->td_transfer_last;
1347 usb_pc_cpu_invalidate(td->page_cache);
1348 status =
1349 td->itd_status[0] | td->itd_status[1] |
1350 td->itd_status[2] | td->itd_status[3] |
1351 td->itd_status[4] | td->itd_status[5] |
1352 td->itd_status[6] | td->itd_status[7];
1353
1354 /* also check first transfer */
1355 td = xfer->td_transfer_first;
1356 usb_pc_cpu_invalidate(td->page_cache);
1357 status |=
1358 td->itd_status[0] | td->itd_status[1] |
1359 td->itd_status[2] | td->itd_status[3] |
1360 td->itd_status[4] | td->itd_status[5] |
1361 td->itd_status[6] | td->itd_status[7];
1362
1363 /* if no transactions are active we continue */
1364 if (!(status & htohc32(sc, EHCI_ITD_ACTIVE))) {
1365 ehci_device_done(xfer, USB_ERR_NORMAL_COMPLETION);
1366 goto transferred;
1367 }
1368 } else {
1369 ehci_qtd_t *td;
1370 ehci_qh_t *qh;
1371
1372 /* non-isochronous transfer */
1373
1374 /*
1375 * check whether there is an error somewhere in the middle,
1376 * or whether there was a short packet (SPD and not ACTIVE)
1377 */
1378 td = xfer->td_transfer_cache;
1379
1380 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1381
1382 usb_pc_cpu_invalidate(qh->page_cache);
1383
1384 status = hc32toh(sc, qh->qh_qtd.qtd_status);
1385 if (status & EHCI_QTD_ACTIVE) {
1386 /* transfer is pending */
1387 goto done;
1388 }
1389
1390 while (1) {
1391 usb_pc_cpu_invalidate(td->page_cache);
1392 status = hc32toh(sc, td->qtd_status);
1393
1394 /*
1395 * Check if there is an active TD which
1396 * indicates that the transfer isn't done.
1397 */
1398 if (status & EHCI_QTD_ACTIVE) {
1399 /* update cache */
1400 if (xfer->td_transfer_cache != td) {
1401 xfer->td_transfer_cache = td;
1402 if (qh->qh_qtd.qtd_next &
1403 htohc32(sc, EHCI_LINK_TERMINATE)) {
1404 /* XXX - manually advance to next frame */
1405 qh->qh_qtd.qtd_next = td->qtd_self;
1406 usb_pc_cpu_flush(td->page_cache);
1407 }
1408 }
1409 goto done;
1410 }
1411 /*
1412 * last transfer descriptor makes the transfer done
1413 */
1414 if (((void *)td) == xfer->td_transfer_last) {
1415 break;
1416 }
1417 /*
1418 * any kind of error makes the transfer done
1419 */
1420 if (status & EHCI_QTD_HALTED) {
1421 break;
1422 }
1423 /*
1424 * if there is no alternate next transfer, a short
1425 * packet also makes the transfer done
1426 */
1427 if (EHCI_QTD_GET_BYTES(status)) {
1428 if (xfer->flags_int.short_frames_ok) {
1429 /* follow alt next */
1430 if (td->alt_next) {
1431 td = td->alt_next;
1432 continue;
1433 }
1434 }
1435 /* transfer is done */
1436 break;
1437 }
1438 td = td->obj_next;
1439 }
1440 ehci_non_isoc_done(xfer);
1441 goto transferred;
1442 }
1443
1444done:
1445 DPRINTFN(13, "xfer=%p is still active\n", xfer);
1446 return (0);
1447
1448transferred:
1449 return (1);
1450}
1451
1452static void
1453ehci_pcd_enable(ehci_softc_t *sc)
1454{
1455 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
1456
1457 sc->sc_eintrs |= EHCI_STS_PCD;
1458 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1459
1460 /* acknowledge any PCD interrupt */
1461 EOWRITE4(sc, EHCI_USBSTS, EHCI_STS_PCD);
1462
1463 ehci_root_intr(sc);
1464}
1465
1466static void
1467ehci_interrupt_poll(ehci_softc_t *sc)
1468{
1469 struct usb_xfer *xfer;
1470
1471repeat:
1472 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
1473 /*
1474 * check if transfer is transferred
1475 */
1476 if (ehci_check_transfer(xfer)) {
1477 /* queue has been modified */
1478 goto repeat;
1479 }
1480 }
1481}
1482
1483/*
1484 * Some EHCI chips from VIA / ATI seem to trigger interrupts before
1485 * writing back the qTD status, or miss signalling occasionally under
1486 * heavy load. If the host machine is too fast, we can miss
1487 * transaction completion - when we scan the active list the
1488 * transaction still seems to be active. This generally exhibits
1489 * itself as a umass stall that never recovers.
1490 *
1491 * We work around this behaviour by setting up this callback after any
1492 * softintr that completes with transactions still pending, giving us
1493 * another chance to check for completion after the writeback has
1494 * taken place.
1495 */
1496static void
1497ehci_poll_timeout(void *arg)
1498{
1499 ehci_softc_t *sc = arg;
1500
1501 DPRINTFN(3, "\n");
1502 ehci_interrupt_poll(sc);
1503}
1504
1505/*------------------------------------------------------------------------*
1506 * ehci_interrupt - EHCI interrupt handler
1507 *
1508 * NOTE: Do not access "sc->sc_bus.bdev" inside the interrupt handler,
1509 * hence the interrupt handler will be setup before "sc->sc_bus.bdev"
1510 * is present !
1511 *------------------------------------------------------------------------*/
1512void
1513ehci_interrupt(ehci_softc_t *sc)
1514{
1515 uint32_t status;
1516
1517 USB_BUS_LOCK(&sc->sc_bus);
1518
1519 DPRINTFN(16, "real interrupt\n");
1520
1521#if USB_DEBUG
1522 if (ehcidebug > 15) {
1523 ehci_dump_regs(sc);
1524 }
1525#endif
1526
1527 status = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
1528 if (status == 0) {
1529 /* the interrupt was not for us */
1530 goto done;
1531 }
1532 if (!(status & sc->sc_eintrs)) {
1533 goto done;
1534 }
1535 EOWRITE4(sc, EHCI_USBSTS, status); /* acknowledge */
1536
1537 status &= sc->sc_eintrs;
1538
1539 if (status & EHCI_STS_HSE) {
1540 printf("%s: unrecoverable error, "
1541 "controller halted\n", __FUNCTION__);
1542#if USB_DEBUG
1543 ehci_dump_regs(sc);
1544 ehci_dump_isoc(sc);
1545#endif
1546 }
1547 if (status & EHCI_STS_PCD) {
1548 /*
1549 * Disable PCD interrupt for now, because it will be
1550 * on until the port has been reset.
1551 */
1552 sc->sc_eintrs &= ~EHCI_STS_PCD;
1553 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1554
1555 ehci_root_intr(sc);
1556
1557 /* do not allow RHSC interrupts > 1 per second */
1558 usb_callout_reset(&sc->sc_tmo_pcd, hz,
1559 (void *)&ehci_pcd_enable, sc);
1560 }
1561 status &= ~(EHCI_STS_INT | EHCI_STS_ERRINT | EHCI_STS_PCD | EHCI_STS_IAA);
1562
1563 if (status != 0) {
1564 /* block unprocessed interrupts */
1565 sc->sc_eintrs &= ~status;
1566 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1567 printf("%s: blocking interrupts 0x%x\n", __FUNCTION__, status);
1568 }
1569 /* poll all the USB transfers */
1570 ehci_interrupt_poll(sc);
1571
1572 if (sc->sc_flags & EHCI_SCFLG_LOSTINTRBUG) {
1573 usb_callout_reset(&sc->sc_tmo_poll, hz / 128,
1574 (void *)&ehci_poll_timeout, sc);
1575 }
1576
1577done:
1578 USB_BUS_UNLOCK(&sc->sc_bus);
1579}
1580
1581/*
1582 * called when a request does not complete
1583 */
1584static void
1585ehci_timeout(void *arg)
1586{
1587 struct usb_xfer *xfer = arg;
1588
1589 DPRINTF("xfer=%p\n", xfer);
1590
1591 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1592
1593 /* transfer is transferred */
1594 ehci_device_done(xfer, USB_ERR_TIMEOUT);
1595}
1596
1597static void
1598ehci_do_poll(struct usb_bus *bus)
1599{
1600 ehci_softc_t *sc = EHCI_BUS2SC(bus);
1601
1602 USB_BUS_LOCK(&sc->sc_bus);
1603 ehci_interrupt_poll(sc);
1604 USB_BUS_UNLOCK(&sc->sc_bus);
1605}
1606
1607static void
1608ehci_setup_standard_chain_sub(struct ehci_std_temp *temp)
1609{
1610 struct usb_page_search buf_res;
1611 ehci_qtd_t *td;
1612 ehci_qtd_t *td_next;
1613 ehci_qtd_t *td_alt_next;
1614 uint32_t buf_offset;
1615 uint32_t average;
1616 uint32_t len_old;
1617 uint32_t terminate;
1618 uint8_t shortpkt_old;
1619 uint8_t precompute;
1620
1621 terminate = htohc32(temp->sc, EHCI_LINK_TERMINATE);
1622 td_alt_next = NULL;
1623 buf_offset = 0;
1624 shortpkt_old = temp->shortpkt;
1625 len_old = temp->len;
1626 precompute = 1;
1627
1628restart:
1629
1630 td = temp->td;
1631 td_next = temp->td_next;
1632
1633 while (1) {
1634
1635 if (temp->len == 0) {
1636
1637 if (temp->shortpkt) {
1638 break;
1639 }
1640 /* send a Zero Length Packet, ZLP, last */
1641
1642 temp->shortpkt = 1;
1643 average = 0;
1644
1645 } else {
1646
1647 average = temp->average;
1648
1649 if (temp->len < average) {
1650 if (temp->len % temp->max_frame_size) {
1651 temp->shortpkt = 1;
1652 }
1653 average = temp->len;
1654 }
1655 }
1656
1657 if (td_next == NULL) {
1658 panic("%s: out of EHCI transfer descriptors!", __FUNCTION__);
1659 }
1660 /* get next TD */
1661
1662 td = td_next;
1663 td_next = td->obj_next;
1664
1665 /* check if we are pre-computing */
1666
1667 if (precompute) {
1668
1669 /* update remaining length */
1670
1671 temp->len -= average;
1672
1673 continue;
1674 }
1675 /* fill out current TD */
1676
1677 td->qtd_status =
1678 temp->qtd_status |
1679 htohc32(temp->sc, EHCI_QTD_IOC |
1680 EHCI_QTD_SET_BYTES(average));
1681
1682 if (average == 0) {
1683
1684 if (temp->auto_data_toggle == 0) {
1685
1686 /* update data toggle, ZLP case */
1687
1688 temp->qtd_status ^=
1689 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1690 }
1691 td->len = 0;
1692
1693 td->qtd_buffer[0] = 0;
1694 td->qtd_buffer_hi[0] = 0;
1695
1696 td->qtd_buffer[1] = 0;
1697 td->qtd_buffer_hi[1] = 0;
1698
1699 } else {
1700
1701 uint8_t x;
1702
1703 if (temp->auto_data_toggle == 0) {
1704
1705 /* update data toggle */
1706
1707 if (((average + temp->max_frame_size - 1) /
1708 temp->max_frame_size) & 1) {
1709 temp->qtd_status ^=
1710 htohc32(temp->sc, EHCI_QTD_TOGGLE_MASK);
1711 }
1712 }
1713 td->len = average;
1714
1715 /* update remaining length */
1716
1717 temp->len -= average;
1718
1719 /* fill out buffer pointers */
1720
1721 usbd_get_page(temp->pc, buf_offset, &buf_res);
1722 td->qtd_buffer[0] =
1723 htohc32(temp->sc, buf_res.physaddr);
1724 td->qtd_buffer_hi[0] = 0;
1725
1726 x = 1;
1727
1728 while (average > EHCI_PAGE_SIZE) {
1729 average -= EHCI_PAGE_SIZE;
1730 buf_offset += EHCI_PAGE_SIZE;
1731 usbd_get_page(temp->pc, buf_offset, &buf_res);
1732 td->qtd_buffer[x] =
1733 htohc32(temp->sc,
1734 buf_res.physaddr & (~0xFFF));
1735 td->qtd_buffer_hi[x] = 0;
1736 x++;
1737 }
1738
1739 /*
1740 * NOTE: The "average" variable is never zero after
1741 * exiting the loop above !
1742 *
1743 * NOTE: We have to subtract one from the offset to
1744 * ensure that we are computing the physical address
1745 * of a valid page !
1746 */
1747 buf_offset += average;
1748 usbd_get_page(temp->pc, buf_offset - 1, &buf_res);
1749 td->qtd_buffer[x] =
1750 htohc32(temp->sc,
1751 buf_res.physaddr & (~0xFFF));
1752 td->qtd_buffer_hi[x] = 0;
1753 }
1754
1755 if (temp->can_use_next) {
1756 if (td_next) {
1757 /* link the current TD with the next one */
1758 td->qtd_next = td_next->qtd_self;
1759 }
1760 } else {
1761 /*
1762 * BUG WARNING: The EHCI HW can use the
1763 * qtd_next field instead of qtd_altnext when
1764 * a short packet is received! We work this
1765 * around in software by not queueing more
1766 * than one job/TD at a time!
1767 */
1768 td->qtd_next = terminate;
1769 }
1770
1771 td->qtd_altnext = terminate;
1772 td->alt_next = td_alt_next;
1773
1774 usb_pc_cpu_flush(td->page_cache);
1775 }
1776
1777 if (precompute) {
1778 precompute = 0;
1779
1780 /* setup alt next pointer, if any */
1781 if (temp->last_frame) {
1782 td_alt_next = NULL;
1783 } else {
1784 /* we use this field internally */
1785 td_alt_next = td_next;
1786 }
1787
1788 /* restore */
1789 temp->shortpkt = shortpkt_old;
1790 temp->len = len_old;
1791 goto restart;
1792 }
1793 temp->td = td;
1794 temp->td_next = td_next;
1795}
1796
1797static void
1798ehci_setup_standard_chain(struct usb_xfer *xfer, ehci_qh_t **qh_last)
1799{
1800 struct ehci_std_temp temp;
1801 struct usb_pipe_methods *methods;
1802 ehci_qh_t *qh;
1803 ehci_qtd_t *td;
1804 uint32_t qh_endp;
1805 uint32_t qh_endphub;
1806 uint32_t x;
1807
1808 DPRINTFN(9, "addr=%d endpt=%d sumlen=%d speed=%d\n",
1809 xfer->address, UE_GET_ADDR(xfer->endpointno),
1810 xfer->sumlen, usbd_get_speed(xfer->xroot->udev));
1811
1812 temp.average = xfer->max_hc_frame_size;
1813 temp.max_frame_size = xfer->max_frame_size;
1814 temp.sc = EHCI_BUS2SC(xfer->xroot->bus);
1815
1816 /* toggle the DMA set we are using */
1817 xfer->flags_int.curr_dma_set ^= 1;
1818
1819 /* get next DMA set */
1820 td = xfer->td_start[xfer->flags_int.curr_dma_set];
1821
1822 xfer->td_transfer_first = td;
1823 xfer->td_transfer_cache = td;
1824
1825 temp.td = NULL;
1826 temp.td_next = td;
1827 temp.qtd_status = 0;
1828 temp.last_frame = 0;
1829 temp.setup_alt_next = xfer->flags_int.short_frames_ok;
1830 temp.can_use_next = (xfer->flags_int.control_xfr ||
1831 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT));
1832
1833 if (xfer->flags_int.control_xfr) {
1834 if (xfer->endpoint->toggle_next) {
1835 /* DATA1 is next */
1836 temp.qtd_status |=
1837 htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
1838 }
1839 temp.auto_data_toggle = 0;
1840 } else {
1841 temp.auto_data_toggle = 1;
1842 }
1843
1844 if (usbd_get_speed(xfer->xroot->udev) != USB_SPEED_HIGH) {
1845 /* max 3 retries */
1846 temp.qtd_status |=
1847 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1848 }
1849 /* check if we should prepend a setup message */
1850
1851 if (xfer->flags_int.control_xfr) {
1852 if (xfer->flags_int.control_hdr) {
1853
1854 temp.qtd_status &=
1855 htohc32(temp.sc, EHCI_QTD_SET_CERR(3));
1856 temp.qtd_status |= htohc32(temp.sc,
1857 EHCI_QTD_ACTIVE |
1858 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
1859 EHCI_QTD_SET_TOGGLE(0));
1860
1861 temp.len = xfer->frlengths[0];
1862 temp.pc = xfer->frbuffers + 0;
1863 temp.shortpkt = temp.len ? 1 : 0;
1864 /* check for last frame */
1865 if (xfer->nframes == 1) {
1866 /* no STATUS stage yet, SETUP is last */
1867 if (xfer->flags_int.control_act) {
1868 temp.last_frame = 1;
1869 temp.setup_alt_next = 0;
1870 }
1871 }
1872 ehci_setup_standard_chain_sub(&temp);
1873 }
1874 x = 1;
1875 } else {
1876 x = 0;
1877 }
1878
1879 while (x != xfer->nframes) {
1880
1881 /* DATA0 / DATA1 message */
1882
1883 temp.len = xfer->frlengths[x];
1884 temp.pc = xfer->frbuffers + x;
1885
1886 x++;
1887
1888 if (x == xfer->nframes) {
1889 if (xfer->flags_int.control_xfr) {
1890 /* no STATUS stage yet, DATA is last */
1891 if (xfer->flags_int.control_act) {
1892 temp.last_frame = 1;
1893 temp.setup_alt_next = 0;
1894 }
1895 } else {
1896 temp.last_frame = 1;
1897 temp.setup_alt_next = 0;
1898 }
1899 }
1900 /* keep previous data toggle and error count */
1901
1902 temp.qtd_status &=
1903 htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1904 EHCI_QTD_SET_TOGGLE(1));
1905
1906 if (temp.len == 0) {
1907
1908 /* make sure that we send an USB packet */
1909
1910 temp.shortpkt = 0;
1911
1912 } else {
1913
1914 /* regular data transfer */
1915
1916 temp.shortpkt = (xfer->flags.force_short_xfer) ? 0 : 1;
1917 }
1918
1919 /* set endpoint direction */
1920
1921 temp.qtd_status |=
1922 (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) ?
1923 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1924 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN)) :
1925 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1926 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT));
1927
1928 ehci_setup_standard_chain_sub(&temp);
1929 }
1930
1931 /* check if we should append a status stage */
1932
1933 if (xfer->flags_int.control_xfr &&
1934 !xfer->flags_int.control_act) {
1935
1936 /*
1937 * Send a DATA1 message and invert the current endpoint
1938 * direction.
1939 */
1940
1941 temp.qtd_status &= htohc32(temp.sc, EHCI_QTD_SET_CERR(3) |
1942 EHCI_QTD_SET_TOGGLE(1));
1943 temp.qtd_status |=
1944 (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) ?
1945 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1946 EHCI_QTD_SET_PID(EHCI_QTD_PID_IN) |
1947 EHCI_QTD_SET_TOGGLE(1)) :
1948 htohc32(temp.sc, EHCI_QTD_ACTIVE |
1949 EHCI_QTD_SET_PID(EHCI_QTD_PID_OUT) |
1950 EHCI_QTD_SET_TOGGLE(1));
1951
1952 temp.len = 0;
1953 temp.pc = NULL;
1954 temp.shortpkt = 0;
1955 temp.last_frame = 1;
1956 temp.setup_alt_next = 0;
1957
1958 ehci_setup_standard_chain_sub(&temp);
1959 }
1960 td = temp.td;
1961
1962 /* the last TD terminates the transfer: */
1963 td->qtd_next = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1964 td->qtd_altnext = htohc32(temp.sc, EHCI_LINK_TERMINATE);
1965
1966 usb_pc_cpu_flush(td->page_cache);
1967
1968 /* must have at least one frame! */
1969
1970 xfer->td_transfer_last = td;
1971
1972#if USB_DEBUG
1973 if (ehcidebug > 8) {
1974 DPRINTF("nexttog=%d; data before transfer:\n",
1975 xfer->endpoint->toggle_next);
1976 ehci_dump_sqtds(temp.sc,
1977 xfer->td_transfer_first);
1978 }
1979#endif
1980
1981 methods = xfer->endpoint->methods;
1982
1983 qh = xfer->qh_start[xfer->flags_int.curr_dma_set];
1984
1985 /* the "qh_link" field is filled when the QH is added */
1986
1987 qh_endp =
1988 (EHCI_QH_SET_ADDR(xfer->address) |
1989 EHCI_QH_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
1990 EHCI_QH_SET_MPL(xfer->max_packet_size));
1991
1992 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_HIGH) {
1993 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH);
1994 if (methods != &ehci_device_intr_methods)
1995 qh_endp |= EHCI_QH_SET_NRL(8);
1996 } else {
1997
1998 if (usbd_get_speed(xfer->xroot->udev) == USB_SPEED_FULL) {
1999 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_FULL);
2000 } else {
2001 qh_endp |= EHCI_QH_SET_EPS(EHCI_QH_SPEED_LOW);
2002 }
2003
2004 if (methods == &ehci_device_ctrl_methods) {
2005 qh_endp |= EHCI_QH_CTL;
2006 }
2007 if (methods != &ehci_device_intr_methods) {
2008 /* Only try one time per microframe! */
2009 qh_endp |= EHCI_QH_SET_NRL(1);
2010 }
2011 }
2012
2013 if (temp.auto_data_toggle == 0) {
2014 /* software computes the data toggle */
2015 qh_endp |= EHCI_QH_DTC;
2016 }
2017
2018 qh->qh_endp = htohc32(temp.sc, qh_endp);
2019
2020 qh_endphub =
2021 (EHCI_QH_SET_MULT(xfer->max_packet_count & 3) |
2022 EHCI_QH_SET_CMASK(xfer->endpoint->usb_cmask) |
2023 EHCI_QH_SET_SMASK(xfer->endpoint->usb_smask) |
2024 EHCI_QH_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2025 EHCI_QH_SET_PORT(xfer->xroot->udev->hs_port_no));
2026
2027 qh->qh_endphub = htohc32(temp.sc, qh_endphub);
2028 qh->qh_curqtd = 0;
2029
2030 /* fill the overlay qTD */
2031
2032 if (temp.auto_data_toggle && xfer->endpoint->toggle_next) {
2033 /* DATA1 is next */
2034 qh->qh_qtd.qtd_status = htohc32(temp.sc, EHCI_QTD_SET_TOGGLE(1));
2035 } else {
2036 qh->qh_qtd.qtd_status = 0;
2037 }
2038
2039 td = xfer->td_transfer_first;
2040
2041 qh->qh_qtd.qtd_next = td->qtd_self;
2042 qh->qh_qtd.qtd_altnext =
2043 htohc32(temp.sc, EHCI_LINK_TERMINATE);
2044
2045 usb_pc_cpu_flush(qh->page_cache);
2046
2047 if (xfer->xroot->udev->flags.self_suspended == 0) {
2048 EHCI_APPEND_QH(qh, *qh_last);
2049 }
2050}
2051
2052static void
2053ehci_root_intr(ehci_softc_t *sc)
2054{
2055 uint16_t i;
2056 uint16_t m;
2057
2058 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2059
2060 /* clear any old interrupt data */
2061 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2062
2063 /* set bits */
2064 m = (sc->sc_noport + 1);
2065 if (m > (8 * sizeof(sc->sc_hub_idata))) {
2066 m = (8 * sizeof(sc->sc_hub_idata));
2067 }
2068 for (i = 1; i < m; i++) {
2069 /* pick out CHANGE bits from the status register */
2070 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR) {
2071 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2072 DPRINTF("port %d changed\n", i);
2073 }
2074 }
2075 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2076 sizeof(sc->sc_hub_idata));
2077}
2078
2079static void
2080ehci_isoc_fs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2081{
2082 uint32_t nframes = xfer->nframes;
2083 uint32_t status;
2084 uint32_t *plen = xfer->frlengths;
2085 uint16_t len = 0;
2086 ehci_sitd_t *td = xfer->td_transfer_first;
2087 ehci_sitd_t **pp_last = &sc->sc_isoc_fs_p_last[xfer->qh_pos];
2088
2089 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2090 xfer, xfer->endpoint);
2091
2092 while (nframes--) {
2093 if (td == NULL) {
2094 panic("%s:%d: out of TD's\n",
2095 __FUNCTION__, __LINE__);
2096 }
2097 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2098 pp_last = &sc->sc_isoc_fs_p_last[0];
2099 }
2100#if USB_DEBUG
2101 if (ehcidebug > 15) {
2102 DPRINTF("isoc FS-TD\n");
2103 ehci_dump_sitd(sc, td);
2104 }
2105#endif
2106 usb_pc_cpu_invalidate(td->page_cache);
2107 status = hc32toh(sc, td->sitd_status);
2108
2109 len = EHCI_SITD_GET_LEN(status);
2110
2111 DPRINTFN(2, "status=0x%08x, rem=%u\n", status, len);
2112
2113 if (*plen >= len) {
2114 len = *plen - len;
2115 } else {
2116 len = 0;
2117 }
2118
2119 *plen = len;
2120
2121 /* remove FS-TD from schedule */
2122 EHCI_REMOVE_FS_TD(td, *pp_last);
2123
2124 pp_last++;
2125 plen++;
2126 td = td->obj_next;
2127 }
2128
2129 xfer->aframes = xfer->nframes;
2130}
2131
2132static void
2133ehci_isoc_hs_done(ehci_softc_t *sc, struct usb_xfer *xfer)
2134{
2135 uint32_t nframes = xfer->nframes;
2136 uint32_t status;
2137 uint32_t *plen = xfer->frlengths;
2138 uint16_t len = 0;
2139 uint8_t td_no = 0;
2140 ehci_itd_t *td = xfer->td_transfer_first;
2141 ehci_itd_t **pp_last = &sc->sc_isoc_hs_p_last[xfer->qh_pos];
2142
2143 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
2144 xfer, xfer->endpoint);
2145
2146 while (nframes) {
2147 if (td == NULL) {
2148 panic("%s:%d: out of TD's\n",
2149 __FUNCTION__, __LINE__);
2150 }
2151 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2152 pp_last = &sc->sc_isoc_hs_p_last[0];
2153 }
2154#if USB_DEBUG
2155 if (ehcidebug > 15) {
2156 DPRINTF("isoc HS-TD\n");
2157 ehci_dump_itd(sc, td);
2158 }
2159#endif
2160
2161 usb_pc_cpu_invalidate(td->page_cache);
2162 status = hc32toh(sc, td->itd_status[td_no]);
2163
2164 len = EHCI_ITD_GET_LEN(status);
2165
2166 DPRINTFN(2, "status=0x%08x, len=%u\n", status, len);
2167
2168 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2169
2170 if (*plen >= len) {
2171 /*
2172 * The length is valid. NOTE: The
2173 * complete length is written back
2174 * into the status field, and not the
2175 * remainder like with other transfer
2176 * descriptor types.
2177 */
2178 } else {
2179 /* Invalid length - truncate */
2180 len = 0;
2181 }
2182
2183 *plen = len;
2184 plen++;
2185 nframes--;
2186 }
2187
2188 td_no++;
2189
2190 if ((td_no == 8) || (nframes == 0)) {
2191 /* remove HS-TD from schedule */
2192 EHCI_REMOVE_HS_TD(td, *pp_last);
2193 pp_last++;
2194
2195 td_no = 0;
2196 td = td->obj_next;
2197 }
2198 }
2199 xfer->aframes = xfer->nframes;
2200}
2201
2202/* NOTE: "done" can be run two times in a row,
2203 * from close and from interrupt
2204 */
2205static void
2206ehci_device_done(struct usb_xfer *xfer, usb_error_t error)
2207{
2208 struct usb_pipe_methods *methods = xfer->endpoint->methods;
2209 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2210
2211 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2212
2213 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2214 xfer, xfer->endpoint, error);
2215
2216 if ((methods == &ehci_device_bulk_methods) ||
2217 (methods == &ehci_device_ctrl_methods)) {
2218#if USB_DEBUG
2219 if (ehcidebug > 8) {
2220 DPRINTF("nexttog=%d; data after transfer:\n",
2221 xfer->endpoint->toggle_next);
2222 ehci_dump_sqtds(sc,
2223 xfer->td_transfer_first);
2224 }
2225#endif
2226
2227 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2228 sc->sc_async_p_last);
2229 }
2230 if (methods == &ehci_device_intr_methods) {
2231 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
2232 sc->sc_intr_p_last[xfer->qh_pos]);
2233 }
2234 /*
2235 * Only finish isochronous transfers once which will update
2236 * "xfer->frlengths".
2237 */
2238 if (xfer->td_transfer_first &&
2239 xfer->td_transfer_last) {
2240 if (methods == &ehci_device_isoc_fs_methods) {
2241 ehci_isoc_fs_done(sc, xfer);
2242 }
2243 if (methods == &ehci_device_isoc_hs_methods) {
2244 ehci_isoc_hs_done(sc, xfer);
2245 }
2246 xfer->td_transfer_first = NULL;
2247 xfer->td_transfer_last = NULL;
2248 }
2249 /* dequeue transfer and start next transfer */
2250 usbd_transfer_done(xfer, error);
2251}
2252
2253/*------------------------------------------------------------------------*
2254 * ehci bulk support
2255 *------------------------------------------------------------------------*/
2256static void
2257ehci_device_bulk_open(struct usb_xfer *xfer)
2258{
2259 return;
2260}
2261
2262static void
2263ehci_device_bulk_close(struct usb_xfer *xfer)
2264{
2265 ehci_device_done(xfer, USB_ERR_CANCELLED);
2266}
2267
2268static void
2269ehci_device_bulk_enter(struct usb_xfer *xfer)
2270{
2271 return;
2272}
2273
2274static void
2275ehci_device_bulk_start(struct usb_xfer *xfer)
2276{
2277 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2278 uint32_t temp;
2279
2280 /* setup TD's and QH */
2281 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2282
2283 /* put transfer on interrupt queue */
2284 ehci_transfer_intr_enqueue(xfer);
2285
2286 /* XXX Performance quirk: Some Host Controllers have a too low
2287 * interrupt rate. Issue an IAAD to stimulate the Host
2288 * Controller after queueing the BULK transfer.
2289 */
2290 temp = EOREAD4(sc, EHCI_USBCMD);
2291 if (!(temp & EHCI_CMD_IAAD))
2292 EOWRITE4(sc, EHCI_USBCMD, temp | EHCI_CMD_IAAD);
2293}
2294
2295struct usb_pipe_methods ehci_device_bulk_methods =
2296{
2297 .open = ehci_device_bulk_open,
2298 .close = ehci_device_bulk_close,
2299 .enter = ehci_device_bulk_enter,
2300 .start = ehci_device_bulk_start,
2301};
2302
2303/*------------------------------------------------------------------------*
2304 * ehci control support
2305 *------------------------------------------------------------------------*/
2306static void
2307ehci_device_ctrl_open(struct usb_xfer *xfer)
2308{
2309 return;
2310}
2311
2312static void
2313ehci_device_ctrl_close(struct usb_xfer *xfer)
2314{
2315 ehci_device_done(xfer, USB_ERR_CANCELLED);
2316}
2317
2318static void
2319ehci_device_ctrl_enter(struct usb_xfer *xfer)
2320{
2321 return;
2322}
2323
2324static void
2325ehci_device_ctrl_start(struct usb_xfer *xfer)
2326{
2327 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2328
2329 /* setup TD's and QH */
2330 ehci_setup_standard_chain(xfer, &sc->sc_async_p_last);
2331
2332 /* put transfer on interrupt queue */
2333 ehci_transfer_intr_enqueue(xfer);
2334}
2335
2336struct usb_pipe_methods ehci_device_ctrl_methods =
2337{
2338 .open = ehci_device_ctrl_open,
2339 .close = ehci_device_ctrl_close,
2340 .enter = ehci_device_ctrl_enter,
2341 .start = ehci_device_ctrl_start,
2342};
2343
2344/*------------------------------------------------------------------------*
2345 * ehci interrupt support
2346 *------------------------------------------------------------------------*/
2347static void
2348ehci_device_intr_open(struct usb_xfer *xfer)
2349{
2350 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2351 uint16_t best;
2352 uint16_t bit;
2353 uint16_t x;
2354
2355 usb_hs_bandwidth_alloc(xfer);
2356
2357 /*
2358 * Find the best QH position corresponding to the given interval:
2359 */
2360
2361 best = 0;
2362 bit = EHCI_VIRTUAL_FRAMELIST_COUNT / 2;
2363 while (bit) {
2364 if (xfer->interval >= bit) {
2365 x = bit;
2366 best = bit;
2367 while (x & bit) {
2368 if (sc->sc_intr_stat[x] <
2369 sc->sc_intr_stat[best]) {
2370 best = x;
2371 }
2372 x++;
2373 }
2374 break;
2375 }
2376 bit >>= 1;
2377 }
2378
2379 sc->sc_intr_stat[best]++;
2380 xfer->qh_pos = best;
2381
2382 DPRINTFN(3, "best=%d interval=%d\n",
2383 best, xfer->interval);
2384}
2385
2386static void
2387ehci_device_intr_close(struct usb_xfer *xfer)
2388{
2389 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2390
2391 sc->sc_intr_stat[xfer->qh_pos]--;
2392
2393 ehci_device_done(xfer, USB_ERR_CANCELLED);
2394
2395 /* bandwidth must be freed after device done */
2396 usb_hs_bandwidth_free(xfer);
2397}
2398
2399static void
2400ehci_device_intr_enter(struct usb_xfer *xfer)
2401{
2402 return;
2403}
2404
2405static void
2406ehci_device_intr_start(struct usb_xfer *xfer)
2407{
2408 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2409
2410 /* setup TD's and QH */
2411 ehci_setup_standard_chain(xfer, &sc->sc_intr_p_last[xfer->qh_pos]);
2412
2413 /* put transfer on interrupt queue */
2414 ehci_transfer_intr_enqueue(xfer);
2415}
2416
2417struct usb_pipe_methods ehci_device_intr_methods =
2418{
2419 .open = ehci_device_intr_open,
2420 .close = ehci_device_intr_close,
2421 .enter = ehci_device_intr_enter,
2422 .start = ehci_device_intr_start,
2423};
2424
2425/*------------------------------------------------------------------------*
2426 * ehci full speed isochronous support
2427 *------------------------------------------------------------------------*/
2428static void
2429ehci_device_isoc_fs_open(struct usb_xfer *xfer)
2430{
2431 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2432 ehci_sitd_t *td;
2433 uint32_t sitd_portaddr;
2434 uint8_t ds;
2435
2436 sitd_portaddr =
2437 EHCI_SITD_SET_ADDR(xfer->address) |
2438 EHCI_SITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)) |
2439 EHCI_SITD_SET_HUBA(xfer->xroot->udev->hs_hub_addr) |
2440 EHCI_SITD_SET_PORT(xfer->xroot->udev->hs_port_no);
2441
2442 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2443 sitd_portaddr |= EHCI_SITD_SET_DIR_IN;
2444 }
2445 sitd_portaddr = htohc32(sc, sitd_portaddr);
2446
2447 /* initialize all TD's */
2448
2449 for (ds = 0; ds != 2; ds++) {
2450
2451 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2452
2453 td->sitd_portaddr = sitd_portaddr;
2454
2455 /*
2456 * TODO: make some kind of automatic
2457 * SMASK/CMASK selection based on micro-frame
2458 * usage
2459 *
2460 * micro-frame usage (8 microframes per 1ms)
2461 */
2462 td->sitd_back = htohc32(sc, EHCI_LINK_TERMINATE);
2463
2464 usb_pc_cpu_flush(td->page_cache);
2465 }
2466 }
2467}
2468
2469static void
2470ehci_device_isoc_fs_close(struct usb_xfer *xfer)
2471{
2472 ehci_device_done(xfer, USB_ERR_CANCELLED);
2473}
2474
2475static void
2476ehci_device_isoc_fs_enter(struct usb_xfer *xfer)
2477{
2478 struct usb_page_search buf_res;
2479 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2480 struct usb_fs_isoc_schedule *fss_start;
2481 struct usb_fs_isoc_schedule *fss_end;
2482 struct usb_fs_isoc_schedule *fss;
2483 ehci_sitd_t *td;
2484 ehci_sitd_t *td_last = NULL;
2485 ehci_sitd_t **pp_last;
2486 uint32_t *plen;
2487 uint32_t buf_offset;
2488 uint32_t nframes;
2489 uint32_t temp;
2490 uint32_t sitd_mask;
2491 uint16_t tlen;
2492 uint8_t sa;
2493 uint8_t sb;
2494 uint8_t error;
2495
2496#if USB_DEBUG
2497 uint8_t once = 1;
2498
2499#endif
2500
2501 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2502 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2503
2504 /* get the current frame index */
2505
2506 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2507
2508 /*
2509 * check if the frame index is within the window where the frames
2510 * will be inserted
2511 */
2512 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2513 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2514
2515 if ((xfer->endpoint->is_synced == 0) ||
2516 (buf_offset < xfer->nframes)) {
2517 /*
2518 * If there is data underflow or the pipe queue is empty we
2519 * schedule the transfer a few frames ahead of the current
2520 * frame position. Else two isochronous transfers might
2521 * overlap.
2522 */
2523 xfer->endpoint->isoc_next = (nframes + 3) &
2524 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2525 xfer->endpoint->is_synced = 1;
2526 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2527 }
2528 /*
2529 * compute how many milliseconds the insertion is ahead of the
2530 * current frame position:
2531 */
2532 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2533 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2534
2535 /*
2536 * pre-compute when the isochronous transfer will be finished:
2537 */
2538 xfer->isoc_time_complete =
2539 usbd_fs_isoc_schedule_isoc_time_expand
2540 (xfer->xroot->udev, &fss_start, &fss_end, nframes) + buf_offset +
2541 xfer->nframes;
2542
2543 /* get the real number of frames */
2544
2545 nframes = xfer->nframes;
2546
2547 buf_offset = 0;
2548
2549 plen = xfer->frlengths;
2550
2551 /* toggle the DMA set we are using */
2552 xfer->flags_int.curr_dma_set ^= 1;
2553
2554 /* get next DMA set */
2555 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2556 xfer->td_transfer_first = td;
2557
2558 pp_last = &sc->sc_isoc_fs_p_last[xfer->endpoint->isoc_next];
2559
2560 /* store starting position */
2561
2562 xfer->qh_pos = xfer->endpoint->isoc_next;
2563
2564 fss = fss_start + (xfer->qh_pos % USB_ISOC_TIME_MAX);
2565
2566 while (nframes--) {
2567 if (td == NULL) {
2568 panic("%s:%d: out of TD's\n",
2569 __FUNCTION__, __LINE__);
2570 }
2571 if (pp_last >= &sc->sc_isoc_fs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2572 pp_last = &sc->sc_isoc_fs_p_last[0];
2573 }
2574 if (fss >= fss_end) {
2575 fss = fss_start;
2576 }
2577 /* reuse sitd_portaddr and sitd_back from last transfer */
2578
2579 if (*plen > xfer->max_frame_size) {
2580#if USB_DEBUG
2581 if (once) {
2582 once = 0;
2583 printf("%s: frame length(%d) exceeds %d "
2584 "bytes (frame truncated)\n",
2585 __FUNCTION__, *plen,
2586 xfer->max_frame_size);
2587 }
2588#endif
2589 *plen = xfer->max_frame_size;
2590 }
2591 /*
2592 * We currently don't care if the ISOCHRONOUS schedule is
2593 * full!
2594 */
2595 error = usbd_fs_isoc_schedule_alloc(fss, &sa, *plen);
2596 if (error) {
2597 /*
2598 * The FULL speed schedule is FULL! Set length
2599 * to zero.
2600 */
2601 *plen = 0;
2602 }
2603 if (*plen) {
2604 /*
2605 * only call "usbd_get_page()" when we have a
2606 * non-zero length
2607 */
2608 usbd_get_page(xfer->frbuffers, buf_offset, &buf_res);
2609 td->sitd_bp[0] = htohc32(sc, buf_res.physaddr);
2610 buf_offset += *plen;
2611 /*
2612 * NOTE: We need to subtract one from the offset so
2613 * that we are on a valid page!
2614 */
2615 usbd_get_page(xfer->frbuffers, buf_offset - 1,
2616 &buf_res);
2617 temp = buf_res.physaddr & ~0xFFF;
2618 } else {
2619 td->sitd_bp[0] = 0;
2620 temp = 0;
2621 }
2622
2623 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_OUT) {
2624 tlen = *plen;
2625 if (tlen <= 188) {
2626 temp |= 1; /* T-count = 1, TP = ALL */
2627 tlen = 1;
2628 } else {
2629 tlen += 187;
2630 tlen /= 188;
2631 temp |= tlen; /* T-count = [1..6] */
2632 temp |= 8; /* TP = Begin */
2633 }
2634
2635 tlen += sa;
2636
2637 if (tlen >= 8) {
2638 sb = 0;
2639 } else {
2640 sb = (1 << tlen);
2641 }
2642
2643 sa = (1 << sa);
2644 sa = (sb - sa) & 0x3F;
2645 sb = 0;
2646 } else {
2647 sb = (-(4 << sa)) & 0xFE;
2648 sa = (1 << sa) & 0x3F;
2649 }
2650
2651 sitd_mask = (EHCI_SITD_SET_SMASK(sa) |
2652 EHCI_SITD_SET_CMASK(sb));
2653
2654 td->sitd_bp[1] = htohc32(sc, temp);
2655
2656 td->sitd_mask = htohc32(sc, sitd_mask);
2657
2658 if (nframes == 0) {
2659 td->sitd_status = htohc32(sc,
2660 EHCI_SITD_IOC |
2661 EHCI_SITD_ACTIVE |
2662 EHCI_SITD_SET_LEN(*plen));
2663 } else {
2664 td->sitd_status = htohc32(sc,
2665 EHCI_SITD_ACTIVE |
2666 EHCI_SITD_SET_LEN(*plen));
2667 }
2668 usb_pc_cpu_flush(td->page_cache);
2669
2670#if USB_DEBUG
2671 if (ehcidebug > 15) {
2672 DPRINTF("FS-TD %d\n", nframes);
2673 ehci_dump_sitd(sc, td);
2674 }
2675#endif
2676 /* insert TD into schedule */
2677 EHCI_APPEND_FS_TD(td, *pp_last);
2678 pp_last++;
2679
2680 plen++;
2681 fss++;
2682 td_last = td;
2683 td = td->obj_next;
2684 }
2685
2686 xfer->td_transfer_last = td_last;
2687
2688 /* update isoc_next */
2689 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_fs_p_last[0]) &
2690 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2691}
2692
2693static void
2694ehci_device_isoc_fs_start(struct usb_xfer *xfer)
2695{
2696 /* put transfer on interrupt queue */
2697 ehci_transfer_intr_enqueue(xfer);
2698}
2699
2700struct usb_pipe_methods ehci_device_isoc_fs_methods =
2701{
2702 .open = ehci_device_isoc_fs_open,
2703 .close = ehci_device_isoc_fs_close,
2704 .enter = ehci_device_isoc_fs_enter,
2705 .start = ehci_device_isoc_fs_start,
2706};
2707
2708/*------------------------------------------------------------------------*
2709 * ehci high speed isochronous support
2710 *------------------------------------------------------------------------*/
2711static void
2712ehci_device_isoc_hs_open(struct usb_xfer *xfer)
2713{
2714 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2715 ehci_itd_t *td;
2716 uint32_t temp;
2717 uint8_t ds;
2718
2719 usb_hs_bandwidth_alloc(xfer);
2720
2721 /* initialize all TD's */
2722
2723 for (ds = 0; ds != 2; ds++) {
2724
2725 for (td = xfer->td_start[ds]; td; td = td->obj_next) {
2726
2727 /* set TD inactive */
2728 td->itd_status[0] = 0;
2729 td->itd_status[1] = 0;
2730 td->itd_status[2] = 0;
2731 td->itd_status[3] = 0;
2732 td->itd_status[4] = 0;
2733 td->itd_status[5] = 0;
2734 td->itd_status[6] = 0;
2735 td->itd_status[7] = 0;
2736
2737 /* set endpoint and address */
2738 td->itd_bp[0] = htohc32(sc,
2739 EHCI_ITD_SET_ADDR(xfer->address) |
2740 EHCI_ITD_SET_ENDPT(UE_GET_ADDR(xfer->endpointno)));
2741
2742 temp =
2743 EHCI_ITD_SET_MPL(xfer->max_packet_size & 0x7FF);
2744
2745 /* set direction */
2746 if (UE_GET_DIR(xfer->endpointno) == UE_DIR_IN) {
2747 temp |= EHCI_ITD_SET_DIR_IN;
2748 }
2749 /* set maximum packet size */
2750 td->itd_bp[1] = htohc32(sc, temp);
2751
2752 /* set transfer multiplier */
2753 td->itd_bp[2] = htohc32(sc, xfer->max_packet_count & 3);
2754
2755 usb_pc_cpu_flush(td->page_cache);
2756 }
2757 }
2758}
2759
2760static void
2761ehci_device_isoc_hs_close(struct usb_xfer *xfer)
2762{
2763 ehci_device_done(xfer, USB_ERR_CANCELLED);
2764
2765 /* bandwidth must be freed after device done */
2766 usb_hs_bandwidth_free(xfer);
2767}
2768
2769static void
2770ehci_device_isoc_hs_enter(struct usb_xfer *xfer)
2771{
2772 struct usb_page_search buf_res;
2773 ehci_softc_t *sc = EHCI_BUS2SC(xfer->xroot->bus);
2774 ehci_itd_t *td;
2775 ehci_itd_t *td_last = NULL;
2776 ehci_itd_t **pp_last;
2777 bus_size_t page_addr;
2778 uint32_t *plen;
2779 uint32_t status;
2780 uint32_t buf_offset;
2781 uint32_t nframes;
2782 uint32_t itd_offset[8 + 1];
2783 uint8_t x;
2784 uint8_t td_no;
2785 uint8_t page_no;
2786
2787#if USB_DEBUG
2788 uint8_t once = 1;
2789
2790#endif
2791
2792 DPRINTFN(6, "xfer=%p next=%d nframes=%d\n",
2793 xfer, xfer->endpoint->isoc_next, xfer->nframes);
2794
2795 /* get the current frame index */
2796
2797 nframes = EOREAD4(sc, EHCI_FRINDEX) / 8;
2798
2799 /*
2800 * check if the frame index is within the window where the frames
2801 * will be inserted
2802 */
2803 buf_offset = (nframes - xfer->endpoint->isoc_next) &
2804 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2805
2806 if ((xfer->endpoint->is_synced == 0) ||
2807 (buf_offset < ((xfer->nframes + 7) / 8))) {
2808 /*
2809 * If there is data underflow or the pipe queue is empty we
2810 * schedule the transfer a few frames ahead of the current
2811 * frame position. Else two isochronous transfers might
2812 * overlap.
2813 */
2814 xfer->endpoint->isoc_next = (nframes + 3) &
2815 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2816 xfer->endpoint->is_synced = 1;
2817 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2818 }
2819 /*
2820 * compute how many milliseconds the insertion is ahead of the
2821 * current frame position:
2822 */
2823 buf_offset = (xfer->endpoint->isoc_next - nframes) &
2824 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2825
2826 /*
2827 * pre-compute when the isochronous transfer will be finished:
2828 */
2829 xfer->isoc_time_complete =
2830 usb_isoc_time_expand(&sc->sc_bus, nframes) + buf_offset +
2831 ((xfer->nframes + 7) / 8);
2832
2833 /* get the real number of frames */
2834
2835 nframes = xfer->nframes;
2836
2837 buf_offset = 0;
2838 td_no = 0;
2839
2840 plen = xfer->frlengths;
2841
2842 /* toggle the DMA set we are using */
2843 xfer->flags_int.curr_dma_set ^= 1;
2844
2845 /* get next DMA set */
2846 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2847 xfer->td_transfer_first = td;
2848
2849 pp_last = &sc->sc_isoc_hs_p_last[xfer->endpoint->isoc_next];
2850
2851 /* store starting position */
2852
2853 xfer->qh_pos = xfer->endpoint->isoc_next;
2854
2855 while (nframes) {
2856 if (td == NULL) {
2857 panic("%s:%d: out of TD's\n",
2858 __FUNCTION__, __LINE__);
2859 }
2860 if (pp_last >= &sc->sc_isoc_hs_p_last[EHCI_VIRTUAL_FRAMELIST_COUNT]) {
2861 pp_last = &sc->sc_isoc_hs_p_last[0];
2862 }
2863 /* range check */
2864 if (*plen > xfer->max_frame_size) {
2865#if USB_DEBUG
2866 if (once) {
2867 once = 0;
2868 printf("%s: frame length(%d) exceeds %d bytes "
2869 "(frame truncated)\n",
2870 __FUNCTION__, *plen, xfer->max_frame_size);
2871 }
2872#endif
2873 *plen = xfer->max_frame_size;
2874 }
2875
2876 if (xfer->endpoint->usb_smask & (1 << td_no)) {
2877 status = (EHCI_ITD_SET_LEN(*plen) |
2878 EHCI_ITD_ACTIVE |
2879 EHCI_ITD_SET_PG(0));
2880 td->itd_status[td_no] = htohc32(sc, status);
2881 itd_offset[td_no] = buf_offset;
2882 buf_offset += *plen;
2883 plen++;
2884 nframes --;
2885 } else {
2886 td->itd_status[td_no] = 0; /* not active */
2887 itd_offset[td_no] = buf_offset;
2888 }
2889
2890 td_no++;
2891
2892 if ((td_no == 8) || (nframes == 0)) {
2893
2894 /* the rest of the transfers are not active, if any */
2895 for (x = td_no; x != 8; x++) {
2896 td->itd_status[x] = 0; /* not active */
2897 }
2898
2899 /* check if there is any data to be transferred */
2900 if (itd_offset[0] != buf_offset) {
2901 page_no = 0;
2902 itd_offset[td_no] = buf_offset;
2903
2904 /* get first page offset */
2905 usbd_get_page(xfer->frbuffers, itd_offset[0], &buf_res);
2906 /* get page address */
2907 page_addr = buf_res.physaddr & ~0xFFF;
2908 /* update page address */
2909 td->itd_bp[0] &= htohc32(sc, 0xFFF);
2910 td->itd_bp[0] |= htohc32(sc, page_addr);
2911
2912 for (x = 0; x != td_no; x++) {
2913 /* set page number and page offset */
2914 status = (EHCI_ITD_SET_PG(page_no) |
2915 (buf_res.physaddr & 0xFFF));
2916 td->itd_status[x] |= htohc32(sc, status);
2917
2918 /* get next page offset */
2919 if (itd_offset[x + 1] == buf_offset) {
2920 /*
2921 * We subtract one so that
2922 * we don't go off the last
2923 * page!
2924 */
2925 usbd_get_page(xfer->frbuffers, buf_offset - 1, &buf_res);
2926 } else {
2927 usbd_get_page(xfer->frbuffers, itd_offset[x + 1], &buf_res);
2928 }
2929
2930 /* check if we need a new page */
2931 if ((buf_res.physaddr ^ page_addr) & ~0xFFF) {
2932 /* new page needed */
2933 page_addr = buf_res.physaddr & ~0xFFF;
2934 if (page_no == 6) {
2935 panic("%s: too many pages\n", __FUNCTION__);
2936 }
2937 page_no++;
2938 /* update page address */
2939 td->itd_bp[page_no] &= htohc32(sc, 0xFFF);
2940 td->itd_bp[page_no] |= htohc32(sc, page_addr);
2941 }
2942 }
2943 }
2944 /* set IOC bit if we are complete */
2945 if (nframes == 0) {
2946 td->itd_status[td_no - 1] |= htohc32(sc, EHCI_ITD_IOC);
2947 }
2948 usb_pc_cpu_flush(td->page_cache);
2949#if USB_DEBUG
2950 if (ehcidebug > 15) {
2951 DPRINTF("HS-TD %d\n", nframes);
2952 ehci_dump_itd(sc, td);
2953 }
2954#endif
2955 /* insert TD into schedule */
2956 EHCI_APPEND_HS_TD(td, *pp_last);
2957 pp_last++;
2958
2959 td_no = 0;
2960 td_last = td;
2961 td = td->obj_next;
2962 }
2963 }
2964
2965 xfer->td_transfer_last = td_last;
2966
2967 /* update isoc_next */
2968 xfer->endpoint->isoc_next = (pp_last - &sc->sc_isoc_hs_p_last[0]) &
2969 (EHCI_VIRTUAL_FRAMELIST_COUNT - 1);
2970}
2971
2972static void
2973ehci_device_isoc_hs_start(struct usb_xfer *xfer)
2974{
2975 /* put transfer on interrupt queue */
2976 ehci_transfer_intr_enqueue(xfer);
2977}
2978
2979struct usb_pipe_methods ehci_device_isoc_hs_methods =
2980{
2981 .open = ehci_device_isoc_hs_open,
2982 .close = ehci_device_isoc_hs_close,
2983 .enter = ehci_device_isoc_hs_enter,
2984 .start = ehci_device_isoc_hs_start,
2985};
2986
2987/*------------------------------------------------------------------------*
2988 * ehci root control support
2989 *------------------------------------------------------------------------*
2990 * Simulate a hardware hub by handling all the necessary requests.
2991 *------------------------------------------------------------------------*/
2992
2993static const
2994struct usb_device_descriptor ehci_devd =
2995{
2996 sizeof(struct usb_device_descriptor),
2997 UDESC_DEVICE, /* type */
2998 {0x00, 0x02}, /* USB version */
2999 UDCLASS_HUB, /* class */
3000 UDSUBCLASS_HUB, /* subclass */
3001 UDPROTO_HSHUBSTT, /* protocol */
3002 64, /* max packet */
3003 {0}, {0}, {0x00, 0x01}, /* device id */
3004 1, 2, 0, /* string indicies */
3005 1 /* # of configurations */
3006};
3007
3008static const
3009struct usb_device_qualifier ehci_odevd =
3010{
3011 sizeof(struct usb_device_qualifier),
3012 UDESC_DEVICE_QUALIFIER, /* type */
3013 {0x00, 0x02}, /* USB version */
3014 UDCLASS_HUB, /* class */
3015 UDSUBCLASS_HUB, /* subclass */
3016 UDPROTO_FSHUB, /* protocol */
3017 0, /* max packet */
3018 0, /* # of configurations */
3019 0
3020};
3021
3022static const struct ehci_config_desc ehci_confd = {
3023 .confd = {
3024 .bLength = sizeof(struct usb_config_descriptor),
3025 .bDescriptorType = UDESC_CONFIG,
3026 .wTotalLength[0] = sizeof(ehci_confd),
3027 .bNumInterface = 1,
3028 .bConfigurationValue = 1,
3029 .iConfiguration = 0,
3030 .bmAttributes = UC_SELF_POWERED,
3031 .bMaxPower = 0 /* max power */
3032 },
3033 .ifcd = {
3034 .bLength = sizeof(struct usb_interface_descriptor),
3035 .bDescriptorType = UDESC_INTERFACE,
3036 .bNumEndpoints = 1,
3037 .bInterfaceClass = UICLASS_HUB,
3038 .bInterfaceSubClass = UISUBCLASS_HUB,
3039 .bInterfaceProtocol = UIPROTO_HSHUBSTT,
3040 0
3041 },
3042 .endpd = {
3043 .bLength = sizeof(struct usb_endpoint_descriptor),
3044 .bDescriptorType = UDESC_ENDPOINT,
3045 .bEndpointAddress = UE_DIR_IN | EHCI_INTR_ENDPT,
3046 .bmAttributes = UE_INTERRUPT,
3047 .wMaxPacketSize[0] = 8, /* max packet (63 ports) */
3048 .bInterval = 255,
3049 },
3050};
3051
3052static const
3053struct usb_hub_descriptor ehci_hubd =
3054{
3055 0, /* dynamic length */
3056 UDESC_HUB,
3057 0,
3058 {0, 0},
3059 0,
3060 0,
3061 {0},
3062};
3063
3064static void
3065ehci_disown(ehci_softc_t *sc, uint16_t index, uint8_t lowspeed)
3066{
3067 uint32_t port;
3068 uint32_t v;
3069
3070 DPRINTF("index=%d lowspeed=%d\n", index, lowspeed);
3071
3072 port = EHCI_PORTSC(index);
3073 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3074 EOWRITE4(sc, port, v | EHCI_PS_PO);
3075}
3076
3077static usb_error_t
3078ehci_roothub_exec(struct usb_device *udev,
3079 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3080{
3081 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3082 const char *str_ptr;
3083 const void *ptr;
3084 uint32_t port;
3085 uint32_t v;
3086 uint16_t len;
3087 uint16_t i;
3088 uint16_t value;
3089 uint16_t index;
3090 uint8_t l;
3091 usb_error_t err;
3092
3093 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3094
3095 /* buffer reset */
3096 ptr = (const void *)&sc->sc_hub_desc;
3097 len = 0;
3098 err = 0;
3099
3100 value = UGETW(req->wValue);
3101 index = UGETW(req->wIndex);
3102
3103 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3104 "wValue=0x%04x wIndex=0x%04x\n",
3105 req->bmRequestType, req->bRequest,
3106 UGETW(req->wLength), value, index);
3107
3108#define C(x,y) ((x) | ((y) << 8))
3109 switch (C(req->bRequest, req->bmRequestType)) {
3110 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3111 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3112 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3113 /*
3114 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3115 * for the integrated root hub.
3116 */
3117 break;
3118 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3119 len = 1;
3120 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3121 break;
3122 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3123 switch (value >> 8) {
3124 case UDESC_DEVICE:
3125 if ((value & 0xff) != 0) {
3126 err = USB_ERR_IOERROR;
3127 goto done;
3128 }
3129 len = sizeof(ehci_devd);
3130 ptr = (const void *)&ehci_devd;
3131 break;
3132 /*
3133 * We can't really operate at another speed,
3134 * but the specification says we need this
3135 * descriptor:
3136 */
3137 case UDESC_DEVICE_QUALIFIER:
3138 if ((value & 0xff) != 0) {
3139 err = USB_ERR_IOERROR;
3140 goto done;
3141 }
3142 len = sizeof(ehci_odevd);
3143 ptr = (const void *)&ehci_odevd;
3144 break;
3145
3146 case UDESC_CONFIG:
3147 if ((value & 0xff) != 0) {
3148 err = USB_ERR_IOERROR;
3149 goto done;
3150 }
3151 len = sizeof(ehci_confd);
3152 ptr = (const void *)&ehci_confd;
3153 break;
3154
3155 case UDESC_STRING:
3156 switch (value & 0xff) {
3157 case 0: /* Language table */
3158 str_ptr = "\001";
3159 break;
3160
3161 case 1: /* Vendor */
3162 str_ptr = sc->sc_vendor;
3163 break;
3164
3165 case 2: /* Product */
3166 str_ptr = "EHCI root HUB";
3167 break;
3168
3169 default:
3170 str_ptr = "";
3171 break;
3172 }
3173
3174 len = usb_make_str_desc(
3175 sc->sc_hub_desc.temp,
3176 sizeof(sc->sc_hub_desc.temp),
3177 str_ptr);
3178 break;
3179 default:
3180 err = USB_ERR_IOERROR;
3181 goto done;
3182 }
3183 break;
3184 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3185 len = 1;
3186 sc->sc_hub_desc.temp[0] = 0;
3187 break;
3188 case C(UR_GET_STATUS, UT_READ_DEVICE):
3189 len = 2;
3190 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3191 break;
3192 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3193 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3194 len = 2;
3195 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3196 break;
3197 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3198 if (value >= EHCI_MAX_DEVICES) {
3199 err = USB_ERR_IOERROR;
3200 goto done;
3201 }
3202 sc->sc_addr = value;
3203 break;
3204 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3205 if ((value != 0) && (value != 1)) {
3206 err = USB_ERR_IOERROR;
3207 goto done;
3208 }
3209 sc->sc_conf = value;
3210 break;
3211 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3212 break;
3213 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3214 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3215 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3216 err = USB_ERR_IOERROR;
3217 goto done;
3218 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3219 break;
3220 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3221 break;
3222 /* Hub requests */
3223 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3224 break;
3225 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3226 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3227
3228 if ((index < 1) ||
3229 (index > sc->sc_noport)) {
3230 err = USB_ERR_IOERROR;
3231 goto done;
3232 }
3233 port = EHCI_PORTSC(index);
3234 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3235 switch (value) {
3236 case UHF_PORT_ENABLE:
3237 EOWRITE4(sc, port, v & ~EHCI_PS_PE);
3238 break;
3239 case UHF_PORT_SUSPEND:
3240 if ((v & EHCI_PS_SUSP) && (!(v & EHCI_PS_FPR))) {
3241
3242 /*
3243 * waking up a High Speed device is rather
3244 * complicated if
3245 */
3246 EOWRITE4(sc, port, v | EHCI_PS_FPR);
3247 }
3248 /* wait 20ms for resume sequence to complete */
3249 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3250
3251 EOWRITE4(sc, port, v & ~(EHCI_PS_SUSP |
3252 EHCI_PS_FPR | (3 << 10) /* High Speed */ ));
3253
3254 /* 4ms settle time */
3255 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3256 break;
3257 case UHF_PORT_POWER:
3258 EOWRITE4(sc, port, v & ~EHCI_PS_PP);
3259 break;
3260 case UHF_PORT_TEST:
3261 DPRINTFN(3, "clear port test "
3262 "%d\n", index);
3263 break;
3264 case UHF_PORT_INDICATOR:
3265 DPRINTFN(3, "clear port ind "
3266 "%d\n", index);
3267 EOWRITE4(sc, port, v & ~EHCI_PS_PIC);
3268 break;
3269 case UHF_C_PORT_CONNECTION:
3270 EOWRITE4(sc, port, v | EHCI_PS_CSC);
3271 break;
3272 case UHF_C_PORT_ENABLE:
3273 EOWRITE4(sc, port, v | EHCI_PS_PEC);
3274 break;
3275 case UHF_C_PORT_SUSPEND:
3276 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3277 break;
3278 case UHF_C_PORT_OVER_CURRENT:
3279 EOWRITE4(sc, port, v | EHCI_PS_OCC);
3280 break;
3281 case UHF_C_PORT_RESET:
3282 sc->sc_isreset = 0;
3283 break;
3284 default:
3285 err = USB_ERR_IOERROR;
3286 goto done;
3287 }
3288 break;
3289 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3290 if ((value & 0xff) != 0) {
3291 err = USB_ERR_IOERROR;
3292 goto done;
3293 }
3294 v = EOREAD4(sc, EHCI_HCSPARAMS);
3295
3296 sc->sc_hub_desc.hubd = ehci_hubd;
3297 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3298 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics,
3299 (EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH) |
3300 (EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS)) ?
3301 UHD_PORT_IND : 0));
3302 /* XXX can't find out? */
3303 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 200;
3304 for (l = 0; l < sc->sc_noport; l++) {
3305 /* XXX can't find out? */
3306 sc->sc_hub_desc.hubd.DeviceRemovable[l / 8] &= ~(1 << (l % 8));
3307 }
3308 sc->sc_hub_desc.hubd.bDescLength =
3309 8 + ((sc->sc_noport + 7) / 8);
3310 len = sc->sc_hub_desc.hubd.bDescLength;
3311 break;
3312 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3313 len = 16;
3314 bzero(sc->sc_hub_desc.temp, 16);
3315 break;
3316 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3317 DPRINTFN(9, "get port status i=%d\n",
3318 index);
3319 if ((index < 1) ||
3320 (index > sc->sc_noport)) {
3321 err = USB_ERR_IOERROR;
3322 goto done;
3323 }
3324 v = EOREAD4(sc, EHCI_PORTSC(index));
3325 DPRINTFN(9, "port status=0x%04x\n", v);
3326 if (sc->sc_flags & (EHCI_SCFLG_FORCESPEED | EHCI_SCFLG_TT)) {
3327 if ((v & 0xc000000) == 0x8000000)
3328 i = UPS_HIGH_SPEED;
3329 else if ((v & 0xc000000) == 0x4000000)
3330 i = UPS_LOW_SPEED;
3331 else
3332 i = 0;
3333 } else {
3334 i = UPS_HIGH_SPEED;
3335 }
3336 if (v & EHCI_PS_CS)
3337 i |= UPS_CURRENT_CONNECT_STATUS;
3338 if (v & EHCI_PS_PE)
3339 i |= UPS_PORT_ENABLED;
3340 if ((v & EHCI_PS_SUSP) && !(v & EHCI_PS_FPR))
3341 i |= UPS_SUSPEND;
3342 if (v & EHCI_PS_OCA)
3343 i |= UPS_OVERCURRENT_INDICATOR;
3344 if (v & EHCI_PS_PR)
3345 i |= UPS_RESET;
3346 if (v & EHCI_PS_PP)
3347 i |= UPS_PORT_POWER;
3348 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3349 i = 0;
3350 if (v & EHCI_PS_CSC)
3351 i |= UPS_C_CONNECT_STATUS;
3352 if (v & EHCI_PS_PEC)
3353 i |= UPS_C_PORT_ENABLED;
3354 if (v & EHCI_PS_OCC)
3355 i |= UPS_C_OVERCURRENT_INDICATOR;
3356 if (v & EHCI_PS_FPR)
3357 i |= UPS_C_SUSPEND;
3358 if (sc->sc_isreset)
3359 i |= UPS_C_PORT_RESET;
3360 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3361 len = sizeof(sc->sc_hub_desc.ps);
3362 break;
3363 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3364 err = USB_ERR_IOERROR;
3365 goto done;
3366 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3367 break;
3368 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3369 if ((index < 1) ||
3370 (index > sc->sc_noport)) {
3371 err = USB_ERR_IOERROR;
3372 goto done;
3373 }
3374 port = EHCI_PORTSC(index);
3375 v = EOREAD4(sc, port) & ~EHCI_PS_CLEAR;
3376 switch (value) {
3377 case UHF_PORT_ENABLE:
3378 EOWRITE4(sc, port, v | EHCI_PS_PE);
3379 break;
3380 case UHF_PORT_SUSPEND:
3381 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
3382 break;
3383 case UHF_PORT_RESET:
3384 DPRINTFN(6, "reset port %d\n", index);
3385#if USB_DEBUG
3386 if (ehcinohighspeed) {
3387 /*
3388 * Connect USB device to companion
3389 * controller.
3390 */
3391 ehci_disown(sc, index, 1);
3392 break;
3393 }
3394#endif
3395 if (EHCI_PS_IS_LOWSPEED(v) &&
3396 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3397 /* Low speed device, give up ownership. */
3398 ehci_disown(sc, index, 1);
3399 break;
3400 }
3401 /* Start reset sequence. */
3402 v &= ~(EHCI_PS_PE | EHCI_PS_PR);
3403 EOWRITE4(sc, port, v | EHCI_PS_PR);
3404
3405 /* Wait for reset to complete. */
3406 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3407 USB_MS_TO_TICKS(USB_PORT_ROOT_RESET_DELAY));
3408
3409 /* Terminate reset sequence. */
3410 if (!(sc->sc_flags & EHCI_SCFLG_NORESTERM))
3411 EOWRITE4(sc, port, v);
3412
3413 /* Wait for HC to complete reset. */
3414 usb_pause_mtx(&sc->sc_bus.bus_mtx,
3415 USB_MS_TO_TICKS(EHCI_PORT_RESET_COMPLETE));
3416
3417 v = EOREAD4(sc, port);
3418 DPRINTF("ehci after reset, status=0x%08x\n", v);
3419 if (v & EHCI_PS_PR) {
3420 device_printf(sc->sc_bus.bdev,
3421 "port reset timeout\n");
3422 err = USB_ERR_TIMEOUT;
3423 goto done;
3424 }
3425 if (!(v & EHCI_PS_PE) &&
3426 (sc->sc_flags & EHCI_SCFLG_TT) == 0) {
3427 /* Not a high speed device, give up ownership.*/
3428 ehci_disown(sc, index, 0);
3429 break;
3430 }
3431 sc->sc_isreset = 1;
3432 DPRINTF("ehci port %d reset, status = 0x%08x\n",
3433 index, v);
3434 break;
3435
3436 case UHF_PORT_POWER:
3437 DPRINTFN(3, "set port power %d\n", index);
3438 EOWRITE4(sc, port, v | EHCI_PS_PP);
3439 break;
3440
3441 case UHF_PORT_TEST:
3442 DPRINTFN(3, "set port test %d\n", index);
3443 break;
3444
3445 case UHF_PORT_INDICATOR:
3446 DPRINTFN(3, "set port ind %d\n", index);
3447 EOWRITE4(sc, port, v | EHCI_PS_PIC);
3448 break;
3449
3450 default:
3451 err = USB_ERR_IOERROR;
3452 goto done;
3453 }
3454 break;
3455 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3456 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3457 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3458 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3459 break;
3460 default:
3461 err = USB_ERR_IOERROR;
3462 goto done;
3463 }
3464done:
3465 *plength = len;
3466 *pptr = ptr;
3467 return (err);
3468}
3469
3470static void
3471ehci_xfer_setup(struct usb_setup_params *parm)
3472{
3473 struct usb_page_search page_info;
3474 struct usb_page_cache *pc;
3475 ehci_softc_t *sc;
3476 struct usb_xfer *xfer;
3477 void *last_obj;
3478 uint32_t nqtd;
3479 uint32_t nqh;
3480 uint32_t nsitd;
3481 uint32_t nitd;
3482 uint32_t n;
3483
3484 sc = EHCI_BUS2SC(parm->udev->bus);
3485 xfer = parm->curr_xfer;
3486
3487 nqtd = 0;
3488 nqh = 0;
3489 nsitd = 0;
3490 nitd = 0;
3491
3492 /*
3493 * compute maximum number of some structures
3494 */
3495 if (parm->methods == &ehci_device_ctrl_methods) {
3496
3497 /*
3498 * The proof for the "nqtd" formula is illustrated like
3499 * this:
3500 *
3501 * +------------------------------------+
3502 * | |
3503 * | |remainder -> |
3504 * | +-----+---+ |
3505 * | | xxx | x | frm 0 |
3506 * | +-----+---++ |
3507 * | | xxx | xx | frm 1 |
3508 * | +-----+----+ |
3509 * | ... |
3510 * +------------------------------------+
3511 *
3512 * "xxx" means a completely full USB transfer descriptor
3513 *
3514 * "x" and "xx" means a short USB packet
3515 *
3516 * For the remainder of an USB transfer modulo
3517 * "max_data_length" we need two USB transfer descriptors.
3518 * One to transfer the remaining data and one to finalise
3519 * with a zero length packet in case the "force_short_xfer"
3520 * flag is set. We only need two USB transfer descriptors in
3521 * the case where the transfer length of the first one is a
3522 * factor of "max_frame_size". The rest of the needed USB
3523 * transfer descriptors is given by the buffer size divided
3524 * by the maximum data payload.
3525 */
3526 parm->hc_max_packet_size = 0x400;
3527 parm->hc_max_packet_count = 1;
3528 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3529 xfer->flags_int.bdma_enable = 1;
3530
3531 usbd_transfer_setup_sub(parm);
3532
3533 nqh = 1;
3534 nqtd = ((2 * xfer->nframes) + 1 /* STATUS */
3535 + (xfer->max_data_length / xfer->max_hc_frame_size));
3536
3537 } else if (parm->methods == &ehci_device_bulk_methods) {
3538
3539 parm->hc_max_packet_size = 0x400;
3540 parm->hc_max_packet_count = 1;
3541 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3542 xfer->flags_int.bdma_enable = 1;
3543
3544 usbd_transfer_setup_sub(parm);
3545
3546 nqh = 1;
3547 nqtd = ((2 * xfer->nframes)
3548 + (xfer->max_data_length / xfer->max_hc_frame_size));
3549
3550 } else if (parm->methods == &ehci_device_intr_methods) {
3551
3552 if (parm->speed == USB_SPEED_HIGH) {
3553 parm->hc_max_packet_size = 0x400;
3554 parm->hc_max_packet_count = 3;
3555 } else if (parm->speed == USB_SPEED_FULL) {
3556 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME;
3557 parm->hc_max_packet_count = 1;
3558 } else {
3559 parm->hc_max_packet_size = USB_FS_BYTES_PER_HS_UFRAME / 8;
3560 parm->hc_max_packet_count = 1;
3561 }
3562
3563 parm->hc_max_frame_size = EHCI_QTD_PAYLOAD_MAX;
3564 xfer->flags_int.bdma_enable = 1;
3565
3566 usbd_transfer_setup_sub(parm);
3567
3568 nqh = 1;
3569 nqtd = ((2 * xfer->nframes)
3570 + (xfer->max_data_length / xfer->max_hc_frame_size));
3571
3572 } else if (parm->methods == &ehci_device_isoc_fs_methods) {
3573
3574 parm->hc_max_packet_size = 0x3FF;
3575 parm->hc_max_packet_count = 1;
3576 parm->hc_max_frame_size = 0x3FF;
3577 xfer->flags_int.bdma_enable = 1;
3578
3579 usbd_transfer_setup_sub(parm);
3580
3581 nsitd = xfer->nframes;
3582
3583 } else if (parm->methods == &ehci_device_isoc_hs_methods) {
3584
3585 parm->hc_max_packet_size = 0x400;
3586 parm->hc_max_packet_count = 3;
3587 parm->hc_max_frame_size = 0xC00;
3588 xfer->flags_int.bdma_enable = 1;
3589
3590 usbd_transfer_setup_sub(parm);
3591
3592 nitd = ((xfer->nframes + 7) / 8) <<
3593 usbd_xfer_get_fps_shift(xfer);
3594
3595 } else {
3596
3597 parm->hc_max_packet_size = 0x400;
3598 parm->hc_max_packet_count = 1;
3599 parm->hc_max_frame_size = 0x400;
3600
3601 usbd_transfer_setup_sub(parm);
3602 }
3603
3604alloc_dma_set:
3605
3606 if (parm->err) {
3607 return;
3608 }
3609 /*
3610 * Allocate queue heads and transfer descriptors
3611 */
3612 last_obj = NULL;
3613
3614 if (usbd_transfer_setup_sub_malloc(
3615 parm, &pc, sizeof(ehci_itd_t),
3616 EHCI_ITD_ALIGN, nitd)) {
3617 parm->err = USB_ERR_NOMEM;
3618 return;
3619 }
3620 if (parm->buf) {
3621 for (n = 0; n != nitd; n++) {
3622 ehci_itd_t *td;
3623
3624 usbd_get_page(pc + n, 0, &page_info);
3625
3626 td = page_info.buffer;
3627
3628 /* init TD */
3629 td->itd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_ITD);
3630 td->obj_next = last_obj;
3631 td->page_cache = pc + n;
3632
3633 last_obj = td;
3634
3635 usb_pc_cpu_flush(pc + n);
3636 }
3637 }
3638 if (usbd_transfer_setup_sub_malloc(
3639 parm, &pc, sizeof(ehci_sitd_t),
3640 EHCI_SITD_ALIGN, nsitd)) {
3641 parm->err = USB_ERR_NOMEM;
3642 return;
3643 }
3644 if (parm->buf) {
3645 for (n = 0; n != nsitd; n++) {
3646 ehci_sitd_t *td;
3647
3648 usbd_get_page(pc + n, 0, &page_info);
3649
3650 td = page_info.buffer;
3651
3652 /* init TD */
3653 td->sitd_self = htohc32(sc, page_info.physaddr | EHCI_LINK_SITD);
3654 td->obj_next = last_obj;
3655 td->page_cache = pc + n;
3656
3657 last_obj = td;
3658
3659 usb_pc_cpu_flush(pc + n);
3660 }
3661 }
3662 if (usbd_transfer_setup_sub_malloc(
3663 parm, &pc, sizeof(ehci_qtd_t),
3664 EHCI_QTD_ALIGN, nqtd)) {
3665 parm->err = USB_ERR_NOMEM;
3666 return;
3667 }
3668 if (parm->buf) {
3669 for (n = 0; n != nqtd; n++) {
3670 ehci_qtd_t *qtd;
3671
3672 usbd_get_page(pc + n, 0, &page_info);
3673
3674 qtd = page_info.buffer;
3675
3676 /* init TD */
3677 qtd->qtd_self = htohc32(sc, page_info.physaddr);
3678 qtd->obj_next = last_obj;
3679 qtd->page_cache = pc + n;
3680
3681 last_obj = qtd;
3682
3683 usb_pc_cpu_flush(pc + n);
3684 }
3685 }
3686 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3687
3688 last_obj = NULL;
3689
3690 if (usbd_transfer_setup_sub_malloc(
3691 parm, &pc, sizeof(ehci_qh_t),
3692 EHCI_QH_ALIGN, nqh)) {
3693 parm->err = USB_ERR_NOMEM;
3694 return;
3695 }
3696 if (parm->buf) {
3697 for (n = 0; n != nqh; n++) {
3698 ehci_qh_t *qh;
3699
3700 usbd_get_page(pc + n, 0, &page_info);
3701
3702 qh = page_info.buffer;
3703
3704 /* init QH */
3705 qh->qh_self = htohc32(sc, page_info.physaddr | EHCI_LINK_QH);
3706 qh->obj_next = last_obj;
3707 qh->page_cache = pc + n;
3708
3709 last_obj = qh;
3710
3711 usb_pc_cpu_flush(pc + n);
3712 }
3713 }
3714 xfer->qh_start[xfer->flags_int.curr_dma_set] = last_obj;
3715
3716 if (!xfer->flags_int.curr_dma_set) {
3717 xfer->flags_int.curr_dma_set = 1;
3718 goto alloc_dma_set;
3719 }
3720}
3721
3722static void
3723ehci_xfer_unsetup(struct usb_xfer *xfer)
3724{
3725 return;
3726}
3727
3728static void
3729ehci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3730 struct usb_endpoint *ep)
3731{
3732 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3733
3734 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d (%d)\n",
3735 ep, udev->address,
3736 edesc->bEndpointAddress, udev->flags.usb_mode,
3737 sc->sc_addr);
3738
3739 if (udev->flags.usb_mode != USB_MODE_HOST) {
3740 /* not supported */
3741 return;
3742 }
3743 if (udev->device_index != sc->sc_addr) {
3744
3745 if ((udev->speed != USB_SPEED_HIGH) &&
3746 ((udev->hs_hub_addr == 0) ||
3747 (udev->hs_port_no == 0) ||
3748 (udev->parent_hs_hub == NULL) ||
3749 (udev->parent_hs_hub->hub == NULL))) {
3750 /* We need a transaction translator */
3751 goto done;
3752 }
3753 switch (edesc->bmAttributes & UE_XFERTYPE) {
3754 case UE_CONTROL:
3755 ep->methods = &ehci_device_ctrl_methods;
3756 break;
3757 case UE_INTERRUPT:
3758 ep->methods = &ehci_device_intr_methods;
3759 break;
3760 case UE_ISOCHRONOUS:
3761 if (udev->speed == USB_SPEED_HIGH) {
3762 ep->methods = &ehci_device_isoc_hs_methods;
3763 } else if (udev->speed == USB_SPEED_FULL) {
3764 ep->methods = &ehci_device_isoc_fs_methods;
3765 }
3766 break;
3767 case UE_BULK:
3768 if (udev->speed != USB_SPEED_LOW) {
3769 ep->methods = &ehci_device_bulk_methods;
3770 }
3771 break;
3772 default:
3773 /* do nothing */
3774 break;
3775 }
3776 }
3777done:
3778 return;
3779}
3780
3781static void
3782ehci_get_dma_delay(struct usb_bus *bus, uint32_t *pus)
3783{
3784 /*
3785 * Wait until the hardware has finished any possible use of
3786 * the transfer descriptor(s) and QH
3787 */
3788 *pus = (188); /* microseconds */
3789}
3790
3791static void
3792ehci_device_resume(struct usb_device *udev)
3793{
3794 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3795 struct usb_xfer *xfer;
3796 struct usb_pipe_methods *methods;
3797
3798 DPRINTF("\n");
3799
3800 USB_BUS_LOCK(udev->bus);
3801
3802 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3803
3804 if (xfer->xroot->udev == udev) {
3805
3806 methods = xfer->endpoint->methods;
3807
3808 if ((methods == &ehci_device_bulk_methods) ||
3809 (methods == &ehci_device_ctrl_methods)) {
3810 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3811 sc->sc_async_p_last);
3812 }
3813 if (methods == &ehci_device_intr_methods) {
3814 EHCI_APPEND_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3815 sc->sc_intr_p_last[xfer->qh_pos]);
3816 }
3817 }
3818 }
3819
3820 USB_BUS_UNLOCK(udev->bus);
3821
3822 return;
3823}
3824
3825static void
3826ehci_device_suspend(struct usb_device *udev)
3827{
3828 ehci_softc_t *sc = EHCI_BUS2SC(udev->bus);
3829 struct usb_xfer *xfer;
3830 struct usb_pipe_methods *methods;
3831
3832 DPRINTF("\n");
3833
3834 USB_BUS_LOCK(udev->bus);
3835
3836 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3837
3838 if (xfer->xroot->udev == udev) {
3839
3840 methods = xfer->endpoint->methods;
3841
3842 if ((methods == &ehci_device_bulk_methods) ||
3843 (methods == &ehci_device_ctrl_methods)) {
3844 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3845 sc->sc_async_p_last);
3846 }
3847 if (methods == &ehci_device_intr_methods) {
3848 EHCI_REMOVE_QH(xfer->qh_start[xfer->flags_int.curr_dma_set],
3849 sc->sc_intr_p_last[xfer->qh_pos]);
3850 }
3851 }
3852 }
3853
3854 USB_BUS_UNLOCK(udev->bus);
3855
3856 return;
3857}
3858
3859static void
3860ehci_set_hw_power(struct usb_bus *bus)
3861{
3862 ehci_softc_t *sc = EHCI_BUS2SC(bus);
3863 uint32_t temp;
3864 uint32_t flags;
3865
3866 DPRINTF("\n");
3867
3868 USB_BUS_LOCK(bus);
3869
3870 flags = bus->hw_power_state;
3871
3872 temp = EOREAD4(sc, EHCI_USBCMD);
3873
3874 temp &= ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
3875
3876 if (flags & (USB_HW_POWER_CONTROL |
3877 USB_HW_POWER_BULK)) {
3878 DPRINTF("Async is active\n");
3879 temp |= EHCI_CMD_ASE;
3880 }
3881 if (flags & (USB_HW_POWER_INTERRUPT |
3882 USB_HW_POWER_ISOC)) {
3883 DPRINTF("Periodic is active\n");
3884 temp |= EHCI_CMD_PSE;
3885 }
3886 EOWRITE4(sc, EHCI_USBCMD, temp);
3887
3888 USB_BUS_UNLOCK(bus);
3889
3890 return;
3891}
3892
3893struct usb_bus_methods ehci_bus_methods =
3894{
3895 .endpoint_init = ehci_ep_init,
3896 .xfer_setup = ehci_xfer_setup,
3897 .xfer_unsetup = ehci_xfer_unsetup,
3898 .get_dma_delay = ehci_get_dma_delay,
3899 .device_resume = ehci_device_resume,
3900 .device_suspend = ehci_device_suspend,
3901 .set_hw_power = ehci_set_hw_power,
3902 .roothub_exec = ehci_roothub_exec,
3903 .xfer_poll = ehci_do_poll,
3904};
|