1/*-
|
2 * Copyright (c) 2006 Benno Rice. All rights reserved.
|
| 2 * Copyright (c) 2008 Benno Rice. All rights reserved. |
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25#include <sys/cdefs.h>
|
26__FBSDID("$FreeBSD: head/sys/dev/smc/if_smc.c 179592 2008-06-06 05:00:49Z benno $");
|
| 26__FBSDID("$FreeBSD: head/sys/dev/smc/if_smc.c 179718 2008-06-11 06:53:55Z benno $"); |
27
28/*
29 * Driver for SMSC LAN91C111, may work for older variants.
30 */
31
32#ifdef HAVE_KERNEL_OPTION_HEADERS
33#include "opt_device_polling.h"
34#endif
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/errno.h>
39#include <sys/kernel.h>
40#include <sys/sockio.h>
41#include <sys/malloc.h>
42#include <sys/mbuf.h>
43#include <sys/queue.h>
44#include <sys/socket.h>
45#include <sys/syslog.h>
46#include <sys/taskqueue.h>
47
48#include <sys/module.h>
49#include <sys/bus.h>
50
51#include <machine/bus.h>
52#include <machine/resource.h>
53#include <sys/rman.h>
54
55#include <net/ethernet.h>
56#include <net/if.h>
57#include <net/if_arp.h>
58#include <net/if_dl.h>
59#include <net/if_types.h>
60#include <net/if_mib.h>
61#include <net/if_media.h>
62
63#ifdef INET
64#include <netinet/in.h>
65#include <netinet/in_systm.h>
66#include <netinet/in_var.h>
67#include <netinet/ip.h>
68#endif
69
70#include <net/bpf.h>
71#include <net/bpfdesc.h>
72
73#include <dev/smc/if_smcreg.h>
74#include <dev/smc/if_smcvar.h>
75
76#include <dev/mii/mii.h>
77#include <dev/mii/miivar.h>
78
79devclass_t smc_devclass;
80
81static const char *smc_chip_ids[16] = {
82 NULL, NULL, NULL,
83 /* 3 */ "SMSC LAN91C90 or LAN91C92",
84 /* 4 */ "SMSC LAN91C94",
85 /* 5 */ "SMSC LAN91C95",
86 /* 6 */ "SMSC LAN91C96",
87 /* 7 */ "SMSC LAN91C100",
88 /* 8 */ "SMSC LAN91C100FD",
89 /* 9 */ "SMSC LAN91C110FD or LAN91C111FD",
90 NULL, NULL, NULL,
91 NULL, NULL, NULL
92};
93
94static void smc_init(void *);
95static void smc_start(struct ifnet *);
96static int smc_ioctl(struct ifnet *, u_long, caddr_t);
97
98static void smc_init_locked(struct smc_softc *);
99static void smc_start_locked(struct ifnet *);
100static void smc_reset(struct smc_softc *);
101static int smc_mii_ifmedia_upd(struct ifnet *);
102static void smc_mii_ifmedia_sts(struct ifnet *, struct ifmediareq *);
103static void smc_mii_tick(void *);
104static void smc_mii_mediachg(struct smc_softc *);
105static int smc_mii_mediaioctl(struct smc_softc *, struct ifreq *, u_long);
106
107static void smc_task_rx(void *, int);
108static void smc_task_tx(void *, int);
109
110static driver_filter_t smc_intr;
111static timeout_t smc_watchdog;
112#ifdef DEVICE_POLLING
113static poll_handler_t smc_poll;
114#endif
115
116static __inline void
117smc_select_bank(struct smc_softc *sc, uint16_t bank)
118{
119
|
120 bus_space_write_2(sc->smc_bst, sc->smc_bsh, BSR, bank & BSR_BANK_MASK);
|
| 120 bus_write_2(sc->smc_reg, BSR, bank & BSR_BANK_MASK); |
121}
122
123/* Never call this when not in bank 2. */
124static __inline void
125smc_mmu_wait(struct smc_softc *sc)
126{
127
|
128 KASSERT((bus_space_read_2(sc->smc_bst, sc->smc_bsh, BSR) &
|
| 128 KASSERT((bus_read_2(sc->smc_reg, BSR) & |
129 BSR_BANK_MASK) == 2, ("%s: smc_mmu_wait called when not in bank 2",
130 device_get_nameunit(sc->smc_dev)));
|
131 while (bus_space_read_2(sc->smc_bst, sc->smc_bsh, MMUCR) & MMUCR_BUSY)
|
| 131 while (bus_read_2(sc->smc_reg, MMUCR) & MMUCR_BUSY) |
132 ;
133}
134
135static __inline uint8_t
136smc_read_1(struct smc_softc *sc, bus_addr_t offset)
137{
138
|
139 return (bus_space_read_1(sc->smc_bst, sc->smc_bsh, offset));
|
| 139 return (bus_read_1(sc->smc_reg, offset)); |
140}
141
142static __inline void
143smc_write_1(struct smc_softc *sc, bus_addr_t offset, uint8_t val)
144{
145
|
146 bus_space_write_1(sc->smc_bst, sc->smc_bsh, offset, val);
|
| 146 bus_write_1(sc->smc_reg, offset, val); |
147}
148
149static __inline uint16_t
150smc_read_2(struct smc_softc *sc, bus_addr_t offset)
151{
152
|
153 return (bus_space_read_2(sc->smc_bst, sc->smc_bsh, offset));
|
| 153 return (bus_read_2(sc->smc_reg, offset)); |
154}
155
156static __inline void
157smc_write_2(struct smc_softc *sc, bus_addr_t offset, uint16_t val)
158{
159
|
160 bus_space_write_2(sc->smc_bst, sc->smc_bsh, offset, val);
|
| 160 bus_write_2(sc->smc_reg, offset, val); |
161}
162
163static __inline void
164smc_read_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap,
165 bus_size_t count)
166{
167
|
168 bus_space_read_multi_2(sc->smc_bst, sc->smc_bsh, offset, datap, count);
|
| 168 bus_read_multi_2(sc->smc_reg, offset, datap, count); |
169}
170
171static __inline void
172smc_write_multi_2(struct smc_softc *sc, bus_addr_t offset, uint16_t *datap,
173 bus_size_t count)
174{
175
|
176 bus_space_write_multi_2(sc->smc_bst, sc->smc_bsh, offset, datap, count);
|
| 176 bus_write_multi_2(sc->smc_reg, offset, datap, count); |
177}
178
179int
180smc_probe(device_t dev)
181{
182 int rid, type, error;
183 uint16_t val;
184 struct smc_softc *sc;
185 struct resource *reg;
|
186 bus_space_tag_t bst;
187 bus_space_handle_t bsh;
|
186
187 sc = device_get_softc(dev);
188 rid = 0;
189 type = SYS_RES_IOPORT;
190 error = 0;
191
192 if (sc->smc_usemem)
193 type = SYS_RES_MEMORY;
194
195 reg = bus_alloc_resource(dev, type, &rid, 0, ~0, 16, RF_ACTIVE);
196 if (reg == NULL) {
197 if (bootverbose)
198 device_printf(dev,
199 "could not allocate I/O resource for probe\n");
200 return (ENXIO);
201 }
202
|
205 bst = rman_get_bustag(reg);
206 bsh = rman_get_bushandle(reg);
207
|
203 /* Check for the identification value in the BSR. */
|
209 val = bus_space_read_2(bst, bsh, BSR);
|
| 204 val = bus_read_2(reg, BSR); |
205 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
206 if (bootverbose)
207 device_printf(dev, "identification value not in BSR\n");
208 error = ENXIO;
209 goto done;
210 }
211
212 /*
213 * Try switching banks and make sure we still get the identification
214 * value.
215 */
|
221 bus_space_write_2(bst, bsh, BSR, 0);
222 val = bus_space_read_2(bst, bsh, BSR);
|
216 bus_write_2(reg, BSR, 0);
217 val = bus_read_2(reg, BSR); |
218 if ((val & BSR_IDENTIFY_MASK) != BSR_IDENTIFY) {
219 if (bootverbose)
220 device_printf(dev,
221 "identification value not in BSR after write\n");
222 error = ENXIO;
223 goto done;
224 }
225
226#if 0
227 /* Check the BAR. */
|
233 bus_space_write_2(bst, bsh, BSR, 1);
234 val = bus_space_read_2(bst, bsh, BAR);
|
228 bus_write_2(reg, BSR, 1);
229 val = bus_read_2(reg, BAR); |
230 val = BAR_ADDRESS(val);
231 if (rman_get_start(reg) != val) {
232 if (bootverbose)
233 device_printf(dev, "BAR address %x does not match "
234 "I/O resource address %lx\n", val,
235 rman_get_start(reg));
236 error = ENXIO;
237 goto done;
238 }
239#endif
240
241 /* Compare REV against known chip revisions. */
|
247 bus_space_write_2(bst, bsh, BSR, 3);
248 val = bus_space_read_2(bst, bsh, REV);
|
242 bus_write_2(reg, BSR, 3);
243 val = bus_read_2(reg, REV); |
244 val = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
245 if (smc_chip_ids[val] == NULL) {
246 if (bootverbose)
247 device_printf(dev, "Unknown chip revision: %d\n", val);
248 error = ENXIO;
249 goto done;
250 }
251
252 device_set_desc(dev, smc_chip_ids[val]);
253
254done:
255 bus_release_resource(dev, type, rid, reg);
256 return (error);
257}
258
259int
260smc_attach(device_t dev)
261{
262 int type, error;
263 uint16_t val;
264 u_char eaddr[ETHER_ADDR_LEN];
265 struct smc_softc *sc;
266 struct ifnet *ifp;
267
268 sc = device_get_softc(dev);
269 error = 0;
270
271 sc->smc_dev = dev;
272
273 /* Set up watchdog callout. */
274 callout_init(&sc->smc_watchdog, 1);
275
276 ifp = sc->smc_ifp = if_alloc(IFT_ETHER);
277 if (ifp == NULL) {
278 error = ENOSPC;
279 goto done;
280 }
281
282 mtx_init(&sc->smc_mtx, device_get_nameunit(dev), NULL, MTX_SPIN);
283
284 type = SYS_RES_IOPORT;
285 if (sc->smc_usemem)
286 type = SYS_RES_MEMORY;
287
288 sc->smc_reg_rid = 0;
289 sc->smc_reg = bus_alloc_resource(dev, type, &sc->smc_reg_rid, 0, ~0,
290 16, RF_ACTIVE);
291 if (sc->smc_reg == NULL) {
292 error = ENXIO;
293 goto done;
294 }
295
296 sc->smc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->smc_irq_rid, 0,
297 ~0, 1, RF_ACTIVE | RF_SHAREABLE);
298 if (sc->smc_irq == NULL) {
299 error = ENXIO;
300 goto done;
301 }
302
|
308 sc->smc_bst = rman_get_bustag(sc->smc_reg);
309 sc->smc_bsh = rman_get_bushandle(sc->smc_reg);
310
|
303 SMC_LOCK(sc);
304 smc_reset(sc);
305 SMC_UNLOCK(sc);
306
307 smc_select_bank(sc, 3);
308 val = smc_read_2(sc, REV);
309 sc->smc_chip = (val & REV_CHIP_MASK) >> REV_CHIP_SHIFT;
310 sc->smc_rev = (val * REV_REV_MASK) >> REV_REV_SHIFT;
311 if (bootverbose)
312 device_printf(dev, "revision %x\n", sc->smc_rev);
313
314 callout_init(&sc->smc_mii_tick_ch, 1);
315 if (sc->smc_chip >= REV_CHIP_91110FD) {
316 mii_phy_probe(dev, &sc->smc_miibus, smc_mii_ifmedia_upd,
317 smc_mii_ifmedia_sts);
318 if (sc->smc_miibus != NULL) {
319 sc->smc_mii_tick = smc_mii_tick;
320 sc->smc_mii_mediachg = smc_mii_mediachg;
321 sc->smc_mii_mediaioctl = smc_mii_mediaioctl;
322 }
323 }
324
325 smc_select_bank(sc, 1);
326 eaddr[0] = smc_read_1(sc, IAR0);
327 eaddr[1] = smc_read_1(sc, IAR1);
328 eaddr[2] = smc_read_1(sc, IAR2);
329 eaddr[3] = smc_read_1(sc, IAR3);
330 eaddr[4] = smc_read_1(sc, IAR4);
331 eaddr[5] = smc_read_1(sc, IAR5);
332
333 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
334 ifp->if_softc = sc;
335 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
336 ifp->if_init = smc_init;
337 ifp->if_ioctl = smc_ioctl;
338 ifp->if_start = smc_start;
339 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
340 IFQ_SET_READY(&ifp->if_snd);
341
342 ifp->if_capabilities = ifp->if_capenable = 0;
343
344#ifdef DEVICE_POLLING
345 ifp->if_capabilities |= IFCAP_POLLING;
346#endif
347
348 ether_ifattach(ifp, eaddr);
349
350 /* Set up taskqueue */
351 TASK_INIT(&sc->smc_rx, SMC_RX_PRIORITY, smc_task_rx, ifp);
352 TASK_INIT(&sc->smc_tx, SMC_TX_PRIORITY, smc_task_tx, ifp);
353 sc->smc_tq = taskqueue_create_fast("smc_taskq", M_NOWAIT,
354 taskqueue_thread_enqueue, &sc->smc_tq);
355 taskqueue_start_threads(&sc->smc_tq, 1, PI_NET, "%s taskq",
356 device_get_nameunit(sc->smc_dev));
357
358 /* Mask all interrupts. */
359 sc->smc_mask = 0;
360 smc_write_1(sc, MSK, 0);
361
362 /* Wire up interrupt */
363 error = bus_setup_intr(dev, sc->smc_irq,
364 INTR_TYPE_NET|INTR_MPSAFE, smc_intr, NULL, ifp, &sc->smc_ih);
365 if (error != 0)
366 goto done;
367
368done:
369 if (error != 0)
370 smc_detach(dev);
371 return (error);
372}
373
374int
375smc_detach(device_t dev)
376{
377 int type;
378 struct smc_softc *sc;
379
380 sc = device_get_softc(dev);
381
382 callout_stop(&sc->smc_watchdog);
383
384 if (mtx_initialized(&sc->smc_mtx))
385 SMC_LOCK(sc);
386
387#ifdef DEVICE_POLLING
388 if (sc->smc_ifp->if_capenable & IFCAP_POLLING)
389 ether_poll_deregister(sc->smc_ifp);
390#endif
391
392 if (sc->smc_ih != NULL)
393 bus_teardown_intr(sc->smc_dev, sc->smc_irq, sc->smc_ih);
394
395 if (sc->smc_ifp != NULL) {
396 ether_ifdetach(sc->smc_ifp);
397 if_free(sc->smc_ifp);
398 }
399
400 if (sc->smc_miibus != NULL) {
401 device_delete_child(sc->smc_dev, sc->smc_miibus);
402 bus_generic_detach(sc->smc_dev);
403 }
404
405 if (sc->smc_reg != NULL) {
406 type = SYS_RES_IOPORT;
407 if (sc->smc_usemem)
408 type = SYS_RES_MEMORY;
409
410 bus_release_resource(sc->smc_dev, type, sc->smc_reg_rid,
411 sc->smc_reg);
412 }
413
414 if (sc->smc_irq != NULL)
415 bus_release_resource(sc->smc_dev, SYS_RES_IRQ, sc->smc_irq_rid,
416 sc->smc_irq);
417
418 if (sc->smc_tq != NULL)
419 taskqueue_free(sc->smc_tq);
420
421 if (mtx_initialized(&sc->smc_mtx))
422 mtx_destroy(&sc->smc_mtx);
423
424 return (0);
425}
426
427static void
428smc_start(struct ifnet *ifp)
429{
430 struct smc_softc *sc;
431
432 sc = ifp->if_softc;
433 SMC_LOCK(sc);
434 smc_start_locked(ifp);
435 SMC_UNLOCK(sc);
436}
437
438static void
439smc_start_locked(struct ifnet *ifp)
440{
441 struct smc_softc *sc;
442 struct mbuf *m;
443 u_int len, npages, spin_count;
444
445 sc = ifp->if_softc;
446 SMC_ASSERT_LOCKED(sc);
447
448 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
449 return;
450 if (IFQ_IS_EMPTY(&ifp->if_snd))
451 return;
452
453 /*
454 * Grab the next packet. If it's too big, drop it.
455 */
456 SMC_UNLOCK(sc);
457 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
458 SMC_LOCK(sc);
459 len = m_length(m, NULL);
460 len += (len & 1);
461 if (len > ETHER_MAX_LEN - ETHER_CRC_LEN) {
462 if_printf(ifp, "large packet discarded\n");
463 ++ifp->if_oerrors;
464 m_freem(m);
465 return; /* XXX readcheck? */
466 }
467
468 /*
469 * Flag that we're busy.
470 */
471 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
472 sc->smc_pending = m;
473
474 /*
475 * Work out how many 256 byte "pages" we need. We have to include the
476 * control data for the packet in this calculation.
477 */
478 npages = (len * PKT_CTRL_DATA_LEN) >> 8;
479 if (npages == 0)
480 npages = 1;
481
482 /*
483 * Request memory.
484 */
485 smc_select_bank(sc, 2);
486 smc_mmu_wait(sc);
487 smc_write_2(sc, MMUCR, MMUCR_CMD_TX_ALLOC | npages);
488
489 /*
490 * Spin briefly to see if the allocation succeeds.
491 */
492 spin_count = TX_ALLOC_WAIT_TIME;
493 do {
494 if (smc_read_1(sc, IST) & ALLOC_INT) {
495 smc_write_1(sc, ACK, ALLOC_INT);
496 break;
497 }
498 } while (--spin_count);
499
500 /*
501 * If the allocation is taking too long, unmask the alloc interrupt
502 * and wait.
503 */
504 if (spin_count == 0) {
505 sc->smc_mask |= ALLOC_INT;
506 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
507 smc_write_1(sc, MSK, sc->smc_mask);
508 return;
509 }
510
511 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
512}
513
514static void
515smc_task_tx(void *context, int pending)
516{
517 struct ifnet *ifp;
518 struct smc_softc *sc;
519 struct mbuf *m, *m0;
520 u_int packet, len;
521 uint8_t *data;
522
523 (void)pending;
524 ifp = (struct ifnet *)context;
525 sc = ifp->if_softc;
526
527 SMC_LOCK(sc);
528
529 if (sc->smc_pending == NULL) {
530 SMC_UNLOCK(sc);
531 goto next_packet;
532 }
533
534 m = m0 = sc->smc_pending;
535 sc->smc_pending = NULL;
536 smc_select_bank(sc, 2);
537
538 /*
539 * Check the allocation result.
540 */
541 packet = smc_read_1(sc, ARR);
542
543 /*
544 * If the allocation failed, requeue the packet and retry.
545 */
546 if (packet & ARR_FAILED) {
547 IFQ_DRV_PREPEND(&ifp->if_snd, m);
548 ++ifp->if_oerrors;
549 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
550 smc_start_locked(ifp);
551 SMC_UNLOCK(sc);
552 return;
553 }
554
555 /*
556 * Tell the device to write to our packet number.
557 */
558 smc_write_1(sc, PNR, packet);
559 smc_write_2(sc, PTR, 0 | PTR_AUTO_INCR);
560
561 /*
562 * Tell the device how long the packet is (including control data).
563 */
564 len = m_length(m, 0);
565 len += PKT_CTRL_DATA_LEN;
566 smc_write_2(sc, DATA0, 0);
567 smc_write_2(sc, DATA0, len);
568
569 /*
570 * Push the data out to the device.
571 */
572 data = NULL;
573 for (; m != NULL; m = m->m_next) {
574 data = mtod(m, uint8_t *);
575 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2);
576 }
577
578 /*
579 * Push out the control byte and and the odd byte if needed.
580 */
581 if ((len & 1) != 0 && data != NULL)
582 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[m->m_len - 1]);
583 else
584 smc_write_2(sc, DATA0, 0);
585
586 /*
587 * Unmask the TX empty interrupt.
588 */
589 sc->smc_mask |= TX_EMPTY_INT;
590 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
591 smc_write_1(sc, MSK, sc->smc_mask);
592
593 /*
594 * Enqueue the packet.
595 */
596 smc_mmu_wait(sc);
597 smc_write_2(sc, MMUCR, MMUCR_CMD_ENQUEUE);
598 callout_reset(&sc->smc_watchdog, hz * 2, smc_watchdog, ifp);
599
600 /*
601 * Finish up.
602 */
603 ifp->if_opackets++;
604 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
605 SMC_UNLOCK(sc);
606 BPF_MTAP(ifp, m0);
607 m_freem(m0);
608
609next_packet:
610 /*
611 * See if there's anything else to do.
612 */
613 smc_start(ifp);
614}
615
616static void
617smc_task_rx(void *context, int pending)
618{
619 u_int packet, status, len;
620 uint8_t *data;
621 struct ifnet *ifp;
622 struct smc_softc *sc;
623 struct mbuf *m, *mhead, *mtail;
624
625 (void)pending;
626 ifp = (struct ifnet *)context;
627 sc = ifp->if_softc;
628 mhead = mtail = NULL;
629
630 SMC_LOCK(sc);
631
632 packet = smc_read_1(sc, FIFO_RX);
633 while ((packet & FIFO_EMPTY) == 0) {
634 /*
635 * Grab an mbuf and attach a cluster.
636 */
637 MGETHDR(m, M_DONTWAIT, MT_DATA);
638 if (m == NULL) {
639 break;
640 }
641 MCLGET(m, M_DONTWAIT);
642 if ((m->m_flags & M_EXT) == 0) {
643 m_freem(m);
644 break;
645 }
646
647 /*
648 * Point to the start of the packet.
649 */
650 smc_select_bank(sc, 2);
651 smc_write_1(sc, PNR, packet);
652 smc_write_2(sc, PTR, 0 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
653
654 /*
655 * Grab status and packet length.
656 */
657 status = smc_read_2(sc, DATA0);
658 len = smc_read_2(sc, DATA0) & RX_LEN_MASK;
659 len -= 6;
660 if (status & RX_ODDFRM)
661 len += 1;
662
663 /*
664 * Check for errors.
665 */
666 if (status & (RX_TOOSHORT | RX_TOOLNG | RX_BADCRC | RX_ALGNERR)) {
667 smc_mmu_wait(sc);
668 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
669 ifp->if_ierrors++;
670 m_freem(m);
671 break;
672 }
673
674 /*
675 * Set the mbuf up the way we want it.
676 */
677 m->m_pkthdr.rcvif = ifp;
678 m->m_pkthdr.len = m->m_len = len + 2; /* XXX: Is this right? */
679 m_adj(m, ETHER_ALIGN);
680
681 /*
682 * Pull the packet out of the device. Make sure we're in the
683 * right bank first as things may have changed while we were
684 * allocating our mbuf.
685 */
686 smc_select_bank(sc, 2);
687 smc_write_1(sc, PNR, packet);
688 smc_write_2(sc, PTR, 4 | PTR_READ | PTR_RCV | PTR_AUTO_INCR);
689 data = mtod(m, uint8_t *);
690 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1);
691 if (len & 1) {
692 data += len & ~1;
693 *data = smc_read_1(sc, DATA0);
694 }
695
696 /*
697 * Tell the device we're done.
698 */
699 smc_mmu_wait(sc);
700 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE);
701 if (m == NULL) {
702 break;
703 }
704
705 if (mhead == NULL) {
706 mhead = mtail = m;
707 m->m_next = NULL;
708 } else {
709 mtail->m_next = m;
710 mtail = m;
711 }
712 packet = smc_read_1(sc, FIFO_RX);
713 }
714
715 sc->smc_mask |= RCV_INT;
716 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
717 smc_write_1(sc, MSK, sc->smc_mask);
718
719 SMC_UNLOCK(sc);
720
721 while (mhead != NULL) {
722 m = mhead;
723 mhead = mhead->m_next;
724 m->m_next = NULL;
725 ifp->if_ipackets++;
726 (*ifp->if_input)(ifp, m);
727 }
728}
729
730#ifdef DEVICE_POLLING
731static void
732smc_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
733{
734 struct smc_softc *sc;
735
736 sc = ifp->if_softc;
737
738 SMC_LOCK(sc);
739 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
740 SMC_UNLOCK(sc);
741 return;
742 }
743 SMC_UNLOCK(sc);
744
745 if (cmd == POLL_AND_CHECK_STATUS)
746 smc_intr(ifp);
747}
748#endif
749
750static int
751smc_intr(void *context)
752{
753 struct smc_softc *sc;
754 struct ifnet *ifp;
755 u_int status, packet, counter, tcr;
756
757 ifp = (struct ifnet *)context;
758 sc = ifp->if_softc;
759
760 SMC_LOCK(sc);
761 smc_select_bank(sc, 2);
762
763 /*
764 * Get the current mask, and then block all interrupts while we're
765 * working.
766 */
767 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
768 smc_write_1(sc, MSK, 0);
769
770 /*
771 * Find out what interrupts are flagged.
772 */
773 status = smc_read_1(sc, IST) & sc->smc_mask;
774
775 /*
776 * Transmit error
777 */
778 if (status & TX_INT) {
779 /*
780 * Kill off the packet if there is one and re-enable transmit.
781 */
782 packet = smc_read_1(sc, FIFO_TX);
783 if ((packet & FIFO_EMPTY) == 0) {
784 smc_write_1(sc, PNR, packet);
785 smc_write_2(sc, PTR, 0 | PTR_READ |
786 PTR_AUTO_INCR);
787 tcr = smc_read_2(sc, DATA0);
788 if ((tcr & EPHSR_TX_SUC) == 0)
789 device_printf(sc->smc_dev,
790 "bad packet\n");
791 smc_mmu_wait(sc);
792 smc_write_2(sc, MMUCR, MMUCR_CMD_RELEASE_PKT);
793
794 smc_select_bank(sc, 0);
795 tcr = smc_read_2(sc, TCR);
796 tcr |= TCR_TXENA | TCR_PAD_EN;
797 smc_write_2(sc, TCR, tcr);
798 smc_select_bank(sc, 2);
799 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
800 }
801
802 /*
803 * Ack the interrupt.
804 */
805 smc_write_1(sc, ACK, TX_INT);
806 }
807
808 /*
809 * Receive
810 */
811 if (status & RCV_INT) {
812 smc_write_1(sc, ACK, RCV_INT);
813 sc->smc_mask &= ~RCV_INT;
814 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_rx);
815 }
816
817 /*
818 * Allocation
819 */
820 if (status & ALLOC_INT) {
821 smc_write_1(sc, ACK, ALLOC_INT);
822 sc->smc_mask &= ~ALLOC_INT;
823 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
824 }
825
826 /*
827 * Receive overrun
828 */
829 if (status & RX_OVRN_INT) {
830 smc_write_1(sc, ACK, RX_OVRN_INT);
831 ifp->if_ierrors++;
832 }
833
834 /*
835 * Transmit empty
836 */
837 if (status & TX_EMPTY_INT) {
838 smc_write_1(sc, ACK, TX_EMPTY_INT);
839 sc->smc_mask &= ~TX_EMPTY_INT;
840 callout_stop(&sc->smc_watchdog);
841
842 /*
843 * Update collision stats.
844 */
845 smc_select_bank(sc, 0);
846 counter = smc_read_2(sc, ECR);
847 smc_select_bank(sc, 2);
848 ifp->if_collisions +=
849 (counter & ECR_SNGLCOL_MASK) >> ECR_SNGLCOL_SHIFT;
850 ifp->if_collisions +=
851 (counter & ECR_MULCOL_MASK) >> ECR_MULCOL_SHIFT;
852
853 /*
854 * See if there are any packets to transmit.
855 */
856 taskqueue_enqueue_fast(sc->smc_tq, &sc->smc_tx);
857 }
858
859 /*
860 * Update the interrupt mask.
861 */
862 if ((ifp->if_capenable & IFCAP_POLLING) == 0)
863 smc_write_1(sc, MSK, sc->smc_mask);
864
865 SMC_UNLOCK(sc);
866
867 return (FILTER_HANDLED);
868}
869
870static u_int
871smc_mii_readbits(struct smc_softc *sc, int nbits)
872{
873 u_int mgmt, mask, val;
874
875 SMC_ASSERT_LOCKED(sc);
876 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
877 ("%s: smc_mii_readbits called with bank %d (!= 3)",
878 device_get_nameunit(sc->smc_dev),
879 smc_read_2(sc, BSR) & BSR_BANK_MASK));
880
881 /*
882 * Set up the MGMT (aka MII) register.
883 */
884 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO);
885 smc_write_2(sc, MGMT, mgmt);
886
887 /*
888 * Read the bits in.
889 */
890 for (mask = 1 << (nbits - 1), val = 0; mask; mask >>= 1) {
891 if (smc_read_2(sc, MGMT) & MGMT_MDI)
892 val |= mask;
893
894 smc_write_2(sc, MGMT, mgmt);
895 DELAY(1);
896 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK);
897 DELAY(1);
898 }
899
900 return (val);
901}
902
903static void
904smc_mii_writebits(struct smc_softc *sc, u_int val, int nbits)
905{
906 u_int mgmt, mask;
907
908 SMC_ASSERT_LOCKED(sc);
909 KASSERT((smc_read_2(sc, BSR) & BSR_BANK_MASK) == 3,
910 ("%s: smc_mii_writebits called with bank %d (!= 3)",
911 device_get_nameunit(sc->smc_dev),
912 smc_read_2(sc, BSR) & BSR_BANK_MASK));
913
914 /*
915 * Set up the MGMT (aka MII) register).
916 */
917 mgmt = smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO);
918 mgmt |= MGMT_MDOE;
919
920 /*
921 * Push the bits out.
922 */
923 for (mask = 1 << (nbits - 1); mask; mask >>= 1) {
924 if (val & mask)
925 mgmt |= MGMT_MDO;
926 else
927 mgmt &= ~MGMT_MDO;
928
929 smc_write_2(sc, MGMT, mgmt);
930 DELAY(1);
931 smc_write_2(sc, MGMT, mgmt | MGMT_MCLK);
932 DELAY(1);
933 }
934}
935
936int
937smc_miibus_readreg(device_t dev, int phy, int reg)
938{
939 struct smc_softc *sc;
940 int val;
941
942 sc = device_get_softc(dev);
943
944 SMC_LOCK(sc);
945
946 smc_select_bank(sc, 3);
947
948 /*
949 * Send out the idle pattern.
950 */
951 smc_mii_writebits(sc, 0xffffffff, 32);
952
953 /*
954 * Start code + read opcode + phy address + phy register
955 */
956 smc_mii_writebits(sc, 6 << 10 | phy << 5 | reg, 14);
957
958 /*
959 * Turnaround + data
960 */
961 val = smc_mii_readbits(sc, 18);
962
963 /*
964 * Reset the MDIO interface.
965 */
966 smc_write_2(sc, MGMT,
967 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO));
968
969 SMC_UNLOCK(sc);
970 return (val);
971}
972
973void
974smc_miibus_writereg(device_t dev, int phy, int reg, int data)
975{
976 struct smc_softc *sc;
977
978 sc = device_get_softc(dev);
979
980 SMC_LOCK(sc);
981
982 smc_select_bank(sc, 3);
983
984 /*
985 * Send idle pattern.
986 */
987 smc_mii_writebits(sc, 0xffffffff, 32);
988
989 /*
990 * Start code + write opcode + phy address + phy register + turnaround
991 * + data.
992 */
993 smc_mii_writebits(sc, 5 << 28 | phy << 23 | reg << 18 | 2 << 16 | data,
994 32);
995
996 /*
997 * Reset MDIO interface.
998 */
999 smc_write_2(sc, MGMT,
1000 smc_read_2(sc, MGMT) & ~(MGMT_MCLK | MGMT_MDOE | MGMT_MDO));
1001
1002 SMC_UNLOCK(sc);
1003}
1004
1005void
1006smc_miibus_statchg(device_t dev)
1007{
1008 struct smc_softc *sc;
1009 struct mii_data *mii;
1010 uint16_t tcr;
1011
1012 sc = device_get_softc(dev);
1013 mii = device_get_softc(sc->smc_miibus);
1014
1015 SMC_LOCK(sc);
1016
1017 smc_select_bank(sc, 0);
1018 tcr = smc_read_2(sc, TCR);
1019
1020 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
1021 tcr |= TCR_SWFDUP;
1022 else
1023 tcr &= ~TCR_SWFDUP;
1024
1025 smc_write_2(sc, TCR, tcr);
1026
1027 SMC_UNLOCK(sc);
1028}
1029
1030static int
1031smc_mii_ifmedia_upd(struct ifnet *ifp)
1032{
1033 struct smc_softc *sc;
1034 struct mii_data *mii;
1035
1036 sc = ifp->if_softc;
1037 if (sc->smc_miibus == NULL)
1038 return (ENXIO);
1039
1040 mii = device_get_softc(sc->smc_miibus);
1041 return (mii_mediachg(mii));
1042}
1043
1044static void
1045smc_mii_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1046{
1047 struct smc_softc *sc;
1048 struct mii_data *mii;
1049
1050 sc = ifp->if_softc;
1051 if (sc->smc_miibus == NULL)
1052 return;
1053
1054 mii = device_get_softc(sc->smc_miibus);
1055 mii_pollstat(mii);
1056 ifmr->ifm_active = mii->mii_media_active;
1057 ifmr->ifm_status = mii->mii_media_status;
1058}
1059
1060static void
1061smc_mii_tick(void *context)
1062{
1063 struct smc_softc *sc;
1064
1065 sc = (struct smc_softc *)context;
1066
1067 if (sc->smc_miibus == NULL)
1068 return;
1069
1070 mii_tick(device_get_softc(sc->smc_miibus));
1071 callout_reset(&sc->smc_mii_tick_ch, hz, smc_mii_tick, sc);
1072}
1073
1074static void
1075smc_mii_mediachg(struct smc_softc *sc)
1076{
1077
1078 if (sc->smc_miibus == NULL)
1079 return;
1080 mii_mediachg(device_get_softc(sc->smc_miibus));
1081}
1082
1083static int
1084smc_mii_mediaioctl(struct smc_softc *sc, struct ifreq *ifr, u_long command)
1085{
1086 struct mii_data *mii;
1087
1088 if (sc->smc_miibus == NULL)
1089 return (EINVAL);
1090
1091 mii = device_get_softc(sc->smc_miibus);
1092 return (ifmedia_ioctl(sc->smc_ifp, ifr, &mii->mii_media, command));
1093}
1094
1095static void
1096smc_reset(struct smc_softc *sc)
1097{
1098 u_int ctr;
1099
1100 SMC_ASSERT_LOCKED(sc);
1101
1102 smc_select_bank(sc, 2);
1103
1104 /*
1105 * Mask all interrupts.
1106 */
1107 smc_write_1(sc, MSK, 0);
1108
1109 /*
1110 * Tell the device to reset.
1111 */
1112 smc_select_bank(sc, 0);
1113 smc_write_2(sc, RCR, RCR_SOFT_RST);
1114
1115 /*
1116 * Set up the configuration register.
1117 */
1118 smc_select_bank(sc, 1);
1119 smc_write_2(sc, CR, CR_EPH_POWER_EN);
1120 DELAY(1);
1121
1122 /*
1123 * Turn off transmit and receive.
1124 */
1125 smc_select_bank(sc, 0);
1126 smc_write_2(sc, TCR, 0);
1127 smc_write_2(sc, RCR, 0);
1128
1129 /*
1130 * Set up the control register.
1131 */
1132 smc_select_bank(sc, 1);
1133 ctr = smc_read_2(sc, CTR);
1134 ctr |= CTR_LE_ENABLE | CTR_AUTO_RELEASE;
1135 smc_write_2(sc, CTR, ctr);
1136
1137 /*
1138 * Reset the MMU.
1139 */
1140 smc_select_bank(sc, 2);
1141 smc_mmu_wait(sc);
1142 smc_write_2(sc, MMUCR, MMUCR_CMD_MMU_RESET);
1143}
1144
1145static void
1146smc_enable(struct smc_softc *sc)
1147{
1148 struct ifnet *ifp;
1149
1150 SMC_ASSERT_LOCKED(sc);
1151 ifp = sc->smc_ifp;
1152
1153 /*
1154 * Set up the receive/PHY control register.
1155 */
1156 smc_select_bank(sc, 0);
1157 smc_write_2(sc, RPCR, RPCR_ANEG | (RPCR_LED_LINK_ANY << RPCR_LSA_SHIFT)
1158 | (RPCR_LED_ACT_ANY << RPCR_LSB_SHIFT));
1159
1160 /*
1161 * Set up the transmit and receive control registers.
1162 */
1163 smc_write_2(sc, TCR, TCR_TXENA | TCR_PAD_EN);
1164 smc_write_2(sc, RCR, RCR_RXEN | RCR_STRIP_CRC);
1165
1166 /*
1167 * Set up the interrupt mask.
1168 */
1169 smc_select_bank(sc, 2);
1170 sc->smc_mask = EPH_INT | RX_OVRN_INT | RCV_INT | TX_INT;
1171 if ((ifp->if_capenable & IFCAP_POLLING) != 0)
1172 smc_write_1(sc, MSK, sc->smc_mask);
1173}
1174
1175static void
1176smc_stop(struct smc_softc *sc)
1177{
1178
1179 SMC_ASSERT_LOCKED(sc);
1180
1181 /*
1182 * Turn off watchdog.
1183 */
1184 callout_stop(&sc->smc_watchdog);
1185
1186 /*
1187 * Mask all interrupts.
1188 */
1189 smc_select_bank(sc, 2);
1190 sc->smc_mask = 0;
1191 smc_write_1(sc, MSK, 0);
1192#ifdef DEVICE_POLLING
1193 ether_poll_deregister(sc->smc_ifp);
1194 sc->smc_ifp->if_capenable &= ~IFCAP_POLLING;
1195#endif
1196
1197 /*
1198 * Disable transmit and receive.
1199 */
1200 smc_select_bank(sc, 0);
1201 smc_write_2(sc, TCR, 0);
1202 smc_write_2(sc, RCR, 0);
1203
1204 sc->smc_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1205}
1206
1207static void
1208smc_watchdog(void *arg)
1209{
1210 struct ifnet *ifp;
1211
1212 ifp = (struct ifnet *)arg;
1213 if_printf(ifp, "watchdog timeout\n");
1214 smc_intr(ifp);
1215}
1216
1217static void
1218smc_init(void *context)
1219{
1220 struct smc_softc *sc;
1221
1222 sc = (struct smc_softc *)context;
1223 SMC_LOCK(sc);
1224 smc_init_locked(sc);
1225 SMC_UNLOCK(sc);
1226}
1227
1228static void
1229smc_init_locked(struct smc_softc *sc)
1230{
1231 struct ifnet *ifp;
1232
1233 ifp = sc->smc_ifp;
1234
1235 SMC_ASSERT_LOCKED(sc);
1236
1237 smc_reset(sc);
1238 smc_enable(sc);
1239
1240 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1241 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1242
1243 smc_start_locked(ifp);
1244
1245 if (sc->smc_mii_tick != NULL)
1246 callout_reset(&sc->smc_mii_tick_ch, hz, sc->smc_mii_tick, sc);
1247
1248#ifdef DEVICE_POLLING
1249 SMC_UNLOCK(sc);
1250 ether_poll_register(smc_poll, ifp);
1251 SMC_LOCK(sc);
1252 ifp->if_capenable |= IFCAP_POLLING;
1253#endif
1254}
1255
1256static int
1257smc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1258{
1259 struct smc_softc *sc;
1260 int error;
1261
1262 sc = ifp->if_softc;
1263 error = 0;
1264
1265 switch (cmd) {
1266 case SIOCSIFFLAGS:
1267 if ((ifp->if_flags & IFF_UP) == 0 &&
1268 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1269 SMC_LOCK(sc);
1270 smc_stop(sc);
1271 SMC_UNLOCK(sc);
1272 } else {
1273 smc_init(sc);
1274 if (sc->smc_mii_mediachg != NULL)
1275 sc->smc_mii_mediachg(sc);
1276 }
1277 break;
1278
1279 case SIOCADDMULTI:
1280 case SIOCDELMULTI:
1281 /* XXX
1282 SMC_LOCK(sc);
1283 smc_setmcast(sc);
1284 SMC_UNLOCK(sc);
1285 */
1286 error = EINVAL;
1287 break;
1288
1289 case SIOCGIFMEDIA:
1290 case SIOCSIFMEDIA:
1291 if (sc->smc_mii_mediaioctl == NULL) {
1292 error = EINVAL;
1293 break;
1294 }
1295 sc->smc_mii_mediaioctl(sc, (struct ifreq *)data, cmd);
1296 break;
1297
1298 default:
1299 error = ether_ioctl(ifp, cmd, data);
1300 break;
1301 }
1302
1303 return (error);
1304}
|