1/*-
| 1/*-
|
2 * Copyright (c) 1998 Nicolas Souchu
| 2 * Copyright (c) 1998, 2001 Nicolas Souchu
|
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
| 3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
|
26 * $FreeBSD: head/sys/dev/smbus/smbconf.c 59760 2000-04-29 15:36:14Z phk $
| 26 * $FreeBSD: head/sys/dev/smbus/smbconf.c 93023 2002-03-23 15:49:15Z nsouch $
|
27 *
28 */
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/module.h>
32#include <sys/bus.h>
33
34#include <dev/smbus/smbconf.h>
35#include <dev/smbus/smbus.h>
36#include "smbus_if.h"
37
38/*
39 * smbus_intr()
40 */
41void
42smbus_intr(device_t bus, u_char devaddr, char low, char high, int error)
43{
44 struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus);
45
46 /* call owner's intr routine */
47 if (sc->owner)
48 SMBUS_INTR(sc->owner, devaddr, low, high, error);
49
50 return;
51}
52
53/*
54 * smbus_error()
55 *
56 * Converts an smbus error to a unix error.
57 */
58int
59smbus_error(int smb_error)
60{
61 int error = 0;
62
63 if (smb_error == SMB_ENOERR)
64 return (0);
65
66 if (smb_error & (SMB_ENOTSUPP)) {
67 error = ENODEV;
68 } else if (smb_error & (SMB_ENOACK)) {
69 error = ENXIO;
70 } else if (smb_error & (SMB_ETIMEOUT)) {
71 error = EWOULDBLOCK;
72 } else if (smb_error & (SMB_EBUSY)) {
73 error = EBUSY;
74 } else {
75 error = EINVAL;
76 }
77
78 return (error);
79}
80
| 27 *
28 */
29#include <sys/param.h>
30#include <sys/systm.h>
31#include <sys/module.h>
32#include <sys/bus.h>
33
34#include <dev/smbus/smbconf.h>
35#include <dev/smbus/smbus.h>
36#include "smbus_if.h"
37
38/*
39 * smbus_intr()
40 */
41void
42smbus_intr(device_t bus, u_char devaddr, char low, char high, int error)
43{
44 struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus);
45
46 /* call owner's intr routine */
47 if (sc->owner)
48 SMBUS_INTR(sc->owner, devaddr, low, high, error);
49
50 return;
51}
52
53/*
54 * smbus_error()
55 *
56 * Converts an smbus error to a unix error.
57 */
58int
59smbus_error(int smb_error)
60{
61 int error = 0;
62
63 if (smb_error == SMB_ENOERR)
64 return (0);
65
66 if (smb_error & (SMB_ENOTSUPP)) {
67 error = ENODEV;
68 } else if (smb_error & (SMB_ENOACK)) {
69 error = ENXIO;
70 } else if (smb_error & (SMB_ETIMEOUT)) {
71 error = EWOULDBLOCK;
72 } else if (smb_error & (SMB_EBUSY)) {
73 error = EBUSY;
74 } else {
75 error = EINVAL;
76 }
77
78 return (error);
79}
80
|
81/*
82 * smbus_alloc_bus()
83 *
84 * Allocate a new bus connected to the given parent device
85 */
86device_t
87smbus_alloc_bus(device_t parent)
88{
89 device_t child;
90
91 /* add the bus to the parent */
92 child = device_add_child(parent, "smbus", -1);
93
94 return (child);
95}
96
| |
97static int
98smbus_poll(struct smbus_softc *sc, int how)
99{
100 int error;
101
102 switch (how) {
103 case (SMB_WAIT | SMB_INTR):
104 error = tsleep(sc, SMBPRI|PCATCH, "smbreq", 0);
105 break;
106
107 case (SMB_WAIT | SMB_NOINTR):
108 error = tsleep(sc, SMBPRI, "smbreq", 0);
109 break;
110
111 default:
112 return (EWOULDBLOCK);
113 break;
114 }
115
116 return (error);
117}
118
119/*
120 * smbus_request_bus()
121 *
122 * Allocate the device to perform transfers.
123 *
124 * how : SMB_WAIT or SMB_DONTWAIT
125 */
126int
127smbus_request_bus(device_t bus, device_t dev, int how)
128{
129 struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus);
130 int s, error = 0;
131
132 /* first, ask the underlying layers if the request is ok */
133 do {
134 error = SMBUS_CALLBACK(device_get_parent(bus),
135 SMB_REQUEST_BUS, (caddr_t)&how);
136 if (error)
137 error = smbus_poll(sc, how);
138 } while (error == EWOULDBLOCK);
139
140 while (!error) {
141 s = splhigh();
142 if (sc->owner && sc->owner != dev) {
143 splx(s);
144
145 error = smbus_poll(sc, how);
146 } else {
147 sc->owner = dev;
148
149 splx(s);
150 return (0);
151 }
152
153 /* free any allocated resource */
154 if (error)
155 SMBUS_CALLBACK(device_get_parent(bus), SMB_RELEASE_BUS,
156 (caddr_t)&how);
157 }
158
159 return (error);
160}
161
162/*
163 * smbus_release_bus()
164 *
165 * Release the device allocated with smbus_request_dev()
166 */
167int
168smbus_release_bus(device_t bus, device_t dev)
169{
170 struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus);
171 int s, error;
172
173 /* first, ask the underlying layers if the release is ok */
174 error = SMBUS_CALLBACK(device_get_parent(bus), SMB_RELEASE_BUS, NULL);
175
176 if (error)
177 return (error);
178
179 s = splhigh();
180 if (sc->owner != dev) {
181 splx(s);
182 return (EACCES);
183 }
184
185 sc->owner = 0;
186 splx(s);
187
188 /* wakeup waiting processes */
189 wakeup(sc);
190
191 return (0);
192}
| 81static int
82smbus_poll(struct smbus_softc *sc, int how)
83{
84 int error;
85
86 switch (how) {
87 case (SMB_WAIT | SMB_INTR):
88 error = tsleep(sc, SMBPRI|PCATCH, "smbreq", 0);
89 break;
90
91 case (SMB_WAIT | SMB_NOINTR):
92 error = tsleep(sc, SMBPRI, "smbreq", 0);
93 break;
94
95 default:
96 return (EWOULDBLOCK);
97 break;
98 }
99
100 return (error);
101}
102
103/*
104 * smbus_request_bus()
105 *
106 * Allocate the device to perform transfers.
107 *
108 * how : SMB_WAIT or SMB_DONTWAIT
109 */
110int
111smbus_request_bus(device_t bus, device_t dev, int how)
112{
113 struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus);
114 int s, error = 0;
115
116 /* first, ask the underlying layers if the request is ok */
117 do {
118 error = SMBUS_CALLBACK(device_get_parent(bus),
119 SMB_REQUEST_BUS, (caddr_t)&how);
120 if (error)
121 error = smbus_poll(sc, how);
122 } while (error == EWOULDBLOCK);
123
124 while (!error) {
125 s = splhigh();
126 if (sc->owner && sc->owner != dev) {
127 splx(s);
128
129 error = smbus_poll(sc, how);
130 } else {
131 sc->owner = dev;
132
133 splx(s);
134 return (0);
135 }
136
137 /* free any allocated resource */
138 if (error)
139 SMBUS_CALLBACK(device_get_parent(bus), SMB_RELEASE_BUS,
140 (caddr_t)&how);
141 }
142
143 return (error);
144}
145
146/*
147 * smbus_release_bus()
148 *
149 * Release the device allocated with smbus_request_dev()
150 */
151int
152smbus_release_bus(device_t bus, device_t dev)
153{
154 struct smbus_softc *sc = (struct smbus_softc *)device_get_softc(bus);
155 int s, error;
156
157 /* first, ask the underlying layers if the release is ok */
158 error = SMBUS_CALLBACK(device_get_parent(bus), SMB_RELEASE_BUS, NULL);
159
160 if (error)
161 return (error);
162
163 s = splhigh();
164 if (sc->owner != dev) {
165 splx(s);
166 return (EACCES);
167 }
168
169 sc->owner = 0;
170 splx(s);
171
172 /* wakeup waiting processes */
173 wakeup(sc);
174
175 return (0);
176}
|
193
194/*
195 * smbus_get_addr()
196 *
197 * Get the I2C 7 bits address of the device
198 */
199u_char
200smbus_get_addr(device_t dev)
201{
202 uintptr_t addr;
203 device_t parent = device_get_parent(dev);
204
205 BUS_READ_IVAR(parent, dev, SMBUS_IVAR_ADDR, &addr);
206
207 return ((u_char)addr);
208}
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