1/*-
2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/sfxge/common/efx_ev.c 280510 2015-03-25 10:13:19Z arybchik $");
28
29#include "efsys.h"
30#include "efx.h"
31#include "efx_types.h"
32#include "efx_regs.h"
33#include "efx_impl.h"
34
35#if EFSYS_OPT_QSTATS
36#define EFX_EV_QSTAT_INCR(_eep, _stat) \
37 do { \
38 (_eep)->ee_stat[_stat]++; \
39 _NOTE(CONSTANTCONDITION) \
40 } while (B_FALSE)
41#else
42#define EFX_EV_QSTAT_INCR(_eep, _stat)
43#endif
44
45 __checkReturn int
46efx_ev_init(
47 __in efx_nic_t *enp)
48{
49 efx_oword_t oword;
50 int rc;
51
52 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
53 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
54
55 if (enp->en_mod_flags & EFX_MOD_EV) {
56 rc = EINVAL;
57 goto fail1;
58 }
59
60 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
61
62 /*
63 * Program the event queue for receive and transmit queue
64 * flush events.
65 */
66 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
67 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
68 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
69
70 enp->en_mod_flags |= EFX_MOD_EV;
71 return (0);
72
73fail1:
74 EFSYS_PROBE1(fail1, int, rc);
75
76 return (rc);
77}
78
79static __checkReturn boolean_t
80efx_ev_rx_not_ok(
81 __in efx_evq_t *eep,
82 __in efx_qword_t *eqp,
83 __in uint32_t label,
84 __in uint32_t id,
85 __inout uint16_t *flagsp)
86{
87 boolean_t ignore = B_FALSE;
88
89 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
90 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
91 EFSYS_PROBE(tobe_disc);
92 /* Assume this is a unicast address mismatch, unless below
93 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
94 * EV_RX_PAUSE_FRM_ERR is set.
95 */
96 (*flagsp) |= EFX_ADDR_MISMATCH;
97 }
98
99 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
100 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
101 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
102 (*flagsp) |= EFX_DISCARD;
103
104#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
105 /* Lookout for payload queue ran dry errors and ignore them.
106 *
107 * Sadly for the header/data split cases, the descriptor
108 * pointer in this event refers to the header queue and
109 * therefore cannot be easily detected as duplicate.
110 * So we drop these and rely on the receive processing seeing
111 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
112 * the partially received packet.
113 */
114 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
115 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
116 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
117 ignore = B_TRUE;
118#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
119 }
120
121 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
122 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
123 EFSYS_PROBE(crc_err);
124 (*flagsp) &= ~EFX_ADDR_MISMATCH;
125 (*flagsp) |= EFX_DISCARD;
126 }
127
128 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
129 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
130 EFSYS_PROBE(pause_frm_err);
131 (*flagsp) &= ~EFX_ADDR_MISMATCH;
132 (*flagsp) |= EFX_DISCARD;
133 }
134
135 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
136 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
137 EFSYS_PROBE(owner_id_err);
138 (*flagsp) |= EFX_DISCARD;
139 }
140
141 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
142 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
143 EFSYS_PROBE(ipv4_err);
144 (*flagsp) &= ~EFX_CKSUM_IPV4;
145 }
146
147 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
148 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
149 EFSYS_PROBE(udp_chk_err);
150 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
151 }
152
153 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
154 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
155
156 /*
157 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
158 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
159 * condition.
160 */
161 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
162 }
163
164 return (ignore);
165}
166
167static __checkReturn boolean_t
168efx_ev_rx(
169 __in efx_evq_t *eep,
170 __in efx_qword_t *eqp,
171 __in const efx_ev_callbacks_t *eecp,
172 __in_opt void *arg)
173{
174 efx_nic_t *enp = eep->ee_enp;
175 uint32_t id;
176 uint32_t size;
177 uint32_t label;
178 boolean_t ok;
179#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
180 boolean_t sop;
181 boolean_t jumbo_cont;
182#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
183 uint32_t hdr_type;
184 boolean_t is_v6;
185 uint16_t flags;
186 boolean_t ignore;
187 boolean_t should_abort;
188
189 EFX_EV_QSTAT_INCR(eep, EV_RX);
190
191 /* Basic packet information */
192 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
193 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
194 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
195 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
196
197#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
198 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
199 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
200#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
201
202 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
203
204 is_v6 = (enp->en_family != EFX_FAMILY_FALCON &&
205 EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
206
207 /*
208 * If packet is marked as OK and packet type is TCP/IP or
209 * UDP/IP or other IP, then we can rely on the hardware checksums.
210 */
211 switch (hdr_type) {
212 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
213 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
214 if (is_v6) {
215 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
216 flags |= EFX_PKT_IPV6;
217 } else {
218 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
219 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
220 }
221 break;
222
223 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
224 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
225 if (is_v6) {
226 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
227 flags |= EFX_PKT_IPV6;
228 } else {
229 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
230 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
231 }
232 break;
233
234 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
235 if (is_v6) {
236 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
237 flags = EFX_PKT_IPV6;
238 } else {
239 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
240 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
241 }
242 break;
243
244 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
245 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
246 flags = 0;
247 break;
248
249 default:
250 EFSYS_ASSERT(B_FALSE);
251 flags = 0;
252 break;
253 }
254
255#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT
256 /* Report scatter and header/lookahead split buffer flags */
257 if (sop)
258 flags |= EFX_PKT_START;
259 if (jumbo_cont)
260 flags |= EFX_PKT_CONT;
261#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */
262
263 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
264 if (!ok) {
265 ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags);
266 if (ignore) {
267 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
268 uint32_t, size, uint16_t, flags);
269
270 return (B_FALSE);
271 }
272 }
273
274 /* If we're not discarding the packet then it is ok */
275 if (~flags & EFX_DISCARD)
276 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
277
278 /* Detect multicast packets that didn't match the filter */
279 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
280 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
281
282 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
283 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
284 } else {
285 EFSYS_PROBE(mcast_mismatch);
286 flags |= EFX_ADDR_MISMATCH;
287 }
288 } else {
289 flags |= EFX_PKT_UNICAST;
290 }
291
292 /*
293 * The packet parser in Siena can abort parsing packets under
294 * certain error conditions, setting the PKT_NOT_PARSED bit
295 * (which clears PKT_OK). If this is set, then don't trust
296 * the PKT_TYPE field.
297 */
298 if (enp->en_family != EFX_FAMILY_FALCON && !ok) {
299 uint32_t parse_err;
300
301 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
302 if (parse_err != 0)
303 flags |= EFX_CHECK_VLAN;
304 }
305
306 if (~flags & EFX_CHECK_VLAN) {
307 uint32_t pkt_type;
308
309 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
310 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
311 flags |= EFX_PKT_VLAN_TAGGED;
312 }
313
314 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
315 uint32_t, size, uint16_t, flags);
316
317 EFSYS_ASSERT(eecp->eec_rx != NULL);
318 should_abort = eecp->eec_rx(arg, label, id, size, flags);
319
320 return (should_abort);
321}
322
323static __checkReturn boolean_t
324efx_ev_tx(
325 __in efx_evq_t *eep,
326 __in efx_qword_t *eqp,
327 __in const efx_ev_callbacks_t *eecp,
328 __in_opt void *arg)
329{
330 uint32_t id;
331 uint32_t label;
332 boolean_t should_abort;
333
334 EFX_EV_QSTAT_INCR(eep, EV_TX);
335
336 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
337 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
338 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
339 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
340
341 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
342 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
343
344 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
345
346 EFSYS_ASSERT(eecp->eec_tx != NULL);
347 should_abort = eecp->eec_tx(arg, label, id);
348
349 return (should_abort);
350 }
351
352 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
353 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
354 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
355 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
356
357 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
358 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
359
360 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
361 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
362
363 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
364 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
365
366 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
367 return (B_FALSE);
368}
369
370static __checkReturn boolean_t
371efx_ev_global(
372 __in efx_evq_t *eep,
373 __in efx_qword_t *eqp,
374 __in const efx_ev_callbacks_t *eecp,
375 __in_opt void *arg)
376{
377 efx_nic_t *enp = eep->ee_enp;
378 efx_port_t *epp = &(enp->en_port);
379 boolean_t should_abort;
380
381 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
382 should_abort = B_FALSE;
383
384 /* Check for a link management event */
385 if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) {
386 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT);
387
388 EFSYS_PROBE(xg_mgt);
389
390 epp->ep_mac_poll_needed = B_TRUE;
391 }
392
393 return (should_abort);
394}
395
396static __checkReturn boolean_t
397efx_ev_driver(
398 __in efx_evq_t *eep,
399 __in efx_qword_t *eqp,
400 __in const efx_ev_callbacks_t *eecp,
401 __in_opt void *arg)
402{
403 boolean_t should_abort;
404
405 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
406 should_abort = B_FALSE;
407
408 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
409 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
410 uint32_t txq_index;
411
412 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
413
414 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
415
416 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
417
418 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
419 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
420
421 break;
422 }
423 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
424 uint32_t rxq_index;
425 uint32_t failed;
426
427 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
428 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
429
430 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
431 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
432
433 if (failed) {
434 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
435
436 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
437
438 should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index);
439 } else {
440 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
441
442 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
443
444 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
445 }
446
447 break;
448 }
449 case FSE_AZ_EVQ_INIT_DONE_EV:
450 EFSYS_ASSERT(eecp->eec_initialized != NULL);
451 should_abort = eecp->eec_initialized(arg);
452
453 break;
454
455 case FSE_AZ_EVQ_NOT_EN_EV:
456 EFSYS_PROBE(evq_not_en);
457 break;
458
459 case FSE_AZ_SRM_UPD_DONE_EV: {
460 uint32_t code;
461
462 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
463
464 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
465
466 EFSYS_ASSERT(eecp->eec_sram != NULL);
467 should_abort = eecp->eec_sram(arg, code);
468
469 break;
470 }
471 case FSE_AZ_WAKE_UP_EV: {
472 uint32_t id;
473
474 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
475
476 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
477 should_abort = eecp->eec_wake_up(arg, id);
478
479 break;
480 }
481 case FSE_AZ_TX_PKT_NON_TCP_UDP:
482 EFSYS_PROBE(tx_pkt_non_tcp_udp);
483 break;
484
485 case FSE_AZ_TIMER_EV: {
486 uint32_t id;
487
488 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
489
490 EFSYS_ASSERT(eecp->eec_timer != NULL);
491 should_abort = eecp->eec_timer(arg, id);
492
493 break;
494 }
495 case FSE_AZ_RX_DSC_ERROR_EV:
496 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
497
498 EFSYS_PROBE(rx_dsc_error);
499
500 EFSYS_ASSERT(eecp->eec_exception != NULL);
501 should_abort = eecp->eec_exception(arg,
502 EFX_EXCEPTION_RX_DSC_ERROR, 0);
503
504 break;
505
506 case FSE_AZ_TX_DSC_ERROR_EV:
507 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
508
509 EFSYS_PROBE(tx_dsc_error);
510
511 EFSYS_ASSERT(eecp->eec_exception != NULL);
512 should_abort = eecp->eec_exception(arg,
513 EFX_EXCEPTION_TX_DSC_ERROR, 0);
514
515 break;
516
517 default:
518 break;
519 }
520
521 return (should_abort);
522}
523
524static __checkReturn boolean_t
525efx_ev_drv_gen(
526 __in efx_evq_t *eep,
527 __in efx_qword_t *eqp,
528 __in const efx_ev_callbacks_t *eecp,
529 __in_opt void *arg)
530{
531 uint32_t data;
532 boolean_t should_abort;
533
534 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
535
536 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
537 if (data >= ((uint32_t)1 << 16)) {
538 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
539 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
540 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
541 return (B_TRUE);
542 }
543
544 EFSYS_ASSERT(eecp->eec_software != NULL);
545 should_abort = eecp->eec_software(arg, (uint16_t)data);
546
547 return (should_abort);
548}
549
550#if EFSYS_OPT_MCDI
551
552static __checkReturn boolean_t
553efx_ev_mcdi(
554 __in efx_evq_t *eep,
555 __in efx_qword_t *eqp,
556 __in const efx_ev_callbacks_t *eecp,
557 __in_opt void *arg)
558{
559 efx_nic_t *enp = eep->ee_enp;
560 unsigned code;
561 boolean_t should_abort = B_FALSE;
562
563 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
564
565 if (enp->en_family != EFX_FAMILY_SIENA)
566 goto out;
567
568 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
569
570 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
571 switch (code) {
572 case MCDI_EVENT_CODE_BADSSERT:
573 efx_mcdi_ev_death(enp, EINTR);
574 break;
575
576 case MCDI_EVENT_CODE_CMDDONE:
577 efx_mcdi_ev_cpl(enp,
578 MCDI_EV_FIELD(*eqp, CMDDONE_SEQ),
579 MCDI_EV_FIELD(*eqp, CMDDONE_DATALEN),
580 MCDI_EV_FIELD(*eqp, CMDDONE_ERRNO));
581 break;
582
583 case MCDI_EVENT_CODE_LINKCHANGE: {
584 efx_link_mode_t link_mode;
585
586 siena_phy_link_ev(enp, eqp, &link_mode);
587 should_abort = eecp->eec_link_change(arg, link_mode);
588 break;
589 }
590 case MCDI_EVENT_CODE_SENSOREVT: {
591#if EFSYS_OPT_MON_STATS
592 efx_mon_stat_t id;
593 efx_mon_stat_value_t value;
594 int rc;
595
596 if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0)
597 should_abort = eecp->eec_monitor(arg, id, value);
598 else if (rc == ENOTSUP) {
599 should_abort = eecp->eec_exception(arg,
600 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
601 MCDI_EV_FIELD(eqp, DATA));
602 } else
603 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
604#else
605 should_abort = B_FALSE;
606#endif
607 break;
608 }
609 case MCDI_EVENT_CODE_SCHEDERR:
610 /* Informational only */
611 break;
612
613 case MCDI_EVENT_CODE_REBOOT:
614 efx_mcdi_ev_death(enp, EIO);
615 break;
616
617 case MCDI_EVENT_CODE_MAC_STATS_DMA:
618#if EFSYS_OPT_MAC_STATS
619 if (eecp->eec_mac_stats != NULL) {
620 eecp->eec_mac_stats(arg,
621 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
622 }
623#endif
624 break;
625
626 case MCDI_EVENT_CODE_FWALERT: {
627 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
628
629 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
630 should_abort = eecp->eec_exception(arg,
631 EFX_EXCEPTION_FWALERT_SRAM,
632 MCDI_EV_FIELD(eqp, FWALERT_DATA));
633 else
634 should_abort = eecp->eec_exception(arg,
635 EFX_EXCEPTION_UNKNOWN_FWALERT,
636 MCDI_EV_FIELD(eqp, DATA));
637 break;
638 }
639
640 default:
641 EFSYS_PROBE1(mc_pcol_error, int, code);
642 break;
643 }
644
645out:
646 return (should_abort);
647}
648
649#endif /* EFSYS_OPT_SIENA */
650
651 __checkReturn int
652efx_ev_qprime(
653 __in efx_evq_t *eep,
654 __in unsigned int count)
655{
656 efx_nic_t *enp = eep->ee_enp;
657 uint32_t rptr;
658 efx_dword_t dword;
659 int rc;
660
661 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
662
663 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
664 rc = EINVAL;
665 goto fail1;
666 }
667
668 rptr = count & eep->ee_mask;
669
670 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
671
672 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
673 &dword, B_FALSE);
674
675 return (0);
676
677fail1:
678 EFSYS_PROBE1(fail1, int, rc);
679
680 return (rc);
681}
682
683 __checkReturn boolean_t
684efx_ev_qpending(
685 __in efx_evq_t *eep,
686 __in unsigned int count)
687{
688 size_t offset;
689 efx_qword_t qword;
690
691 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
692
693 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
694 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
695
696 return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff &&
697 EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff);
698}
699
700#if EFSYS_OPT_EV_PREFETCH
701
702 void
703efx_ev_qprefetch(
704 __in efx_evq_t *eep,
705 __in unsigned int count)
706{
707 unsigned int offset;
708
709 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
710
711 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
712 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
713}
714
715#endif /* EFSYS_OPT_EV_PREFETCH */
716
717#define EFX_EV_BATCH 8
718
719#define EFX_EV_PRESENT(_qword) \
720 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
721 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
722
723 void
724efx_ev_qpoll(
725 __in efx_evq_t *eep,
726 __inout unsigned int *countp,
727 __in const efx_ev_callbacks_t *eecp,
728 __in_opt void *arg)
729{
730 efx_qword_t ev[EFX_EV_BATCH];
731 unsigned int batch;
732 unsigned int total;
733 unsigned int count;
734 unsigned int index;
735 size_t offset;
736
737 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
738 EFSYS_ASSERT(countp != NULL);
739 EFSYS_ASSERT(eecp != NULL);
740
741 count = *countp;
742 do {
743 /* Read up until the end of the batch period */
744 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
745 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
746 for (total = 0; total < batch; ++total) {
747 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
748
749 if (!EFX_EV_PRESENT(ev[total]))
750 break;
751
752 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
753 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
754 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
755
756 offset += sizeof (efx_qword_t);
757 }
758
759#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
760 /*
761 * Prefetch the next batch when we get within PREFETCH_PERIOD
762 * of a completed batch. If the batch is smaller, then prefetch
763 * immediately.
764 */
765 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
766 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
767#endif /* EFSYS_OPT_EV_PREFETCH */
768
769 /* Process the batch of events */
770 for (index = 0; index < total; ++index) {
771 boolean_t should_abort;
772 uint32_t code;
773 efx_ev_handler_t handler;
774
775#if EFSYS_OPT_EV_PREFETCH
776 /* Prefetch if we've now reached the batch period */
777 if (total == batch &&
778 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
779 offset = (count + batch) & eep->ee_mask;
780 offset *= sizeof (efx_qword_t);
781
782 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
783 }
784#endif /* EFSYS_OPT_EV_PREFETCH */
785
786 EFX_EV_QSTAT_INCR(eep, EV_ALL);
787
788 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
789 handler = eep->ee_handler[code];
790 EFSYS_ASSERT(handler != NULL);
791 should_abort = handler(eep, &(ev[index]), eecp, arg);
792 if (should_abort) {
793 /* Ignore subsequent events */
794 total = index + 1;
795 break;
796 }
797 }
798
799 /*
800 * Now that the hardware has most likely moved onto dma'ing
801 * into the next cache line, clear the processed events. Take
802 * care to only clear out events that we've processed
803 */
804 EFX_SET_QWORD(ev[0]);
805 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
806 for (index = 0; index < total; ++index) {
807 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
808 offset += sizeof (efx_qword_t);
809 }
810
811 count += total;
812
813 } while (total == batch);
814
815 *countp = count;
816}
817
818 void
819efx_ev_qpost(
820 __in efx_evq_t *eep,
821 __in uint16_t data)
822{
823 efx_nic_t *enp = eep->ee_enp;
824 efx_qword_t ev;
825 efx_oword_t oword;
826
827 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
828
829 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
830 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
831
832 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
833 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
834 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
835
836 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
837}
838
839 __checkReturn int
840efx_ev_qmoderate(
841 __in efx_evq_t *eep,
842 __in unsigned int us)
843{
844 efx_nic_t *enp = eep->ee_enp;
845 unsigned int locked;
846 efx_dword_t dword;
847 int rc;
848
849 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
850
851 if (us > enp->en_nic_cfg.enc_evq_moderation_max) {
852 rc = EINVAL;
853 goto fail1;
854 }
855
856 /* If the value is zero then disable the timer */
857 if (us == 0) {
858 if (enp->en_family == EFX_FAMILY_FALCON)
859 EFX_POPULATE_DWORD_2(dword,
860 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS,
861 FRF_AB_TC_TIMER_VAL, 0);
862 else
863 EFX_POPULATE_DWORD_2(dword,
864 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
865 FRF_CZ_TC_TIMER_VAL, 0);
866 } else {
867 uint32_t timer_val;
868
869 /* Calculate the timer value in quanta */
870 us -= (us % EFX_EV_TIMER_QUANTUM);
871 if (us < EFX_EV_TIMER_QUANTUM)
872 us = EFX_EV_TIMER_QUANTUM;
873
874 timer_val = us / EFX_EV_TIMER_QUANTUM;
875
876 /* Moderation value is base 0 so we need to deduct 1 */
877 if (enp->en_family == EFX_FAMILY_FALCON)
878 EFX_POPULATE_DWORD_2(dword,
879 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF,
880 FRF_AB_TIMER_VAL, timer_val - 1);
881 else
882 EFX_POPULATE_DWORD_2(dword,
883 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
884 FRF_CZ_TC_TIMER_VAL, timer_val - 1);
885 }
886
887 locked = (eep->ee_index == 0) ? 1 : 0;
888
889 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
890 eep->ee_index, &dword, locked);
891
892 return (0);
893
894fail1:
895 EFSYS_PROBE1(fail1, int, rc);
896
897 return (rc);
898}
899
900 __checkReturn int
901efx_ev_qcreate(
902 __in efx_nic_t *enp,
903 __in unsigned int index,
904 __in efsys_mem_t *esmp,
905 __in size_t n,
906 __in uint32_t id,
907 __deref_out efx_evq_t **eepp)
908{
909 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
910 uint32_t size;
911 efx_evq_t *eep;
912 efx_oword_t oword;
913 int rc;
914
915 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
916 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
917
918 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
919
920 if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) {
921 rc = EINVAL;
922 goto fail1;
923 }
924 if (index >= encp->enc_evq_limit) {
925 rc = EINVAL;
926 goto fail2;
927 }
928#if EFSYS_OPT_RX_SCALE
929 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
930 index >= EFX_MAXRSS_LEGACY) {
931 rc = EINVAL;
932 goto fail3;
933 }
934#endif
935 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
936 size++)
937 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
938 break;
939 if (id + (1 << size) >= encp->enc_buftbl_limit) {
940 rc = EINVAL;
941 goto fail4;
942 }
943
944 /* Allocate an EVQ object */
945 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
946 if (eep == NULL) {
947 rc = ENOMEM;
948 goto fail5;
949 }
950
951 eep->ee_magic = EFX_EVQ_MAGIC;
952 eep->ee_enp = enp;
953 eep->ee_index = index;
954 eep->ee_mask = n - 1;
955 eep->ee_esmp = esmp;
956
957 /* Set up the handler table */
958 eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx;
959 eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx;
960 eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver;
961 eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global;
962 eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen;
963#if EFSYS_OPT_MCDI
964 eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi;
965#endif /* EFSYS_OPT_SIENA */
966
967 /* Set up the new event queue */
968 if (enp->en_family != EFX_FAMILY_FALCON) {
969 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
970 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword);
971 }
972
973 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
974 FRF_AZ_EVQ_BUF_BASE_ID, id);
975
976 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword);
977
978 enp->en_ev_qcount++;
979 *eepp = eep;
980 return (0);
981
982fail5:
983 EFSYS_PROBE(fail5);
984fail4:
985 EFSYS_PROBE(fail4);
986#if EFSYS_OPT_RX_SCALE
987fail3:
988 EFSYS_PROBE(fail3);
989#endif
990fail2:
991 EFSYS_PROBE(fail2);
992fail1:
993 EFSYS_PROBE1(fail1, int, rc);
994
995 return (rc);
996}
997
998#if EFSYS_OPT_QSTATS
999#if EFSYS_OPT_NAMES
1000/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */
1001static const char __cs * __cs __efx_ev_qstat_name[] = {
1002 "all",
1003 "rx",
1004 "rx_ok",
1005 "rx_recovery",
1006 "rx_frm_trunc",
1007 "rx_tobe_disc",
1008 "rx_pause_frm_err",
1009 "rx_buf_owner_id_err",
1010 "rx_ipv4_hdr_chksum_err",
1011 "rx_tcp_udp_chksum_err",
1012 "rx_eth_crc_err",
1013 "rx_ip_frag_err",
1014 "rx_mcast_pkt",
1015 "rx_mcast_hash_match",
1016 "rx_tcp_ipv4",
1017 "rx_tcp_ipv6",
1018 "rx_udp_ipv4",
1019 "rx_udp_ipv6",
1020 "rx_other_ipv4",
1021 "rx_other_ipv6",
1022 "rx_non_ip",
1023 "rx_overrun",
1024 "tx",
1025 "tx_wq_ff_full",
1026 "tx_pkt_err",
1027 "tx_pkt_too_big",
1028 "tx_unexpected",
1029 "global",
1030 "global_phy",
1031 "global_mnt",
1032 "global_rx_recovery",
1033 "driver",
1034 "driver_srm_upd_done",
1035 "driver_tx_descq_fls_done",
1036 "driver_rx_descq_fls_done",
1037 "driver_rx_descq_fls_failed",
1038 "driver_rx_dsc_error",
1039 "driver_tx_dsc_error",
1040 "drv_gen",
1041 "mcdi_response",
1042};
1043/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1044
1045 const char __cs *
1046efx_ev_qstat_name(
1047 __in efx_nic_t *enp,
1048 __in unsigned int id)
1049{
1050 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1051 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1052
1053 return (__efx_ev_qstat_name[id]);
1054}
1055#endif /* EFSYS_OPT_NAMES */
1056#endif /* EFSYS_OPT_QSTATS */
1057
1058#if EFSYS_OPT_QSTATS
1059 void
1060efx_ev_qstats_update(
1061 __in efx_evq_t *eep,
1062 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1063{
1064 unsigned int id;
1065
1066 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1067
1068 for (id = 0; id < EV_NQSTATS; id++) {
1069 efsys_stat_t *essp = &stat[id];
1070
1071 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1072 eep->ee_stat[id] = 0;
1073 }
1074}
1075#endif /* EFSYS_OPT_QSTATS */
1076
1077 void
1078efx_ev_qdestroy(
1079 __in efx_evq_t *eep)
1080{
1081 efx_nic_t *enp = eep->ee_enp;
1082 efx_oword_t oword;
1083
1084 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1085
1086 EFSYS_ASSERT(enp->en_ev_qcount != 0);
1087 --enp->en_ev_qcount;
1088
1089 /* Purge event queue */
1090 EFX_ZERO_OWORD(oword);
1091
1092 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1093 eep->ee_index, &oword);
1094
1095 if (enp->en_family != EFX_FAMILY_FALCON) {
1096 EFX_ZERO_OWORD(oword);
1097 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL,
1098 eep->ee_index, &oword);
1099 }
1100
1101 /* Free the EVQ object */
1102 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
1103}
1104
1105 void
1106efx_ev_fini(
1107 __in efx_nic_t *enp)
1108{
1109 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1110 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
1111 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
1112 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
1113 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
1114 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
1115
1116 enp->en_mod_flags &= ~EFX_MOD_EV;
1117}
2 * Copyright 2007-2009 Solarflare Communications Inc. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26#include <sys/cdefs.h>
27__FBSDID("$FreeBSD: stable/10/sys/dev/sfxge/common/efx_ev.c 280510 2015-03-25 10:13:19Z arybchik $");
28
29#include "efsys.h"
30#include "efx.h"
31#include "efx_types.h"
32#include "efx_regs.h"
33#include "efx_impl.h"
34
35#if EFSYS_OPT_QSTATS
36#define EFX_EV_QSTAT_INCR(_eep, _stat) \
37 do { \
38 (_eep)->ee_stat[_stat]++; \
39 _NOTE(CONSTANTCONDITION) \
40 } while (B_FALSE)
41#else
42#define EFX_EV_QSTAT_INCR(_eep, _stat)
43#endif
44
45 __checkReturn int
46efx_ev_init(
47 __in efx_nic_t *enp)
48{
49 efx_oword_t oword;
50 int rc;
51
52 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
53 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
54
55 if (enp->en_mod_flags & EFX_MOD_EV) {
56 rc = EINVAL;
57 goto fail1;
58 }
59
60 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
61
62 /*
63 * Program the event queue for receive and transmit queue
64 * flush events.
65 */
66 EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
67 EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
68 EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
69
70 enp->en_mod_flags |= EFX_MOD_EV;
71 return (0);
72
73fail1:
74 EFSYS_PROBE1(fail1, int, rc);
75
76 return (rc);
77}
78
79static __checkReturn boolean_t
80efx_ev_rx_not_ok(
81 __in efx_evq_t *eep,
82 __in efx_qword_t *eqp,
83 __in uint32_t label,
84 __in uint32_t id,
85 __inout uint16_t *flagsp)
86{
87 boolean_t ignore = B_FALSE;
88
89 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
90 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
91 EFSYS_PROBE(tobe_disc);
92 /* Assume this is a unicast address mismatch, unless below
93 * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
94 * EV_RX_PAUSE_FRM_ERR is set.
95 */
96 (*flagsp) |= EFX_ADDR_MISMATCH;
97 }
98
99 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
100 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
101 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
102 (*flagsp) |= EFX_DISCARD;
103
104#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
105 /* Lookout for payload queue ran dry errors and ignore them.
106 *
107 * Sadly for the header/data split cases, the descriptor
108 * pointer in this event refers to the header queue and
109 * therefore cannot be easily detected as duplicate.
110 * So we drop these and rely on the receive processing seeing
111 * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
112 * the partially received packet.
113 */
114 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
115 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
116 (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
117 ignore = B_TRUE;
118#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
119 }
120
121 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
122 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
123 EFSYS_PROBE(crc_err);
124 (*flagsp) &= ~EFX_ADDR_MISMATCH;
125 (*flagsp) |= EFX_DISCARD;
126 }
127
128 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
129 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
130 EFSYS_PROBE(pause_frm_err);
131 (*flagsp) &= ~EFX_ADDR_MISMATCH;
132 (*flagsp) |= EFX_DISCARD;
133 }
134
135 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
136 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
137 EFSYS_PROBE(owner_id_err);
138 (*flagsp) |= EFX_DISCARD;
139 }
140
141 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
142 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
143 EFSYS_PROBE(ipv4_err);
144 (*flagsp) &= ~EFX_CKSUM_IPV4;
145 }
146
147 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
148 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
149 EFSYS_PROBE(udp_chk_err);
150 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
151 }
152
153 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
154 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
155
156 /*
157 * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
158 * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
159 * condition.
160 */
161 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
162 }
163
164 return (ignore);
165}
166
167static __checkReturn boolean_t
168efx_ev_rx(
169 __in efx_evq_t *eep,
170 __in efx_qword_t *eqp,
171 __in const efx_ev_callbacks_t *eecp,
172 __in_opt void *arg)
173{
174 efx_nic_t *enp = eep->ee_enp;
175 uint32_t id;
176 uint32_t size;
177 uint32_t label;
178 boolean_t ok;
179#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
180 boolean_t sop;
181 boolean_t jumbo_cont;
182#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
183 uint32_t hdr_type;
184 boolean_t is_v6;
185 uint16_t flags;
186 boolean_t ignore;
187 boolean_t should_abort;
188
189 EFX_EV_QSTAT_INCR(eep, EV_RX);
190
191 /* Basic packet information */
192 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
193 size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
194 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
195 ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
196
197#if (EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER)
198 sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
199 jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
200#endif /* EFSYS_OPT_RX_HDR_SPLIT || EFSYS_OPT_RX_SCATTER */
201
202 hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
203
204 is_v6 = (enp->en_family != EFX_FAMILY_FALCON &&
205 EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
206
207 /*
208 * If packet is marked as OK and packet type is TCP/IP or
209 * UDP/IP or other IP, then we can rely on the hardware checksums.
210 */
211 switch (hdr_type) {
212 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
213 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
214 if (is_v6) {
215 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
216 flags |= EFX_PKT_IPV6;
217 } else {
218 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
219 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
220 }
221 break;
222
223 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
224 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
225 if (is_v6) {
226 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
227 flags |= EFX_PKT_IPV6;
228 } else {
229 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
230 flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
231 }
232 break;
233
234 case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
235 if (is_v6) {
236 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
237 flags = EFX_PKT_IPV6;
238 } else {
239 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
240 flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
241 }
242 break;
243
244 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
245 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
246 flags = 0;
247 break;
248
249 default:
250 EFSYS_ASSERT(B_FALSE);
251 flags = 0;
252 break;
253 }
254
255#if EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT
256 /* Report scatter and header/lookahead split buffer flags */
257 if (sop)
258 flags |= EFX_PKT_START;
259 if (jumbo_cont)
260 flags |= EFX_PKT_CONT;
261#endif /* EFSYS_OPT_RX_SCATTER || EFSYS_OPT_RX_HDR_SPLIT */
262
263 /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
264 if (!ok) {
265 ignore = efx_ev_rx_not_ok(eep, eqp, label, id, &flags);
266 if (ignore) {
267 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
268 uint32_t, size, uint16_t, flags);
269
270 return (B_FALSE);
271 }
272 }
273
274 /* If we're not discarding the packet then it is ok */
275 if (~flags & EFX_DISCARD)
276 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
277
278 /* Detect multicast packets that didn't match the filter */
279 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
280 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
281
282 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
283 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
284 } else {
285 EFSYS_PROBE(mcast_mismatch);
286 flags |= EFX_ADDR_MISMATCH;
287 }
288 } else {
289 flags |= EFX_PKT_UNICAST;
290 }
291
292 /*
293 * The packet parser in Siena can abort parsing packets under
294 * certain error conditions, setting the PKT_NOT_PARSED bit
295 * (which clears PKT_OK). If this is set, then don't trust
296 * the PKT_TYPE field.
297 */
298 if (enp->en_family != EFX_FAMILY_FALCON && !ok) {
299 uint32_t parse_err;
300
301 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
302 if (parse_err != 0)
303 flags |= EFX_CHECK_VLAN;
304 }
305
306 if (~flags & EFX_CHECK_VLAN) {
307 uint32_t pkt_type;
308
309 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
310 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
311 flags |= EFX_PKT_VLAN_TAGGED;
312 }
313
314 EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
315 uint32_t, size, uint16_t, flags);
316
317 EFSYS_ASSERT(eecp->eec_rx != NULL);
318 should_abort = eecp->eec_rx(arg, label, id, size, flags);
319
320 return (should_abort);
321}
322
323static __checkReturn boolean_t
324efx_ev_tx(
325 __in efx_evq_t *eep,
326 __in efx_qword_t *eqp,
327 __in const efx_ev_callbacks_t *eecp,
328 __in_opt void *arg)
329{
330 uint32_t id;
331 uint32_t label;
332 boolean_t should_abort;
333
334 EFX_EV_QSTAT_INCR(eep, EV_TX);
335
336 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
337 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
338 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
339 EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
340
341 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
342 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
343
344 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
345
346 EFSYS_ASSERT(eecp->eec_tx != NULL);
347 should_abort = eecp->eec_tx(arg, label, id);
348
349 return (should_abort);
350 }
351
352 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
353 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
354 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
355 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
356
357 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
358 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
359
360 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
361 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
362
363 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
364 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
365
366 EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
367 return (B_FALSE);
368}
369
370static __checkReturn boolean_t
371efx_ev_global(
372 __in efx_evq_t *eep,
373 __in efx_qword_t *eqp,
374 __in const efx_ev_callbacks_t *eecp,
375 __in_opt void *arg)
376{
377 efx_nic_t *enp = eep->ee_enp;
378 efx_port_t *epp = &(enp->en_port);
379 boolean_t should_abort;
380
381 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
382 should_abort = B_FALSE;
383
384 /* Check for a link management event */
385 if (EFX_QWORD_FIELD(*eqp, FSF_BZ_GLB_EV_XG_MNT_INTR) != 0) {
386 EFX_EV_QSTAT_INCR(eep, EV_GLOBAL_MNT);
387
388 EFSYS_PROBE(xg_mgt);
389
390 epp->ep_mac_poll_needed = B_TRUE;
391 }
392
393 return (should_abort);
394}
395
396static __checkReturn boolean_t
397efx_ev_driver(
398 __in efx_evq_t *eep,
399 __in efx_qword_t *eqp,
400 __in const efx_ev_callbacks_t *eecp,
401 __in_opt void *arg)
402{
403 boolean_t should_abort;
404
405 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
406 should_abort = B_FALSE;
407
408 switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
409 case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
410 uint32_t txq_index;
411
412 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
413
414 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
415
416 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
417
418 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
419 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
420
421 break;
422 }
423 case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
424 uint32_t rxq_index;
425 uint32_t failed;
426
427 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
428 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
429
430 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
431 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
432
433 if (failed) {
434 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
435
436 EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
437
438 should_abort = eecp->eec_rxq_flush_failed(arg, rxq_index);
439 } else {
440 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
441
442 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
443
444 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
445 }
446
447 break;
448 }
449 case FSE_AZ_EVQ_INIT_DONE_EV:
450 EFSYS_ASSERT(eecp->eec_initialized != NULL);
451 should_abort = eecp->eec_initialized(arg);
452
453 break;
454
455 case FSE_AZ_EVQ_NOT_EN_EV:
456 EFSYS_PROBE(evq_not_en);
457 break;
458
459 case FSE_AZ_SRM_UPD_DONE_EV: {
460 uint32_t code;
461
462 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
463
464 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
465
466 EFSYS_ASSERT(eecp->eec_sram != NULL);
467 should_abort = eecp->eec_sram(arg, code);
468
469 break;
470 }
471 case FSE_AZ_WAKE_UP_EV: {
472 uint32_t id;
473
474 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
475
476 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
477 should_abort = eecp->eec_wake_up(arg, id);
478
479 break;
480 }
481 case FSE_AZ_TX_PKT_NON_TCP_UDP:
482 EFSYS_PROBE(tx_pkt_non_tcp_udp);
483 break;
484
485 case FSE_AZ_TIMER_EV: {
486 uint32_t id;
487
488 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
489
490 EFSYS_ASSERT(eecp->eec_timer != NULL);
491 should_abort = eecp->eec_timer(arg, id);
492
493 break;
494 }
495 case FSE_AZ_RX_DSC_ERROR_EV:
496 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
497
498 EFSYS_PROBE(rx_dsc_error);
499
500 EFSYS_ASSERT(eecp->eec_exception != NULL);
501 should_abort = eecp->eec_exception(arg,
502 EFX_EXCEPTION_RX_DSC_ERROR, 0);
503
504 break;
505
506 case FSE_AZ_TX_DSC_ERROR_EV:
507 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
508
509 EFSYS_PROBE(tx_dsc_error);
510
511 EFSYS_ASSERT(eecp->eec_exception != NULL);
512 should_abort = eecp->eec_exception(arg,
513 EFX_EXCEPTION_TX_DSC_ERROR, 0);
514
515 break;
516
517 default:
518 break;
519 }
520
521 return (should_abort);
522}
523
524static __checkReturn boolean_t
525efx_ev_drv_gen(
526 __in efx_evq_t *eep,
527 __in efx_qword_t *eqp,
528 __in const efx_ev_callbacks_t *eecp,
529 __in_opt void *arg)
530{
531 uint32_t data;
532 boolean_t should_abort;
533
534 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
535
536 data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
537 if (data >= ((uint32_t)1 << 16)) {
538 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
539 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
540 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
541 return (B_TRUE);
542 }
543
544 EFSYS_ASSERT(eecp->eec_software != NULL);
545 should_abort = eecp->eec_software(arg, (uint16_t)data);
546
547 return (should_abort);
548}
549
550#if EFSYS_OPT_MCDI
551
552static __checkReturn boolean_t
553efx_ev_mcdi(
554 __in efx_evq_t *eep,
555 __in efx_qword_t *eqp,
556 __in const efx_ev_callbacks_t *eecp,
557 __in_opt void *arg)
558{
559 efx_nic_t *enp = eep->ee_enp;
560 unsigned code;
561 boolean_t should_abort = B_FALSE;
562
563 EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
564
565 if (enp->en_family != EFX_FAMILY_SIENA)
566 goto out;
567
568 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
569
570 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
571 switch (code) {
572 case MCDI_EVENT_CODE_BADSSERT:
573 efx_mcdi_ev_death(enp, EINTR);
574 break;
575
576 case MCDI_EVENT_CODE_CMDDONE:
577 efx_mcdi_ev_cpl(enp,
578 MCDI_EV_FIELD(*eqp, CMDDONE_SEQ),
579 MCDI_EV_FIELD(*eqp, CMDDONE_DATALEN),
580 MCDI_EV_FIELD(*eqp, CMDDONE_ERRNO));
581 break;
582
583 case MCDI_EVENT_CODE_LINKCHANGE: {
584 efx_link_mode_t link_mode;
585
586 siena_phy_link_ev(enp, eqp, &link_mode);
587 should_abort = eecp->eec_link_change(arg, link_mode);
588 break;
589 }
590 case MCDI_EVENT_CODE_SENSOREVT: {
591#if EFSYS_OPT_MON_STATS
592 efx_mon_stat_t id;
593 efx_mon_stat_value_t value;
594 int rc;
595
596 if ((rc = siena_mon_ev(enp, eqp, &id, &value)) == 0)
597 should_abort = eecp->eec_monitor(arg, id, value);
598 else if (rc == ENOTSUP) {
599 should_abort = eecp->eec_exception(arg,
600 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
601 MCDI_EV_FIELD(eqp, DATA));
602 } else
603 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
604#else
605 should_abort = B_FALSE;
606#endif
607 break;
608 }
609 case MCDI_EVENT_CODE_SCHEDERR:
610 /* Informational only */
611 break;
612
613 case MCDI_EVENT_CODE_REBOOT:
614 efx_mcdi_ev_death(enp, EIO);
615 break;
616
617 case MCDI_EVENT_CODE_MAC_STATS_DMA:
618#if EFSYS_OPT_MAC_STATS
619 if (eecp->eec_mac_stats != NULL) {
620 eecp->eec_mac_stats(arg,
621 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
622 }
623#endif
624 break;
625
626 case MCDI_EVENT_CODE_FWALERT: {
627 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
628
629 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
630 should_abort = eecp->eec_exception(arg,
631 EFX_EXCEPTION_FWALERT_SRAM,
632 MCDI_EV_FIELD(eqp, FWALERT_DATA));
633 else
634 should_abort = eecp->eec_exception(arg,
635 EFX_EXCEPTION_UNKNOWN_FWALERT,
636 MCDI_EV_FIELD(eqp, DATA));
637 break;
638 }
639
640 default:
641 EFSYS_PROBE1(mc_pcol_error, int, code);
642 break;
643 }
644
645out:
646 return (should_abort);
647}
648
649#endif /* EFSYS_OPT_SIENA */
650
651 __checkReturn int
652efx_ev_qprime(
653 __in efx_evq_t *eep,
654 __in unsigned int count)
655{
656 efx_nic_t *enp = eep->ee_enp;
657 uint32_t rptr;
658 efx_dword_t dword;
659 int rc;
660
661 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
662
663 if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
664 rc = EINVAL;
665 goto fail1;
666 }
667
668 rptr = count & eep->ee_mask;
669
670 EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
671
672 EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
673 &dword, B_FALSE);
674
675 return (0);
676
677fail1:
678 EFSYS_PROBE1(fail1, int, rc);
679
680 return (rc);
681}
682
683 __checkReturn boolean_t
684efx_ev_qpending(
685 __in efx_evq_t *eep,
686 __in unsigned int count)
687{
688 size_t offset;
689 efx_qword_t qword;
690
691 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
692
693 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
694 EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
695
696 return (EFX_QWORD_FIELD(qword, EFX_DWORD_0) != 0xffffffff &&
697 EFX_QWORD_FIELD(qword, EFX_DWORD_1) != 0xffffffff);
698}
699
700#if EFSYS_OPT_EV_PREFETCH
701
702 void
703efx_ev_qprefetch(
704 __in efx_evq_t *eep,
705 __in unsigned int count)
706{
707 unsigned int offset;
708
709 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
710
711 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
712 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
713}
714
715#endif /* EFSYS_OPT_EV_PREFETCH */
716
717#define EFX_EV_BATCH 8
718
719#define EFX_EV_PRESENT(_qword) \
720 (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff && \
721 EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
722
723 void
724efx_ev_qpoll(
725 __in efx_evq_t *eep,
726 __inout unsigned int *countp,
727 __in const efx_ev_callbacks_t *eecp,
728 __in_opt void *arg)
729{
730 efx_qword_t ev[EFX_EV_BATCH];
731 unsigned int batch;
732 unsigned int total;
733 unsigned int count;
734 unsigned int index;
735 size_t offset;
736
737 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
738 EFSYS_ASSERT(countp != NULL);
739 EFSYS_ASSERT(eecp != NULL);
740
741 count = *countp;
742 do {
743 /* Read up until the end of the batch period */
744 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
745 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
746 for (total = 0; total < batch; ++total) {
747 EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
748
749 if (!EFX_EV_PRESENT(ev[total]))
750 break;
751
752 EFSYS_PROBE3(event, unsigned int, eep->ee_index,
753 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
754 uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
755
756 offset += sizeof (efx_qword_t);
757 }
758
759#if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
760 /*
761 * Prefetch the next batch when we get within PREFETCH_PERIOD
762 * of a completed batch. If the batch is smaller, then prefetch
763 * immediately.
764 */
765 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
766 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
767#endif /* EFSYS_OPT_EV_PREFETCH */
768
769 /* Process the batch of events */
770 for (index = 0; index < total; ++index) {
771 boolean_t should_abort;
772 uint32_t code;
773 efx_ev_handler_t handler;
774
775#if EFSYS_OPT_EV_PREFETCH
776 /* Prefetch if we've now reached the batch period */
777 if (total == batch &&
778 index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
779 offset = (count + batch) & eep->ee_mask;
780 offset *= sizeof (efx_qword_t);
781
782 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
783 }
784#endif /* EFSYS_OPT_EV_PREFETCH */
785
786 EFX_EV_QSTAT_INCR(eep, EV_ALL);
787
788 code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
789 handler = eep->ee_handler[code];
790 EFSYS_ASSERT(handler != NULL);
791 should_abort = handler(eep, &(ev[index]), eecp, arg);
792 if (should_abort) {
793 /* Ignore subsequent events */
794 total = index + 1;
795 break;
796 }
797 }
798
799 /*
800 * Now that the hardware has most likely moved onto dma'ing
801 * into the next cache line, clear the processed events. Take
802 * care to only clear out events that we've processed
803 */
804 EFX_SET_QWORD(ev[0]);
805 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
806 for (index = 0; index < total; ++index) {
807 EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
808 offset += sizeof (efx_qword_t);
809 }
810
811 count += total;
812
813 } while (total == batch);
814
815 *countp = count;
816}
817
818 void
819efx_ev_qpost(
820 __in efx_evq_t *eep,
821 __in uint16_t data)
822{
823 efx_nic_t *enp = eep->ee_enp;
824 efx_qword_t ev;
825 efx_oword_t oword;
826
827 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
828
829 EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
830 FSF_AZ_EV_DATA_DW0, (uint32_t)data);
831
832 EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
833 EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
834 EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
835
836 EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
837}
838
839 __checkReturn int
840efx_ev_qmoderate(
841 __in efx_evq_t *eep,
842 __in unsigned int us)
843{
844 efx_nic_t *enp = eep->ee_enp;
845 unsigned int locked;
846 efx_dword_t dword;
847 int rc;
848
849 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
850
851 if (us > enp->en_nic_cfg.enc_evq_moderation_max) {
852 rc = EINVAL;
853 goto fail1;
854 }
855
856 /* If the value is zero then disable the timer */
857 if (us == 0) {
858 if (enp->en_family == EFX_FAMILY_FALCON)
859 EFX_POPULATE_DWORD_2(dword,
860 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_DIS,
861 FRF_AB_TC_TIMER_VAL, 0);
862 else
863 EFX_POPULATE_DWORD_2(dword,
864 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
865 FRF_CZ_TC_TIMER_VAL, 0);
866 } else {
867 uint32_t timer_val;
868
869 /* Calculate the timer value in quanta */
870 us -= (us % EFX_EV_TIMER_QUANTUM);
871 if (us < EFX_EV_TIMER_QUANTUM)
872 us = EFX_EV_TIMER_QUANTUM;
873
874 timer_val = us / EFX_EV_TIMER_QUANTUM;
875
876 /* Moderation value is base 0 so we need to deduct 1 */
877 if (enp->en_family == EFX_FAMILY_FALCON)
878 EFX_POPULATE_DWORD_2(dword,
879 FRF_AB_TC_TIMER_MODE, FFE_AB_TIMER_MODE_INT_HLDOFF,
880 FRF_AB_TIMER_VAL, timer_val - 1);
881 else
882 EFX_POPULATE_DWORD_2(dword,
883 FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
884 FRF_CZ_TC_TIMER_VAL, timer_val - 1);
885 }
886
887 locked = (eep->ee_index == 0) ? 1 : 0;
888
889 EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
890 eep->ee_index, &dword, locked);
891
892 return (0);
893
894fail1:
895 EFSYS_PROBE1(fail1, int, rc);
896
897 return (rc);
898}
899
900 __checkReturn int
901efx_ev_qcreate(
902 __in efx_nic_t *enp,
903 __in unsigned int index,
904 __in efsys_mem_t *esmp,
905 __in size_t n,
906 __in uint32_t id,
907 __deref_out efx_evq_t **eepp)
908{
909 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
910 uint32_t size;
911 efx_evq_t *eep;
912 efx_oword_t oword;
913 int rc;
914
915 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
916 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
917
918 EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
919
920 if (!ISP2(n) || !(n & EFX_EVQ_NEVS_MASK)) {
921 rc = EINVAL;
922 goto fail1;
923 }
924 if (index >= encp->enc_evq_limit) {
925 rc = EINVAL;
926 goto fail2;
927 }
928#if EFSYS_OPT_RX_SCALE
929 if (enp->en_intr.ei_type == EFX_INTR_LINE &&
930 index >= EFX_MAXRSS_LEGACY) {
931 rc = EINVAL;
932 goto fail3;
933 }
934#endif
935 for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
936 size++)
937 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
938 break;
939 if (id + (1 << size) >= encp->enc_buftbl_limit) {
940 rc = EINVAL;
941 goto fail4;
942 }
943
944 /* Allocate an EVQ object */
945 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
946 if (eep == NULL) {
947 rc = ENOMEM;
948 goto fail5;
949 }
950
951 eep->ee_magic = EFX_EVQ_MAGIC;
952 eep->ee_enp = enp;
953 eep->ee_index = index;
954 eep->ee_mask = n - 1;
955 eep->ee_esmp = esmp;
956
957 /* Set up the handler table */
958 eep->ee_handler[FSE_AZ_EV_CODE_RX_EV] = efx_ev_rx;
959 eep->ee_handler[FSE_AZ_EV_CODE_TX_EV] = efx_ev_tx;
960 eep->ee_handler[FSE_AZ_EV_CODE_DRIVER_EV] = efx_ev_driver;
961 eep->ee_handler[FSE_AZ_EV_CODE_GLOBAL_EV] = efx_ev_global;
962 eep->ee_handler[FSE_AZ_EV_CODE_DRV_GEN_EV] = efx_ev_drv_gen;
963#if EFSYS_OPT_MCDI
964 eep->ee_handler[FSE_AZ_EV_CODE_MCDI_EVRESPONSE] = efx_ev_mcdi;
965#endif /* EFSYS_OPT_SIENA */
966
967 /* Set up the new event queue */
968 if (enp->en_family != EFX_FAMILY_FALCON) {
969 EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
970 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword);
971 }
972
973 EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
974 FRF_AZ_EVQ_BUF_BASE_ID, id);
975
976 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword);
977
978 enp->en_ev_qcount++;
979 *eepp = eep;
980 return (0);
981
982fail5:
983 EFSYS_PROBE(fail5);
984fail4:
985 EFSYS_PROBE(fail4);
986#if EFSYS_OPT_RX_SCALE
987fail3:
988 EFSYS_PROBE(fail3);
989#endif
990fail2:
991 EFSYS_PROBE(fail2);
992fail1:
993 EFSYS_PROBE1(fail1, int, rc);
994
995 return (rc);
996}
997
998#if EFSYS_OPT_QSTATS
999#if EFSYS_OPT_NAMES
1000/* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock 67e9bdcd920059bd */
1001static const char __cs * __cs __efx_ev_qstat_name[] = {
1002 "all",
1003 "rx",
1004 "rx_ok",
1005 "rx_recovery",
1006 "rx_frm_trunc",
1007 "rx_tobe_disc",
1008 "rx_pause_frm_err",
1009 "rx_buf_owner_id_err",
1010 "rx_ipv4_hdr_chksum_err",
1011 "rx_tcp_udp_chksum_err",
1012 "rx_eth_crc_err",
1013 "rx_ip_frag_err",
1014 "rx_mcast_pkt",
1015 "rx_mcast_hash_match",
1016 "rx_tcp_ipv4",
1017 "rx_tcp_ipv6",
1018 "rx_udp_ipv4",
1019 "rx_udp_ipv6",
1020 "rx_other_ipv4",
1021 "rx_other_ipv6",
1022 "rx_non_ip",
1023 "rx_overrun",
1024 "tx",
1025 "tx_wq_ff_full",
1026 "tx_pkt_err",
1027 "tx_pkt_too_big",
1028 "tx_unexpected",
1029 "global",
1030 "global_phy",
1031 "global_mnt",
1032 "global_rx_recovery",
1033 "driver",
1034 "driver_srm_upd_done",
1035 "driver_tx_descq_fls_done",
1036 "driver_rx_descq_fls_done",
1037 "driver_rx_descq_fls_failed",
1038 "driver_rx_dsc_error",
1039 "driver_tx_dsc_error",
1040 "drv_gen",
1041 "mcdi_response",
1042};
1043/* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1044
1045 const char __cs *
1046efx_ev_qstat_name(
1047 __in efx_nic_t *enp,
1048 __in unsigned int id)
1049{
1050 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1051 EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1052
1053 return (__efx_ev_qstat_name[id]);
1054}
1055#endif /* EFSYS_OPT_NAMES */
1056#endif /* EFSYS_OPT_QSTATS */
1057
1058#if EFSYS_OPT_QSTATS
1059 void
1060efx_ev_qstats_update(
1061 __in efx_evq_t *eep,
1062 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
1063{
1064 unsigned int id;
1065
1066 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1067
1068 for (id = 0; id < EV_NQSTATS; id++) {
1069 efsys_stat_t *essp = &stat[id];
1070
1071 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1072 eep->ee_stat[id] = 0;
1073 }
1074}
1075#endif /* EFSYS_OPT_QSTATS */
1076
1077 void
1078efx_ev_qdestroy(
1079 __in efx_evq_t *eep)
1080{
1081 efx_nic_t *enp = eep->ee_enp;
1082 efx_oword_t oword;
1083
1084 EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1085
1086 EFSYS_ASSERT(enp->en_ev_qcount != 0);
1087 --enp->en_ev_qcount;
1088
1089 /* Purge event queue */
1090 EFX_ZERO_OWORD(oword);
1091
1092 EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1093 eep->ee_index, &oword);
1094
1095 if (enp->en_family != EFX_FAMILY_FALCON) {
1096 EFX_ZERO_OWORD(oword);
1097 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL,
1098 eep->ee_index, &oword);
1099 }
1100
1101 /* Free the EVQ object */
1102 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
1103}
1104
1105 void
1106efx_ev_fini(
1107 __in efx_nic_t *enp)
1108{
1109 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1110 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
1111 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
1112 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
1113 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
1114 EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
1115
1116 enp->en_mod_flags &= ~EFX_MOD_EV;
1117}