| if_rlreg.h (185903) | if_rlreg.h (186210) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/pci/if_rlreg.h 185903 2008-12-11 02:24:11Z yongari $ | 32 * $FreeBSD: head/sys/pci/if_rlreg.h 186210 2008-12-17 06:01:03Z yongari $ |
| 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 85 unchanged lines hidden (view full) --- 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129#define RL_PHYAR 0x0060 130#define RL_TBICSR 0x0064 131#define RL_TBI_ANAR 0x0068 132#define RL_TBI_LPAR 0x006A 133#define RL_GMEDIASTAT 0x006C /* 8 bits */ | 33 */ 34 35/* 36 * RealTek 8129/8139 register offsets 37 */ 38#define RL_IDR0 0x0000 /* ID register 0 (station addr) */ 39#define RL_IDR1 0x0001 /* Must use 32-bit accesses (?) */ 40#define RL_IDR2 0x0002 --- 85 unchanged lines hidden (view full) --- 126 * Registers specific to the 8169 gigE chip 127 */ 128#define RL_TIMERINT_8169 0x0058 /* different offset than 8139 */ 129#define RL_PHYAR 0x0060 130#define RL_TBICSR 0x0064 131#define RL_TBI_ANAR 0x0068 132#define RL_TBI_LPAR 0x006A 133#define RL_GMEDIASTAT 0x006C /* 8 bits */ |
| 134#define RL_MACDBG 0x006D /* 8 bits, 8168C SPIN2 only */ 135#define RL_GPIO 0x006E /* 8 bits, 8168C SPIN2 only */ |
|
| 134#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 135#define RL_GTXSTART 0x0038 /* 8 bits */ 136 137/* 138 * TX config register bits 139 */ 140#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 141#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ --- 741 unchanged lines hidden (view full) --- 883#define RL_FLAG_PAR 0x0020 884#define RL_FLAG_DESCV2 0x0040 885#define RL_FLAG_MACSTAT 0x0080 886#define RL_FLAG_FASTETHER 0x0100 887#define RL_FLAG_CMDSTOP 0x0200 888#define RL_FLAG_PHY8169 0x0400 889#define RL_FLAG_PHY8110S 0x0800 890#define RL_FLAG_WOLRXENB 0x1000 | 136#define RL_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */ 137#define RL_GTXSTART 0x0038 /* 8 bits */ 138 139/* 140 * TX config register bits 141 */ 142#define RL_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */ 143#define RL_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */ --- 741 unchanged lines hidden (view full) --- 885#define RL_FLAG_PAR 0x0020 886#define RL_FLAG_DESCV2 0x0040 887#define RL_FLAG_MACSTAT 0x0080 888#define RL_FLAG_FASTETHER 0x0100 889#define RL_FLAG_CMDSTOP 0x0200 890#define RL_FLAG_PHY8169 0x0400 891#define RL_FLAG_PHY8110S 0x0800 892#define RL_FLAG_WOLRXENB 0x1000 |
| 893#define RL_FLAG_MACSLEEP 0x2000 |
|
| 891#define RL_FLAG_LINK 0x8000 892}; 893 894#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 895#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 896#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 897 898/* --- 242 unchanged lines hidden --- | 894#define RL_FLAG_LINK 0x8000 895}; 896 897#define RL_LOCK(_sc) mtx_lock(&(_sc)->rl_mtx) 898#define RL_UNLOCK(_sc) mtx_unlock(&(_sc)->rl_mtx) 899#define RL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->rl_mtx, MA_OWNED) 900 901/* --- 242 unchanged lines hidden --- |