Deleted Added
sdiff udiff text old ( 158878 ) new ( 159962 )
full compact
if_re.c (158878) if_re.c (159962)
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1997, 1998-2003
3 * Bill Paul <wpaul@windriver.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 17 unchanged lines hidden (view full) ---

26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 158878 2006-05-24 11:55:25Z glebius $");
34__FBSDID("$FreeBSD: head/sys/dev/re/if_re.c 159962 2006-06-26 20:31:32Z wpaul $");
35
36/*
35
36/*
37 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44/*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
38 *
39 * Written by Bill Paul <wpaul@windriver.com>
40 * Senior Networking Software Engineer
41 * Wind River Systems
42 */
43
44/*
45 * This driver is designed to support RealTek's next generation of
46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
47 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
48 * and the RTL8110S.
47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on

--- 59 unchanged lines hidden (view full) ---

116#include <sys/endian.h>
117#include <sys/systm.h>
118#include <sys/sockio.h>
119#include <sys/mbuf.h>
120#include <sys/malloc.h>
121#include <sys/module.h>
122#include <sys/kernel.h>
123#include <sys/socket.h>
49 *
50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
51 * with the older 8139 family, however it also supports a special
52 * C+ mode of operation that provides several new performance enhancing
53 * features. These include:
54 *
55 * o Descriptor based DMA mechanism. Each descriptor represents
56 * a single packet fragment. Data buffers may be aligned on

--- 59 unchanged lines hidden (view full) ---

116#include <sys/endian.h>
117#include <sys/systm.h>
118#include <sys/sockio.h>
119#include <sys/mbuf.h>
120#include <sys/malloc.h>
121#include <sys/module.h>
122#include <sys/kernel.h>
123#include <sys/socket.h>
124#include <sys/lock.h>
125#include <sys/mutex.h>
126#include <sys/taskqueue.h>
124
125#include <net/if.h>
126#include <net/if_arp.h>
127#include <net/ethernet.h>
128#include <net/if_dl.h>
129#include <net/if_media.h>
130#include <net/if_types.h>
131#include <net/if_vlan_var.h>

--- 30 unchanged lines hidden (view full) ---

162/*
163 * Various supported device vendors/types and their names.
164 */
165static struct rl_type re_devs[] = {
166 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
167 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
168 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
169 "RealTek 8139C+ 10/100BaseTX" },
127
128#include <net/if.h>
129#include <net/if_arp.h>
130#include <net/ethernet.h>
131#include <net/if_dl.h>
132#include <net/if_media.h>
133#include <net/if_types.h>
134#include <net/if_vlan_var.h>

--- 30 unchanged lines hidden (view full) ---

165/*
166 * Various supported device vendors/types and their names.
167 */
168static struct rl_type re_devs[] = {
169 { DLINK_VENDORID, DLINK_DEVICEID_528T, RL_HWREV_8169S,
170 "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
171 { RT_VENDORID, RT_DEVICEID_8139, RL_HWREV_8139CPLUS,
172 "RealTek 8139C+ 10/100BaseTX" },
173 { RT_VENDORID, RT_DEVICEID_8101E, RL_HWREV_8101E,
174 "RealTek 8101E PCIe 10/100baseTX" },
170 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168,
175 { RT_VENDORID, RT_DEVICEID_8168, RL_HWREV_8168,
171 "Realtek 8168B/8111B Gigabit Ethernet" },
176 "RealTek 8168B/8111B PCIe Gigabit Ethernet" },
172 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
173 "RealTek 8169 Gigabit Ethernet" },
174 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
175 "RealTek 8169S Single-chip Gigabit Ethernet" },
177 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169,
178 "RealTek 8169 Gigabit Ethernet" },
179 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169S,
180 "RealTek 8169S Single-chip Gigabit Ethernet" },
176 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169SB,
177 "RealTek 8169SB Single-chip Gigabit Ethernet" },
181 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SB,
182 "RealTek 8169SB/8110SB Single-chip Gigabit Ethernet" },
183 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8169_8110SC,
184 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
178 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
179 "RealTek 8110S Single-chip Gigabit Ethernet" },
180 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
181 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
182 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
183 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
184 { 0, 0, 0, NULL }
185};
186
187static struct rl_hwrev re_hwrevs[] = {
188 { RL_HWREV_8139, RL_8139, "" },
189 { RL_HWREV_8139A, RL_8139, "A" },
190 { RL_HWREV_8139AG, RL_8139, "A-G" },
191 { RL_HWREV_8139B, RL_8139, "B" },
192 { RL_HWREV_8130, RL_8139, "8130" },
193 { RL_HWREV_8139C, RL_8139, "C" },
194 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
195 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
185 { RT_VENDORID, RT_DEVICEID_8169, RL_HWREV_8110S,
186 "RealTek 8110S Single-chip Gigabit Ethernet" },
187 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, RL_HWREV_8169S,
188 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" },
189 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, RL_HWREV_8169S,
190 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" },
191 { 0, 0, 0, NULL }
192};
193
194static struct rl_hwrev re_hwrevs[] = {
195 { RL_HWREV_8139, RL_8139, "" },
196 { RL_HWREV_8139A, RL_8139, "A" },
197 { RL_HWREV_8139AG, RL_8139, "A-G" },
198 { RL_HWREV_8139B, RL_8139, "B" },
199 { RL_HWREV_8130, RL_8139, "8130" },
200 { RL_HWREV_8139C, RL_8139, "C" },
201 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C" },
202 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+"},
203 { RL_HWREV_8168, RL_8169, "8168"},
196 { RL_HWREV_8169, RL_8169, "8169"},
197 { RL_HWREV_8169S, RL_8169, "8169S"},
204 { RL_HWREV_8169, RL_8169, "8169"},
205 { RL_HWREV_8169S, RL_8169, "8169S"},
198 { RL_HWREV_8169SB, RL_8169, "8169SB"},
199 { RL_HWREV_8110S, RL_8169, "8110S"},
206 { RL_HWREV_8110S, RL_8169, "8110S"},
207 { RL_HWREV_8169_8110SB, RL_8169, "8169SB"},
208 { RL_HWREV_8169_8110SC, RL_8169, "8169SC"},
200 { RL_HWREV_8100, RL_8139, "8100"},
201 { RL_HWREV_8101, RL_8139, "8101"},
209 { RL_HWREV_8100, RL_8139, "8100"},
210 { RL_HWREV_8101, RL_8139, "8101"},
202 { RL_HWREV_8168, RL_8169, "8168/8111B"},
211 { RL_HWREV_8100E, RL_8169, "8100E"},
212 { RL_HWREV_8101E, RL_8169, "8101E"},
203 { 0, 0, NULL }
204};
205
206static int re_probe (device_t);
207static int re_attach (device_t);
208static int re_detach (device_t);
209
210static int re_encap (struct rl_softc *, struct mbuf **, int *);

--- 4 unchanged lines hidden (view full) ---

215static int re_allocmem (device_t, struct rl_softc *);
216static int re_newbuf (struct rl_softc *, int, struct mbuf *);
217static int re_rx_list_init (struct rl_softc *);
218static int re_tx_list_init (struct rl_softc *);
219#ifdef RE_FIXUP_RX
220static __inline void re_fixup_rx
221 (struct mbuf *);
222#endif
213 { 0, 0, NULL }
214};
215
216static int re_probe (device_t);
217static int re_attach (device_t);
218static int re_detach (device_t);
219
220static int re_encap (struct rl_softc *, struct mbuf **, int *);

--- 4 unchanged lines hidden (view full) ---

225static int re_allocmem (device_t, struct rl_softc *);
226static int re_newbuf (struct rl_softc *, int, struct mbuf *);
227static int re_rx_list_init (struct rl_softc *);
228static int re_tx_list_init (struct rl_softc *);
229#ifdef RE_FIXUP_RX
230static __inline void re_fixup_rx
231 (struct mbuf *);
232#endif
223static void re_rxeof (struct rl_softc *);
233static int re_rxeof (struct rl_softc *);
224static void re_txeof (struct rl_softc *);
225#ifdef DEVICE_POLLING
226static void re_poll (struct ifnet *, enum poll_cmd, int);
227static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
228#endif
229static void re_intr (void *);
230static void re_tick (void *);
234static void re_txeof (struct rl_softc *);
235#ifdef DEVICE_POLLING
236static void re_poll (struct ifnet *, enum poll_cmd, int);
237static void re_poll_locked (struct ifnet *, enum poll_cmd, int);
238#endif
239static void re_intr (void *);
240static void re_tick (void *);
241static void re_tx_task (void *, int);
242static void re_int_task (void *, int);
231static void re_start (struct ifnet *);
243static void re_start (struct ifnet *);
232static void re_start_locked (struct ifnet *);
233static int re_ioctl (struct ifnet *, u_long, caddr_t);
234static void re_init (void *);
235static void re_init_locked (struct rl_softc *);
236static void re_stop (struct rl_softc *);
237static void re_watchdog (struct ifnet *);
238static int re_suspend (device_t);
239static int re_resume (device_t);
240static void re_shutdown (device_t);
241static int re_ifmedia_upd (struct ifnet *);
242static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
243
244static void re_eeprom_putbyte (struct rl_softc *, int);
245static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
244static int re_ioctl (struct ifnet *, u_long, caddr_t);
245static void re_init (void *);
246static void re_init_locked (struct rl_softc *);
247static void re_stop (struct rl_softc *);
248static void re_watchdog (struct ifnet *);
249static int re_suspend (device_t);
250static int re_resume (device_t);
251static void re_shutdown (device_t);
252static int re_ifmedia_upd (struct ifnet *);
253static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
254
255static void re_eeprom_putbyte (struct rl_softc *, int);
256static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
246static void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
257static void re_read_eeprom (struct rl_softc *, caddr_t, int, int);
247static int re_gmii_readreg (device_t, int, int);
248static int re_gmii_writereg (device_t, int, int, int);
249
250static int re_miibus_readreg (device_t, int, int);
251static int re_miibus_writereg (device_t, int, int, int);
252static void re_miibus_statchg (device_t);
253
254static void re_setmulti (struct rl_softc *);
255static void re_reset (struct rl_softc *);
256
258static int re_gmii_readreg (device_t, int, int);
259static int re_gmii_writereg (device_t, int, int, int);
260
261static int re_miibus_readreg (device_t, int, int);
262static int re_miibus_writereg (device_t, int, int, int);
263static void re_miibus_statchg (device_t);
264
265static void re_setmulti (struct rl_softc *);
266static void re_reset (struct rl_softc *);
267
268#ifdef RE_DIAG
257static int re_diag (struct rl_softc *);
269static int re_diag (struct rl_softc *);
270#endif
258
259#ifdef RE_USEIOSPACE
260#define RL_RES SYS_RES_IOPORT
261#define RL_RID RL_PCI_LOIO
262#else
263#define RL_RES SYS_RES_MEMORY
264#define RL_RID RL_PCI_LOMEM
265#endif

--- 44 unchanged lines hidden (view full) ---

310 */
311static void
312re_eeprom_putbyte(sc, addr)
313 struct rl_softc *sc;
314 int addr;
315{
316 register int d, i;
317
271
272#ifdef RE_USEIOSPACE
273#define RL_RES SYS_RES_IOPORT
274#define RL_RID RL_PCI_LOIO
275#else
276#define RL_RES SYS_RES_MEMORY
277#define RL_RID RL_PCI_LOMEM
278#endif

--- 44 unchanged lines hidden (view full) ---

323 */
324static void
325re_eeprom_putbyte(sc, addr)
326 struct rl_softc *sc;
327 int addr;
328{
329 register int d, i;
330
318 d = addr | sc->rl_eecmd_read;
331 d = addr | (RL_9346_READ << sc->rl_eewidth);
319
320 /*
321 * Feed in each bit and strobe the clock.
322 */
332
333 /*
334 * Feed in each bit and strobe the clock.
335 */
323 for (i = 0x400; i; i >>= 1) {
336
337 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) {
324 if (d & i) {
325 EE_SET(RL_EE_DATAIN);
326 } else {
327 EE_CLR(RL_EE_DATAIN);
328 }
329 DELAY(100);
330 EE_SET(RL_EE_CLK);
331 DELAY(150);
332 EE_CLR(RL_EE_CLK);
333 DELAY(100);
334 }
338 if (d & i) {
339 EE_SET(RL_EE_DATAIN);
340 } else {
341 EE_CLR(RL_EE_DATAIN);
342 }
343 DELAY(100);
344 EE_SET(RL_EE_CLK);
345 DELAY(150);
346 EE_CLR(RL_EE_CLK);
347 DELAY(100);
348 }
349
350 return;
335}
336
337/*
338 * Read a word of data stored in the EEPROM at address 'addr.'
339 */
340static void
341re_eeprom_getword(sc, addr, dest)
342 struct rl_softc *sc;
343 int addr;
344 u_int16_t *dest;
345{
346 register int i;
347 u_int16_t word = 0;
348
351}
352
353/*
354 * Read a word of data stored in the EEPROM at address 'addr.'
355 */
356static void
357re_eeprom_getword(sc, addr, dest)
358 struct rl_softc *sc;
359 int addr;
360 u_int16_t *dest;
361{
362 register int i;
363 u_int16_t word = 0;
364
349 /* Enter EEPROM access mode. */
350 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
351
352 /*
353 * Send address of word we want to read.
354 */
355 re_eeprom_putbyte(sc, addr);
356
365 /*
366 * Send address of word we want to read.
367 */
368 re_eeprom_putbyte(sc, addr);
369
357 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
358
359 /*
360 * Start reading bits from EEPROM.
361 */
362 for (i = 0x8000; i; i >>= 1) {
363 EE_SET(RL_EE_CLK);
364 DELAY(100);
365 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
366 word |= i;
367 EE_CLR(RL_EE_CLK);
368 DELAY(100);
369 }
370
370 /*
371 * Start reading bits from EEPROM.
372 */
373 for (i = 0x8000; i; i >>= 1) {
374 EE_SET(RL_EE_CLK);
375 DELAY(100);
376 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
377 word |= i;
378 EE_CLR(RL_EE_CLK);
379 DELAY(100);
380 }
381
371 /* Turn off EEPROM access mode. */
372 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
373
374 *dest = word;
382 *dest = word;
383
384 return;
375}
376
377/*
378 * Read a sequence of words from the EEPROM.
379 */
380static void
385}
386
387/*
388 * Read a sequence of words from the EEPROM.
389 */
390static void
381re_read_eeprom(sc, dest, off, cnt, swap)
391re_read_eeprom(sc, dest, off, cnt)
382 struct rl_softc *sc;
383 caddr_t dest;
384 int off;
385 int cnt;
392 struct rl_softc *sc;
393 caddr_t dest;
394 int off;
395 int cnt;
386 int swap;
387{
388 int i;
389 u_int16_t word = 0, *ptr;
390
396{
397 int i;
398 u_int16_t word = 0, *ptr;
399
400 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
401
402 DELAY(100);
403
391 for (i = 0; i < cnt; i++) {
404 for (i = 0; i < cnt; i++) {
405 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL);
392 re_eeprom_getword(sc, off + i, &word);
406 re_eeprom_getword(sc, off + i, &word);
407 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL);
393 ptr = (u_int16_t *)(dest + (i * 2));
408 ptr = (u_int16_t *)(dest + (i * 2));
394 if (swap)
395 *ptr = ntohs(word);
396 else
397 *ptr = word;
409 *ptr = le16toh(word);
398 }
410 }
411
412 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM);
413
414 return;
399}
400
401static int
402re_gmii_readreg(dev, phy, reg)
403 device_t dev;
404 int phy, reg;
405{
406 struct rl_softc *sc;

--- 244 unchanged lines hidden (view full) ---

651 break;
652 }
653 if (i == RL_TIMEOUT)
654 if_printf(sc->rl_ifp, "reset never completed!\n");
655
656 CSR_WRITE_1(sc, 0x82, 1);
657}
658
415}
416
417static int
418re_gmii_readreg(dev, phy, reg)
419 device_t dev;
420 int phy, reg;
421{
422 struct rl_softc *sc;

--- 244 unchanged lines hidden (view full) ---

667 break;
668 }
669 if (i == RL_TIMEOUT)
670 if_printf(sc->rl_ifp, "reset never completed!\n");
671
672 CSR_WRITE_1(sc, 0x82, 1);
673}
674
675#ifdef RE_DIAG
676
659/*
660 * The following routine is designed to test for a defect on some
661 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
662 * lines connected to the bus, however for a 32-bit only card, they
663 * should be pulled high. The result of this defect is that the
664 * NIC will not work right if you plug it into a 64-bit slot: DMA
665 * operations will be done with 64-bit transfers, which will fail
666 * because the 64-bit data lines aren't connected.

--- 14 unchanged lines hidden (view full) ---

681 struct rl_softc *sc;
682{
683 struct ifnet *ifp = sc->rl_ifp;
684 struct mbuf *m0;
685 struct ether_header *eh;
686 struct rl_desc *cur_rx;
687 u_int16_t status;
688 u_int32_t rxstat;
677/*
678 * The following routine is designed to test for a defect on some
679 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
680 * lines connected to the bus, however for a 32-bit only card, they
681 * should be pulled high. The result of this defect is that the
682 * NIC will not work right if you plug it into a 64-bit slot: DMA
683 * operations will be done with 64-bit transfers, which will fail
684 * because the 64-bit data lines aren't connected.

--- 14 unchanged lines hidden (view full) ---

699 struct rl_softc *sc;
700{
701 struct ifnet *ifp = sc->rl_ifp;
702 struct mbuf *m0;
703 struct ether_header *eh;
704 struct rl_desc *cur_rx;
705 u_int16_t status;
706 u_int32_t rxstat;
689 int total_len, i, error = 0;
707 int total_len, i, error = 0, phyaddr;
690 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
691 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
692
693 /* Allocate a single mbuf */
694 MGETHDR(m0, M_DONTWAIT, MT_DATA);
695 if (m0 == NULL)
696 return (ENOBUFS);
697

--- 5 unchanged lines hidden (view full) ---

703 * following special functions:
704 * - Puts receiver in promiscuous mode
705 * - Enables digital loopback mode
706 * - Leaves interrupts turned off
707 */
708
709 ifp->if_flags |= IFF_PROMISC;
710 sc->rl_testmode = 1;
708 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
709 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
710
711 /* Allocate a single mbuf */
712 MGETHDR(m0, M_DONTWAIT, MT_DATA);
713 if (m0 == NULL)
714 return (ENOBUFS);
715

--- 5 unchanged lines hidden (view full) ---

721 * following special functions:
722 * - Puts receiver in promiscuous mode
723 * - Enables digital loopback mode
724 * - Leaves interrupts turned off
725 */
726
727 ifp->if_flags |= IFF_PROMISC;
728 sc->rl_testmode = 1;
729 re_reset(sc);
711 re_init_locked(sc);
730 re_init_locked(sc);
712 re_stop(sc);
731 sc->rl_link = 1;
732 if (sc->rl_type == RL_8169)
733 phyaddr = 1;
734 else
735 phyaddr = 0;
736
737 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
738 for (i = 0; i < RL_TIMEOUT; i++) {
739 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR);
740 if (!(status & BMCR_RESET))
741 break;
742 }
743
744 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP);
745 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
746
713 DELAY(100000);
747 DELAY(100000);
714 re_init_locked(sc);
715
716 /* Put some data in the mbuf */
717
718 eh = mtod(m0, struct ether_header *);
719 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
720 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
721 eh->ether_type = htons(ETHERTYPE_IP);
722 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;

--- 10 unchanged lines hidden (view full) ---

733 RL_LOCK(sc);
734 m0 = NULL;
735
736 /* Wait for it to propagate through the chip */
737
738 DELAY(100000);
739 for (i = 0; i < RL_TIMEOUT; i++) {
740 status = CSR_READ_2(sc, RL_ISR);
748
749 /* Put some data in the mbuf */
750
751 eh = mtod(m0, struct ether_header *);
752 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
753 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
754 eh->ether_type = htons(ETHERTYPE_IP);
755 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;

--- 10 unchanged lines hidden (view full) ---

766 RL_LOCK(sc);
767 m0 = NULL;
768
769 /* Wait for it to propagate through the chip */
770
771 DELAY(100000);
772 for (i = 0; i < RL_TIMEOUT; i++) {
773 status = CSR_READ_2(sc, RL_ISR);
774 CSR_WRITE_2(sc, RL_ISR, status);
741 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
742 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
743 break;
744 DELAY(10);
745 }
746
747 if (i == RL_TIMEOUT) {
748 if_printf(ifp, "diagnostic failed, failed to receive packet "

--- 48 unchanged lines hidden (view full) ---

797 if_printf(ifp, "Read the re(4) man page for more details.\n");
798 error = EIO;
799 }
800
801done:
802 /* Turn interface off, release resources */
803
804 sc->rl_testmode = 0;
775 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
776 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
777 break;
778 DELAY(10);
779 }
780
781 if (i == RL_TIMEOUT) {
782 if_printf(ifp, "diagnostic failed, failed to receive packet "

--- 48 unchanged lines hidden (view full) ---

831 if_printf(ifp, "Read the re(4) man page for more details.\n");
832 error = EIO;
833 }
834
835done:
836 /* Turn interface off, release resources */
837
838 sc->rl_testmode = 0;
839 sc->rl_link = 0;
805 ifp->if_flags &= ~IFF_PROMISC;
806 re_stop(sc);
807 if (m0 != NULL)
808 m_freem(m0);
809
810 RL_UNLOCK(sc);
811
812 return (error);
813}
814
840 ifp->if_flags &= ~IFF_PROMISC;
841 re_stop(sc);
842 if (m0 != NULL)
843 m_freem(m0);
844
845 RL_UNLOCK(sc);
846
847 return (error);
848}
849
850#endif
851
815/*
816 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
817 * IDs against our list and return a device name if we find a match.
818 */
819static int
820re_probe(dev)
821 device_t dev;
822{

--- 259 unchanged lines hidden (view full) ---

1082 struct rl_softc *sc;
1083 struct ifnet *ifp;
1084 struct rl_hwrev *hw_rev;
1085 int hwrev;
1086 u_int16_t re_did = 0;
1087 int error = 0, rid, i;
1088
1089 sc = device_get_softc(dev);
852/*
853 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
854 * IDs against our list and return a device name if we find a match.
855 */
856static int
857re_probe(dev)
858 device_t dev;
859{

--- 259 unchanged lines hidden (view full) ---

1119 struct rl_softc *sc;
1120 struct ifnet *ifp;
1121 struct rl_hwrev *hw_rev;
1122 int hwrev;
1123 u_int16_t re_did = 0;
1124 int error = 0, rid, i;
1125
1126 sc = device_get_softc(dev);
1127 sc->rl_dev = dev;
1090
1091 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1092 MTX_DEF);
1128
1129 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1130 MTX_DEF);
1131 mtx_init(&sc->rl_intlock, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1132 MTX_SPIN);
1093 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1094
1095 /*
1096 * Map control/status registers.
1097 */
1098 pci_enable_busmaster(dev);
1099
1100 rid = RL_RID;

--- 30 unchanged lines hidden (view full) ---

1131 while (hw_rev->rl_desc != NULL) {
1132 if (hw_rev->rl_rev == hwrev) {
1133 sc->rl_type = hw_rev->rl_type;
1134 break;
1135 }
1136 hw_rev++;
1137 }
1138
1133 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0);
1134
1135 /*
1136 * Map control/status registers.
1137 */
1138 pci_enable_busmaster(dev);
1139
1140 rid = RL_RID;

--- 30 unchanged lines hidden (view full) ---

1171 while (hw_rev->rl_desc != NULL) {
1172 if (hw_rev->rl_rev == hwrev) {
1173 sc->rl_type = hw_rev->rl_type;
1174 break;
1175 }
1176 hw_rev++;
1177 }
1178
1139 if (sc->rl_type == RL_8169) {
1179 sc->rl_eewidth = 6;
1180 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
1181 if (re_did != 0x8129)
1182 sc->rl_eewidth = 8;
1140
1183
1141 /* Set RX length mask */
1184 /*
1185 * Get station address from the EEPROM.
1186 */
1187 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3);
1188 for (i = 0; i < 3; i++) {
1189 eaddr[(i * 2) + 0] = as[i] & 0xff;
1190 eaddr[(i * 2) + 1] = as[i] >> 8;
1191 }
1142
1192
1193 if (sc->rl_type == RL_8169) {
1194 /* Set RX length mask */
1143 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1195 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
1144
1145 /* Force station address autoload from the EEPROM */
1146
1147 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
1148 for (i = 0; i < RL_TIMEOUT; i++) {
1149 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
1150 break;
1151 DELAY(100);
1152 }
1153 if (i == RL_TIMEOUT)
1154 device_printf(dev, "eeprom autoload timed out\n");
1155
1156 for (i = 0; i < ETHER_ADDR_LEN; i++)
1157 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
1196 sc->rl_txstart = RL_GTXSTART;
1158 } else {
1197 } else {
1159
1160 /* Set RX length mask */
1198 /* Set RX length mask */
1161
1162 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1199 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
1163
1164 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
1165 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
1166 if (re_did != 0x8129)
1167 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
1168
1169 /*
1170 * Get station address from the EEPROM.
1171 */
1172 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
1173 for (i = 0; i < 3; i++) {
1174 eaddr[(i * 2) + 0] = as[i] & 0xff;
1175 eaddr[(i * 2) + 1] = as[i] >> 8;
1176 }
1200 sc->rl_txstart = RL_TXSTART;
1177 }
1178
1179 /*
1180 * Allocate the parent bus DMA tag appropriate for PCI.
1181 */
1182#define RL_NSEG_NEW 32
1183 error = bus_dma_tag_create(NULL, /* parent */
1184 1, 0, /* alignment, boundary */

--- 30 unchanged lines hidden (view full) ---

1215
1216 ifp->if_softc = sc;
1217 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1218 ifp->if_mtu = ETHERMTU;
1219 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1220 ifp->if_ioctl = re_ioctl;
1221 ifp->if_capabilities = IFCAP_VLAN_MTU;
1222 ifp->if_start = re_start;
1201 }
1202
1203 /*
1204 * Allocate the parent bus DMA tag appropriate for PCI.
1205 */
1206#define RL_NSEG_NEW 32
1207 error = bus_dma_tag_create(NULL, /* parent */
1208 1, 0, /* alignment, boundary */

--- 30 unchanged lines hidden (view full) ---

1239
1240 ifp->if_softc = sc;
1241 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1242 ifp->if_mtu = ETHERMTU;
1243 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1244 ifp->if_ioctl = re_ioctl;
1245 ifp->if_capabilities = IFCAP_VLAN_MTU;
1246 ifp->if_start = re_start;
1223 ifp->if_hwassist = /*RE_CSUM_FEATURES*/0;
1247 ifp->if_hwassist = RE_CSUM_FEATURES;
1224 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1225 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1226#ifdef DEVICE_POLLING
1227 ifp->if_capabilities |= IFCAP_POLLING;
1228#endif
1229 ifp->if_watchdog = re_watchdog;
1230 ifp->if_init = re_init;
1248 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING;
1249 ifp->if_capenable = ifp->if_capabilities & ~IFCAP_HWCSUM;
1250#ifdef DEVICE_POLLING
1251 ifp->if_capabilities |= IFCAP_POLLING;
1252#endif
1253 ifp->if_watchdog = re_watchdog;
1254 ifp->if_init = re_init;
1231 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1255 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
1232 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1233 IFQ_SET_READY(&ifp->if_snd);
1234
1256 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN;
1257 IFQ_SET_READY(&ifp->if_snd);
1258
1259 TASK_INIT(&sc->rl_txtask, 1, re_tx_task, ifp);
1260 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc);
1261
1235 /*
1236 * Call MI attach routine.
1237 */
1238 ether_ifattach(ifp, eaddr);
1239
1262 /*
1263 * Call MI attach routine.
1264 */
1265 ether_ifattach(ifp, eaddr);
1266
1240 /* Perform hardware diagnostic. */
1241 error = re_diag(sc);
1267#ifdef RE_DIAG
1268 /*
1269 * Perform hardware diagnostic on the original RTL8169.
1270 * Some 32-bit cards were incorrectly wired and would
1271 * malfunction if plugged into a 64-bit slot.
1272 */
1242
1273
1243 if (error) {
1244 device_printf(dev, "attach aborted due to hardware diag failure\n");
1245 ether_ifdetach(ifp);
1246 goto fail;
1274 if (hwrev == RL_HWREV_8169) {
1275 error = re_diag(sc);
1276 if (error) {
1277 device_printf(dev,
1278 "attach aborted due to hardware diag failure\n");
1279 ether_ifdetach(ifp);
1280 goto fail;
1281 }
1247 }
1282 }
1283#endif
1248
1249 /* Hook interrupt last to avoid having to lock softc */
1284
1285 /* Hook interrupt last to avoid having to lock softc */
1250 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE,
1251 re_intr, sc, &sc->rl_intrhand);
1286 error = bus_setup_intr(dev, sc->rl_irq, INTR_TYPE_NET | INTR_MPSAFE |
1287 INTR_FAST, re_intr, sc, &sc->rl_intrhand);
1252 if (error) {
1253 device_printf(dev, "couldn't set up irq\n");
1254 ether_ifdetach(ifp);
1255 }
1256
1257fail:
1288 if (error) {
1289 device_printf(dev, "couldn't set up irq\n");
1290 ether_ifdetach(ifp);
1291 }
1292
1293fail:
1294
1258 if (error)
1259 re_detach(dev);
1260
1261 return (error);
1262}
1263
1264/*
1265 * Shutdown hardware and free up resources. This can be called any

--- 13 unchanged lines hidden (view full) ---

1279 sc = device_get_softc(dev);
1280 ifp = sc->rl_ifp;
1281 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1282
1283#ifdef DEVICE_POLLING
1284 if (ifp->if_capenable & IFCAP_POLLING)
1285 ether_poll_deregister(ifp);
1286#endif
1295 if (error)
1296 re_detach(dev);
1297
1298 return (error);
1299}
1300
1301/*
1302 * Shutdown hardware and free up resources. This can be called any

--- 13 unchanged lines hidden (view full) ---

1316 sc = device_get_softc(dev);
1317 ifp = sc->rl_ifp;
1318 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized"));
1319
1320#ifdef DEVICE_POLLING
1321 if (ifp->if_capenable & IFCAP_POLLING)
1322 ether_poll_deregister(ifp);
1323#endif
1287
1288 /* These should only be active if attach succeeded */
1289 if (device_is_attached(dev)) {
1290 RL_LOCK(sc);
1291#if 0
1292 sc->suspended = 1;
1293#endif
1294 re_stop(sc);
1295 RL_UNLOCK(sc);

--- 76 unchanged lines hidden (view full) ---

1372 sc->rl_ldata.rl_smap);
1373 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1374 }
1375
1376 if (sc->rl_parent_tag)
1377 bus_dma_tag_destroy(sc->rl_parent_tag);
1378
1379 mtx_destroy(&sc->rl_mtx);
1324 /* These should only be active if attach succeeded */
1325 if (device_is_attached(dev)) {
1326 RL_LOCK(sc);
1327#if 0
1328 sc->suspended = 1;
1329#endif
1330 re_stop(sc);
1331 RL_UNLOCK(sc);

--- 76 unchanged lines hidden (view full) ---

1408 sc->rl_ldata.rl_smap);
1409 bus_dma_tag_destroy(sc->rl_ldata.rl_stag);
1410 }
1411
1412 if (sc->rl_parent_tag)
1413 bus_dma_tag_destroy(sc->rl_parent_tag);
1414
1415 mtx_destroy(&sc->rl_mtx);
1416 mtx_destroy(&sc->rl_intlock);
1380
1381 return (0);
1382}
1383
1384static int
1385re_newbuf(sc, idx, m)
1386 struct rl_softc *sc;
1387 int idx;

--- 117 unchanged lines hidden (view full) ---

1505 return (0);
1506}
1507
1508/*
1509 * RX handler for C+ and 8169. For the gigE chips, we support
1510 * the reception of jumbo frames that have been fragmented
1511 * across multiple 2K mbuf cluster buffers.
1512 */
1417
1418 return (0);
1419}
1420
1421static int
1422re_newbuf(sc, idx, m)
1423 struct rl_softc *sc;
1424 int idx;

--- 117 unchanged lines hidden (view full) ---

1542 return (0);
1543}
1544
1545/*
1546 * RX handler for C+ and 8169. For the gigE chips, we support
1547 * the reception of jumbo frames that have been fragmented
1548 * across multiple 2K mbuf cluster buffers.
1549 */
1513static void
1550static int
1514re_rxeof(sc)
1515 struct rl_softc *sc;
1516{
1517 struct mbuf *m;
1518 struct ifnet *ifp;
1519 int i, total_len;
1520 struct rl_desc *cur_rx;
1521 u_int32_t rxstat, rxvlan;
1551re_rxeof(sc)
1552 struct rl_softc *sc;
1553{
1554 struct mbuf *m;
1555 struct ifnet *ifp;
1556 int i, total_len;
1557 struct rl_desc *cur_rx;
1558 u_int32_t rxstat, rxvlan;
1559 int maxpkt = 16;
1522
1523 RL_LOCK_ASSERT(sc);
1524
1525 ifp = sc->rl_ifp;
1526 i = sc->rl_ldata.rl_rx_prodidx;
1527
1528 /* Invalidate the descriptor memory */
1529
1530 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1531 sc->rl_ldata.rl_rx_list_map,
1532 BUS_DMASYNC_POSTREAD);
1533
1560
1561 RL_LOCK_ASSERT(sc);
1562
1563 ifp = sc->rl_ifp;
1564 i = sc->rl_ldata.rl_rx_prodidx;
1565
1566 /* Invalidate the descriptor memory */
1567
1568 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1569 sc->rl_ldata.rl_rx_list_map,
1570 BUS_DMASYNC_POSTREAD);
1571
1534 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1572 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i]) && maxpkt) {
1535 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1536 m = sc->rl_ldata.rl_rx_mbuf[i];
1537 total_len = RL_RXBYTES(cur_rx);
1538 rxstat = le32toh(cur_rx->rl_cmdstat);
1539 rxvlan = le32toh(cur_rx->rl_vlanctl);
1540
1541 /* Invalidate the RX mbuf and unload its map */
1542

--- 121 unchanged lines hidden (view full) ---

1664 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1665 (RL_UDPPKT(rxstat) &&
1666 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1667 m->m_pkthdr.csum_flags |=
1668 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1669 m->m_pkthdr.csum_data = 0xffff;
1670 }
1671 }
1573 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1574 m = sc->rl_ldata.rl_rx_mbuf[i];
1575 total_len = RL_RXBYTES(cur_rx);
1576 rxstat = le32toh(cur_rx->rl_cmdstat);
1577 rxvlan = le32toh(cur_rx->rl_vlanctl);
1578
1579 /* Invalidate the RX mbuf and unload its map */
1580

--- 121 unchanged lines hidden (view full) ---

1702 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1703 (RL_UDPPKT(rxstat) &&
1704 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) {
1705 m->m_pkthdr.csum_flags |=
1706 CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1707 m->m_pkthdr.csum_data = 0xffff;
1708 }
1709 }
1672
1710 maxpkt--;
1673 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1674 VLAN_INPUT_TAG(ifp, m,
1675 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)));
1676 if (m == NULL)
1677 continue;
1678 }
1679 RL_UNLOCK(sc);
1680 (*ifp->if_input)(ifp, m);
1681 RL_LOCK(sc);
1682 }
1683
1684 /* Flush the RX DMA ring */
1685
1686 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1687 sc->rl_ldata.rl_rx_list_map,
1688 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1689
1690 sc->rl_ldata.rl_rx_prodidx = i;
1711 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1712 VLAN_INPUT_TAG(ifp, m,
1713 ntohs((rxvlan & RL_RDESC_VLANCTL_DATA)));
1714 if (m == NULL)
1715 continue;
1716 }
1717 RL_UNLOCK(sc);
1718 (*ifp->if_input)(ifp, m);
1719 RL_LOCK(sc);
1720 }
1721
1722 /* Flush the RX DMA ring */
1723
1724 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag,
1725 sc->rl_ldata.rl_rx_list_map,
1726 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1727
1728 sc->rl_ldata.rl_rx_prodidx = i;
1729
1730 if (maxpkt)
1731 return(EAGAIN);
1732
1733 return(0);
1691}
1692
1693static void
1694re_txeof(sc)
1695 struct rl_softc *sc;
1696{
1697 struct ifnet *ifp;
1698 u_int32_t txstat;
1699 int idx;
1700
1701 ifp = sc->rl_ifp;
1702 idx = sc->rl_ldata.rl_tx_considx;
1703
1704 /* Invalidate the TX descriptor list */
1705
1706 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1707 sc->rl_ldata.rl_tx_list_map,
1708 BUS_DMASYNC_POSTREAD);
1709
1734}
1735
1736static void
1737re_txeof(sc)
1738 struct rl_softc *sc;
1739{
1740 struct ifnet *ifp;
1741 u_int32_t txstat;
1742 int idx;
1743
1744 ifp = sc->rl_ifp;
1745 idx = sc->rl_ldata.rl_tx_considx;
1746
1747 /* Invalidate the TX descriptor list */
1748
1749 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
1750 sc->rl_ldata.rl_tx_list_map,
1751 BUS_DMASYNC_POSTREAD);
1752
1710 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1753 while (sc->rl_ldata.rl_tx_free < RL_TX_DESC_CNT) {
1711
1712 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1713 if (txstat & RL_TDESC_CMD_OWN)
1714 break;
1715
1754
1755 txstat = le32toh(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1756 if (txstat & RL_TDESC_CMD_OWN)
1757 break;
1758
1759 sc->rl_ldata.rl_tx_list[idx].rl_bufaddr_lo = 0;
1760
1716 /*
1717 * We only stash mbufs in the last descriptor
1718 * in a fragment chain, which also happens to
1719 * be the only place where the TX status bits
1720 * are valid.
1721 */
1722
1723 if (txstat & RL_TDESC_CMD_EOF) {

--- 10 unchanged lines hidden (view full) ---

1734 ifp->if_opackets++;
1735 }
1736 sc->rl_ldata.rl_tx_free++;
1737 RL_DESC_INC(idx);
1738 }
1739
1740 /* No changes made to the TX ring, so no flush needed */
1741
1761 /*
1762 * We only stash mbufs in the last descriptor
1763 * in a fragment chain, which also happens to
1764 * be the only place where the TX status bits
1765 * are valid.
1766 */
1767
1768 if (txstat & RL_TDESC_CMD_EOF) {

--- 10 unchanged lines hidden (view full) ---

1779 ifp->if_opackets++;
1780 }
1781 sc->rl_ldata.rl_tx_free++;
1782 RL_DESC_INC(idx);
1783 }
1784
1785 /* No changes made to the TX ring, so no flush needed */
1786
1742 if (idx != sc->rl_ldata.rl_tx_considx) {
1787 if (sc->rl_ldata.rl_tx_free) {
1743 sc->rl_ldata.rl_tx_considx = idx;
1744 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1745 ifp->if_timer = 0;
1746 }
1747
1788 sc->rl_ldata.rl_tx_considx = idx;
1789 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1790 ifp->if_timer = 0;
1791 }
1792
1793#ifdef RE_TX_MODERATION
1748 /*
1749 * If not all descriptors have been released reaped yet,
1750 * reload the timer so that we will eventually get another
1751 * interrupt that will cause us to re-enter this routine.
1752 * This is done in case the transmitter has gone idle.
1753 */
1754 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1755 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1794 /*
1795 * If not all descriptors have been released reaped yet,
1796 * reload the timer so that we will eventually get another
1797 * interrupt that will cause us to re-enter this routine.
1798 * This is done in case the transmitter has gone idle.
1799 */
1800 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1801 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1802#endif
1756}
1757
1758static void
1759re_tick(xsc)
1760 void *xsc;
1761{
1762 struct rl_softc *sc;
1763 struct mii_data *mii;
1803}
1804
1805static void
1806re_tick(xsc)
1807 void *xsc;
1808{
1809 struct rl_softc *sc;
1810 struct mii_data *mii;
1811 struct ifnet *ifp;
1764
1765 sc = xsc;
1812
1813 sc = xsc;
1814 ifp = sc->rl_ifp;
1766
1767 RL_LOCK_ASSERT(sc);
1768
1769 mii = device_get_softc(sc->rl_miibus);
1770
1771 mii_tick(mii);
1815
1816 RL_LOCK_ASSERT(sc);
1817
1818 mii = device_get_softc(sc->rl_miibus);
1819
1820 mii_tick(mii);
1821 if (sc->rl_link) {
1822 if (!(mii->mii_media_status & IFM_ACTIVE))
1823 sc->rl_link = 0;
1824 } else {
1825 if (mii->mii_media_status & IFM_ACTIVE &&
1826 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1827 sc->rl_link = 1;
1828 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1829 taskqueue_enqueue_fast(taskqueue_fast,
1830 &sc->rl_txtask);
1831 }
1832 }
1772
1773 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1774}
1775
1776#ifdef DEVICE_POLLING
1777static void
1778re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1779{

--- 12 unchanged lines hidden (view full) ---

1792
1793 RL_LOCK_ASSERT(sc);
1794
1795 sc->rxcycles = count;
1796 re_rxeof(sc);
1797 re_txeof(sc);
1798
1799 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1833
1834 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
1835}
1836
1837#ifdef DEVICE_POLLING
1838static void
1839re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1840{

--- 12 unchanged lines hidden (view full) ---

1853
1854 RL_LOCK_ASSERT(sc);
1855
1856 sc->rxcycles = count;
1857 re_rxeof(sc);
1858 re_txeof(sc);
1859
1860 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1800 re_start_locked(ifp);
1861 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
1801
1802 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1803 u_int16_t status;
1804
1805 status = CSR_READ_2(sc, RL_ISR);
1806 if (status == 0xffff)
1807 return;
1808 if (status)

--- 12 unchanged lines hidden (view full) ---

1821#endif /* DEVICE_POLLING */
1822
1823static void
1824re_intr(arg)
1825 void *arg;
1826{
1827 struct rl_softc *sc;
1828 struct ifnet *ifp;
1862
1863 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1864 u_int16_t status;
1865
1866 status = CSR_READ_2(sc, RL_ISR);
1867 if (status == 0xffff)
1868 return;
1869 if (status)

--- 12 unchanged lines hidden (view full) ---

1882#endif /* DEVICE_POLLING */
1883
1884static void
1885re_intr(arg)
1886 void *arg;
1887{
1888 struct rl_softc *sc;
1889 struct ifnet *ifp;
1890 uint16_t status;
1891
1892 sc = arg;
1893 ifp = sc->rl_ifp;
1894
1895 mtx_lock_spin(&sc->rl_intlock);
1896 status = CSR_READ_2(sc, RL_ISR);
1897 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) {
1898 mtx_unlock_spin(&sc->rl_intlock);
1899 return;
1900 }
1901 CSR_WRITE_2(sc, RL_IMR, 0);
1902 mtx_unlock_spin(&sc->rl_intlock);
1903
1904 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1905
1906 return;
1907}
1908
1909static void
1910re_int_task(arg, npending)
1911 void *arg;
1912 int npending;
1913{
1914 struct rl_softc *sc;
1915 struct ifnet *ifp;
1829 u_int16_t status;
1916 u_int16_t status;
1917 int rval = 0;
1830
1831 sc = arg;
1918
1919 sc = arg;
1920 ifp = sc->rl_ifp;
1832
1833 RL_LOCK(sc);
1834
1921
1922 RL_LOCK(sc);
1923
1835 ifp = sc->rl_ifp;
1924 status = CSR_READ_2(sc, RL_ISR);
1925 CSR_WRITE_2(sc, RL_ISR, status);
1836
1926
1837 if (sc->suspended || !(ifp->if_flags & IFF_UP))
1838 goto done_locked;
1927 if (sc->suspended || !(ifp->if_flags & IFF_UP)) {
1928 RL_UNLOCK(sc);
1929 return;
1930 }
1839
1840#ifdef DEVICE_POLLING
1931
1932#ifdef DEVICE_POLLING
1841 if (ifp->if_capenable & IFCAP_POLLING)
1842 goto done_locked;
1933 if (ifp->if_capenable & IFCAP_POLLING) {
1934 RL_UNLOCK(sc);
1935 return;
1936 }
1843#endif
1844
1937#endif
1938
1845 for (;;) {
1939 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW))
1940 rval = re_rxeof(sc);
1846
1941
1847 status = CSR_READ_2(sc, RL_ISR);
1848 /* If the card has gone away the read returns 0xffff. */
1849 if (status == 0xffff)
1850 break;
1851 if (status)
1852 CSR_WRITE_2(sc, RL_ISR, status);
1942#ifdef RE_TX_MODERATION
1943 if (status & (RL_ISR_TIMEOUT_EXPIRED|
1944#else
1945 if (status & (RL_ISR_TX_OK|
1946#endif
1947 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL))
1948 re_txeof(sc);
1853
1949
1854 if ((status & RL_INTRS_CPLUS) == 0)
1855 break;
1950 if (status & RL_ISR_SYSTEM_ERR) {
1951 re_reset(sc);
1952 re_init_locked(sc);
1953 }
1856
1954
1857 if (((status & RL_ISR_RX_OK) ||
1858 (status & RL_ISR_RX_ERR)) &&
1859 ifp->if_drv_flags & IFF_DRV_RUNNING)
1860 re_rxeof(sc);
1955 if (status & RL_ISR_LINKCHG) {
1956 callout_stop(&sc->rl_stat_callout);
1957 re_tick(sc);
1958 }
1861
1959
1862 if (((status & RL_ISR_TIMEOUT_EXPIRED) ||
1863 (status & RL_ISR_TX_ERR) ||
1864 (status & RL_ISR_TX_DESC_UNAVAIL)) &&
1865 ifp->if_drv_flags & IFF_DRV_RUNNING)
1866 re_txeof(sc);
1960 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1961 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_txtask);
1867
1962
1868 if (status & RL_ISR_SYSTEM_ERR) {
1869 re_reset(sc);
1870 re_init_locked(sc);
1871 }
1963 RL_UNLOCK(sc);
1872
1964
1873 if (status & RL_ISR_LINKCHG) {
1874 callout_stop(&sc->rl_stat_callout);
1875 re_tick(sc);
1876 }
1965 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) {
1966 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask);
1967 return;
1877 }
1878
1968 }
1969
1879 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1880 re_start_locked(ifp);
1970 mtx_lock_spin(&sc->rl_intlock);
1971 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1972 mtx_unlock_spin(&sc->rl_intlock);
1881
1973
1882done_locked:
1883 RL_UNLOCK(sc);
1974 return;
1884}
1885
1886static int
1887re_encap(sc, m_head, idx)
1888 struct rl_softc *sc;
1889 struct mbuf **m_head;
1890 int *idx;
1891{

--- 89 unchanged lines hidden (view full) ---

1981 /* Transfer ownership of packet to the chip. */
1982
1983 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
1984 htole32(RL_TDESC_CMD_OWN);
1985 if (*idx != arg.rl_idx)
1986 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1987 htole32(RL_TDESC_CMD_OWN);
1988
1975}
1976
1977static int
1978re_encap(sc, m_head, idx)
1979 struct rl_softc *sc;
1980 struct mbuf **m_head;
1981 int *idx;
1982{

--- 89 unchanged lines hidden (view full) ---

2072 /* Transfer ownership of packet to the chip. */
2073
2074 sc->rl_ldata.rl_tx_list[arg.rl_idx].rl_cmdstat |=
2075 htole32(RL_TDESC_CMD_OWN);
2076 if (*idx != arg.rl_idx)
2077 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
2078 htole32(RL_TDESC_CMD_OWN);
2079
1989 RL_DESC_INC(arg.rl_idx);
2080 RL_DESC_INC(arg.rl_idx);
1990 *idx = arg.rl_idx;
1991
1992 return (0);
1993}
1994
1995static void
2081 *idx = arg.rl_idx;
2082
2083 return (0);
2084}
2085
2086static void
1996re_start(ifp)
1997 struct ifnet *ifp;
2087re_tx_task(arg, npending)
2088 void *arg;
2089 int npending;
1998{
2090{
1999 struct rl_softc *sc;
2091 struct ifnet *ifp;
2000
2092
2001 sc = ifp->if_softc;
2002 RL_LOCK(sc);
2003 re_start_locked(ifp);
2004 RL_UNLOCK(sc);
2093 ifp = arg;
2094 re_start(ifp);
2095
2096 return;
2005}
2006
2007/*
2008 * Main transmit routine for C+ and gigE NICs.
2009 */
2010static void
2097}
2098
2099/*
2100 * Main transmit routine for C+ and gigE NICs.
2101 */
2102static void
2011re_start_locked(ifp)
2103re_start(ifp)
2012 struct ifnet *ifp;
2013{
2014 struct rl_softc *sc;
2015 struct mbuf *m_head = NULL;
2016 int idx, queued = 0;
2017
2018 sc = ifp->if_softc;
2019
2104 struct ifnet *ifp;
2105{
2106 struct rl_softc *sc;
2107 struct mbuf *m_head = NULL;
2108 int idx, queued = 0;
2109
2110 sc = ifp->if_softc;
2111
2020 RL_LOCK_ASSERT(sc);
2112 RL_LOCK(sc);
2021
2113
2114 if (!sc->rl_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) {
2115 RL_UNLOCK(sc);
2116 return;
2117 }
2118
2022 idx = sc->rl_ldata.rl_tx_prodidx;
2023
2024 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2025 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2026 if (m_head == NULL)
2027 break;
2028
2029 if (re_encap(sc, &m_head, &idx)) {

--- 6 unchanged lines hidden (view full) ---

2036 * If there's a BPF listener, bounce a copy of this frame
2037 * to him.
2038 */
2039 BPF_MTAP(ifp, m_head);
2040
2041 queued++;
2042 }
2043
2119 idx = sc->rl_ldata.rl_tx_prodidx;
2120
2121 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
2122 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2123 if (m_head == NULL)
2124 break;
2125
2126 if (re_encap(sc, &m_head, &idx)) {

--- 6 unchanged lines hidden (view full) ---

2133 * If there's a BPF listener, bounce a copy of this frame
2134 * to him.
2135 */
2136 BPF_MTAP(ifp, m_head);
2137
2138 queued++;
2139 }
2140
2044 if (queued == 0)
2141 if (queued == 0) {
2142#ifdef RE_TX_MODERATION
2143 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
2144 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2145#endif
2146 RL_UNLOCK(sc);
2045 return;
2147 return;
2148 }
2046
2047 /* Flush the TX descriptors */
2048
2049 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2050 sc->rl_ldata.rl_tx_list_map,
2051 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2052
2053 sc->rl_ldata.rl_tx_prodidx = idx;
2054
2055 /*
2056 * RealTek put the TX poll request register in a different
2057 * location on the 8169 gigE chip. I don't know why.
2058 */
2059
2149
2150 /* Flush the TX descriptors */
2151
2152 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag,
2153 sc->rl_ldata.rl_tx_list_map,
2154 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2155
2156 sc->rl_ldata.rl_tx_prodidx = idx;
2157
2158 /*
2159 * RealTek put the TX poll request register in a different
2160 * location on the 8169 gigE chip. I don't know why.
2161 */
2162
2060 if (sc->rl_type == RL_8169)
2061 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
2062 else
2063 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
2163 CSR_WRITE_2(sc, sc->rl_txstart, RL_TXSTART_START);
2064
2164
2165#ifdef RE_TX_MODERATION
2065 /*
2066 * Use the countdown timer for interrupt moderation.
2067 * 'TX done' interrupts are disabled. Instead, we reset the
2068 * countdown timer, which will begin counting until it hits
2069 * the value in the TIMERINT register, and then trigger an
2070 * interrupt. Each time we write to the TIMERCNT register,
2071 * the timer count is reset to 0.
2072 */
2073 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2166 /*
2167 * Use the countdown timer for interrupt moderation.
2168 * 'TX done' interrupts are disabled. Instead, we reset the
2169 * countdown timer, which will begin counting until it hits
2170 * the value in the TIMERINT register, and then trigger an
2171 * interrupt. Each time we write to the TIMERCNT register,
2172 * the timer count is reset to 0.
2173 */
2174 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
2175#endif
2074
2075 /*
2076 * Set a timeout in case the chip goes out to lunch.
2077 */
2176
2177 /*
2178 * Set a timeout in case the chip goes out to lunch.
2179 */
2180
2078 ifp->if_timer = 5;
2181 ifp->if_timer = 5;
2182
2183 RL_UNLOCK(sc);
2184
2185 return;
2079}
2080
2081static void
2082re_init(xsc)
2083 void *xsc;
2084{
2085 struct rl_softc *sc = xsc;
2086

--- 7 unchanged lines hidden (view full) ---

2094 struct rl_softc *sc;
2095{
2096 struct ifnet *ifp = sc->rl_ifp;
2097 struct mii_data *mii;
2098 u_int32_t rxcfg = 0;
2099 union {
2100 uint32_t align_dummy;
2101 u_char eaddr[ETHER_ADDR_LEN];
2186}
2187
2188static void
2189re_init(xsc)
2190 void *xsc;
2191{
2192 struct rl_softc *sc = xsc;
2193

--- 7 unchanged lines hidden (view full) ---

2201 struct rl_softc *sc;
2202{
2203 struct ifnet *ifp = sc->rl_ifp;
2204 struct mii_data *mii;
2205 u_int32_t rxcfg = 0;
2206 union {
2207 uint32_t align_dummy;
2208 u_char eaddr[ETHER_ADDR_LEN];
2102 } eaddr;
2209 } eaddr;
2103
2104 RL_LOCK_ASSERT(sc);
2105
2106 mii = device_get_softc(sc->rl_miibus);
2107
2108 /*
2109 * Cancel pending I/O and free all RX/TX buffers.
2110 */
2111 re_stop(sc);
2112
2113 /*
2114 * Enable C+ RX and TX mode, as well as VLAN stripping and
2115 * RX checksum offload. We must configure the C+ register
2116 * before all others.
2117 */
2118 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2119 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2210
2211 RL_LOCK_ASSERT(sc);
2212
2213 mii = device_get_softc(sc->rl_miibus);
2214
2215 /*
2216 * Cancel pending I/O and free all RX/TX buffers.
2217 */
2218 re_stop(sc);
2219
2220 /*
2221 * Enable C+ RX and TX mode, as well as VLAN stripping and
2222 * RX checksum offload. We must configure the C+ register
2223 * before all others.
2224 */
2225 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
2226 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
2120 RL_CPLUSCMD_VLANSTRIP|
2121 (ifp->if_capenable & IFCAP_RXCSUM ?
2122 RL_CPLUSCMD_RXCSUM_ENB : 0));
2227 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
2123
2124 /*
2125 * Init our MAC address. Even though the chipset
2126 * documentation doesn't mention it, we need to enter "Config
2127 * register write enable" mode to modify the ID registers.
2128 */
2129 /* Copy MAC address on stack to align. */
2130 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2131 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2228
2229 /*
2230 * Init our MAC address. Even though the chipset
2231 * documentation doesn't mention it, we need to enter "Config
2232 * register write enable" mode to modify the ID registers.
2233 */
2234 /* Copy MAC address on stack to align. */
2235 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN);
2236 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
2132 CSR_WRITE_STREAM_4(sc, RL_IDR0,
2133 *(u_int32_t *)(&eaddr.eaddr[0]));
2134 CSR_WRITE_STREAM_4(sc, RL_IDR4,
2135 *(u_int32_t *)(&eaddr.eaddr[4]));
2237 CSR_WRITE_4(sc, RL_IDR0,
2238 htole32(*(u_int32_t *)(&eaddr.eaddr[0])));
2239 CSR_WRITE_4(sc, RL_IDR4,
2240 htole32(*(u_int32_t *)(&eaddr.eaddr[4])));
2136 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2137
2138 /*
2139 * For C+ mode, initialize the RX descriptors and mbufs.
2140 */
2141 re_rx_list_init(sc);
2142 re_tx_list_init(sc);
2143

--- 44 unchanged lines hidden (view full) ---

2188#ifdef DEVICE_POLLING
2189 /*
2190 * Disable interrupts if we are polling.
2191 */
2192 if (ifp->if_capenable & IFCAP_POLLING)
2193 CSR_WRITE_2(sc, RL_IMR, 0);
2194 else /* otherwise ... */
2195#endif
2241 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
2242
2243 /*
2244 * For C+ mode, initialize the RX descriptors and mbufs.
2245 */
2246 re_rx_list_init(sc);
2247 re_tx_list_init(sc);
2248

--- 44 unchanged lines hidden (view full) ---

2293#ifdef DEVICE_POLLING
2294 /*
2295 * Disable interrupts if we are polling.
2296 */
2297 if (ifp->if_capenable & IFCAP_POLLING)
2298 CSR_WRITE_2(sc, RL_IMR, 0);
2299 else /* otherwise ... */
2300#endif
2301
2196 /*
2197 * Enable interrupts.
2198 */
2302 /*
2303 * Enable interrupts.
2304 */
2305 mtx_lock_spin(&sc->rl_intlock);
2199 if (sc->rl_testmode)
2200 CSR_WRITE_2(sc, RL_IMR, 0);
2201 else
2202 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2306 if (sc->rl_testmode)
2307 CSR_WRITE_2(sc, RL_IMR, 0);
2308 else
2309 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2310 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS);
2311 mtx_unlock_spin(&sc->rl_intlock);
2203
2204 /* Set initial TX threshold */
2205 sc->rl_txthresh = RL_TX_THRESH_INIT;
2206
2207 /* Start RX/TX process. */
2208 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2209#ifdef notdef
2210 /* Enable receiver and transmitter. */

--- 10 unchanged lines hidden (view full) ---

2221
2222 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2223 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2224 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2225 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2226
2227 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2228
2312
2313 /* Set initial TX threshold */
2314 sc->rl_txthresh = RL_TX_THRESH_INIT;
2315
2316 /* Start RX/TX process. */
2317 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
2318#ifdef notdef
2319 /* Enable receiver and transmitter. */

--- 10 unchanged lines hidden (view full) ---

2330
2331 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
2332 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr));
2333 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
2334 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr));
2335
2336 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
2337
2338#ifdef RE_TX_MODERATION
2229 /*
2230 * Initialize the timer interrupt register so that
2231 * a timer interrupt will be generated once the timer
2232 * reaches a certain number of ticks. The timer is
2233 * reloaded on each transmit. This gives us TX interrupt
2234 * moderation, which dramatically improves TX frame rate.
2235 */
2236 if (sc->rl_type == RL_8169)
2237 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2238 else
2239 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2339 /*
2340 * Initialize the timer interrupt register so that
2341 * a timer interrupt will be generated once the timer
2342 * reaches a certain number of ticks. The timer is
2343 * reloaded on each transmit. This gives us TX interrupt
2344 * moderation, which dramatically improves TX frame rate.
2345 */
2346 if (sc->rl_type == RL_8169)
2347 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
2348 else
2349 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
2350#endif
2240
2241 /*
2242 * For 8169 gigE NICs, set the max allowed RX packet
2243 * size so we can receive jumbo frames.
2244 */
2245 if (sc->rl_type == RL_8169)
2246 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2247
2248 if (sc->rl_testmode)
2249 return;
2250
2251 mii_mediachg(mii);
2252
2253 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2254
2255 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2256 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2257
2351
2352 /*
2353 * For 8169 gigE NICs, set the max allowed RX packet
2354 * size so we can receive jumbo frames.
2355 */
2356 if (sc->rl_type == RL_8169)
2357 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
2358
2359 if (sc->rl_testmode)
2360 return;
2361
2362 mii_mediachg(mii);
2363
2364 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
2365
2366 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2367 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2368
2369
2370 sc->rl_link = 0;
2371
2258 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2259}
2260
2261/*
2262 * Set media options.
2263 */
2264static int
2265re_ifmedia_upd(ifp)

--- 156 unchanged lines hidden (view full) ---

2422 ifp = sc->rl_ifp;
2423 ifp->if_timer = 0;
2424
2425 callout_stop(&sc->rl_stat_callout);
2426 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2427
2428 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2429 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2372 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc);
2373}
2374
2375/*
2376 * Set media options.
2377 */
2378static int
2379re_ifmedia_upd(ifp)

--- 156 unchanged lines hidden (view full) ---

2536 ifp = sc->rl_ifp;
2537 ifp->if_timer = 0;
2538
2539 callout_stop(&sc->rl_stat_callout);
2540 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2541
2542 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
2543 CSR_WRITE_2(sc, RL_IMR, 0x0000);
2544 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
2430
2431 if (sc->rl_head != NULL) {
2432 m_freem(sc->rl_head);
2433 sc->rl_head = sc->rl_tail = NULL;
2434 }
2435
2436 /* Free the TX list buffers. */
2437

--- 92 unchanged lines hidden --- 		2545
2546 if (sc->rl_head != NULL) {
2547 m_freem(sc->rl_head);
2548 sc->rl_head = sc->rl_tail = NULL;
2549 }
2550
2551 /* Free the TX list buffers. */
2552

--- 92 unchanged lines hidden ---