| pcivar.h (163805) | pcivar.h (164264) |
|---|---|
| 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * | 1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 9 unchanged lines hidden (view full) --- 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * |
| 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 163805 2006-10-30 19:18:46Z imp $ | 26 * $FreeBSD: head/sys/dev/pci/pcivar.h 164264 2006-11-13 21:47:30Z jhb $ |
| 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 --- 37 unchanged lines hidden (view full) --- 72 struct vpd_readonly *vpd_ros; 73 int vpd_wcnt; 74 struct vpd_write *vpd_w; 75}; 76 77/* Interesting values for PCI MSI */ 78struct pcicfg_msi { 79 uint16_t msi_ctrl; /* Message Control */ | 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 --- 37 unchanged lines hidden (view full) --- 72 struct vpd_readonly *vpd_ros; 73 int vpd_wcnt; 74 struct vpd_write *vpd_w; 75}; 76 77/* Interesting values for PCI MSI */ 78struct pcicfg_msi { 79 uint16_t msi_ctrl; /* Message Control */ |
| 80 uint8_t msi_location; /* Offset of MSI capability registers. */ |
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| 80 uint8_t msi_msgnum; /* Number of messages */ | 81 uint8_t msi_msgnum; /* Number of messages */ |
| 81 uint16_t msi_data; /* Location of MSI data word */ | 82 int msi_alloc; /* Number of allocated messages. */ 83 uint64_t msi_addr; /* Contents of address register. */ 84 uint16_t msi_data; /* Contents of data register. */ |
| 82}; 83 | 85}; 86 |
| 87/* Interesting values for PCI MSI */ 88struct pcicfg_msix { 89 uint16_t msix_ctrl; /* Message Control */ 90 uint8_t msix_location; /* Offset of MSI capability registers. */ 91 uint16_t msix_msgnum; /* Number of messages */ 92 int msix_alloc; /* Number of allocated messages. */ 93 uint8_t msix_table_bar; /* BAR containing vector table. */ 94 uint8_t msix_pba_bar; /* BAR containing PBA. */ 95 uint32_t msix_table_offset; 96 uint32_t msix_pba_offset; 97 struct resource *msix_table_res; /* Resource containing vector table. */ 98 struct resource *msix_pba_res; /* Resource containing PBA. */ 99}; 100 |
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| 84/* config header information common to all header types */ 85typedef struct pcicfg { 86 struct device *dev; /* device which owns this */ 87 88 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 89 uint32_t bios; /* BIOS mapping */ 90 91 uint16_t subvendor; /* card vendor ID */ --- 23 unchanged lines hidden (view full) --- 115 116 uint8_t bus; /* config space bus address */ 117 uint8_t slot; /* config space slot address */ 118 uint8_t func; /* config space function number */ 119 120 struct pcicfg_pp pp; /* pci power management */ 121 struct pcicfg_vpd vpd; /* pci vital product data */ 122 struct pcicfg_msi msi; /* pci msi */ | 101/* config header information common to all header types */ 102typedef struct pcicfg { 103 struct device *dev; /* device which owns this */ 104 105 uint32_t bar[PCI_MAXMAPS_0]; /* BARs */ 106 uint32_t bios; /* BIOS mapping */ 107 108 uint16_t subvendor; /* card vendor ID */ --- 23 unchanged lines hidden (view full) --- 132 133 uint8_t bus; /* config space bus address */ 134 uint8_t slot; /* config space slot address */ 135 uint8_t func; /* config space function number */ 136 137 struct pcicfg_pp pp; /* pci power management */ 138 struct pcicfg_vpd vpd; /* pci vital product data */ 139 struct pcicfg_msi msi; /* pci msi */ |
| 140 struct pcicfg_msix msix; /* pci msi-x */ |
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| 123} pcicfgregs; 124 125/* additional type 1 device config header information (PCI to PCI bridge) */ 126 127#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 128#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 129#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 130#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) --- 235 unchanged lines hidden (view full) --- 366} 367 368static __inline int 369pci_find_extcap(device_t dev, int capability, int *capreg) 370{ 371 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 372} 373 | 141} pcicfgregs; 142 143/* additional type 1 device config header information (PCI to PCI bridge) */ 144 145#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 146#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 147#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 148#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) --- 235 unchanged lines hidden (view full) --- 384} 385 386static __inline int 387pci_find_extcap(device_t dev, int capability, int *capreg) 388{ 389 return PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg); 390} 391 |
| 392static __inline int 393pci_alloc_msi(device_t dev, int *count) 394{ 395 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 396} 397 398static __inline int 399pci_release_msi(device_t dev) 400{ 401 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 402} 403 404static __inline int 405pci_msi_count(device_t dev) 406{ 407 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 408} 409 |
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| 374device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 375device_t pci_find_device(uint16_t, uint16_t); | 410device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 411device_t pci_find_device(uint16_t, uint16_t); |
| 412 413/* Used by MD code to program MSI and MSI-X registers. */ 414void pci_enable_msi(device_t dev, uint64_t address, uint16_t data); 415void pci_enable_msix(device_t dev, u_int index, uint64_t address, 416 uint32_t data); 417void pci_mask_msix(device_t dev, u_int index); 418int pci_pending_msix(device_t dev, u_int index); 419void pci_unmask_msix(device_t dev, u_int index); 420 |
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| 376#endif /* _SYS_BUS_H_ */ 377 378/* 379 * cdev switch for control device, initialised in generic PCI code 380 */ 381extern struct cdevsw pcicdev; 382 383/* 384 * List of all PCI devices, generation count for the list. 385 */ 386STAILQ_HEAD(devlist, pci_devinfo); 387 388extern struct devlist pci_devq; 389extern uint32_t pci_generation; 390 391#endif /* _PCIVAR_H_ */ | 421#endif /* _SYS_BUS_H_ */ 422 423/* 424 * cdev switch for control device, initialised in generic PCI code 425 */ 426extern struct cdevsw pcicdev; 427 428/* 429 * List of all PCI devices, generation count for the list. 430 */ 431STAILQ_HEAD(devlist, pci_devinfo); 432 433extern struct devlist pci_devq; 434extern uint32_t pci_generation; 435 436#endif /* _PCIVAR_H_ */ |