1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
| 1/*-
2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
4 * Copyright (c) 2000 BSDi
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
|
32__FBSDID("$FreeBSD: stable/10/sys/dev/pci/pci_pci.c 279470 2015-03-01 04:22:06Z rstone $");
| 32__FBSDID("$FreeBSD: stable/10/sys/dev/pci/pci_pci.c 280970 2015-04-01 21:48:54Z jhb $");
|
33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/malloc.h>
42#include <sys/module.h>
43#include <sys/rman.h>
44#include <sys/sysctl.h>
45#include <sys/systm.h>
46
47#include <dev/pci/pcivar.h>
48#include <dev/pci/pcireg.h>
49#include <dev/pci/pci_private.h>
50#include <dev/pci/pcib_private.h>
51
52#include "pcib_if.h"
53
54static int pcib_probe(device_t dev);
55static int pcib_suspend(device_t dev);
56static int pcib_resume(device_t dev);
57static int pcib_power_for_sleep(device_t pcib, device_t dev,
58 int *pstate);
59static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev);
60static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
61 u_int f, u_int reg, int width);
62static void pcib_write_config(device_t dev, u_int b, u_int s,
63 u_int f, u_int reg, uint32_t val, int width);
64static int pcib_ari_maxslots(device_t dev);
65static int pcib_ari_maxfuncs(device_t dev);
66static int pcib_try_enable_ari(device_t pcib, device_t dev);
67
68static device_method_t pcib_methods[] = {
69 /* Device interface */
70 DEVMETHOD(device_probe, pcib_probe),
71 DEVMETHOD(device_attach, pcib_attach),
72 DEVMETHOD(device_detach, bus_generic_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 DEVMETHOD(device_suspend, pcib_suspend),
75 DEVMETHOD(device_resume, pcib_resume),
76
77 /* Bus interface */
78 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
79 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
80 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
81#ifdef NEW_PCIB
82 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
83 DEVMETHOD(bus_release_resource, pcib_release_resource),
84#else
85 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
86 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
87#endif
88 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
89 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
90 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
91 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
92
93 /* pcib interface */
94 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
95 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
96 DEVMETHOD(pcib_read_config, pcib_read_config),
97 DEVMETHOD(pcib_write_config, pcib_write_config),
98 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
99 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
100 DEVMETHOD(pcib_release_msi, pcib_release_msi),
101 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
102 DEVMETHOD(pcib_release_msix, pcib_release_msix),
103 DEVMETHOD(pcib_map_msi, pcib_map_msi),
104 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
105 DEVMETHOD(pcib_get_rid, pcib_ari_get_rid),
106 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
107
108 DEVMETHOD_END
109};
110
111static devclass_t pcib_devclass;
112
113DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
114DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
115
116#ifdef NEW_PCIB
117SYSCTL_DECL(_hw_pci);
118
119static int pci_clear_pcib;
120TUNABLE_INT("hw.pci.clear_pcib", &pci_clear_pcib);
121SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
122 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
123
124/*
125 * Is a resource from a child device sub-allocated from one of our
126 * resource managers?
127 */
128static int
129pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
130{
131
132 switch (type) {
| 33
34/*
35 * PCI:PCI bridge support.
36 */
37
38#include <sys/param.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/malloc.h>
42#include <sys/module.h>
43#include <sys/rman.h>
44#include <sys/sysctl.h>
45#include <sys/systm.h>
46
47#include <dev/pci/pcivar.h>
48#include <dev/pci/pcireg.h>
49#include <dev/pci/pci_private.h>
50#include <dev/pci/pcib_private.h>
51
52#include "pcib_if.h"
53
54static int pcib_probe(device_t dev);
55static int pcib_suspend(device_t dev);
56static int pcib_resume(device_t dev);
57static int pcib_power_for_sleep(device_t pcib, device_t dev,
58 int *pstate);
59static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev);
60static uint32_t pcib_read_config(device_t dev, u_int b, u_int s,
61 u_int f, u_int reg, int width);
62static void pcib_write_config(device_t dev, u_int b, u_int s,
63 u_int f, u_int reg, uint32_t val, int width);
64static int pcib_ari_maxslots(device_t dev);
65static int pcib_ari_maxfuncs(device_t dev);
66static int pcib_try_enable_ari(device_t pcib, device_t dev);
67
68static device_method_t pcib_methods[] = {
69 /* Device interface */
70 DEVMETHOD(device_probe, pcib_probe),
71 DEVMETHOD(device_attach, pcib_attach),
72 DEVMETHOD(device_detach, bus_generic_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 DEVMETHOD(device_suspend, pcib_suspend),
75 DEVMETHOD(device_resume, pcib_resume),
76
77 /* Bus interface */
78 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
79 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
80 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
81#ifdef NEW_PCIB
82 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource),
83 DEVMETHOD(bus_release_resource, pcib_release_resource),
84#else
85 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
86 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
87#endif
88 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
89 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
90 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
91 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
92
93 /* pcib interface */
94 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots),
95 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs),
96 DEVMETHOD(pcib_read_config, pcib_read_config),
97 DEVMETHOD(pcib_write_config, pcib_write_config),
98 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
99 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
100 DEVMETHOD(pcib_release_msi, pcib_release_msi),
101 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
102 DEVMETHOD(pcib_release_msix, pcib_release_msix),
103 DEVMETHOD(pcib_map_msi, pcib_map_msi),
104 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep),
105 DEVMETHOD(pcib_get_rid, pcib_ari_get_rid),
106 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari),
107
108 DEVMETHOD_END
109};
110
111static devclass_t pcib_devclass;
112
113DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc));
114DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL);
115
116#ifdef NEW_PCIB
117SYSCTL_DECL(_hw_pci);
118
119static int pci_clear_pcib;
120TUNABLE_INT("hw.pci.clear_pcib", &pci_clear_pcib);
121SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0,
122 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows.");
123
124/*
125 * Is a resource from a child device sub-allocated from one of our
126 * resource managers?
127 */
128static int
129pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r)
130{
131
132 switch (type) {
|
| 133#ifdef PCI_RES_BUS
134 case PCI_RES_BUS:
135 return (rman_is_region_manager(r, &sc->bus.rman));
136#endif
|
133 case SYS_RES_IOPORT:
134 return (rman_is_region_manager(r, &sc->io.rman));
135 case SYS_RES_MEMORY:
136 /* Prefetchable resources may live in either memory rman. */
137 if (rman_get_flags(r) & RF_PREFETCHABLE &&
138 rman_is_region_manager(r, &sc->pmem.rman))
139 return (1);
140 return (rman_is_region_manager(r, &sc->mem.rman));
141 }
142 return (0);
143}
144
145static int
146pcib_is_window_open(struct pcib_window *pw)
147{
148
149 return (pw->valid && pw->base < pw->limit);
150}
151
152/*
153 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
154 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
155 * when allocating the resource windows and rely on the PCI bus driver
156 * to do this for us.
157 */
158static void
159pcib_activate_window(struct pcib_softc *sc, int type)
160{
161
162 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
163}
164
165static void
166pcib_write_windows(struct pcib_softc *sc, int mask)
167{
168 device_t dev;
169 uint32_t val;
170
171 dev = sc->dev;
172 if (sc->io.valid && mask & WIN_IO) {
173 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
174 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
175 pci_write_config(dev, PCIR_IOBASEH_1,
176 sc->io.base >> 16, 2);
177 pci_write_config(dev, PCIR_IOLIMITH_1,
178 sc->io.limit >> 16, 2);
179 }
180 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
181 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
182 }
183
184 if (mask & WIN_MEM) {
185 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
186 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
187 }
188
189 if (sc->pmem.valid && mask & WIN_PMEM) {
190 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
191 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
192 pci_write_config(dev, PCIR_PMBASEH_1,
193 sc->pmem.base >> 32, 4);
194 pci_write_config(dev, PCIR_PMLIMITH_1,
195 sc->pmem.limit >> 32, 4);
196 }
197 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
198 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
199 }
200}
201
202/*
203 * This is used to reject I/O port allocations that conflict with an
204 * ISA alias range.
205 */
206static int
207pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count)
208{
209 u_long next_alias;
210
211 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
212 return (0);
213
214 /* Only check fixed ranges for overlap. */
215 if (start + count - 1 != end)
216 return (0);
217
218 /* ISA aliases are only in the lower 64KB of I/O space. */
219 if (start >= 65536)
220 return (0);
221
222 /* Check for overlap with 0x000 - 0x0ff as a special case. */
223 if (start < 0x100)
224 goto alias;
225
226 /*
227 * If the start address is an alias, the range is an alias.
228 * Otherwise, compute the start of the next alias range and
229 * check if it is before the end of the candidate range.
230 */
231 if ((start & 0x300) != 0)
232 goto alias;
233 next_alias = (start & ~0x3fful) | 0x100;
234 if (next_alias <= end)
235 goto alias;
236 return (0);
237
238alias:
239 if (bootverbose)
240 device_printf(sc->dev,
241 "I/O range %#lx-%#lx overlaps with an ISA alias\n", start,
242 end);
243 return (1);
244}
245
246static void
247pcib_add_window_resources(struct pcib_window *w, struct resource **res,
248 int count)
249{
250 struct resource **newarray;
251 int error, i;
252
253 newarray = malloc(sizeof(struct resource *) * (w->count + count),
254 M_DEVBUF, M_WAITOK);
255 if (w->res != NULL)
256 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
257 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
258 free(w->res, M_DEVBUF);
259 w->res = newarray;
260 w->count += count;
261
262 for (i = 0; i < count; i++) {
263 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
264 rman_get_end(res[i]));
265 if (error)
266 panic("Failed to add resource to rman");
267 }
268}
269
270typedef void (nonisa_callback)(u_long start, u_long end, void *arg);
271
272static void
273pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb,
274 void *arg)
275{
276 u_long next_end;
277
278 /*
279 * If start is within an ISA alias range, move up to the start
280 * of the next non-alias range. As a special case, addresses
281 * in the range 0x000 - 0x0ff should also be skipped since
282 * those are used for various system I/O devices in ISA
283 * systems.
284 */
285 if (start <= 65535) {
286 if (start < 0x100 || (start & 0x300) != 0) {
287 start &= ~0x3ff;
288 start += 0x400;
289 }
290 }
291
292 /* ISA aliases are only in the lower 64KB of I/O space. */
293 while (start <= MIN(end, 65535)) {
294 next_end = MIN(start | 0xff, end);
295 cb(start, next_end, arg);
296 start += 0x400;
297 }
298
299 if (start <= end)
300 cb(start, end, arg);
301}
302
303static void
304count_ranges(u_long start, u_long end, void *arg)
305{
306 int *countp;
307
308 countp = arg;
309 (*countp)++;
310}
311
312struct alloc_state {
313 struct resource **res;
314 struct pcib_softc *sc;
315 int count, error;
316};
317
318static void
319alloc_ranges(u_long start, u_long end, void *arg)
320{
321 struct alloc_state *as;
322 struct pcib_window *w;
323 int rid;
324
325 as = arg;
326 if (as->error != 0)
327 return;
328
329 w = &as->sc->io;
330 rid = w->reg;
331 if (bootverbose)
332 device_printf(as->sc->dev,
333 "allocating non-ISA range %#lx-%#lx\n", start, end);
334 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
335 &rid, start, end, end - start + 1, 0);
336 if (as->res[as->count] == NULL)
337 as->error = ENXIO;
338 else
339 as->count++;
340}
341
342static int
343pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end)
344{
345 struct alloc_state as;
346 int i, new_count;
347
348 /* First, see how many ranges we need. */
349 new_count = 0;
350 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
351
352 /* Second, allocate the ranges. */
353 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
354 M_WAITOK);
355 as.sc = sc;
356 as.count = 0;
357 as.error = 0;
358 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
359 if (as.error != 0) {
360 for (i = 0; i < as.count; i++)
361 bus_release_resource(sc->dev, SYS_RES_IOPORT,
362 sc->io.reg, as.res[i]);
363 free(as.res, M_DEVBUF);
364 return (as.error);
365 }
366 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
367
368 /* Third, add the ranges to the window. */
369 pcib_add_window_resources(&sc->io, as.res, as.count);
370 free(as.res, M_DEVBUF);
371 return (0);
372}
373
374static void
375pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
376 int flags, pci_addr_t max_address)
377{
378 struct resource *res;
379 char buf[64];
380 int error, rid;
381
382 if (max_address != (u_long)max_address)
383 max_address = ~0ul;
384 w->rman.rm_start = 0;
385 w->rman.rm_end = max_address;
386 w->rman.rm_type = RMAN_ARRAY;
387 snprintf(buf, sizeof(buf), "%s %s window",
388 device_get_nameunit(sc->dev), w->name);
389 w->rman.rm_descr = strdup(buf, M_DEVBUF);
390 error = rman_init(&w->rman);
391 if (error)
392 panic("Failed to initialize %s %s rman",
393 device_get_nameunit(sc->dev), w->name);
394
395 if (!pcib_is_window_open(w))
396 return;
397
398 if (w->base > max_address || w->limit > max_address) {
399 device_printf(sc->dev,
400 "initial %s window has too many bits, ignoring\n", w->name);
401 return;
402 }
403 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
404 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
405 else {
406 rid = w->reg;
407 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
408 w->limit - w->base + 1, flags);
409 if (res != NULL)
410 pcib_add_window_resources(w, &res, 1);
411 }
412 if (w->res == NULL) {
413 device_printf(sc->dev,
414 "failed to allocate initial %s window: %#jx-%#jx\n",
415 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
416 w->base = max_address;
417 w->limit = 0;
418 pcib_write_windows(sc, w->mask);
419 return;
420 }
421 pcib_activate_window(sc, type);
422}
423
424/*
425 * Initialize I/O windows.
426 */
427static void
428pcib_probe_windows(struct pcib_softc *sc)
429{
430 pci_addr_t max;
431 device_t dev;
432 uint32_t val;
433
434 dev = sc->dev;
435
436 if (pci_clear_pcib) {
437 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
438 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
439 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
440 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
441 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
442 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
443 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
444 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
445 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
446 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
447 }
448
449 /* Determine if the I/O port window is implemented. */
450 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
451 if (val == 0) {
452 /*
453 * If 'val' is zero, then only 16-bits of I/O space
454 * are supported.
455 */
456 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
457 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
458 sc->io.valid = 1;
459 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
460 }
461 } else
462 sc->io.valid = 1;
463
464 /* Read the existing I/O port window. */
465 if (sc->io.valid) {
466 sc->io.reg = PCIR_IOBASEL_1;
467 sc->io.step = 12;
468 sc->io.mask = WIN_IO;
469 sc->io.name = "I/O port";
470 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
471 sc->io.base = PCI_PPBIOBASE(
472 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
473 sc->io.limit = PCI_PPBIOLIMIT(
474 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
475 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
476 max = 0xffffffff;
477 } else {
478 sc->io.base = PCI_PPBIOBASE(0, val);
479 sc->io.limit = PCI_PPBIOLIMIT(0,
480 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
481 max = 0xffff;
482 }
483 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
484 }
485
486 /* Read the existing memory window. */
487 sc->mem.valid = 1;
488 sc->mem.reg = PCIR_MEMBASE_1;
489 sc->mem.step = 20;
490 sc->mem.mask = WIN_MEM;
491 sc->mem.name = "memory";
492 sc->mem.base = PCI_PPBMEMBASE(0,
493 pci_read_config(dev, PCIR_MEMBASE_1, 2));
494 sc->mem.limit = PCI_PPBMEMLIMIT(0,
495 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
496 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
497
498 /* Determine if the prefetchable memory window is implemented. */
499 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
500 if (val == 0) {
501 /*
502 * If 'val' is zero, then only 32-bits of memory space
503 * are supported.
504 */
505 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
506 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
507 sc->pmem.valid = 1;
508 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
509 }
510 } else
511 sc->pmem.valid = 1;
512
513 /* Read the existing prefetchable memory window. */
514 if (sc->pmem.valid) {
515 sc->pmem.reg = PCIR_PMBASEL_1;
516 sc->pmem.step = 20;
517 sc->pmem.mask = WIN_PMEM;
518 sc->pmem.name = "prefetch";
519 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
520 sc->pmem.base = PCI_PPBMEMBASE(
521 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
522 sc->pmem.limit = PCI_PPBMEMLIMIT(
523 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
524 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
525 max = 0xffffffffffffffff;
526 } else {
527 sc->pmem.base = PCI_PPBMEMBASE(0, val);
528 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
529 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
530 max = 0xffffffff;
531 }
532 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
533 RF_PREFETCHABLE, max);
534 }
535}
536
| 137 case SYS_RES_IOPORT:
138 return (rman_is_region_manager(r, &sc->io.rman));
139 case SYS_RES_MEMORY:
140 /* Prefetchable resources may live in either memory rman. */
141 if (rman_get_flags(r) & RF_PREFETCHABLE &&
142 rman_is_region_manager(r, &sc->pmem.rman))
143 return (1);
144 return (rman_is_region_manager(r, &sc->mem.rman));
145 }
146 return (0);
147}
148
149static int
150pcib_is_window_open(struct pcib_window *pw)
151{
152
153 return (pw->valid && pw->base < pw->limit);
154}
155
156/*
157 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and
158 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus
159 * when allocating the resource windows and rely on the PCI bus driver
160 * to do this for us.
161 */
162static void
163pcib_activate_window(struct pcib_softc *sc, int type)
164{
165
166 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type);
167}
168
169static void
170pcib_write_windows(struct pcib_softc *sc, int mask)
171{
172 device_t dev;
173 uint32_t val;
174
175 dev = sc->dev;
176 if (sc->io.valid && mask & WIN_IO) {
177 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
178 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
179 pci_write_config(dev, PCIR_IOBASEH_1,
180 sc->io.base >> 16, 2);
181 pci_write_config(dev, PCIR_IOLIMITH_1,
182 sc->io.limit >> 16, 2);
183 }
184 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1);
185 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1);
186 }
187
188 if (mask & WIN_MEM) {
189 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2);
190 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2);
191 }
192
193 if (sc->pmem.valid && mask & WIN_PMEM) {
194 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
195 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
196 pci_write_config(dev, PCIR_PMBASEH_1,
197 sc->pmem.base >> 32, 4);
198 pci_write_config(dev, PCIR_PMLIMITH_1,
199 sc->pmem.limit >> 32, 4);
200 }
201 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2);
202 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2);
203 }
204}
205
206/*
207 * This is used to reject I/O port allocations that conflict with an
208 * ISA alias range.
209 */
210static int
211pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count)
212{
213 u_long next_alias;
214
215 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE))
216 return (0);
217
218 /* Only check fixed ranges for overlap. */
219 if (start + count - 1 != end)
220 return (0);
221
222 /* ISA aliases are only in the lower 64KB of I/O space. */
223 if (start >= 65536)
224 return (0);
225
226 /* Check for overlap with 0x000 - 0x0ff as a special case. */
227 if (start < 0x100)
228 goto alias;
229
230 /*
231 * If the start address is an alias, the range is an alias.
232 * Otherwise, compute the start of the next alias range and
233 * check if it is before the end of the candidate range.
234 */
235 if ((start & 0x300) != 0)
236 goto alias;
237 next_alias = (start & ~0x3fful) | 0x100;
238 if (next_alias <= end)
239 goto alias;
240 return (0);
241
242alias:
243 if (bootverbose)
244 device_printf(sc->dev,
245 "I/O range %#lx-%#lx overlaps with an ISA alias\n", start,
246 end);
247 return (1);
248}
249
250static void
251pcib_add_window_resources(struct pcib_window *w, struct resource **res,
252 int count)
253{
254 struct resource **newarray;
255 int error, i;
256
257 newarray = malloc(sizeof(struct resource *) * (w->count + count),
258 M_DEVBUF, M_WAITOK);
259 if (w->res != NULL)
260 bcopy(w->res, newarray, sizeof(struct resource *) * w->count);
261 bcopy(res, newarray + w->count, sizeof(struct resource *) * count);
262 free(w->res, M_DEVBUF);
263 w->res = newarray;
264 w->count += count;
265
266 for (i = 0; i < count; i++) {
267 error = rman_manage_region(&w->rman, rman_get_start(res[i]),
268 rman_get_end(res[i]));
269 if (error)
270 panic("Failed to add resource to rman");
271 }
272}
273
274typedef void (nonisa_callback)(u_long start, u_long end, void *arg);
275
276static void
277pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb,
278 void *arg)
279{
280 u_long next_end;
281
282 /*
283 * If start is within an ISA alias range, move up to the start
284 * of the next non-alias range. As a special case, addresses
285 * in the range 0x000 - 0x0ff should also be skipped since
286 * those are used for various system I/O devices in ISA
287 * systems.
288 */
289 if (start <= 65535) {
290 if (start < 0x100 || (start & 0x300) != 0) {
291 start &= ~0x3ff;
292 start += 0x400;
293 }
294 }
295
296 /* ISA aliases are only in the lower 64KB of I/O space. */
297 while (start <= MIN(end, 65535)) {
298 next_end = MIN(start | 0xff, end);
299 cb(start, next_end, arg);
300 start += 0x400;
301 }
302
303 if (start <= end)
304 cb(start, end, arg);
305}
306
307static void
308count_ranges(u_long start, u_long end, void *arg)
309{
310 int *countp;
311
312 countp = arg;
313 (*countp)++;
314}
315
316struct alloc_state {
317 struct resource **res;
318 struct pcib_softc *sc;
319 int count, error;
320};
321
322static void
323alloc_ranges(u_long start, u_long end, void *arg)
324{
325 struct alloc_state *as;
326 struct pcib_window *w;
327 int rid;
328
329 as = arg;
330 if (as->error != 0)
331 return;
332
333 w = &as->sc->io;
334 rid = w->reg;
335 if (bootverbose)
336 device_printf(as->sc->dev,
337 "allocating non-ISA range %#lx-%#lx\n", start, end);
338 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT,
339 &rid, start, end, end - start + 1, 0);
340 if (as->res[as->count] == NULL)
341 as->error = ENXIO;
342 else
343 as->count++;
344}
345
346static int
347pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end)
348{
349 struct alloc_state as;
350 int i, new_count;
351
352 /* First, see how many ranges we need. */
353 new_count = 0;
354 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count);
355
356 /* Second, allocate the ranges. */
357 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF,
358 M_WAITOK);
359 as.sc = sc;
360 as.count = 0;
361 as.error = 0;
362 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as);
363 if (as.error != 0) {
364 for (i = 0; i < as.count; i++)
365 bus_release_resource(sc->dev, SYS_RES_IOPORT,
366 sc->io.reg, as.res[i]);
367 free(as.res, M_DEVBUF);
368 return (as.error);
369 }
370 KASSERT(as.count == new_count, ("%s: count mismatch", __func__));
371
372 /* Third, add the ranges to the window. */
373 pcib_add_window_resources(&sc->io, as.res, as.count);
374 free(as.res, M_DEVBUF);
375 return (0);
376}
377
378static void
379pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type,
380 int flags, pci_addr_t max_address)
381{
382 struct resource *res;
383 char buf[64];
384 int error, rid;
385
386 if (max_address != (u_long)max_address)
387 max_address = ~0ul;
388 w->rman.rm_start = 0;
389 w->rman.rm_end = max_address;
390 w->rman.rm_type = RMAN_ARRAY;
391 snprintf(buf, sizeof(buf), "%s %s window",
392 device_get_nameunit(sc->dev), w->name);
393 w->rman.rm_descr = strdup(buf, M_DEVBUF);
394 error = rman_init(&w->rman);
395 if (error)
396 panic("Failed to initialize %s %s rman",
397 device_get_nameunit(sc->dev), w->name);
398
399 if (!pcib_is_window_open(w))
400 return;
401
402 if (w->base > max_address || w->limit > max_address) {
403 device_printf(sc->dev,
404 "initial %s window has too many bits, ignoring\n", w->name);
405 return;
406 }
407 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE)
408 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit);
409 else {
410 rid = w->reg;
411 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit,
412 w->limit - w->base + 1, flags);
413 if (res != NULL)
414 pcib_add_window_resources(w, &res, 1);
415 }
416 if (w->res == NULL) {
417 device_printf(sc->dev,
418 "failed to allocate initial %s window: %#jx-%#jx\n",
419 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
420 w->base = max_address;
421 w->limit = 0;
422 pcib_write_windows(sc, w->mask);
423 return;
424 }
425 pcib_activate_window(sc, type);
426}
427
428/*
429 * Initialize I/O windows.
430 */
431static void
432pcib_probe_windows(struct pcib_softc *sc)
433{
434 pci_addr_t max;
435 device_t dev;
436 uint32_t val;
437
438 dev = sc->dev;
439
440 if (pci_clear_pcib) {
441 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
442 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2);
443 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1);
444 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2);
445 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2);
446 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2);
447 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
448 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4);
449 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2);
450 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4);
451 }
452
453 /* Determine if the I/O port window is implemented. */
454 val = pci_read_config(dev, PCIR_IOBASEL_1, 1);
455 if (val == 0) {
456 /*
457 * If 'val' is zero, then only 16-bits of I/O space
458 * are supported.
459 */
460 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1);
461 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) {
462 sc->io.valid = 1;
463 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1);
464 }
465 } else
466 sc->io.valid = 1;
467
468 /* Read the existing I/O port window. */
469 if (sc->io.valid) {
470 sc->io.reg = PCIR_IOBASEL_1;
471 sc->io.step = 12;
472 sc->io.mask = WIN_IO;
473 sc->io.name = "I/O port";
474 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) {
475 sc->io.base = PCI_PPBIOBASE(
476 pci_read_config(dev, PCIR_IOBASEH_1, 2), val);
477 sc->io.limit = PCI_PPBIOLIMIT(
478 pci_read_config(dev, PCIR_IOLIMITH_1, 2),
479 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
480 max = 0xffffffff;
481 } else {
482 sc->io.base = PCI_PPBIOBASE(0, val);
483 sc->io.limit = PCI_PPBIOLIMIT(0,
484 pci_read_config(dev, PCIR_IOLIMITL_1, 1));
485 max = 0xffff;
486 }
487 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max);
488 }
489
490 /* Read the existing memory window. */
491 sc->mem.valid = 1;
492 sc->mem.reg = PCIR_MEMBASE_1;
493 sc->mem.step = 20;
494 sc->mem.mask = WIN_MEM;
495 sc->mem.name = "memory";
496 sc->mem.base = PCI_PPBMEMBASE(0,
497 pci_read_config(dev, PCIR_MEMBASE_1, 2));
498 sc->mem.limit = PCI_PPBMEMLIMIT(0,
499 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
500 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff);
501
502 /* Determine if the prefetchable memory window is implemented. */
503 val = pci_read_config(dev, PCIR_PMBASEL_1, 2);
504 if (val == 0) {
505 /*
506 * If 'val' is zero, then only 32-bits of memory space
507 * are supported.
508 */
509 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2);
510 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) {
511 sc->pmem.valid = 1;
512 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2);
513 }
514 } else
515 sc->pmem.valid = 1;
516
517 /* Read the existing prefetchable memory window. */
518 if (sc->pmem.valid) {
519 sc->pmem.reg = PCIR_PMBASEL_1;
520 sc->pmem.step = 20;
521 sc->pmem.mask = WIN_PMEM;
522 sc->pmem.name = "prefetch";
523 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) {
524 sc->pmem.base = PCI_PPBMEMBASE(
525 pci_read_config(dev, PCIR_PMBASEH_1, 4), val);
526 sc->pmem.limit = PCI_PPBMEMLIMIT(
527 pci_read_config(dev, PCIR_PMLIMITH_1, 4),
528 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
529 max = 0xffffffffffffffff;
530 } else {
531 sc->pmem.base = PCI_PPBMEMBASE(0, val);
532 sc->pmem.limit = PCI_PPBMEMLIMIT(0,
533 pci_read_config(dev, PCIR_PMLIMITL_1, 2));
534 max = 0xffffffff;
535 }
536 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY,
537 RF_PREFETCHABLE, max);
538 }
539}
540
|
| 541#ifdef PCI_RES_BUS
542/*
543 * Allocate a suitable secondary bus for this bridge if needed and
544 * initialize the resource manager for the secondary bus range. Note
545 * that the minimum count is a desired value and this may allocate a
546 * smaller range.
547 */
548void
549pcib_setup_secbus(device_t dev, struct pcib_secbus *bus, int min_count)
550{
551 char buf[64];
552 int error, rid;
553
554 switch (pci_read_config(dev, PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) {
555 case PCIM_HDRTYPE_BRIDGE:
556 bus->sub_reg = PCIR_SUBBUS_1;
557 break;
558 case PCIM_HDRTYPE_CARDBUS:
559 bus->sub_reg = PCIR_SUBBUS_2;
560 break;
561 default:
562 panic("not a PCI bridge");
563 }
564 bus->dev = dev;
565 bus->rman.rm_start = 0;
566 bus->rman.rm_end = PCI_BUSMAX;
567 bus->rman.rm_type = RMAN_ARRAY;
568 snprintf(buf, sizeof(buf), "%s bus numbers", device_get_nameunit(dev));
569 bus->rman.rm_descr = strdup(buf, M_DEVBUF);
570 error = rman_init(&bus->rman);
571 if (error)
572 panic("Failed to initialize %s bus number rman",
573 device_get_nameunit(dev));
574
575 /*
576 * Allocate a bus range. This will return an existing bus range
577 * if one exists, or a new bus range if one does not.
578 */
579 rid = 0;
580 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul,
581 min_count, 0);
582 if (bus->res == NULL) {
583 /*
584 * Fall back to just allocating a range of a single bus
585 * number.
586 */
587 bus->res = bus_alloc_resource(dev, PCI_RES_BUS, &rid, 0ul, ~0ul,
588 1, 0);
589 } else if (rman_get_size(bus->res) < min_count)
590 /*
591 * Attempt to grow the existing range to satisfy the
592 * minimum desired count.
593 */
594 (void)bus_adjust_resource(dev, PCI_RES_BUS, bus->res,
595 rman_get_start(bus->res), rman_get_start(bus->res) +
596 min_count - 1);
597
598 /*
599 * Add the initial resource to the rman.
600 */
601 if (bus->res != NULL) {
602 error = rman_manage_region(&bus->rman, rman_get_start(bus->res),
603 rman_get_end(bus->res));
604 if (error)
605 panic("Failed to add resource to rman");
606 bus->sec = rman_get_start(bus->res);
607 bus->sub = rman_get_end(bus->res);
608 }
609}
610
611static struct resource *
612pcib_suballoc_bus(struct pcib_secbus *bus, device_t child, int *rid,
613 u_long start, u_long end, u_long count, u_int flags)
614{
615 struct resource *res;
616
617 res = rman_reserve_resource(&bus->rman, start, end, count, flags,
618 child);
619 if (res == NULL)
620 return (NULL);
621
622 if (bootverbose)
623 device_printf(bus->dev,
624 "allocated bus range (%lu-%lu) for rid %d of %s\n",
625 rman_get_start(res), rman_get_end(res), *rid,
626 pcib_child_name(child));
627 rman_set_rid(res, *rid);
628 return (res);
629}
630
631/*
632 * Attempt to grow the secondary bus range. This is much simpler than
633 * for I/O windows as the range can only be grown by increasing
634 * subbus.
635 */
636static int
637pcib_grow_subbus(struct pcib_secbus *bus, u_long new_end)
638{
639 u_long old_end;
640 int error;
641
642 old_end = rman_get_end(bus->res);
643 KASSERT(new_end > old_end, ("attempt to shrink subbus"));
644 error = bus_adjust_resource(bus->dev, PCI_RES_BUS, bus->res,
645 rman_get_start(bus->res), new_end);
646 if (error)
647 return (error);
648 if (bootverbose)
649 device_printf(bus->dev, "grew bus range to %lu-%lu\n",
650 rman_get_start(bus->res), rman_get_end(bus->res));
651 error = rman_manage_region(&bus->rman, old_end + 1,
652 rman_get_end(bus->res));
653 if (error)
654 panic("Failed to add resource to rman");
655 bus->sub = rman_get_end(bus->res);
656 pci_write_config(bus->dev, bus->sub_reg, bus->sub, 1);
657 return (0);
658}
659
660struct resource *
661pcib_alloc_subbus(struct pcib_secbus *bus, device_t child, int *rid,
662 u_long start, u_long end, u_long count, u_int flags)
663{
664 struct resource *res;
665 u_long start_free, end_free, new_end;
666
667 /*
668 * First, see if the request can be satisified by the existing
669 * bus range.
670 */
671 res = pcib_suballoc_bus(bus, child, rid, start, end, count, flags);
672 if (res != NULL)
673 return (res);
674
675 /*
676 * Figure out a range to grow the bus range. First, find the
677 * first bus number after the last allocated bus in the rman and
678 * enforce that as a minimum starting point for the range.
679 */
680 if (rman_last_free_region(&bus->rman, &start_free, &end_free) != 0 ||
681 end_free != bus->sub)
682 start_free = bus->sub + 1;
683 if (start_free < start)
684 start_free = start;
685 new_end = start_free + count - 1;
686
687 /*
688 * See if this new range would satisfy the request if it
689 * succeeds.
690 */
691 if (new_end > end)
692 return (NULL);
693
694 /* Finally, attempt to grow the existing resource. */
695 if (bootverbose) {
696 device_printf(bus->dev,
697 "attempting to grow bus range for %lu buses\n", count);
698 printf("\tback candidate range: %lu-%lu\n", start_free,
699 new_end);
700 }
701 if (pcib_grow_subbus(bus, new_end) == 0)
702 return (pcib_suballoc_bus(bus, child, rid, start, end, count,
703 flags));
704 return (NULL);
705}
706#endif
707
|
537#else
538
539/*
540 * Is the prefetch window open (eg, can we allocate memory in it?)
541 */
542static int
543pcib_is_prefetch_open(struct pcib_softc *sc)
544{
545 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
546}
547
548/*
549 * Is the nonprefetch window open (eg, can we allocate memory in it?)
550 */
551static int
552pcib_is_nonprefetch_open(struct pcib_softc *sc)
553{
554 return (sc->membase > 0 && sc->membase < sc->memlimit);
555}
556
557/*
558 * Is the io window open (eg, can we allocate ports in it?)
559 */
560static int
561pcib_is_io_open(struct pcib_softc *sc)
562{
563 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
564}
565
566/*
567 * Get current I/O decode.
568 */
569static void
570pcib_get_io_decode(struct pcib_softc *sc)
571{
572 device_t dev;
573 uint32_t iolow;
574
575 dev = sc->dev;
576
577 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
578 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
579 sc->iobase = PCI_PPBIOBASE(
580 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
581 else
582 sc->iobase = PCI_PPBIOBASE(0, iolow);
583
584 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
585 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
586 sc->iolimit = PCI_PPBIOLIMIT(
587 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
588 else
589 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
590}
591
592/*
593 * Get current memory decode.
594 */
595static void
596pcib_get_mem_decode(struct pcib_softc *sc)
597{
598 device_t dev;
599 pci_addr_t pmemlow;
600
601 dev = sc->dev;
602
603 sc->membase = PCI_PPBMEMBASE(0,
604 pci_read_config(dev, PCIR_MEMBASE_1, 2));
605 sc->memlimit = PCI_PPBMEMLIMIT(0,
606 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
607
608 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
609 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
610 sc->pmembase = PCI_PPBMEMBASE(
611 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
612 else
613 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
614
615 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
616 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
617 sc->pmemlimit = PCI_PPBMEMLIMIT(
618 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
619 else
620 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
621}
622
623/*
624 * Restore previous I/O decode.
625 */
626static void
627pcib_set_io_decode(struct pcib_softc *sc)
628{
629 device_t dev;
630 uint32_t iohi;
631
632 dev = sc->dev;
633
634 iohi = sc->iobase >> 16;
635 if (iohi > 0)
636 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
637 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
638
639 iohi = sc->iolimit >> 16;
640 if (iohi > 0)
641 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
642 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
643}
644
645/*
646 * Restore previous memory decode.
647 */
648static void
649pcib_set_mem_decode(struct pcib_softc *sc)
650{
651 device_t dev;
652 pci_addr_t pmemhi;
653
654 dev = sc->dev;
655
656 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
657 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
658
659 pmemhi = sc->pmembase >> 32;
660 if (pmemhi > 0)
661 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
662 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
663
664 pmemhi = sc->pmemlimit >> 32;
665 if (pmemhi > 0)
666 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
667 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
668}
669#endif
670
671/*
672 * Get current bridge configuration.
673 */
674static void
675pcib_cfg_save(struct pcib_softc *sc)
676{
677 device_t dev;
678
679 dev = sc->dev;
680
681 sc->command = pci_read_config(dev, PCIR_COMMAND, 2);
682 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
| 708#else
709
710/*
711 * Is the prefetch window open (eg, can we allocate memory in it?)
712 */
713static int
714pcib_is_prefetch_open(struct pcib_softc *sc)
715{
716 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit);
717}
718
719/*
720 * Is the nonprefetch window open (eg, can we allocate memory in it?)
721 */
722static int
723pcib_is_nonprefetch_open(struct pcib_softc *sc)
724{
725 return (sc->membase > 0 && sc->membase < sc->memlimit);
726}
727
728/*
729 * Is the io window open (eg, can we allocate ports in it?)
730 */
731static int
732pcib_is_io_open(struct pcib_softc *sc)
733{
734 return (sc->iobase > 0 && sc->iobase < sc->iolimit);
735}
736
737/*
738 * Get current I/O decode.
739 */
740static void
741pcib_get_io_decode(struct pcib_softc *sc)
742{
743 device_t dev;
744 uint32_t iolow;
745
746 dev = sc->dev;
747
748 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1);
749 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
750 sc->iobase = PCI_PPBIOBASE(
751 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow);
752 else
753 sc->iobase = PCI_PPBIOBASE(0, iolow);
754
755 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1);
756 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32)
757 sc->iolimit = PCI_PPBIOLIMIT(
758 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow);
759 else
760 sc->iolimit = PCI_PPBIOLIMIT(0, iolow);
761}
762
763/*
764 * Get current memory decode.
765 */
766static void
767pcib_get_mem_decode(struct pcib_softc *sc)
768{
769 device_t dev;
770 pci_addr_t pmemlow;
771
772 dev = sc->dev;
773
774 sc->membase = PCI_PPBMEMBASE(0,
775 pci_read_config(dev, PCIR_MEMBASE_1, 2));
776 sc->memlimit = PCI_PPBMEMLIMIT(0,
777 pci_read_config(dev, PCIR_MEMLIMIT_1, 2));
778
779 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2);
780 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
781 sc->pmembase = PCI_PPBMEMBASE(
782 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow);
783 else
784 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow);
785
786 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2);
787 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64)
788 sc->pmemlimit = PCI_PPBMEMLIMIT(
789 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow);
790 else
791 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow);
792}
793
794/*
795 * Restore previous I/O decode.
796 */
797static void
798pcib_set_io_decode(struct pcib_softc *sc)
799{
800 device_t dev;
801 uint32_t iohi;
802
803 dev = sc->dev;
804
805 iohi = sc->iobase >> 16;
806 if (iohi > 0)
807 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2);
808 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1);
809
810 iohi = sc->iolimit >> 16;
811 if (iohi > 0)
812 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2);
813 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1);
814}
815
816/*
817 * Restore previous memory decode.
818 */
819static void
820pcib_set_mem_decode(struct pcib_softc *sc)
821{
822 device_t dev;
823 pci_addr_t pmemhi;
824
825 dev = sc->dev;
826
827 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2);
828 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2);
829
830 pmemhi = sc->pmembase >> 32;
831 if (pmemhi > 0)
832 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4);
833 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2);
834
835 pmemhi = sc->pmemlimit >> 32;
836 if (pmemhi > 0)
837 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4);
838 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2);
839}
840#endif
841
842/*
843 * Get current bridge configuration.
844 */
845static void
846pcib_cfg_save(struct pcib_softc *sc)
847{
848 device_t dev;
849
850 dev = sc->dev;
851
852 sc->command = pci_read_config(dev, PCIR_COMMAND, 2);
853 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1);
|
683 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1);
684 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
| 854 sc->bus.sec = pci_read_config(dev, PCIR_SECBUS_1, 1);
855 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
|
685 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
686 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
687#ifndef NEW_PCIB
688 if (sc->command & PCIM_CMD_PORTEN)
689 pcib_get_io_decode(sc);
690 if (sc->command & PCIM_CMD_MEMEN)
691 pcib_get_mem_decode(sc);
692#endif
693}
694
695/*
696 * Restore previous bridge configuration.
697 */
698static void
699pcib_cfg_restore(struct pcib_softc *sc)
700{
701 device_t dev;
702
703 dev = sc->dev;
704
705 pci_write_config(dev, PCIR_COMMAND, sc->command, 2);
706 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
| 856 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2);
857 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1);
858#ifndef NEW_PCIB
859 if (sc->command & PCIM_CMD_PORTEN)
860 pcib_get_io_decode(sc);
861 if (sc->command & PCIM_CMD_MEMEN)
862 pcib_get_mem_decode(sc);
863#endif
864}
865
866/*
867 * Restore previous bridge configuration.
868 */
869static void
870pcib_cfg_restore(struct pcib_softc *sc)
871{
872 device_t dev;
873
874 dev = sc->dev;
875
876 pci_write_config(dev, PCIR_COMMAND, sc->command, 2);
877 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
|
707 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1);
708 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1);
| 878 pci_write_config(dev, PCIR_SECBUS_1, sc->bus.sec, 1);
879 pci_write_config(dev, PCIR_SUBBUS_1, sc->bus.sub, 1);
|
709 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2);
710 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1);
711#ifdef NEW_PCIB
712 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
713#else
714 if (sc->command & PCIM_CMD_PORTEN)
715 pcib_set_io_decode(sc);
716 if (sc->command & PCIM_CMD_MEMEN)
717 pcib_set_mem_decode(sc);
718#endif
719}
720
721/*
722 * Generic device interface
723 */
724static int
725pcib_probe(device_t dev)
726{
727 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
728 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
729 device_set_desc(dev, "PCI-PCI bridge");
730 return(-10000);
731 }
732 return(ENXIO);
733}
734
735void
736pcib_attach_common(device_t dev)
737{
738 struct pcib_softc *sc;
739 struct sysctl_ctx_list *sctx;
740 struct sysctl_oid *soid;
741 int comma;
742
743 sc = device_get_softc(dev);
744 sc->dev = dev;
745
746 /*
747 * Get current bridge configuration.
748 */
749 sc->domain = pci_get_domain(dev);
750 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
751 pcib_cfg_save(sc);
752
753 /*
| 880 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2);
881 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1);
882#ifdef NEW_PCIB
883 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM);
884#else
885 if (sc->command & PCIM_CMD_PORTEN)
886 pcib_set_io_decode(sc);
887 if (sc->command & PCIM_CMD_MEMEN)
888 pcib_set_mem_decode(sc);
889#endif
890}
891
892/*
893 * Generic device interface
894 */
895static int
896pcib_probe(device_t dev)
897{
898 if ((pci_get_class(dev) == PCIC_BRIDGE) &&
899 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) {
900 device_set_desc(dev, "PCI-PCI bridge");
901 return(-10000);
902 }
903 return(ENXIO);
904}
905
906void
907pcib_attach_common(device_t dev)
908{
909 struct pcib_softc *sc;
910 struct sysctl_ctx_list *sctx;
911 struct sysctl_oid *soid;
912 int comma;
913
914 sc = device_get_softc(dev);
915 sc->dev = dev;
916
917 /*
918 * Get current bridge configuration.
919 */
920 sc->domain = pci_get_domain(dev);
921 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2);
922 pcib_cfg_save(sc);
923
924 /*
|
| 925 * The primary bus register should always be the bus of the
926 * parent.
927 */
928 sc->pribus = pci_get_bus(dev);
929 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1);
930
931 /*
|
754 * Setup sysctl reporting nodes
755 */
756 sctx = device_get_sysctl_ctx(dev);
757 soid = device_get_sysctl_tree(dev);
758 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
759 CTLFLAG_RD, &sc->domain, 0, "Domain number");
760 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
761 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
762 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
| 932 * Setup sysctl reporting nodes
933 */
934 sctx = device_get_sysctl_ctx(dev);
935 soid = device_get_sysctl_tree(dev);
936 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain",
937 CTLFLAG_RD, &sc->domain, 0, "Domain number");
938 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus",
939 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number");
940 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus",
|
763 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number");
| 941 CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number");
|
764 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
| 942 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus",
|
765 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number");
| 943 CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number");
|
766
767 /*
768 * Quirk handling.
769 */
770 switch (pci_get_devid(dev)) {
| 944
945 /*
946 * Quirk handling.
947 */
948 switch (pci_get_devid(dev)) {
|
| 949#if !defined(NEW_PCIB) && !defined(PCI_RES_BUS)
|
771 case 0x12258086: /* Intel 82454KX/GX (Orion) */
772 {
773 uint8_t supbus;
774
775 supbus = pci_read_config(dev, 0x41, 1);
776 if (supbus != 0xff) {
| 950 case 0x12258086: /* Intel 82454KX/GX (Orion) */
951 {
952 uint8_t supbus;
953
954 supbus = pci_read_config(dev, 0x41, 1);
955 if (supbus != 0xff) {
|
777 sc->secbus = supbus + 1;
778 sc->subbus = supbus + 1;
| 956 sc->bus.sec = supbus + 1;
957 sc->bus.sub = supbus + 1;
|
779 }
780 break;
781 }
| 958 }
959 break;
960 }
|
| 961#endif
|
782
783 /*
784 * The i82380FB mobile docking controller is a PCI-PCI bridge,
785 * and it is a subtractive bridge. However, the ProgIf is wrong
786 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
787 * happen. There's also a Toshiba bridge that behaves this
788 * way.
789 */
790 case 0x124b8086: /* Intel 82380FB Mobile */
791 case 0x060513d7: /* Toshiba ???? */
792 sc->flags |= PCIB_SUBTRACTIVE;
793 break;
794
| 962
963 /*
964 * The i82380FB mobile docking controller is a PCI-PCI bridge,
965 * and it is a subtractive bridge. However, the ProgIf is wrong
966 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't
967 * happen. There's also a Toshiba bridge that behaves this
968 * way.
969 */
970 case 0x124b8086: /* Intel 82380FB Mobile */
971 case 0x060513d7: /* Toshiba ???? */
972 sc->flags |= PCIB_SUBTRACTIVE;
973 break;
974
|
| 975#if !defined(NEW_PCIB) && !defined(PCI_RES_BUS)
|
795 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
796 case 0x00dd10de:
797 {
798 char *cp;
799
800 if ((cp = getenv("smbios.planar.maker")) == NULL)
801 break;
802 if (strncmp(cp, "Compal", 6) != 0) {
803 freeenv(cp);
804 break;
805 }
806 freeenv(cp);
807 if ((cp = getenv("smbios.planar.product")) == NULL)
808 break;
809 if (strncmp(cp, "08A0", 4) != 0) {
810 freeenv(cp);
811 break;
812 }
813 freeenv(cp);
| 976 /* Compaq R3000 BIOS sets wrong subordinate bus number. */
977 case 0x00dd10de:
978 {
979 char *cp;
980
981 if ((cp = getenv("smbios.planar.maker")) == NULL)
982 break;
983 if (strncmp(cp, "Compal", 6) != 0) {
984 freeenv(cp);
985 break;
986 }
987 freeenv(cp);
988 if ((cp = getenv("smbios.planar.product")) == NULL)
989 break;
990 if (strncmp(cp, "08A0", 4) != 0) {
991 freeenv(cp);
992 break;
993 }
994 freeenv(cp);
|
814 if (sc->subbus < 0xa) {
| 995 if (sc->bus.sub < 0xa) {
|
815 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
| 996 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1);
|
816 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1);
| 997 sc->bus.sub = pci_read_config(dev, PCIR_SUBBUS_1, 1);
|
817 }
818 break;
819 }
| 998 }
999 break;
1000 }
|
| 1001#endif
|
820 }
821
822 if (pci_msi_device_blacklisted(dev))
823 sc->flags |= PCIB_DISABLE_MSI;
824
825 if (pci_msix_device_blacklisted(dev))
826 sc->flags |= PCIB_DISABLE_MSIX;
827
828 /*
829 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
830 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
831 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
832 * This means they act as if they were subtractively decoding
833 * bridges and pass all transactions. Mark them and real ProgIf 1
834 * parts as subtractive.
835 */
836 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
837 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
838 sc->flags |= PCIB_SUBTRACTIVE;
839
840#ifdef NEW_PCIB
| 1002 }
1003
1004 if (pci_msi_device_blacklisted(dev))
1005 sc->flags |= PCIB_DISABLE_MSI;
1006
1007 if (pci_msix_device_blacklisted(dev))
1008 sc->flags |= PCIB_DISABLE_MSIX;
1009
1010 /*
1011 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges,
1012 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM,
1013 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese.
1014 * This means they act as if they were subtractively decoding
1015 * bridges and pass all transactions. Mark them and real ProgIf 1
1016 * parts as subtractive.
1017 */
1018 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 ||
1019 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE)
1020 sc->flags |= PCIB_SUBTRACTIVE;
1021
1022#ifdef NEW_PCIB
|
| 1023#ifdef PCI_RES_BUS
1024 pcib_setup_secbus(dev, &sc->bus, 1);
1025#endif
|
841 pcib_probe_windows(sc);
842#endif
843 if (bootverbose) {
844 device_printf(dev, " domain %d\n", sc->domain);
| 1026 pcib_probe_windows(sc);
1027#endif
1028 if (bootverbose) {
1029 device_printf(dev, " domain %d\n", sc->domain);
|
845 device_printf(dev, " secondary bus %d\n", sc->secbus);
846 device_printf(dev, " subordinate bus %d\n", sc->subbus);
| 1030 device_printf(dev, " secondary bus %d\n", sc->bus.sec);
1031 device_printf(dev, " subordinate bus %d\n", sc->bus.sub);
|
847#ifdef NEW_PCIB
848 if (pcib_is_window_open(&sc->io))
849 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
850 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
851 if (pcib_is_window_open(&sc->mem))
852 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
853 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
854 if (pcib_is_window_open(&sc->pmem))
855 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
856 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
857#else
858 if (pcib_is_io_open(sc))
859 device_printf(dev, " I/O decode 0x%x-0x%x\n",
860 sc->iobase, sc->iolimit);
861 if (pcib_is_nonprefetch_open(sc))
862 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
863 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
864 if (pcib_is_prefetch_open(sc))
865 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
866 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
867#endif
868 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
869 sc->flags & PCIB_SUBTRACTIVE) {
870 device_printf(dev, " special decode ");
871 comma = 0;
872 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
873 printf("ISA");
874 comma = 1;
875 }
876 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
877 printf("%sVGA", comma ? ", " : "");
878 comma = 1;
879 }
880 if (sc->flags & PCIB_SUBTRACTIVE)
881 printf("%ssubtractive", comma ? ", " : "");
882 printf("\n");
883 }
884 }
885
886 /*
| 1032#ifdef NEW_PCIB
1033 if (pcib_is_window_open(&sc->io))
1034 device_printf(dev, " I/O decode 0x%jx-0x%jx\n",
1035 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit);
1036 if (pcib_is_window_open(&sc->mem))
1037 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1038 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit);
1039 if (pcib_is_window_open(&sc->pmem))
1040 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1041 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit);
1042#else
1043 if (pcib_is_io_open(sc))
1044 device_printf(dev, " I/O decode 0x%x-0x%x\n",
1045 sc->iobase, sc->iolimit);
1046 if (pcib_is_nonprefetch_open(sc))
1047 device_printf(dev, " memory decode 0x%jx-0x%jx\n",
1048 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit);
1049 if (pcib_is_prefetch_open(sc))
1050 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n",
1051 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1052#endif
1053 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) ||
1054 sc->flags & PCIB_SUBTRACTIVE) {
1055 device_printf(dev, " special decode ");
1056 comma = 0;
1057 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) {
1058 printf("ISA");
1059 comma = 1;
1060 }
1061 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) {
1062 printf("%sVGA", comma ? ", " : "");
1063 comma = 1;
1064 }
1065 if (sc->flags & PCIB_SUBTRACTIVE)
1066 printf("%ssubtractive", comma ? ", " : "");
1067 printf("\n");
1068 }
1069 }
1070
1071 /*
|
887 * XXX If the secondary bus number is zero, we should assign a bus number
888 * since the BIOS hasn't, then initialise the bridge. A simple
889 * bus_alloc_resource with the a couple of busses seems like the right
890 * approach, but we don't know what busses the BIOS might have already
891 * assigned to other bridges on this bus that probe later than we do.
892 *
893 * If the subordinate bus number is less than the secondary bus number,
894 * we should pick a better value. One sensible alternative would be to
895 * pick 255; the only tradeoff here is that configuration transactions
896 * would be more widely routed than absolutely necessary. We could
897 * then do a walk of the tree later and fix it.
898 */
899
900 /*
| |
901 * Always enable busmastering on bridges so that transactions
902 * initiated on the secondary bus are passed through to the
903 * primary bus.
904 */
905 pci_enable_busmaster(dev);
906}
907
908int
909pcib_attach(device_t dev)
910{
911 struct pcib_softc *sc;
912 device_t child;
913
914 pcib_attach_common(dev);
915 sc = device_get_softc(dev);
| 1072 * Always enable busmastering on bridges so that transactions
1073 * initiated on the secondary bus are passed through to the
1074 * primary bus.
1075 */
1076 pci_enable_busmaster(dev);
1077}
1078
1079int
1080pcib_attach(device_t dev)
1081{
1082 struct pcib_softc *sc;
1083 device_t child;
1084
1085 pcib_attach_common(dev);
1086 sc = device_get_softc(dev);
|
916 if (sc->secbus != 0) {
917 child = device_add_child(dev, "pci", sc->secbus);
| 1087 if (sc->bus.sec != 0) {
1088 child = device_add_child(dev, "pci", sc->bus.sec);
|
918 if (child != NULL)
919 return(bus_generic_attach(dev));
920 }
921
922 /* no secondary bus; we should have fixed this */
923 return(0);
924}
925
926int
927pcib_suspend(device_t dev)
928{
929 device_t pcib;
930 int dstate, error;
931
932 pcib_cfg_save(device_get_softc(dev));
933 error = bus_generic_suspend(dev);
934 if (error == 0 && pci_do_power_suspend) {
935 dstate = PCI_POWERSTATE_D3;
936 pcib = device_get_parent(device_get_parent(dev));
937 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
938 pci_set_powerstate(dev, dstate);
939 }
940 return (error);
941}
942
943int
944pcib_resume(device_t dev)
945{
946 device_t pcib;
947 int dstate;
948
949 if (pci_do_power_resume) {
950 pcib = device_get_parent(device_get_parent(dev));
951 dstate = PCI_POWERSTATE_D0;
952 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
953 pci_set_powerstate(dev, dstate);
954 }
955 pcib_cfg_restore(device_get_softc(dev));
956 return (bus_generic_resume(dev));
957}
958
959int
960pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
961{
962 struct pcib_softc *sc = device_get_softc(dev);
963
964 switch (which) {
965 case PCIB_IVAR_DOMAIN:
966 *result = sc->domain;
967 return(0);
968 case PCIB_IVAR_BUS:
| 1089 if (child != NULL)
1090 return(bus_generic_attach(dev));
1091 }
1092
1093 /* no secondary bus; we should have fixed this */
1094 return(0);
1095}
1096
1097int
1098pcib_suspend(device_t dev)
1099{
1100 device_t pcib;
1101 int dstate, error;
1102
1103 pcib_cfg_save(device_get_softc(dev));
1104 error = bus_generic_suspend(dev);
1105 if (error == 0 && pci_do_power_suspend) {
1106 dstate = PCI_POWERSTATE_D3;
1107 pcib = device_get_parent(device_get_parent(dev));
1108 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
1109 pci_set_powerstate(dev, dstate);
1110 }
1111 return (error);
1112}
1113
1114int
1115pcib_resume(device_t dev)
1116{
1117 device_t pcib;
1118 int dstate;
1119
1120 if (pci_do_power_resume) {
1121 pcib = device_get_parent(device_get_parent(dev));
1122 dstate = PCI_POWERSTATE_D0;
1123 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0)
1124 pci_set_powerstate(dev, dstate);
1125 }
1126 pcib_cfg_restore(device_get_softc(dev));
1127 return (bus_generic_resume(dev));
1128}
1129
1130int
1131pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1132{
1133 struct pcib_softc *sc = device_get_softc(dev);
1134
1135 switch (which) {
1136 case PCIB_IVAR_DOMAIN:
1137 *result = sc->domain;
1138 return(0);
1139 case PCIB_IVAR_BUS:
|
969 *result = sc->secbus;
| 1140 *result = sc->bus.sec;
|
970 return(0);
971 }
972 return(ENOENT);
973}
974
975int
976pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
977{
| 1141 return(0);
1142 }
1143 return(ENOENT);
1144}
1145
1146int
1147pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
1148{
|
978 struct pcib_softc *sc = device_get_softc(dev);
| |
979
980 switch (which) {
981 case PCIB_IVAR_DOMAIN:
982 return(EINVAL);
983 case PCIB_IVAR_BUS:
| 1149
1150 switch (which) {
1151 case PCIB_IVAR_DOMAIN:
1152 return(EINVAL);
1153 case PCIB_IVAR_BUS:
|
984 sc->secbus = value;
985 return(0);
| 1154 return(EINVAL);
|
986 }
987 return(ENOENT);
988}
989
990#ifdef NEW_PCIB
991/*
992 * Attempt to allocate a resource from the existing resources assigned
993 * to a window.
994 */
995static struct resource *
996pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
997 device_t child, int type, int *rid, u_long start, u_long end, u_long count,
998 u_int flags)
999{
1000 struct resource *res;
1001
1002 if (!pcib_is_window_open(w))
1003 return (NULL);
1004
1005 res = rman_reserve_resource(&w->rman, start, end, count,
1006 flags & ~RF_ACTIVE, child);
1007 if (res == NULL)
1008 return (NULL);
1009
1010 if (bootverbose)
1011 device_printf(sc->dev,
1012 "allocated %s range (%#lx-%#lx) for rid %x of %s\n",
1013 w->name, rman_get_start(res), rman_get_end(res), *rid,
1014 pcib_child_name(child));
1015 rman_set_rid(res, *rid);
1016
1017 /*
1018 * If the resource should be active, pass that request up the
1019 * tree. This assumes the parent drivers can handle
1020 * activating sub-allocated resources.
1021 */
1022 if (flags & RF_ACTIVE) {
1023 if (bus_activate_resource(child, type, *rid, res) != 0) {
1024 rman_release_resource(res);
1025 return (NULL);
1026 }
1027 }
1028
1029 return (res);
1030}
1031
1032/* Allocate a fresh resource range for an unconfigured window. */
1033static int
1034pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1035 u_long start, u_long end, u_long count, u_int flags)
1036{
1037 struct resource *res;
1038 u_long base, limit, wmask;
1039 int rid;
1040
1041 /*
1042 * If this is an I/O window on a bridge with ISA enable set
1043 * and the start address is below 64k, then try to allocate an
1044 * initial window of 0x1000 bytes long starting at address
1045 * 0xf000 and walking down. Note that if the original request
1046 * was larger than the non-aliased range size of 0x100 our
1047 * caller would have raised the start address up to 64k
1048 * already.
1049 */
1050 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1051 start < 65536) {
1052 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1053 limit = base + 0xfff;
1054
1055 /*
1056 * Skip ranges that wouldn't work for the
1057 * original request. Note that the actual
1058 * window that overlaps are the non-alias
1059 * ranges within [base, limit], so this isn't
1060 * quite a simple comparison.
1061 */
1062 if (start + count > limit - 0x400)
1063 continue;
1064 if (base == 0) {
1065 /*
1066 * The first open region for the window at
1067 * 0 is 0x400-0x4ff.
1068 */
1069 if (end - count + 1 < 0x400)
1070 continue;
1071 } else {
1072 if (end - count + 1 < base)
1073 continue;
1074 }
1075
1076 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1077 w->base = base;
1078 w->limit = limit;
1079 return (0);
1080 }
1081 }
1082 return (ENOSPC);
1083 }
1084
1085 wmask = (1ul << w->step) - 1;
1086 if (RF_ALIGNMENT(flags) < w->step) {
1087 flags &= ~RF_ALIGNMENT_MASK;
1088 flags |= RF_ALIGNMENT_LOG2(w->step);
1089 }
1090 start &= ~wmask;
1091 end |= wmask;
1092 count = roundup2(count, 1ul << w->step);
1093 rid = w->reg;
1094 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1095 flags & ~RF_ACTIVE);
1096 if (res == NULL)
1097 return (ENOSPC);
1098 pcib_add_window_resources(w, &res, 1);
1099 pcib_activate_window(sc, type);
1100 w->base = rman_get_start(res);
1101 w->limit = rman_get_end(res);
1102 return (0);
1103}
1104
1105/* Try to expand an existing window to the requested base and limit. */
1106static int
1107pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1108 u_long base, u_long limit)
1109{
1110 struct resource *res;
1111 int error, i, force_64k_base;
1112
1113 KASSERT(base <= w->base && limit >= w->limit,
1114 ("attempting to shrink window"));
1115
1116 /*
1117 * XXX: pcib_grow_window() doesn't try to do this anyway and
1118 * the error handling for all the edge cases would be tedious.
1119 */
1120 KASSERT(limit == w->limit || base == w->base,
1121 ("attempting to grow both ends of a window"));
1122
1123 /*
1124 * Yet more special handling for requests to expand an I/O
1125 * window behind an ISA-enabled bridge. Since I/O windows
1126 * have to grow in 0x1000 increments and the end of the 0xffff
1127 * range is an alias, growing a window below 64k will always
1128 * result in allocating new resources and never adjusting an
1129 * existing resource.
1130 */
1131 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1132 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1133 KASSERT(limit == w->limit || limit <= 65535,
1134 ("attempting to grow both ends across 64k ISA alias"));
1135
1136 if (base != w->base)
1137 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1138 else
1139 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
1140 limit);
1141 if (error == 0) {
1142 w->base = base;
1143 w->limit = limit;
1144 }
1145 return (error);
1146 }
1147
1148 /*
1149 * Find the existing resource to adjust. Usually there is only one,
1150 * but for an ISA-enabled bridge we might be growing the I/O window
1151 * above 64k and need to find the existing resource that maps all
1152 * of the area above 64k.
1153 */
1154 for (i = 0; i < w->count; i++) {
1155 if (rman_get_end(w->res[i]) == w->limit)
1156 break;
1157 }
1158 KASSERT(i != w->count, ("did not find existing resource"));
1159 res = w->res[i];
1160
1161 /*
1162 * Usually the resource we found should match the window's
1163 * existing range. The one exception is the ISA-enabled case
1164 * mentioned above in which case the resource should start at
1165 * 64k.
1166 */
1167 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1168 w->base <= 65535) {
1169 KASSERT(rman_get_start(res) == 65536,
1170 ("existing resource mismatch"));
1171 force_64k_base = 1;
1172 } else {
1173 KASSERT(w->base == rman_get_start(res),
1174 ("existing resource mismatch"));
1175 force_64k_base = 0;
1176 }
1177
1178 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1179 rman_get_start(res) : base, limit);
1180 if (error)
1181 return (error);
1182
1183 /* Add the newly allocated region to the resource manager. */
1184 if (w->base != base) {
1185 error = rman_manage_region(&w->rman, base, w->base - 1);
1186 w->base = base;
1187 } else {
1188 error = rman_manage_region(&w->rman, w->limit + 1, limit);
1189 w->limit = limit;
1190 }
1191 if (error) {
1192 if (bootverbose)
1193 device_printf(sc->dev,
1194 "failed to expand %s resource manager\n", w->name);
1195 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1196 rman_get_start(res) : w->base, w->limit);
1197 }
1198 return (error);
1199}
1200
1201/*
1202 * Attempt to grow a window to make room for a given resource request.
1203 */
1204static int
1205pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1206 u_long start, u_long end, u_long count, u_int flags)
1207{
1208 u_long align, start_free, end_free, front, back, wmask;
1209 int error;
1210
1211 /*
1212 * Clamp the desired resource range to the maximum address
1213 * this window supports. Reject impossible requests.
1214 *
1215 * For I/O port requests behind a bridge with the ISA enable
1216 * bit set, force large allocations to start above 64k.
1217 */
1218 if (!w->valid)
1219 return (EINVAL);
1220 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
1221 start < 65536)
1222 start = 65536;
1223 if (end > w->rman.rm_end)
1224 end = w->rman.rm_end;
1225 if (start + count - 1 > end || start + count < start)
1226 return (EINVAL);
1227 wmask = (1ul << w->step) - 1;
1228
1229 /*
1230 * If there is no resource at all, just try to allocate enough
1231 * aligned space for this resource.
1232 */
1233 if (w->res == NULL) {
1234 error = pcib_alloc_new_window(sc, w, type, start, end, count,
1235 flags);
1236 if (error) {
1237 if (bootverbose)
1238 device_printf(sc->dev,
1239 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n",
1240 w->name, start, end, count);
1241 return (error);
1242 }
1243 if (bootverbose)
1244 device_printf(sc->dev,
1245 "allocated initial %s window of %#jx-%#jx\n",
1246 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1247 goto updatewin;
1248 }
1249
1250 /*
1251 * See if growing the window would help. Compute the minimum
1252 * amount of address space needed on both the front and back
1253 * ends of the existing window to satisfy the allocation.
1254 *
1255 * For each end, build a candidate region adjusting for the
1256 * required alignment, etc. If there is a free region at the
1257 * edge of the window, grow from the inner edge of the free
1258 * region. Otherwise grow from the window boundary.
1259 *
1260 * Growing an I/O window below 64k for a bridge with the ISA
1261 * enable bit doesn't require any special magic as the step
1262 * size of an I/O window (1k) always includes multiple
1263 * non-alias ranges when it is grown in either direction.
1264 *
1265 * XXX: Special case: if w->res is completely empty and the
1266 * request size is larger than w->res, we should find the
1267 * optimal aligned buffer containing w->res and allocate that.
1268 */
1269 if (bootverbose)
1270 device_printf(sc->dev,
1271 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n",
1272 w->name, start, end, count);
1273 align = 1ul << RF_ALIGNMENT(flags);
1274 if (start < w->base) {
1275 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
1276 0 || start_free != w->base)
1277 end_free = w->base;
1278 if (end_free > end)
1279 end_free = end + 1;
1280
1281 /* Move end_free down until it is properly aligned. */
1282 end_free &= ~(align - 1);
1283 end_free--;
1284 front = end_free - (count - 1);
1285
1286 /*
1287 * The resource would now be allocated at (front,
1288 * end_free). Ensure that fits in the (start, end)
1289 * bounds. end_free is checked above. If 'front' is
1290 * ok, ensure it is properly aligned for this window.
1291 * Also check for underflow.
1292 */
1293 if (front >= start && front <= end_free) {
1294 if (bootverbose)
1295 printf("\tfront candidate range: %#lx-%#lx\n",
1296 front, end_free);
1297 front &= ~wmask;
1298 front = w->base - front;
1299 } else
1300 front = 0;
1301 } else
1302 front = 0;
1303 if (end > w->limit) {
1304 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
1305 0 || end_free != w->limit)
1306 start_free = w->limit + 1;
1307 if (start_free < start)
1308 start_free = start;
1309
1310 /* Move start_free up until it is properly aligned. */
1311 start_free = roundup2(start_free, align);
1312 back = start_free + count - 1;
1313
1314 /*
1315 * The resource would now be allocated at (start_free,
1316 * back). Ensure that fits in the (start, end)
1317 * bounds. start_free is checked above. If 'back' is
1318 * ok, ensure it is properly aligned for this window.
1319 * Also check for overflow.
1320 */
1321 if (back <= end && start_free <= back) {
1322 if (bootverbose)
1323 printf("\tback candidate range: %#lx-%#lx\n",
1324 start_free, back);
1325 back |= wmask;
1326 back -= w->limit;
1327 } else
1328 back = 0;
1329 } else
1330 back = 0;
1331
1332 /*
1333 * Try to allocate the smallest needed region first.
1334 * If that fails, fall back to the other region.
1335 */
1336 error = ENOSPC;
1337 while (front != 0 || back != 0) {
1338 if (front != 0 && (front <= back || back == 0)) {
1339 error = pcib_expand_window(sc, w, type, w->base - front,
1340 w->limit);
1341 if (error == 0)
1342 break;
1343 front = 0;
1344 } else {
1345 error = pcib_expand_window(sc, w, type, w->base,
1346 w->limit + back);
1347 if (error == 0)
1348 break;
1349 back = 0;
1350 }
1351 }
1352
1353 if (error)
1354 return (error);
1355 if (bootverbose)
1356 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
1357 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1358
1359updatewin:
1360 /* Write the new window. */
1361 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
1362 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
1363 pcib_write_windows(sc, w->mask);
1364 return (0);
1365}
1366
1367/*
1368 * We have to trap resource allocation requests and ensure that the bridge
1369 * is set up to, or capable of handling them.
1370 */
1371struct resource *
1372pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1373 u_long start, u_long end, u_long count, u_int flags)
1374{
1375 struct pcib_softc *sc;
1376 struct resource *r;
1377
1378 sc = device_get_softc(dev);
1379
1380 /*
1381 * VGA resources are decoded iff the VGA enable bit is set in
1382 * the bridge control register. VGA resources do not fall into
1383 * the resource windows and are passed up to the parent.
1384 */
1385 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
1386 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
1387 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
1388 return (bus_generic_alloc_resource(dev, child, type,
1389 rid, start, end, count, flags));
1390 else
1391 return (NULL);
1392 }
1393
1394 switch (type) {
| 1155 }
1156 return(ENOENT);
1157}
1158
1159#ifdef NEW_PCIB
1160/*
1161 * Attempt to allocate a resource from the existing resources assigned
1162 * to a window.
1163 */
1164static struct resource *
1165pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w,
1166 device_t child, int type, int *rid, u_long start, u_long end, u_long count,
1167 u_int flags)
1168{
1169 struct resource *res;
1170
1171 if (!pcib_is_window_open(w))
1172 return (NULL);
1173
1174 res = rman_reserve_resource(&w->rman, start, end, count,
1175 flags & ~RF_ACTIVE, child);
1176 if (res == NULL)
1177 return (NULL);
1178
1179 if (bootverbose)
1180 device_printf(sc->dev,
1181 "allocated %s range (%#lx-%#lx) for rid %x of %s\n",
1182 w->name, rman_get_start(res), rman_get_end(res), *rid,
1183 pcib_child_name(child));
1184 rman_set_rid(res, *rid);
1185
1186 /*
1187 * If the resource should be active, pass that request up the
1188 * tree. This assumes the parent drivers can handle
1189 * activating sub-allocated resources.
1190 */
1191 if (flags & RF_ACTIVE) {
1192 if (bus_activate_resource(child, type, *rid, res) != 0) {
1193 rman_release_resource(res);
1194 return (NULL);
1195 }
1196 }
1197
1198 return (res);
1199}
1200
1201/* Allocate a fresh resource range for an unconfigured window. */
1202static int
1203pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1204 u_long start, u_long end, u_long count, u_int flags)
1205{
1206 struct resource *res;
1207 u_long base, limit, wmask;
1208 int rid;
1209
1210 /*
1211 * If this is an I/O window on a bridge with ISA enable set
1212 * and the start address is below 64k, then try to allocate an
1213 * initial window of 0x1000 bytes long starting at address
1214 * 0xf000 and walking down. Note that if the original request
1215 * was larger than the non-aliased range size of 0x100 our
1216 * caller would have raised the start address up to 64k
1217 * already.
1218 */
1219 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1220 start < 65536) {
1221 for (base = 0xf000; (long)base >= 0; base -= 0x1000) {
1222 limit = base + 0xfff;
1223
1224 /*
1225 * Skip ranges that wouldn't work for the
1226 * original request. Note that the actual
1227 * window that overlaps are the non-alias
1228 * ranges within [base, limit], so this isn't
1229 * quite a simple comparison.
1230 */
1231 if (start + count > limit - 0x400)
1232 continue;
1233 if (base == 0) {
1234 /*
1235 * The first open region for the window at
1236 * 0 is 0x400-0x4ff.
1237 */
1238 if (end - count + 1 < 0x400)
1239 continue;
1240 } else {
1241 if (end - count + 1 < base)
1242 continue;
1243 }
1244
1245 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) {
1246 w->base = base;
1247 w->limit = limit;
1248 return (0);
1249 }
1250 }
1251 return (ENOSPC);
1252 }
1253
1254 wmask = (1ul << w->step) - 1;
1255 if (RF_ALIGNMENT(flags) < w->step) {
1256 flags &= ~RF_ALIGNMENT_MASK;
1257 flags |= RF_ALIGNMENT_LOG2(w->step);
1258 }
1259 start &= ~wmask;
1260 end |= wmask;
1261 count = roundup2(count, 1ul << w->step);
1262 rid = w->reg;
1263 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count,
1264 flags & ~RF_ACTIVE);
1265 if (res == NULL)
1266 return (ENOSPC);
1267 pcib_add_window_resources(w, &res, 1);
1268 pcib_activate_window(sc, type);
1269 w->base = rman_get_start(res);
1270 w->limit = rman_get_end(res);
1271 return (0);
1272}
1273
1274/* Try to expand an existing window to the requested base and limit. */
1275static int
1276pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1277 u_long base, u_long limit)
1278{
1279 struct resource *res;
1280 int error, i, force_64k_base;
1281
1282 KASSERT(base <= w->base && limit >= w->limit,
1283 ("attempting to shrink window"));
1284
1285 /*
1286 * XXX: pcib_grow_window() doesn't try to do this anyway and
1287 * the error handling for all the edge cases would be tedious.
1288 */
1289 KASSERT(limit == w->limit || base == w->base,
1290 ("attempting to grow both ends of a window"));
1291
1292 /*
1293 * Yet more special handling for requests to expand an I/O
1294 * window behind an ISA-enabled bridge. Since I/O windows
1295 * have to grow in 0x1000 increments and the end of the 0xffff
1296 * range is an alias, growing a window below 64k will always
1297 * result in allocating new resources and never adjusting an
1298 * existing resource.
1299 */
1300 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1301 (limit <= 65535 || (base <= 65535 && base != w->base))) {
1302 KASSERT(limit == w->limit || limit <= 65535,
1303 ("attempting to grow both ends across 64k ISA alias"));
1304
1305 if (base != w->base)
1306 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1);
1307 else
1308 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1,
1309 limit);
1310 if (error == 0) {
1311 w->base = base;
1312 w->limit = limit;
1313 }
1314 return (error);
1315 }
1316
1317 /*
1318 * Find the existing resource to adjust. Usually there is only one,
1319 * but for an ISA-enabled bridge we might be growing the I/O window
1320 * above 64k and need to find the existing resource that maps all
1321 * of the area above 64k.
1322 */
1323 for (i = 0; i < w->count; i++) {
1324 if (rman_get_end(w->res[i]) == w->limit)
1325 break;
1326 }
1327 KASSERT(i != w->count, ("did not find existing resource"));
1328 res = w->res[i];
1329
1330 /*
1331 * Usually the resource we found should match the window's
1332 * existing range. The one exception is the ISA-enabled case
1333 * mentioned above in which case the resource should start at
1334 * 64k.
1335 */
1336 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE &&
1337 w->base <= 65535) {
1338 KASSERT(rman_get_start(res) == 65536,
1339 ("existing resource mismatch"));
1340 force_64k_base = 1;
1341 } else {
1342 KASSERT(w->base == rman_get_start(res),
1343 ("existing resource mismatch"));
1344 force_64k_base = 0;
1345 }
1346
1347 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1348 rman_get_start(res) : base, limit);
1349 if (error)
1350 return (error);
1351
1352 /* Add the newly allocated region to the resource manager. */
1353 if (w->base != base) {
1354 error = rman_manage_region(&w->rman, base, w->base - 1);
1355 w->base = base;
1356 } else {
1357 error = rman_manage_region(&w->rman, w->limit + 1, limit);
1358 w->limit = limit;
1359 }
1360 if (error) {
1361 if (bootverbose)
1362 device_printf(sc->dev,
1363 "failed to expand %s resource manager\n", w->name);
1364 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ?
1365 rman_get_start(res) : w->base, w->limit);
1366 }
1367 return (error);
1368}
1369
1370/*
1371 * Attempt to grow a window to make room for a given resource request.
1372 */
1373static int
1374pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type,
1375 u_long start, u_long end, u_long count, u_int flags)
1376{
1377 u_long align, start_free, end_free, front, back, wmask;
1378 int error;
1379
1380 /*
1381 * Clamp the desired resource range to the maximum address
1382 * this window supports. Reject impossible requests.
1383 *
1384 * For I/O port requests behind a bridge with the ISA enable
1385 * bit set, force large allocations to start above 64k.
1386 */
1387 if (!w->valid)
1388 return (EINVAL);
1389 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 &&
1390 start < 65536)
1391 start = 65536;
1392 if (end > w->rman.rm_end)
1393 end = w->rman.rm_end;
1394 if (start + count - 1 > end || start + count < start)
1395 return (EINVAL);
1396 wmask = (1ul << w->step) - 1;
1397
1398 /*
1399 * If there is no resource at all, just try to allocate enough
1400 * aligned space for this resource.
1401 */
1402 if (w->res == NULL) {
1403 error = pcib_alloc_new_window(sc, w, type, start, end, count,
1404 flags);
1405 if (error) {
1406 if (bootverbose)
1407 device_printf(sc->dev,
1408 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n",
1409 w->name, start, end, count);
1410 return (error);
1411 }
1412 if (bootverbose)
1413 device_printf(sc->dev,
1414 "allocated initial %s window of %#jx-%#jx\n",
1415 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1416 goto updatewin;
1417 }
1418
1419 /*
1420 * See if growing the window would help. Compute the minimum
1421 * amount of address space needed on both the front and back
1422 * ends of the existing window to satisfy the allocation.
1423 *
1424 * For each end, build a candidate region adjusting for the
1425 * required alignment, etc. If there is a free region at the
1426 * edge of the window, grow from the inner edge of the free
1427 * region. Otherwise grow from the window boundary.
1428 *
1429 * Growing an I/O window below 64k for a bridge with the ISA
1430 * enable bit doesn't require any special magic as the step
1431 * size of an I/O window (1k) always includes multiple
1432 * non-alias ranges when it is grown in either direction.
1433 *
1434 * XXX: Special case: if w->res is completely empty and the
1435 * request size is larger than w->res, we should find the
1436 * optimal aligned buffer containing w->res and allocate that.
1437 */
1438 if (bootverbose)
1439 device_printf(sc->dev,
1440 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n",
1441 w->name, start, end, count);
1442 align = 1ul << RF_ALIGNMENT(flags);
1443 if (start < w->base) {
1444 if (rman_first_free_region(&w->rman, &start_free, &end_free) !=
1445 0 || start_free != w->base)
1446 end_free = w->base;
1447 if (end_free > end)
1448 end_free = end + 1;
1449
1450 /* Move end_free down until it is properly aligned. */
1451 end_free &= ~(align - 1);
1452 end_free--;
1453 front = end_free - (count - 1);
1454
1455 /*
1456 * The resource would now be allocated at (front,
1457 * end_free). Ensure that fits in the (start, end)
1458 * bounds. end_free is checked above. If 'front' is
1459 * ok, ensure it is properly aligned for this window.
1460 * Also check for underflow.
1461 */
1462 if (front >= start && front <= end_free) {
1463 if (bootverbose)
1464 printf("\tfront candidate range: %#lx-%#lx\n",
1465 front, end_free);
1466 front &= ~wmask;
1467 front = w->base - front;
1468 } else
1469 front = 0;
1470 } else
1471 front = 0;
1472 if (end > w->limit) {
1473 if (rman_last_free_region(&w->rman, &start_free, &end_free) !=
1474 0 || end_free != w->limit)
1475 start_free = w->limit + 1;
1476 if (start_free < start)
1477 start_free = start;
1478
1479 /* Move start_free up until it is properly aligned. */
1480 start_free = roundup2(start_free, align);
1481 back = start_free + count - 1;
1482
1483 /*
1484 * The resource would now be allocated at (start_free,
1485 * back). Ensure that fits in the (start, end)
1486 * bounds. start_free is checked above. If 'back' is
1487 * ok, ensure it is properly aligned for this window.
1488 * Also check for overflow.
1489 */
1490 if (back <= end && start_free <= back) {
1491 if (bootverbose)
1492 printf("\tback candidate range: %#lx-%#lx\n",
1493 start_free, back);
1494 back |= wmask;
1495 back -= w->limit;
1496 } else
1497 back = 0;
1498 } else
1499 back = 0;
1500
1501 /*
1502 * Try to allocate the smallest needed region first.
1503 * If that fails, fall back to the other region.
1504 */
1505 error = ENOSPC;
1506 while (front != 0 || back != 0) {
1507 if (front != 0 && (front <= back || back == 0)) {
1508 error = pcib_expand_window(sc, w, type, w->base - front,
1509 w->limit);
1510 if (error == 0)
1511 break;
1512 front = 0;
1513 } else {
1514 error = pcib_expand_window(sc, w, type, w->base,
1515 w->limit + back);
1516 if (error == 0)
1517 break;
1518 back = 0;
1519 }
1520 }
1521
1522 if (error)
1523 return (error);
1524 if (bootverbose)
1525 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n",
1526 w->name, (uintmax_t)w->base, (uintmax_t)w->limit);
1527
1528updatewin:
1529 /* Write the new window. */
1530 KASSERT((w->base & wmask) == 0, ("start address is not aligned"));
1531 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned"));
1532 pcib_write_windows(sc, w->mask);
1533 return (0);
1534}
1535
1536/*
1537 * We have to trap resource allocation requests and ensure that the bridge
1538 * is set up to, or capable of handling them.
1539 */
1540struct resource *
1541pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1542 u_long start, u_long end, u_long count, u_int flags)
1543{
1544 struct pcib_softc *sc;
1545 struct resource *r;
1546
1547 sc = device_get_softc(dev);
1548
1549 /*
1550 * VGA resources are decoded iff the VGA enable bit is set in
1551 * the bridge control register. VGA resources do not fall into
1552 * the resource windows and are passed up to the parent.
1553 */
1554 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) ||
1555 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) {
1556 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE)
1557 return (bus_generic_alloc_resource(dev, child, type,
1558 rid, start, end, count, flags));
1559 else
1560 return (NULL);
1561 }
1562
1563 switch (type) {
|
| 1564#ifdef PCI_RES_BUS
1565 case PCI_RES_BUS:
1566 return (pcib_alloc_subbus(&sc->bus, child, rid, start, end,
1567 count, flags));
1568#endif
|
1395 case SYS_RES_IOPORT:
1396 if (pcib_is_isa_range(sc, start, end, count))
1397 return (NULL);
1398 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
1399 end, count, flags);
1400 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
1401 break;
1402 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
1403 flags) == 0)
1404 r = pcib_suballoc_resource(sc, &sc->io, child, type,
1405 rid, start, end, count, flags);
1406 break;
1407 case SYS_RES_MEMORY:
1408 /*
1409 * For prefetchable resources, prefer the prefetchable
1410 * memory window, but fall back to the regular memory
1411 * window if that fails. Try both windows before
1412 * attempting to grow a window in case the firmware
1413 * has used a range in the regular memory window to
1414 * map a prefetchable BAR.
1415 */
1416 if (flags & RF_PREFETCHABLE) {
1417 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
1418 rid, start, end, count, flags);
1419 if (r != NULL)
1420 break;
1421 }
1422 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
1423 start, end, count, flags);
1424 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
1425 break;
1426 if (flags & RF_PREFETCHABLE) {
1427 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
1428 count, flags) == 0) {
1429 r = pcib_suballoc_resource(sc, &sc->pmem, child,
1430 type, rid, start, end, count, flags);
1431 if (r != NULL)
1432 break;
1433 }
1434 }
1435 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
1436 flags & ~RF_PREFETCHABLE) == 0)
1437 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
1438 rid, start, end, count, flags);
1439 break;
1440 default:
1441 return (bus_generic_alloc_resource(dev, child, type, rid,
1442 start, end, count, flags));
1443 }
1444
1445 /*
1446 * If attempts to suballocate from the window fail but this is a
1447 * subtractive bridge, pass the request up the tree.
1448 */
1449 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
1450 return (bus_generic_alloc_resource(dev, child, type, rid,
1451 start, end, count, flags));
1452 return (r);
1453}
1454
1455int
1456pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
1457 u_long start, u_long end)
1458{
1459 struct pcib_softc *sc;
1460
1461 sc = device_get_softc(bus);
1462 if (pcib_is_resource_managed(sc, type, r))
1463 return (rman_adjust_resource(r, start, end));
1464 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
1465}
1466
1467int
1468pcib_release_resource(device_t dev, device_t child, int type, int rid,
1469 struct resource *r)
1470{
1471 struct pcib_softc *sc;
1472 int error;
1473
1474 sc = device_get_softc(dev);
1475 if (pcib_is_resource_managed(sc, type, r)) {
1476 if (rman_get_flags(r) & RF_ACTIVE) {
1477 error = bus_deactivate_resource(child, type, rid, r);
1478 if (error)
1479 return (error);
1480 }
1481 return (rman_release_resource(r));
1482 }
1483 return (bus_generic_release_resource(dev, child, type, rid, r));
1484}
1485#else
1486/*
1487 * We have to trap resource allocation requests and ensure that the bridge
1488 * is set up to, or capable of handling them.
1489 */
1490struct resource *
1491pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1492 u_long start, u_long end, u_long count, u_int flags)
1493{
1494 struct pcib_softc *sc = device_get_softc(dev);
1495 const char *name, *suffix;
1496 int ok;
1497
1498 /*
1499 * Fail the allocation for this range if it's not supported.
1500 */
1501 name = device_get_nameunit(child);
1502 if (name == NULL) {
1503 name = "";
1504 suffix = "";
1505 } else
1506 suffix = " ";
1507 switch (type) {
1508 case SYS_RES_IOPORT:
1509 ok = 0;
1510 if (!pcib_is_io_open(sc))
1511 break;
1512 ok = (start >= sc->iobase && end <= sc->iolimit);
1513
1514 /*
1515 * Make sure we allow access to VGA I/O addresses when the
1516 * bridge has the "VGA Enable" bit set.
1517 */
1518 if (!ok && pci_is_vga_ioport_range(start, end))
1519 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
1520
1521 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
1522 if (!ok) {
1523 if (start < sc->iobase)
1524 start = sc->iobase;
1525 if (end > sc->iolimit)
1526 end = sc->iolimit;
1527 if (start < end)
1528 ok = 1;
1529 }
1530 } else {
1531 ok = 1;
1532#if 0
1533 /*
1534 * If we overlap with the subtractive range, then
1535 * pick the upper range to use.
1536 */
1537 if (start < sc->iolimit && end > sc->iobase)
1538 start = sc->iolimit + 1;
1539#endif
1540 }
1541 if (end < start) {
1542 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
1543 end, start);
1544 start = 0;
1545 end = 0;
1546 ok = 0;
1547 }
1548 if (!ok) {
1549 device_printf(dev, "%s%srequested unsupported I/O "
1550 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
1551 name, suffix, start, end, sc->iobase, sc->iolimit);
1552 return (NULL);
1553 }
1554 if (bootverbose)
1555 device_printf(dev,
1556 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
1557 name, suffix, start, end);
1558 break;
1559
1560 case SYS_RES_MEMORY:
1561 ok = 0;
1562 if (pcib_is_nonprefetch_open(sc))
1563 ok = ok || (start >= sc->membase && end <= sc->memlimit);
1564 if (pcib_is_prefetch_open(sc))
1565 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
1566
1567 /*
1568 * Make sure we allow access to VGA memory addresses when the
1569 * bridge has the "VGA Enable" bit set.
1570 */
1571 if (!ok && pci_is_vga_memory_range(start, end))
1572 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
1573
1574 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
1575 if (!ok) {
1576 ok = 1;
1577 if (flags & RF_PREFETCHABLE) {
1578 if (pcib_is_prefetch_open(sc)) {
1579 if (start < sc->pmembase)
1580 start = sc->pmembase;
1581 if (end > sc->pmemlimit)
1582 end = sc->pmemlimit;
1583 } else {
1584 ok = 0;
1585 }
1586 } else { /* non-prefetchable */
1587 if (pcib_is_nonprefetch_open(sc)) {
1588 if (start < sc->membase)
1589 start = sc->membase;
1590 if (end > sc->memlimit)
1591 end = sc->memlimit;
1592 } else {
1593 ok = 0;
1594 }
1595 }
1596 }
1597 } else if (!ok) {
1598 ok = 1; /* subtractive bridge: always ok */
1599#if 0
1600 if (pcib_is_nonprefetch_open(sc)) {
1601 if (start < sc->memlimit && end > sc->membase)
1602 start = sc->memlimit + 1;
1603 }
1604 if (pcib_is_prefetch_open(sc)) {
1605 if (start < sc->pmemlimit && end > sc->pmembase)
1606 start = sc->pmemlimit + 1;
1607 }
1608#endif
1609 }
1610 if (end < start) {
1611 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
1612 end, start);
1613 start = 0;
1614 end = 0;
1615 ok = 0;
1616 }
1617 if (!ok && bootverbose)
1618 device_printf(dev,
1619 "%s%srequested unsupported memory range %#lx-%#lx "
1620 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
1621 name, suffix, start, end,
1622 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
1623 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1624 if (!ok)
1625 return (NULL);
1626 if (bootverbose)
1627 device_printf(dev,"%s%srequested memory range "
1628 "0x%lx-0x%lx: good\n",
1629 name, suffix, start, end);
1630 break;
1631
1632 default:
1633 break;
1634 }
1635 /*
1636 * Bridge is OK decoding this resource, so pass it up.
1637 */
1638 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
1639 count, flags));
1640}
1641#endif
1642
1643/*
1644 * If ARI is enabled on this downstream port, translate the function number
1645 * to the non-ARI slot/function. The downstream port will convert it back in
1646 * hardware. If ARI is not enabled slot and func are not modified.
1647 */
1648static __inline void
1649pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
1650{
1651 struct pcib_softc *sc;
1652 int ari_func;
1653
1654 sc = device_get_softc(pcib);
1655 ari_func = *func;
1656
1657 if (sc->flags & PCIB_ENABLE_ARI) {
1658 KASSERT(*slot == 0,
1659 ("Non-zero slot number with ARI enabled!"));
1660 *slot = PCIE_ARI_SLOT(ari_func);
1661 *func = PCIE_ARI_FUNC(ari_func);
1662 }
1663}
1664
1665
1666static void
1667pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
1668{
1669 uint32_t ctl2;
1670
1671 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
1672 ctl2 |= PCIEM_CTL2_ARI;
1673 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
1674
1675 sc->flags |= PCIB_ENABLE_ARI;
1676}
1677
1678/*
1679 * PCIB interface.
1680 */
1681int
1682pcib_maxslots(device_t dev)
1683{
1684 return (PCI_SLOTMAX);
1685}
1686
1687static int
1688pcib_ari_maxslots(device_t dev)
1689{
1690 struct pcib_softc *sc;
1691
1692 sc = device_get_softc(dev);
1693
1694 if (sc->flags & PCIB_ENABLE_ARI)
1695 return (PCIE_ARI_SLOTMAX);
1696 else
1697 return (PCI_SLOTMAX);
1698}
1699
1700static int
1701pcib_ari_maxfuncs(device_t dev)
1702{
1703 struct pcib_softc *sc;
1704
1705 sc = device_get_softc(dev);
1706
1707 if (sc->flags & PCIB_ENABLE_ARI)
1708 return (PCIE_ARI_FUNCMAX);
1709 else
1710 return (PCI_FUNCMAX);
1711}
1712
1713/*
1714 * Since we are a child of a PCI bus, its parent must support the pcib interface.
1715 */
1716static uint32_t
1717pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
1718{
1719
1720 pcib_xlate_ari(dev, b, &s, &f);
1721 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
1722 f, reg, width));
1723}
1724
1725static void
1726pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
1727{
1728
1729 pcib_xlate_ari(dev, b, &s, &f);
1730 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
1731 reg, val, width);
1732}
1733
1734/*
1735 * Route an interrupt across a PCI bridge.
1736 */
1737int
1738pcib_route_interrupt(device_t pcib, device_t dev, int pin)
1739{
1740 device_t bus;
1741 int parent_intpin;
1742 int intnum;
1743
1744 /*
1745 *
1746 * The PCI standard defines a swizzle of the child-side device/intpin to
1747 * the parent-side intpin as follows.
1748 *
1749 * device = device on child bus
1750 * child_intpin = intpin on child bus slot (0-3)
1751 * parent_intpin = intpin on parent bus slot (0-3)
1752 *
1753 * parent_intpin = (device + child_intpin) % 4
1754 */
1755 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
1756
1757 /*
1758 * Our parent is a PCI bus. Its parent must export the pcib interface
1759 * which includes the ability to route interrupts.
1760 */
1761 bus = device_get_parent(pcib);
1762 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
1763 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
1764 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
1765 pci_get_slot(dev), 'A' + pin - 1, intnum);
1766 }
1767 return(intnum);
1768}
1769
1770/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
1771int
1772pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
1773{
1774 struct pcib_softc *sc = device_get_softc(pcib);
1775 device_t bus;
1776
1777 if (sc->flags & PCIB_DISABLE_MSI)
1778 return (ENXIO);
1779 bus = device_get_parent(pcib);
1780 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
1781 irqs));
1782}
1783
1784/* Pass request to release MSI/MSI-X messages up to the parent bridge. */
1785int
1786pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
1787{
1788 device_t bus;
1789
1790 bus = device_get_parent(pcib);
1791 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
1792}
1793
1794/* Pass request to alloc an MSI-X message up to the parent bridge. */
1795int
1796pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
1797{
1798 struct pcib_softc *sc = device_get_softc(pcib);
1799 device_t bus;
1800
1801 if (sc->flags & PCIB_DISABLE_MSIX)
1802 return (ENXIO);
1803 bus = device_get_parent(pcib);
1804 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
1805}
1806
1807/* Pass request to release an MSI-X message up to the parent bridge. */
1808int
1809pcib_release_msix(device_t pcib, device_t dev, int irq)
1810{
1811 device_t bus;
1812
1813 bus = device_get_parent(pcib);
1814 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
1815}
1816
1817/* Pass request to map MSI/MSI-X message up to parent bridge. */
1818int
1819pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
1820 uint32_t *data)
1821{
1822 device_t bus;
1823 int error;
1824
1825 bus = device_get_parent(pcib);
1826 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
1827 if (error)
1828 return (error);
1829
1830 pci_ht_map_msi(pcib, *addr);
1831 return (0);
1832}
1833
1834/* Pass request for device power state up to parent bridge. */
1835int
1836pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
1837{
1838 device_t bus;
1839
1840 bus = device_get_parent(pcib);
1841 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
1842}
1843
1844static uint16_t
1845pcib_ari_get_rid(device_t pcib, device_t dev)
1846{
1847 struct pcib_softc *sc;
1848 uint8_t bus, slot, func;
1849
1850 sc = device_get_softc(pcib);
1851
1852 if (sc->flags & PCIB_ENABLE_ARI) {
1853 bus = pci_get_bus(dev);
1854 func = pci_get_function(dev);
1855
1856 return (PCI_ARI_RID(bus, func));
1857 } else {
1858 bus = pci_get_bus(dev);
1859 slot = pci_get_slot(dev);
1860 func = pci_get_function(dev);
1861
1862 return (PCI_RID(bus, slot, func));
1863 }
1864}
1865
1866/*
1867 * Check that the downstream port (pcib) and the endpoint device (dev) both
1868 * support ARI. If so, enable it and return 0, otherwise return an error.
1869 */
1870static int
1871pcib_try_enable_ari(device_t pcib, device_t dev)
1872{
1873 struct pcib_softc *sc;
1874 int error;
1875 uint32_t cap2;
1876 int ari_cap_off;
1877 uint32_t ari_ver;
1878 uint32_t pcie_pos;
1879
1880 sc = device_get_softc(pcib);
1881
1882 /*
1883 * ARI is controlled in a register in the PCIe capability structure.
1884 * If the downstream port does not have the PCIe capability structure
1885 * then it does not support ARI.
1886 */
1887 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
1888 if (error != 0)
1889 return (ENODEV);
1890
1891 /* Check that the PCIe port advertises ARI support. */
1892 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
1893 if (!(cap2 & PCIEM_CAP2_ARI))
1894 return (ENODEV);
1895
1896 /*
1897 * Check that the endpoint device advertises ARI support via the ARI
1898 * extended capability structure.
1899 */
1900 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
1901 if (error != 0)
1902 return (ENODEV);
1903
1904 /*
1905 * Finally, check that the endpoint device supports the same version
1906 * of ARI that we do.
1907 */
1908 ari_ver = pci_read_config(dev, ari_cap_off, 4);
1909 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
1910 if (bootverbose)
1911 device_printf(pcib,
1912 "Unsupported version of ARI (%d) detected\n",
1913 PCI_EXTCAP_VER(ari_ver));
1914
1915 return (ENXIO);
1916 }
1917
1918 pcib_enable_ari(sc, pcie_pos);
1919
1920 return (0);
1921}
1922
| 1569 case SYS_RES_IOPORT:
1570 if (pcib_is_isa_range(sc, start, end, count))
1571 return (NULL);
1572 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start,
1573 end, count, flags);
1574 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
1575 break;
1576 if (pcib_grow_window(sc, &sc->io, type, start, end, count,
1577 flags) == 0)
1578 r = pcib_suballoc_resource(sc, &sc->io, child, type,
1579 rid, start, end, count, flags);
1580 break;
1581 case SYS_RES_MEMORY:
1582 /*
1583 * For prefetchable resources, prefer the prefetchable
1584 * memory window, but fall back to the regular memory
1585 * window if that fails. Try both windows before
1586 * attempting to grow a window in case the firmware
1587 * has used a range in the regular memory window to
1588 * map a prefetchable BAR.
1589 */
1590 if (flags & RF_PREFETCHABLE) {
1591 r = pcib_suballoc_resource(sc, &sc->pmem, child, type,
1592 rid, start, end, count, flags);
1593 if (r != NULL)
1594 break;
1595 }
1596 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid,
1597 start, end, count, flags);
1598 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0)
1599 break;
1600 if (flags & RF_PREFETCHABLE) {
1601 if (pcib_grow_window(sc, &sc->pmem, type, start, end,
1602 count, flags) == 0) {
1603 r = pcib_suballoc_resource(sc, &sc->pmem, child,
1604 type, rid, start, end, count, flags);
1605 if (r != NULL)
1606 break;
1607 }
1608 }
1609 if (pcib_grow_window(sc, &sc->mem, type, start, end, count,
1610 flags & ~RF_PREFETCHABLE) == 0)
1611 r = pcib_suballoc_resource(sc, &sc->mem, child, type,
1612 rid, start, end, count, flags);
1613 break;
1614 default:
1615 return (bus_generic_alloc_resource(dev, child, type, rid,
1616 start, end, count, flags));
1617 }
1618
1619 /*
1620 * If attempts to suballocate from the window fail but this is a
1621 * subtractive bridge, pass the request up the tree.
1622 */
1623 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL)
1624 return (bus_generic_alloc_resource(dev, child, type, rid,
1625 start, end, count, flags));
1626 return (r);
1627}
1628
1629int
1630pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r,
1631 u_long start, u_long end)
1632{
1633 struct pcib_softc *sc;
1634
1635 sc = device_get_softc(bus);
1636 if (pcib_is_resource_managed(sc, type, r))
1637 return (rman_adjust_resource(r, start, end));
1638 return (bus_generic_adjust_resource(bus, child, type, r, start, end));
1639}
1640
1641int
1642pcib_release_resource(device_t dev, device_t child, int type, int rid,
1643 struct resource *r)
1644{
1645 struct pcib_softc *sc;
1646 int error;
1647
1648 sc = device_get_softc(dev);
1649 if (pcib_is_resource_managed(sc, type, r)) {
1650 if (rman_get_flags(r) & RF_ACTIVE) {
1651 error = bus_deactivate_resource(child, type, rid, r);
1652 if (error)
1653 return (error);
1654 }
1655 return (rman_release_resource(r));
1656 }
1657 return (bus_generic_release_resource(dev, child, type, rid, r));
1658}
1659#else
1660/*
1661 * We have to trap resource allocation requests and ensure that the bridge
1662 * is set up to, or capable of handling them.
1663 */
1664struct resource *
1665pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
1666 u_long start, u_long end, u_long count, u_int flags)
1667{
1668 struct pcib_softc *sc = device_get_softc(dev);
1669 const char *name, *suffix;
1670 int ok;
1671
1672 /*
1673 * Fail the allocation for this range if it's not supported.
1674 */
1675 name = device_get_nameunit(child);
1676 if (name == NULL) {
1677 name = "";
1678 suffix = "";
1679 } else
1680 suffix = " ";
1681 switch (type) {
1682 case SYS_RES_IOPORT:
1683 ok = 0;
1684 if (!pcib_is_io_open(sc))
1685 break;
1686 ok = (start >= sc->iobase && end <= sc->iolimit);
1687
1688 /*
1689 * Make sure we allow access to VGA I/O addresses when the
1690 * bridge has the "VGA Enable" bit set.
1691 */
1692 if (!ok && pci_is_vga_ioport_range(start, end))
1693 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
1694
1695 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
1696 if (!ok) {
1697 if (start < sc->iobase)
1698 start = sc->iobase;
1699 if (end > sc->iolimit)
1700 end = sc->iolimit;
1701 if (start < end)
1702 ok = 1;
1703 }
1704 } else {
1705 ok = 1;
1706#if 0
1707 /*
1708 * If we overlap with the subtractive range, then
1709 * pick the upper range to use.
1710 */
1711 if (start < sc->iolimit && end > sc->iobase)
1712 start = sc->iolimit + 1;
1713#endif
1714 }
1715 if (end < start) {
1716 device_printf(dev, "ioport: end (%lx) < start (%lx)\n",
1717 end, start);
1718 start = 0;
1719 end = 0;
1720 ok = 0;
1721 }
1722 if (!ok) {
1723 device_printf(dev, "%s%srequested unsupported I/O "
1724 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n",
1725 name, suffix, start, end, sc->iobase, sc->iolimit);
1726 return (NULL);
1727 }
1728 if (bootverbose)
1729 device_printf(dev,
1730 "%s%srequested I/O range 0x%lx-0x%lx: in range\n",
1731 name, suffix, start, end);
1732 break;
1733
1734 case SYS_RES_MEMORY:
1735 ok = 0;
1736 if (pcib_is_nonprefetch_open(sc))
1737 ok = ok || (start >= sc->membase && end <= sc->memlimit);
1738 if (pcib_is_prefetch_open(sc))
1739 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit);
1740
1741 /*
1742 * Make sure we allow access to VGA memory addresses when the
1743 * bridge has the "VGA Enable" bit set.
1744 */
1745 if (!ok && pci_is_vga_memory_range(start, end))
1746 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0;
1747
1748 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) {
1749 if (!ok) {
1750 ok = 1;
1751 if (flags & RF_PREFETCHABLE) {
1752 if (pcib_is_prefetch_open(sc)) {
1753 if (start < sc->pmembase)
1754 start = sc->pmembase;
1755 if (end > sc->pmemlimit)
1756 end = sc->pmemlimit;
1757 } else {
1758 ok = 0;
1759 }
1760 } else { /* non-prefetchable */
1761 if (pcib_is_nonprefetch_open(sc)) {
1762 if (start < sc->membase)
1763 start = sc->membase;
1764 if (end > sc->memlimit)
1765 end = sc->memlimit;
1766 } else {
1767 ok = 0;
1768 }
1769 }
1770 }
1771 } else if (!ok) {
1772 ok = 1; /* subtractive bridge: always ok */
1773#if 0
1774 if (pcib_is_nonprefetch_open(sc)) {
1775 if (start < sc->memlimit && end > sc->membase)
1776 start = sc->memlimit + 1;
1777 }
1778 if (pcib_is_prefetch_open(sc)) {
1779 if (start < sc->pmemlimit && end > sc->pmembase)
1780 start = sc->pmemlimit + 1;
1781 }
1782#endif
1783 }
1784 if (end < start) {
1785 device_printf(dev, "memory: end (%lx) < start (%lx)\n",
1786 end, start);
1787 start = 0;
1788 end = 0;
1789 ok = 0;
1790 }
1791 if (!ok && bootverbose)
1792 device_printf(dev,
1793 "%s%srequested unsupported memory range %#lx-%#lx "
1794 "(decoding %#jx-%#jx, %#jx-%#jx)\n",
1795 name, suffix, start, end,
1796 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit,
1797 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit);
1798 if (!ok)
1799 return (NULL);
1800 if (bootverbose)
1801 device_printf(dev,"%s%srequested memory range "
1802 "0x%lx-0x%lx: good\n",
1803 name, suffix, start, end);
1804 break;
1805
1806 default:
1807 break;
1808 }
1809 /*
1810 * Bridge is OK decoding this resource, so pass it up.
1811 */
1812 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
1813 count, flags));
1814}
1815#endif
1816
1817/*
1818 * If ARI is enabled on this downstream port, translate the function number
1819 * to the non-ARI slot/function. The downstream port will convert it back in
1820 * hardware. If ARI is not enabled slot and func are not modified.
1821 */
1822static __inline void
1823pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func)
1824{
1825 struct pcib_softc *sc;
1826 int ari_func;
1827
1828 sc = device_get_softc(pcib);
1829 ari_func = *func;
1830
1831 if (sc->flags & PCIB_ENABLE_ARI) {
1832 KASSERT(*slot == 0,
1833 ("Non-zero slot number with ARI enabled!"));
1834 *slot = PCIE_ARI_SLOT(ari_func);
1835 *func = PCIE_ARI_FUNC(ari_func);
1836 }
1837}
1838
1839
1840static void
1841pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos)
1842{
1843 uint32_t ctl2;
1844
1845 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4);
1846 ctl2 |= PCIEM_CTL2_ARI;
1847 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4);
1848
1849 sc->flags |= PCIB_ENABLE_ARI;
1850}
1851
1852/*
1853 * PCIB interface.
1854 */
1855int
1856pcib_maxslots(device_t dev)
1857{
1858 return (PCI_SLOTMAX);
1859}
1860
1861static int
1862pcib_ari_maxslots(device_t dev)
1863{
1864 struct pcib_softc *sc;
1865
1866 sc = device_get_softc(dev);
1867
1868 if (sc->flags & PCIB_ENABLE_ARI)
1869 return (PCIE_ARI_SLOTMAX);
1870 else
1871 return (PCI_SLOTMAX);
1872}
1873
1874static int
1875pcib_ari_maxfuncs(device_t dev)
1876{
1877 struct pcib_softc *sc;
1878
1879 sc = device_get_softc(dev);
1880
1881 if (sc->flags & PCIB_ENABLE_ARI)
1882 return (PCIE_ARI_FUNCMAX);
1883 else
1884 return (PCI_FUNCMAX);
1885}
1886
1887/*
1888 * Since we are a child of a PCI bus, its parent must support the pcib interface.
1889 */
1890static uint32_t
1891pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width)
1892{
1893
1894 pcib_xlate_ari(dev, b, &s, &f);
1895 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s,
1896 f, reg, width));
1897}
1898
1899static void
1900pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width)
1901{
1902
1903 pcib_xlate_ari(dev, b, &s, &f);
1904 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f,
1905 reg, val, width);
1906}
1907
1908/*
1909 * Route an interrupt across a PCI bridge.
1910 */
1911int
1912pcib_route_interrupt(device_t pcib, device_t dev, int pin)
1913{
1914 device_t bus;
1915 int parent_intpin;
1916 int intnum;
1917
1918 /*
1919 *
1920 * The PCI standard defines a swizzle of the child-side device/intpin to
1921 * the parent-side intpin as follows.
1922 *
1923 * device = device on child bus
1924 * child_intpin = intpin on child bus slot (0-3)
1925 * parent_intpin = intpin on parent bus slot (0-3)
1926 *
1927 * parent_intpin = (device + child_intpin) % 4
1928 */
1929 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4;
1930
1931 /*
1932 * Our parent is a PCI bus. Its parent must export the pcib interface
1933 * which includes the ability to route interrupts.
1934 */
1935 bus = device_get_parent(pcib);
1936 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1);
1937 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) {
1938 device_printf(pcib, "slot %d INT%c is routed to irq %d\n",
1939 pci_get_slot(dev), 'A' + pin - 1, intnum);
1940 }
1941 return(intnum);
1942}
1943
1944/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */
1945int
1946pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
1947{
1948 struct pcib_softc *sc = device_get_softc(pcib);
1949 device_t bus;
1950
1951 if (sc->flags & PCIB_DISABLE_MSI)
1952 return (ENXIO);
1953 bus = device_get_parent(pcib);
1954 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
1955 irqs));
1956}
1957
1958/* Pass request to release MSI/MSI-X messages up to the parent bridge. */
1959int
1960pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs)
1961{
1962 device_t bus;
1963
1964 bus = device_get_parent(pcib);
1965 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs));
1966}
1967
1968/* Pass request to alloc an MSI-X message up to the parent bridge. */
1969int
1970pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
1971{
1972 struct pcib_softc *sc = device_get_softc(pcib);
1973 device_t bus;
1974
1975 if (sc->flags & PCIB_DISABLE_MSIX)
1976 return (ENXIO);
1977 bus = device_get_parent(pcib);
1978 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
1979}
1980
1981/* Pass request to release an MSI-X message up to the parent bridge. */
1982int
1983pcib_release_msix(device_t pcib, device_t dev, int irq)
1984{
1985 device_t bus;
1986
1987 bus = device_get_parent(pcib);
1988 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq));
1989}
1990
1991/* Pass request to map MSI/MSI-X message up to parent bridge. */
1992int
1993pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
1994 uint32_t *data)
1995{
1996 device_t bus;
1997 int error;
1998
1999 bus = device_get_parent(pcib);
2000 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data);
2001 if (error)
2002 return (error);
2003
2004 pci_ht_map_msi(pcib, *addr);
2005 return (0);
2006}
2007
2008/* Pass request for device power state up to parent bridge. */
2009int
2010pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate)
2011{
2012 device_t bus;
2013
2014 bus = device_get_parent(pcib);
2015 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate));
2016}
2017
2018static uint16_t
2019pcib_ari_get_rid(device_t pcib, device_t dev)
2020{
2021 struct pcib_softc *sc;
2022 uint8_t bus, slot, func;
2023
2024 sc = device_get_softc(pcib);
2025
2026 if (sc->flags & PCIB_ENABLE_ARI) {
2027 bus = pci_get_bus(dev);
2028 func = pci_get_function(dev);
2029
2030 return (PCI_ARI_RID(bus, func));
2031 } else {
2032 bus = pci_get_bus(dev);
2033 slot = pci_get_slot(dev);
2034 func = pci_get_function(dev);
2035
2036 return (PCI_RID(bus, slot, func));
2037 }
2038}
2039
2040/*
2041 * Check that the downstream port (pcib) and the endpoint device (dev) both
2042 * support ARI. If so, enable it and return 0, otherwise return an error.
2043 */
2044static int
2045pcib_try_enable_ari(device_t pcib, device_t dev)
2046{
2047 struct pcib_softc *sc;
2048 int error;
2049 uint32_t cap2;
2050 int ari_cap_off;
2051 uint32_t ari_ver;
2052 uint32_t pcie_pos;
2053
2054 sc = device_get_softc(pcib);
2055
2056 /*
2057 * ARI is controlled in a register in the PCIe capability structure.
2058 * If the downstream port does not have the PCIe capability structure
2059 * then it does not support ARI.
2060 */
2061 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos);
2062 if (error != 0)
2063 return (ENODEV);
2064
2065 /* Check that the PCIe port advertises ARI support. */
2066 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4);
2067 if (!(cap2 & PCIEM_CAP2_ARI))
2068 return (ENODEV);
2069
2070 /*
2071 * Check that the endpoint device advertises ARI support via the ARI
2072 * extended capability structure.
2073 */
2074 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off);
2075 if (error != 0)
2076 return (ENODEV);
2077
2078 /*
2079 * Finally, check that the endpoint device supports the same version
2080 * of ARI that we do.
2081 */
2082 ari_ver = pci_read_config(dev, ari_cap_off, 4);
2083 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) {
2084 if (bootverbose)
2085 device_printf(pcib,
2086 "Unsupported version of ARI (%d) detected\n",
2087 PCI_EXTCAP_VER(ari_ver));
2088
2089 return (ENXIO);
2090 }
2091
2092 pcib_enable_ari(sc, pcie_pos);
2093
2094 return (0);
2095}
2096
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