27 */
28
29#ifndef __NVME_H__
30#define __NVME_H__
31
32#ifdef _KERNEL
33#include <sys/types.h>
34#endif
35
36#include <sys/param.h>
37
38#define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
39#define NVME_RESET_CONTROLLER _IO('n', 1)
40
41#define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
42#define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
43
44/*
45 * Use to mark a command to apply to all namespaces, or to retrieve global
46 * log pages.
47 */
48#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
49
50#define NVME_MAX_XFER_SIZE MAXPHYS
51
52union cap_lo_register {
53 uint32_t raw;
54 struct {
55 /** maximum queue entries supported */
56 uint32_t mqes : 16;
57
58 /** contiguous queues required */
59 uint32_t cqr : 1;
60
61 /** arbitration mechanism supported */
62 uint32_t ams : 2;
63
64 uint32_t reserved1 : 5;
65
66 /** timeout */
67 uint32_t to : 8;
68 } bits __packed;
69} __packed;
70
71union cap_hi_register {
72 uint32_t raw;
73 struct {
74 /** doorbell stride */
75 uint32_t dstrd : 4;
76
77 uint32_t reserved3 : 1;
78
79 /** command sets supported */
80 uint32_t css_nvm : 1;
81
82 uint32_t css_reserved : 3;
83 uint32_t reserved2 : 7;
84
85 /** memory page size minimum */
86 uint32_t mpsmin : 4;
87
88 /** memory page size maximum */
89 uint32_t mpsmax : 4;
90
91 uint32_t reserved1 : 8;
92 } bits __packed;
93} __packed;
94
95union cc_register {
96 uint32_t raw;
97 struct {
98 /** enable */
99 uint32_t en : 1;
100
101 uint32_t reserved1 : 3;
102
103 /** i/o command set selected */
104 uint32_t css : 3;
105
106 /** memory page size */
107 uint32_t mps : 4;
108
109 /** arbitration mechanism selected */
110 uint32_t ams : 3;
111
112 /** shutdown notification */
113 uint32_t shn : 2;
114
115 /** i/o submission queue entry size */
116 uint32_t iosqes : 4;
117
118 /** i/o completion queue entry size */
119 uint32_t iocqes : 4;
120
121 uint32_t reserved2 : 8;
122 } bits __packed;
123} __packed;
124
125enum shn_value {
126 NVME_SHN_NORMAL = 0x1,
127 NVME_SHN_ABRUPT = 0x2,
128};
129
130union csts_register {
131 uint32_t raw;
132 struct {
133 /** ready */
134 uint32_t rdy : 1;
135
136 /** controller fatal status */
137 uint32_t cfs : 1;
138
139 /** shutdown status */
140 uint32_t shst : 2;
141
142 uint32_t reserved1 : 28;
143 } bits __packed;
144} __packed;
145
146enum shst_value {
147 NVME_SHST_NORMAL = 0x0,
148 NVME_SHST_OCCURRING = 0x1,
149 NVME_SHST_COMPLETE = 0x2,
150};
151
152union aqa_register {
153 uint32_t raw;
154 struct {
155 /** admin submission queue size */
156 uint32_t asqs : 12;
157
158 uint32_t reserved1 : 4;
159
160 /** admin completion queue size */
161 uint32_t acqs : 12;
162
163 uint32_t reserved2 : 4;
164 } bits __packed;
165} __packed;
166
167struct nvme_registers
168{
169 /** controller capabilities */
170 union cap_lo_register cap_lo;
171 union cap_hi_register cap_hi;
172
173 uint32_t vs; /* version */
174 uint32_t intms; /* interrupt mask set */
175 uint32_t intmc; /* interrupt mask clear */
176
177 /** controller configuration */
178 union cc_register cc;
179
180 uint32_t reserved1;
181 uint32_t csts; /* controller status */
182 uint32_t reserved2;
183
184 /** admin queue attributes */
185 union aqa_register aqa;
186
187 uint64_t asq; /* admin submission queue base addr */
188 uint64_t acq; /* admin completion queue base addr */
189 uint32_t reserved3[0x3f2];
190
191 struct {
192 uint32_t sq_tdbl; /* submission queue tail doorbell */
193 uint32_t cq_hdbl; /* completion queue head doorbell */
194 } doorbell[1] __packed;
195} __packed;
196
197struct nvme_command
198{
199 /* dword 0 */
200 uint16_t opc : 8; /* opcode */
201 uint16_t fuse : 2; /* fused operation */
202 uint16_t rsvd1 : 6;
203 uint16_t cid; /* command identifier */
204
205 /* dword 1 */
206 uint32_t nsid; /* namespace identifier */
207
208 /* dword 2-3 */
209 uint32_t rsvd2;
210 uint32_t rsvd3;
211
212 /* dword 4-5 */
213 uint64_t mptr; /* metadata pointer */
214
215 /* dword 6-7 */
216 uint64_t prp1; /* prp entry 1 */
217
218 /* dword 8-9 */
219 uint64_t prp2; /* prp entry 2 */
220
221 /* dword 10-15 */
222 uint32_t cdw10; /* command-specific */
223 uint32_t cdw11; /* command-specific */
224 uint32_t cdw12; /* command-specific */
225 uint32_t cdw13; /* command-specific */
226 uint32_t cdw14; /* command-specific */
227 uint32_t cdw15; /* command-specific */
228} __packed;
229
230struct nvme_status {
231
232 uint16_t p : 1; /* phase tag */
233 uint16_t sc : 8; /* status code */
234 uint16_t sct : 3; /* status code type */
235 uint16_t rsvd2 : 2;
236 uint16_t m : 1; /* more */
237 uint16_t dnr : 1; /* do not retry */
238} __packed;
239
240struct nvme_completion {
241
242 /* dword 0 */
243 uint32_t cdw0; /* command-specific */
244
245 /* dword 1 */
246 uint32_t rsvd1;
247
248 /* dword 2 */
249 uint16_t sqhd; /* submission queue head pointer */
250 uint16_t sqid; /* submission queue identifier */
251
252 /* dword 3 */
253 uint16_t cid; /* command identifier */
254 struct nvme_status status;
255} __packed;
256
257struct nvme_dsm_range {
258
259 uint32_t attributes;
260 uint32_t length;
261 uint64_t starting_lba;
262} __packed;
263
264/* status code types */
265enum nvme_status_code_type {
266 NVME_SCT_GENERIC = 0x0,
267 NVME_SCT_COMMAND_SPECIFIC = 0x1,
268 NVME_SCT_MEDIA_ERROR = 0x2,
269 /* 0x3-0x6 - reserved */
270 NVME_SCT_VENDOR_SPECIFIC = 0x7,
271};
272
273/* generic command status codes */
274enum nvme_generic_command_status_code {
275 NVME_SC_SUCCESS = 0x00,
276 NVME_SC_INVALID_OPCODE = 0x01,
277 NVME_SC_INVALID_FIELD = 0x02,
278 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
279 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
280 NVME_SC_ABORTED_POWER_LOSS = 0x05,
281 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
282 NVME_SC_ABORTED_BY_REQUEST = 0x07,
283 NVME_SC_ABORTED_SQ_DELETION = 0x08,
284 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
285 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
286 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
287 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
288
289 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
290 NVME_SC_CAPACITY_EXCEEDED = 0x81,
291 NVME_SC_NAMESPACE_NOT_READY = 0x82,
292};
293
294/* command specific status codes */
295enum nvme_command_specific_status_code {
296 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
297 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
298 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
299 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
300 /* 0x04 - reserved */
301 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
302 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
303 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
304 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
305 NVME_SC_INVALID_LOG_PAGE = 0x09,
306 NVME_SC_INVALID_FORMAT = 0x0a,
307 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
308
309 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
310 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
311 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
312};
313
314/* media error status codes */
315enum nvme_media_error_status_code {
316 NVME_SC_WRITE_FAULTS = 0x80,
317 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
318 NVME_SC_GUARD_CHECK_ERROR = 0x82,
319 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
320 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
321 NVME_SC_COMPARE_FAILURE = 0x85,
322 NVME_SC_ACCESS_DENIED = 0x86,
323};
324
325/* admin opcodes */
326enum nvme_admin_opcode {
327 NVME_OPC_DELETE_IO_SQ = 0x00,
328 NVME_OPC_CREATE_IO_SQ = 0x01,
329 NVME_OPC_GET_LOG_PAGE = 0x02,
330 /* 0x03 - reserved */
331 NVME_OPC_DELETE_IO_CQ = 0x04,
332 NVME_OPC_CREATE_IO_CQ = 0x05,
333 NVME_OPC_IDENTIFY = 0x06,
334 /* 0x07 - reserved */
335 NVME_OPC_ABORT = 0x08,
336 NVME_OPC_SET_FEATURES = 0x09,
337 NVME_OPC_GET_FEATURES = 0x0a,
338 /* 0x0b - reserved */
339 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
340 /* 0x0d-0x0f - reserved */
341 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
342 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
343
344 NVME_OPC_FORMAT_NVM = 0x80,
345 NVME_OPC_SECURITY_SEND = 0x81,
346 NVME_OPC_SECURITY_RECEIVE = 0x82,
347};
348
349/* nvme nvm opcodes */
350enum nvme_nvm_opcode {
351 NVME_OPC_FLUSH = 0x00,
352 NVME_OPC_WRITE = 0x01,
353 NVME_OPC_READ = 0x02,
354 /* 0x03 - reserved */
355 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
356 NVME_OPC_COMPARE = 0x05,
357 /* 0x06-0x07 - reserved */
358 NVME_OPC_DATASET_MANAGEMENT = 0x09,
359};
360
361enum nvme_feature {
362 /* 0x00 - reserved */
363 NVME_FEAT_ARBITRATION = 0x01,
364 NVME_FEAT_POWER_MANAGEMENT = 0x02,
365 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
366 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
367 NVME_FEAT_ERROR_RECOVERY = 0x05,
368 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
369 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
370 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
371 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
372 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
373 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
374 /* 0x0C-0x7F - reserved */
375 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
376 /* 0x81-0xBF - command set specific (reserved) */
377 /* 0xC0-0xFF - vendor specific */
378};
379
380enum nvme_dsm_attribute {
381 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
382 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
383 NVME_DSM_ATTR_DEALLOCATE = 0x4,
384};
385
386enum nvme_activate_action {
387 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
388 NVME_AA_REPLACE_ACTIVATE = 0x1,
389 NVME_AA_ACTIVATE = 0x2,
390};
391
392struct nvme_controller_data {
393
394 /* bytes 0-255: controller capabilities and features */
395
396 /** pci vendor id */
397 uint16_t vid;
398
399 /** pci subsystem vendor id */
400 uint16_t ssvid;
401
402 /** serial number */
403 int8_t sn[20];
404
405 /** model number */
406 int8_t mn[40];
407
408 /** firmware revision */
409 uint8_t fr[8];
410
411 /** recommended arbitration burst */
412 uint8_t rab;
413
414 /** ieee oui identifier */
415 uint8_t ieee[3];
416
417 /** multi-interface capabilities */
418 uint8_t mic;
419
420 /** maximum data transfer size */
421 uint8_t mdts;
422
423 uint8_t reserved1[178];
424
425 /* bytes 256-511: admin command set attributes */
426
427 /** optional admin command support */
428 struct {
429 /* supports security send/receive commands */
430 uint16_t security : 1;
431
432 /* supports format nvm command */
433 uint16_t format : 1;
434
435 /* supports firmware activate/download commands */
436 uint16_t firmware : 1;
437
438 uint16_t oacs_rsvd : 13;
439 } __packed oacs;
440
441 /** abort command limit */
442 uint8_t acl;
443
444 /** asynchronous event request limit */
445 uint8_t aerl;
446
447 /** firmware updates */
448 struct {
449 /* first slot is read-only */
450 uint8_t slot1_ro : 1;
451
452 /* number of firmware slots */
453 uint8_t num_slots : 3;
454
455 uint8_t frmw_rsvd : 4;
456 } __packed frmw;
457
458 /** log page attributes */
459 struct {
460 /* per namespace smart/health log page */
461 uint8_t ns_smart : 1;
462
463 uint8_t lpa_rsvd : 7;
464 } __packed lpa;
465
466 /** error log page entries */
467 uint8_t elpe;
468
469 /** number of power states supported */
470 uint8_t npss;
471
472 /** admin vendor specific command configuration */
473 struct {
474 /* admin vendor specific commands use spec format */
475 uint8_t spec_format : 1;
476
477 uint8_t avscc_rsvd : 7;
478 } __packed avscc;
479
480 uint8_t reserved2[247];
481
482 /* bytes 512-703: nvm command set attributes */
483
484 /** submission queue entry size */
485 struct {
486 uint8_t min : 4;
487 uint8_t max : 4;
488 } __packed sqes;
489
490 /** completion queue entry size */
491 struct {
492 uint8_t min : 4;
493 uint8_t max : 4;
494 } __packed cqes;
495
496 uint8_t reserved3[2];
497
498 /** number of namespaces */
499 uint32_t nn;
500
501 /** optional nvm command support */
502 struct {
503 uint16_t compare : 1;
504 uint16_t write_unc : 1;
505 uint16_t dsm: 1;
506 uint16_t reserved: 13;
507 } __packed oncs;
508
509 /** fused operation support */
510 uint16_t fuses;
511
512 /** format nvm attributes */
513 uint8_t fna;
514
515 /** volatile write cache */
516 struct {
517 uint8_t present : 1;
518 uint8_t reserved : 7;
519 } __packed vwc;
520
521 /* TODO: flesh out remaining nvm command set attributes */
522 uint8_t reserved4[178];
523
524 /* bytes 704-2047: i/o command set attributes */
525 uint8_t reserved5[1344];
526
527 /* bytes 2048-3071: power state descriptors */
528 uint8_t reserved6[1024];
529
530 /* bytes 3072-4095: vendor specific */
531 uint8_t reserved7[1024];
532} __packed __aligned(4);
533
534struct nvme_namespace_data {
535
536 /** namespace size */
537 uint64_t nsze;
538
539 /** namespace capacity */
540 uint64_t ncap;
541
542 /** namespace utilization */
543 uint64_t nuse;
544
545 /** namespace features */
546 struct {
547 /** thin provisioning */
548 uint8_t thin_prov : 1;
549 uint8_t reserved1 : 7;
550 } __packed nsfeat;
551
552 /** number of lba formats */
553 uint8_t nlbaf;
554
555 /** formatted lba size */
556 struct {
557 uint8_t format : 4;
558 uint8_t extended : 1;
559 uint8_t reserved2 : 3;
560 } __packed flbas;
561
562 /** metadata capabilities */
563 struct {
564 /* metadata can be transferred as part of data prp list */
565 uint8_t extended : 1;
566
567 /* metadata can be transferred with separate metadata pointer */
568 uint8_t pointer : 1;
569
570 uint8_t reserved3 : 6;
571 } __packed mc;
572
573 /** end-to-end data protection capabilities */
574 struct {
575 /* protection information type 1 */
576 uint8_t pit1 : 1;
577
578 /* protection information type 2 */
579 uint8_t pit2 : 1;
580
581 /* protection information type 3 */
582 uint8_t pit3 : 1;
583
584 /* first eight bytes of metadata */
585 uint8_t md_start : 1;
586
587 /* last eight bytes of metadata */
588 uint8_t md_end : 1;
589 } __packed dpc;
590
591 /** end-to-end data protection type settings */
592 struct {
593 /* protection information type */
594 uint8_t pit : 3;
595
596 /* 1 == protection info transferred at start of metadata */
597 /* 0 == protection info transferred at end of metadata */
598 uint8_t md_start : 1;
599
600 uint8_t reserved4 : 4;
601 } __packed dps;
602
603 uint8_t reserved5[98];
604
605 /** lba format support */
606 struct {
607 /** metadata size */
608 uint32_t ms : 16;
609
610 /** lba data size */
611 uint32_t lbads : 8;
612
613 /** relative performance */
614 uint32_t rp : 2;
615
616 uint32_t reserved6 : 6;
617 } __packed lbaf[16];
618
619 uint8_t reserved6[192];
620
621 uint8_t vendor_specific[3712];
622} __packed __aligned(4);
623
624enum nvme_log_page {
625
626 /* 0x00 - reserved */
627 NVME_LOG_ERROR = 0x01,
628 NVME_LOG_HEALTH_INFORMATION = 0x02,
629 NVME_LOG_FIRMWARE_SLOT = 0x03,
630 /* 0x04-0x7F - reserved */
631 /* 0x80-0xBF - I/O command set specific */
632 /* 0xC0-0xFF - vendor specific */
633};
634
635struct nvme_error_information_entry {
636
637 uint64_t error_count;
638 uint16_t sqid;
639 uint16_t cid;
640 struct nvme_status status;
641 uint16_t error_location;
642 uint64_t lba;
643 uint32_t nsid;
644 uint8_t vendor_specific;
645 uint8_t reserved[35];
646} __packed __aligned(4);
647
648union nvme_critical_warning_state {
649
650 uint8_t raw;
651
652 struct {
653 uint8_t available_spare : 1;
654 uint8_t temperature : 1;
655 uint8_t device_reliability : 1;
656 uint8_t read_only : 1;
657 uint8_t volatile_memory_backup : 1;
658 uint8_t reserved : 3;
659 } __packed bits;
660} __packed;
661
662struct nvme_health_information_page {
663
664 union nvme_critical_warning_state critical_warning;
665
666 uint16_t temperature;
667 uint8_t available_spare;
668 uint8_t available_spare_threshold;
669 uint8_t percentage_used;
670
671 uint8_t reserved[26];
672
673 /*
674 * Note that the following are 128-bit values, but are
675 * defined as an array of 2 64-bit values.
676 */
677 /* Data Units Read is always in 512-byte units. */
678 uint64_t data_units_read[2];
679 /* Data Units Written is always in 512-byte units. */
680 uint64_t data_units_written[2];
681 /* For NVM command set, this includes Compare commands. */
682 uint64_t host_read_commands[2];
683 uint64_t host_write_commands[2];
684 /* Controller Busy Time is reported in minutes. */
685 uint64_t controller_busy_time[2];
686 uint64_t power_cycles[2];
687 uint64_t power_on_hours[2];
688 uint64_t unsafe_shutdowns[2];
689 uint64_t media_errors[2];
690 uint64_t num_error_info_log_entries[2];
691
692 uint8_t reserved2[320];
693} __packed __aligned(4);
694
695struct nvme_firmware_page {
696
697 struct {
698 uint8_t slot : 3; /* slot for current FW */
699 uint8_t reserved : 5;
700 } __packed afi;
701
702 uint8_t reserved[7];
703 uint64_t revision[7]; /* revisions for 7 slots */
704 uint8_t reserved2[448];
705} __packed __aligned(4);
706
707#define NVME_TEST_MAX_THREADS 128
708
709struct nvme_io_test {
710
711 enum nvme_nvm_opcode opc;
712 uint32_t size;
713 uint32_t time; /* in seconds */
714 uint32_t num_threads;
715 uint32_t flags;
716 uint32_t io_completed[NVME_TEST_MAX_THREADS];
717};
718
719enum nvme_io_test_flags {
720
721 /*
722 * Specifies whether dev_refthread/dev_relthread should be
723 * called during NVME_BIO_TEST. Ignored for other test
724 * types.
725 */
726 NVME_TEST_FLAG_REFTHREAD = 0x1,
727};
728
729struct nvme_pt_command {
730
731 /*
732 * cmd is used to specify a passthrough command to a controller or
733 * namespace.
734 *
735 * The following fields from cmd may be specified by the caller:
736 * * opc (opcode)
737 * * nsid (namespace id) - for admin commands only
738 * * cdw10-cdw15
739 *
740 * Remaining fields must be set to 0 by the caller.
741 */
742 struct nvme_command cmd;
743
744 /*
745 * cpl returns completion status for the passthrough command
746 * specified by cmd.
747 *
748 * The following fields will be filled out by the driver, for
749 * consumption by the caller:
750 * * cdw0
751 * * status (except for phase)
752 *
753 * Remaining fields will be set to 0 by the driver.
754 */
755 struct nvme_completion cpl;
756
757 /* buf is the data buffer associated with this passthrough command. */
758 void * buf;
759
760 /*
761 * len is the length of the data buffer associated with this
762 * passthrough command.
763 */
764 uint32_t len;
765
766 /*
767 * is_read = 1 if the passthrough command will read data into the
768 * supplied buffer.
769 *
770 * is_read = 0 if the passthrough command will write data into the
771 * supplied buffer.
772 */
773 uint32_t is_read;
774
775 /*
776 * driver_lock is used by the driver only. It must be set to 0
777 * by the caller.
778 */
779 struct mtx * driver_lock;
780};
781
782#define nvme_completion_is_error(cpl) \
783 ((cpl)->status.sc != 0 || (cpl)->status.sct != 0)
784
785#ifdef _KERNEL
786
787struct bio;
788
789struct nvme_namespace;
790struct nvme_controller;
791struct nvme_consumer;
792
793typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
794
795typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
796typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
797typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
798 uint32_t, void *, uint32_t);
799typedef void (*nvme_cons_fail_fn_t)(void *);
800
801enum nvme_namespace_flags {
802 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
803 NVME_NS_FLUSH_SUPPORTED = 0x2,
804};
805
806int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
807 struct nvme_pt_command *pt,
808 uint32_t nsid, int is_user_buffer,
809 int is_admin_cmd);
810
811/* Admin functions */
812void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
813 uint8_t feature, uint32_t cdw11,
814 void *payload, uint32_t payload_size,
815 nvme_cb_fn_t cb_fn, void *cb_arg);
816void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
817 uint8_t feature, uint32_t cdw11,
818 void *payload, uint32_t payload_size,
819 nvme_cb_fn_t cb_fn, void *cb_arg);
820void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
821 uint8_t log_page, uint32_t nsid,
822 void *payload, uint32_t payload_size,
823 nvme_cb_fn_t cb_fn, void *cb_arg);
824
825/* NVM I/O functions */
826int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
827 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
828 void *cb_arg);
829int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
830 nvme_cb_fn_t cb_fn, void *cb_arg);
831int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
832 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
833 void *cb_arg);
834int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
835 nvme_cb_fn_t cb_fn, void *cb_arg);
836int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
837 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
838 void *cb_arg);
839int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
840 void *cb_arg);
841
842/* Registration functions */
843struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
844 nvme_cons_ctrlr_fn_t ctrlr_fn,
845 nvme_cons_async_fn_t async_fn,
846 nvme_cons_fail_fn_t fail_fn);
847void nvme_unregister_consumer(struct nvme_consumer *consumer);
848
849/* Controller helper functions */
850device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
851const struct nvme_controller_data *
852 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
853
854/* Namespace helper functions */
855uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
856uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
857uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
858uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
859uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
860const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
861const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
862const struct nvme_namespace_data *
863 nvme_ns_get_data(struct nvme_namespace *ns);
864
865int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
866 nvme_cb_fn_t cb_fn);
867
868#endif /* _KERNEL */
869
870#endif /* __NVME_H__ */
| 27 */
28
29#ifndef __NVME_H__
30#define __NVME_H__
31
32#ifdef _KERNEL
33#include <sys/types.h>
34#endif
35
36#include <sys/param.h>
37
38#define NVME_PASSTHROUGH_CMD _IOWR('n', 0, struct nvme_pt_command)
39#define NVME_RESET_CONTROLLER _IO('n', 1)
40
41#define NVME_IO_TEST _IOWR('n', 100, struct nvme_io_test)
42#define NVME_BIO_TEST _IOWR('n', 101, struct nvme_io_test)
43
44/*
45 * Use to mark a command to apply to all namespaces, or to retrieve global
46 * log pages.
47 */
48#define NVME_GLOBAL_NAMESPACE_TAG ((uint32_t)0xFFFFFFFF)
49
50#define NVME_MAX_XFER_SIZE MAXPHYS
51
52union cap_lo_register {
53 uint32_t raw;
54 struct {
55 /** maximum queue entries supported */
56 uint32_t mqes : 16;
57
58 /** contiguous queues required */
59 uint32_t cqr : 1;
60
61 /** arbitration mechanism supported */
62 uint32_t ams : 2;
63
64 uint32_t reserved1 : 5;
65
66 /** timeout */
67 uint32_t to : 8;
68 } bits __packed;
69} __packed;
70
71union cap_hi_register {
72 uint32_t raw;
73 struct {
74 /** doorbell stride */
75 uint32_t dstrd : 4;
76
77 uint32_t reserved3 : 1;
78
79 /** command sets supported */
80 uint32_t css_nvm : 1;
81
82 uint32_t css_reserved : 3;
83 uint32_t reserved2 : 7;
84
85 /** memory page size minimum */
86 uint32_t mpsmin : 4;
87
88 /** memory page size maximum */
89 uint32_t mpsmax : 4;
90
91 uint32_t reserved1 : 8;
92 } bits __packed;
93} __packed;
94
95union cc_register {
96 uint32_t raw;
97 struct {
98 /** enable */
99 uint32_t en : 1;
100
101 uint32_t reserved1 : 3;
102
103 /** i/o command set selected */
104 uint32_t css : 3;
105
106 /** memory page size */
107 uint32_t mps : 4;
108
109 /** arbitration mechanism selected */
110 uint32_t ams : 3;
111
112 /** shutdown notification */
113 uint32_t shn : 2;
114
115 /** i/o submission queue entry size */
116 uint32_t iosqes : 4;
117
118 /** i/o completion queue entry size */
119 uint32_t iocqes : 4;
120
121 uint32_t reserved2 : 8;
122 } bits __packed;
123} __packed;
124
125enum shn_value {
126 NVME_SHN_NORMAL = 0x1,
127 NVME_SHN_ABRUPT = 0x2,
128};
129
130union csts_register {
131 uint32_t raw;
132 struct {
133 /** ready */
134 uint32_t rdy : 1;
135
136 /** controller fatal status */
137 uint32_t cfs : 1;
138
139 /** shutdown status */
140 uint32_t shst : 2;
141
142 uint32_t reserved1 : 28;
143 } bits __packed;
144} __packed;
145
146enum shst_value {
147 NVME_SHST_NORMAL = 0x0,
148 NVME_SHST_OCCURRING = 0x1,
149 NVME_SHST_COMPLETE = 0x2,
150};
151
152union aqa_register {
153 uint32_t raw;
154 struct {
155 /** admin submission queue size */
156 uint32_t asqs : 12;
157
158 uint32_t reserved1 : 4;
159
160 /** admin completion queue size */
161 uint32_t acqs : 12;
162
163 uint32_t reserved2 : 4;
164 } bits __packed;
165} __packed;
166
167struct nvme_registers
168{
169 /** controller capabilities */
170 union cap_lo_register cap_lo;
171 union cap_hi_register cap_hi;
172
173 uint32_t vs; /* version */
174 uint32_t intms; /* interrupt mask set */
175 uint32_t intmc; /* interrupt mask clear */
176
177 /** controller configuration */
178 union cc_register cc;
179
180 uint32_t reserved1;
181 uint32_t csts; /* controller status */
182 uint32_t reserved2;
183
184 /** admin queue attributes */
185 union aqa_register aqa;
186
187 uint64_t asq; /* admin submission queue base addr */
188 uint64_t acq; /* admin completion queue base addr */
189 uint32_t reserved3[0x3f2];
190
191 struct {
192 uint32_t sq_tdbl; /* submission queue tail doorbell */
193 uint32_t cq_hdbl; /* completion queue head doorbell */
194 } doorbell[1] __packed;
195} __packed;
196
197struct nvme_command
198{
199 /* dword 0 */
200 uint16_t opc : 8; /* opcode */
201 uint16_t fuse : 2; /* fused operation */
202 uint16_t rsvd1 : 6;
203 uint16_t cid; /* command identifier */
204
205 /* dword 1 */
206 uint32_t nsid; /* namespace identifier */
207
208 /* dword 2-3 */
209 uint32_t rsvd2;
210 uint32_t rsvd3;
211
212 /* dword 4-5 */
213 uint64_t mptr; /* metadata pointer */
214
215 /* dword 6-7 */
216 uint64_t prp1; /* prp entry 1 */
217
218 /* dword 8-9 */
219 uint64_t prp2; /* prp entry 2 */
220
221 /* dword 10-15 */
222 uint32_t cdw10; /* command-specific */
223 uint32_t cdw11; /* command-specific */
224 uint32_t cdw12; /* command-specific */
225 uint32_t cdw13; /* command-specific */
226 uint32_t cdw14; /* command-specific */
227 uint32_t cdw15; /* command-specific */
228} __packed;
229
230struct nvme_status {
231
232 uint16_t p : 1; /* phase tag */
233 uint16_t sc : 8; /* status code */
234 uint16_t sct : 3; /* status code type */
235 uint16_t rsvd2 : 2;
236 uint16_t m : 1; /* more */
237 uint16_t dnr : 1; /* do not retry */
238} __packed;
239
240struct nvme_completion {
241
242 /* dword 0 */
243 uint32_t cdw0; /* command-specific */
244
245 /* dword 1 */
246 uint32_t rsvd1;
247
248 /* dword 2 */
249 uint16_t sqhd; /* submission queue head pointer */
250 uint16_t sqid; /* submission queue identifier */
251
252 /* dword 3 */
253 uint16_t cid; /* command identifier */
254 struct nvme_status status;
255} __packed;
256
257struct nvme_dsm_range {
258
259 uint32_t attributes;
260 uint32_t length;
261 uint64_t starting_lba;
262} __packed;
263
264/* status code types */
265enum nvme_status_code_type {
266 NVME_SCT_GENERIC = 0x0,
267 NVME_SCT_COMMAND_SPECIFIC = 0x1,
268 NVME_SCT_MEDIA_ERROR = 0x2,
269 /* 0x3-0x6 - reserved */
270 NVME_SCT_VENDOR_SPECIFIC = 0x7,
271};
272
273/* generic command status codes */
274enum nvme_generic_command_status_code {
275 NVME_SC_SUCCESS = 0x00,
276 NVME_SC_INVALID_OPCODE = 0x01,
277 NVME_SC_INVALID_FIELD = 0x02,
278 NVME_SC_COMMAND_ID_CONFLICT = 0x03,
279 NVME_SC_DATA_TRANSFER_ERROR = 0x04,
280 NVME_SC_ABORTED_POWER_LOSS = 0x05,
281 NVME_SC_INTERNAL_DEVICE_ERROR = 0x06,
282 NVME_SC_ABORTED_BY_REQUEST = 0x07,
283 NVME_SC_ABORTED_SQ_DELETION = 0x08,
284 NVME_SC_ABORTED_FAILED_FUSED = 0x09,
285 NVME_SC_ABORTED_MISSING_FUSED = 0x0a,
286 NVME_SC_INVALID_NAMESPACE_OR_FORMAT = 0x0b,
287 NVME_SC_COMMAND_SEQUENCE_ERROR = 0x0c,
288
289 NVME_SC_LBA_OUT_OF_RANGE = 0x80,
290 NVME_SC_CAPACITY_EXCEEDED = 0x81,
291 NVME_SC_NAMESPACE_NOT_READY = 0x82,
292};
293
294/* command specific status codes */
295enum nvme_command_specific_status_code {
296 NVME_SC_COMPLETION_QUEUE_INVALID = 0x00,
297 NVME_SC_INVALID_QUEUE_IDENTIFIER = 0x01,
298 NVME_SC_MAXIMUM_QUEUE_SIZE_EXCEEDED = 0x02,
299 NVME_SC_ABORT_COMMAND_LIMIT_EXCEEDED = 0x03,
300 /* 0x04 - reserved */
301 NVME_SC_ASYNC_EVENT_REQUEST_LIMIT_EXCEEDED = 0x05,
302 NVME_SC_INVALID_FIRMWARE_SLOT = 0x06,
303 NVME_SC_INVALID_FIRMWARE_IMAGE = 0x07,
304 NVME_SC_INVALID_INTERRUPT_VECTOR = 0x08,
305 NVME_SC_INVALID_LOG_PAGE = 0x09,
306 NVME_SC_INVALID_FORMAT = 0x0a,
307 NVME_SC_FIRMWARE_REQUIRES_RESET = 0x0b,
308
309 NVME_SC_CONFLICTING_ATTRIBUTES = 0x80,
310 NVME_SC_INVALID_PROTECTION_INFO = 0x81,
311 NVME_SC_ATTEMPTED_WRITE_TO_RO_PAGE = 0x82,
312};
313
314/* media error status codes */
315enum nvme_media_error_status_code {
316 NVME_SC_WRITE_FAULTS = 0x80,
317 NVME_SC_UNRECOVERED_READ_ERROR = 0x81,
318 NVME_SC_GUARD_CHECK_ERROR = 0x82,
319 NVME_SC_APPLICATION_TAG_CHECK_ERROR = 0x83,
320 NVME_SC_REFERENCE_TAG_CHECK_ERROR = 0x84,
321 NVME_SC_COMPARE_FAILURE = 0x85,
322 NVME_SC_ACCESS_DENIED = 0x86,
323};
324
325/* admin opcodes */
326enum nvme_admin_opcode {
327 NVME_OPC_DELETE_IO_SQ = 0x00,
328 NVME_OPC_CREATE_IO_SQ = 0x01,
329 NVME_OPC_GET_LOG_PAGE = 0x02,
330 /* 0x03 - reserved */
331 NVME_OPC_DELETE_IO_CQ = 0x04,
332 NVME_OPC_CREATE_IO_CQ = 0x05,
333 NVME_OPC_IDENTIFY = 0x06,
334 /* 0x07 - reserved */
335 NVME_OPC_ABORT = 0x08,
336 NVME_OPC_SET_FEATURES = 0x09,
337 NVME_OPC_GET_FEATURES = 0x0a,
338 /* 0x0b - reserved */
339 NVME_OPC_ASYNC_EVENT_REQUEST = 0x0c,
340 /* 0x0d-0x0f - reserved */
341 NVME_OPC_FIRMWARE_ACTIVATE = 0x10,
342 NVME_OPC_FIRMWARE_IMAGE_DOWNLOAD = 0x11,
343
344 NVME_OPC_FORMAT_NVM = 0x80,
345 NVME_OPC_SECURITY_SEND = 0x81,
346 NVME_OPC_SECURITY_RECEIVE = 0x82,
347};
348
349/* nvme nvm opcodes */
350enum nvme_nvm_opcode {
351 NVME_OPC_FLUSH = 0x00,
352 NVME_OPC_WRITE = 0x01,
353 NVME_OPC_READ = 0x02,
354 /* 0x03 - reserved */
355 NVME_OPC_WRITE_UNCORRECTABLE = 0x04,
356 NVME_OPC_COMPARE = 0x05,
357 /* 0x06-0x07 - reserved */
358 NVME_OPC_DATASET_MANAGEMENT = 0x09,
359};
360
361enum nvme_feature {
362 /* 0x00 - reserved */
363 NVME_FEAT_ARBITRATION = 0x01,
364 NVME_FEAT_POWER_MANAGEMENT = 0x02,
365 NVME_FEAT_LBA_RANGE_TYPE = 0x03,
366 NVME_FEAT_TEMPERATURE_THRESHOLD = 0x04,
367 NVME_FEAT_ERROR_RECOVERY = 0x05,
368 NVME_FEAT_VOLATILE_WRITE_CACHE = 0x06,
369 NVME_FEAT_NUMBER_OF_QUEUES = 0x07,
370 NVME_FEAT_INTERRUPT_COALESCING = 0x08,
371 NVME_FEAT_INTERRUPT_VECTOR_CONFIGURATION = 0x09,
372 NVME_FEAT_WRITE_ATOMICITY = 0x0A,
373 NVME_FEAT_ASYNC_EVENT_CONFIGURATION = 0x0B,
374 /* 0x0C-0x7F - reserved */
375 NVME_FEAT_SOFTWARE_PROGRESS_MARKER = 0x80,
376 /* 0x81-0xBF - command set specific (reserved) */
377 /* 0xC0-0xFF - vendor specific */
378};
379
380enum nvme_dsm_attribute {
381 NVME_DSM_ATTR_INTEGRAL_READ = 0x1,
382 NVME_DSM_ATTR_INTEGRAL_WRITE = 0x2,
383 NVME_DSM_ATTR_DEALLOCATE = 0x4,
384};
385
386enum nvme_activate_action {
387 NVME_AA_REPLACE_NO_ACTIVATE = 0x0,
388 NVME_AA_REPLACE_ACTIVATE = 0x1,
389 NVME_AA_ACTIVATE = 0x2,
390};
391
392struct nvme_controller_data {
393
394 /* bytes 0-255: controller capabilities and features */
395
396 /** pci vendor id */
397 uint16_t vid;
398
399 /** pci subsystem vendor id */
400 uint16_t ssvid;
401
402 /** serial number */
403 int8_t sn[20];
404
405 /** model number */
406 int8_t mn[40];
407
408 /** firmware revision */
409 uint8_t fr[8];
410
411 /** recommended arbitration burst */
412 uint8_t rab;
413
414 /** ieee oui identifier */
415 uint8_t ieee[3];
416
417 /** multi-interface capabilities */
418 uint8_t mic;
419
420 /** maximum data transfer size */
421 uint8_t mdts;
422
423 uint8_t reserved1[178];
424
425 /* bytes 256-511: admin command set attributes */
426
427 /** optional admin command support */
428 struct {
429 /* supports security send/receive commands */
430 uint16_t security : 1;
431
432 /* supports format nvm command */
433 uint16_t format : 1;
434
435 /* supports firmware activate/download commands */
436 uint16_t firmware : 1;
437
438 uint16_t oacs_rsvd : 13;
439 } __packed oacs;
440
441 /** abort command limit */
442 uint8_t acl;
443
444 /** asynchronous event request limit */
445 uint8_t aerl;
446
447 /** firmware updates */
448 struct {
449 /* first slot is read-only */
450 uint8_t slot1_ro : 1;
451
452 /* number of firmware slots */
453 uint8_t num_slots : 3;
454
455 uint8_t frmw_rsvd : 4;
456 } __packed frmw;
457
458 /** log page attributes */
459 struct {
460 /* per namespace smart/health log page */
461 uint8_t ns_smart : 1;
462
463 uint8_t lpa_rsvd : 7;
464 } __packed lpa;
465
466 /** error log page entries */
467 uint8_t elpe;
468
469 /** number of power states supported */
470 uint8_t npss;
471
472 /** admin vendor specific command configuration */
473 struct {
474 /* admin vendor specific commands use spec format */
475 uint8_t spec_format : 1;
476
477 uint8_t avscc_rsvd : 7;
478 } __packed avscc;
479
480 uint8_t reserved2[247];
481
482 /* bytes 512-703: nvm command set attributes */
483
484 /** submission queue entry size */
485 struct {
486 uint8_t min : 4;
487 uint8_t max : 4;
488 } __packed sqes;
489
490 /** completion queue entry size */
491 struct {
492 uint8_t min : 4;
493 uint8_t max : 4;
494 } __packed cqes;
495
496 uint8_t reserved3[2];
497
498 /** number of namespaces */
499 uint32_t nn;
500
501 /** optional nvm command support */
502 struct {
503 uint16_t compare : 1;
504 uint16_t write_unc : 1;
505 uint16_t dsm: 1;
506 uint16_t reserved: 13;
507 } __packed oncs;
508
509 /** fused operation support */
510 uint16_t fuses;
511
512 /** format nvm attributes */
513 uint8_t fna;
514
515 /** volatile write cache */
516 struct {
517 uint8_t present : 1;
518 uint8_t reserved : 7;
519 } __packed vwc;
520
521 /* TODO: flesh out remaining nvm command set attributes */
522 uint8_t reserved4[178];
523
524 /* bytes 704-2047: i/o command set attributes */
525 uint8_t reserved5[1344];
526
527 /* bytes 2048-3071: power state descriptors */
528 uint8_t reserved6[1024];
529
530 /* bytes 3072-4095: vendor specific */
531 uint8_t reserved7[1024];
532} __packed __aligned(4);
533
534struct nvme_namespace_data {
535
536 /** namespace size */
537 uint64_t nsze;
538
539 /** namespace capacity */
540 uint64_t ncap;
541
542 /** namespace utilization */
543 uint64_t nuse;
544
545 /** namespace features */
546 struct {
547 /** thin provisioning */
548 uint8_t thin_prov : 1;
549 uint8_t reserved1 : 7;
550 } __packed nsfeat;
551
552 /** number of lba formats */
553 uint8_t nlbaf;
554
555 /** formatted lba size */
556 struct {
557 uint8_t format : 4;
558 uint8_t extended : 1;
559 uint8_t reserved2 : 3;
560 } __packed flbas;
561
562 /** metadata capabilities */
563 struct {
564 /* metadata can be transferred as part of data prp list */
565 uint8_t extended : 1;
566
567 /* metadata can be transferred with separate metadata pointer */
568 uint8_t pointer : 1;
569
570 uint8_t reserved3 : 6;
571 } __packed mc;
572
573 /** end-to-end data protection capabilities */
574 struct {
575 /* protection information type 1 */
576 uint8_t pit1 : 1;
577
578 /* protection information type 2 */
579 uint8_t pit2 : 1;
580
581 /* protection information type 3 */
582 uint8_t pit3 : 1;
583
584 /* first eight bytes of metadata */
585 uint8_t md_start : 1;
586
587 /* last eight bytes of metadata */
588 uint8_t md_end : 1;
589 } __packed dpc;
590
591 /** end-to-end data protection type settings */
592 struct {
593 /* protection information type */
594 uint8_t pit : 3;
595
596 /* 1 == protection info transferred at start of metadata */
597 /* 0 == protection info transferred at end of metadata */
598 uint8_t md_start : 1;
599
600 uint8_t reserved4 : 4;
601 } __packed dps;
602
603 uint8_t reserved5[98];
604
605 /** lba format support */
606 struct {
607 /** metadata size */
608 uint32_t ms : 16;
609
610 /** lba data size */
611 uint32_t lbads : 8;
612
613 /** relative performance */
614 uint32_t rp : 2;
615
616 uint32_t reserved6 : 6;
617 } __packed lbaf[16];
618
619 uint8_t reserved6[192];
620
621 uint8_t vendor_specific[3712];
622} __packed __aligned(4);
623
624enum nvme_log_page {
625
626 /* 0x00 - reserved */
627 NVME_LOG_ERROR = 0x01,
628 NVME_LOG_HEALTH_INFORMATION = 0x02,
629 NVME_LOG_FIRMWARE_SLOT = 0x03,
630 /* 0x04-0x7F - reserved */
631 /* 0x80-0xBF - I/O command set specific */
632 /* 0xC0-0xFF - vendor specific */
633};
634
635struct nvme_error_information_entry {
636
637 uint64_t error_count;
638 uint16_t sqid;
639 uint16_t cid;
640 struct nvme_status status;
641 uint16_t error_location;
642 uint64_t lba;
643 uint32_t nsid;
644 uint8_t vendor_specific;
645 uint8_t reserved[35];
646} __packed __aligned(4);
647
648union nvme_critical_warning_state {
649
650 uint8_t raw;
651
652 struct {
653 uint8_t available_spare : 1;
654 uint8_t temperature : 1;
655 uint8_t device_reliability : 1;
656 uint8_t read_only : 1;
657 uint8_t volatile_memory_backup : 1;
658 uint8_t reserved : 3;
659 } __packed bits;
660} __packed;
661
662struct nvme_health_information_page {
663
664 union nvme_critical_warning_state critical_warning;
665
666 uint16_t temperature;
667 uint8_t available_spare;
668 uint8_t available_spare_threshold;
669 uint8_t percentage_used;
670
671 uint8_t reserved[26];
672
673 /*
674 * Note that the following are 128-bit values, but are
675 * defined as an array of 2 64-bit values.
676 */
677 /* Data Units Read is always in 512-byte units. */
678 uint64_t data_units_read[2];
679 /* Data Units Written is always in 512-byte units. */
680 uint64_t data_units_written[2];
681 /* For NVM command set, this includes Compare commands. */
682 uint64_t host_read_commands[2];
683 uint64_t host_write_commands[2];
684 /* Controller Busy Time is reported in minutes. */
685 uint64_t controller_busy_time[2];
686 uint64_t power_cycles[2];
687 uint64_t power_on_hours[2];
688 uint64_t unsafe_shutdowns[2];
689 uint64_t media_errors[2];
690 uint64_t num_error_info_log_entries[2];
691
692 uint8_t reserved2[320];
693} __packed __aligned(4);
694
695struct nvme_firmware_page {
696
697 struct {
698 uint8_t slot : 3; /* slot for current FW */
699 uint8_t reserved : 5;
700 } __packed afi;
701
702 uint8_t reserved[7];
703 uint64_t revision[7]; /* revisions for 7 slots */
704 uint8_t reserved2[448];
705} __packed __aligned(4);
706
707#define NVME_TEST_MAX_THREADS 128
708
709struct nvme_io_test {
710
711 enum nvme_nvm_opcode opc;
712 uint32_t size;
713 uint32_t time; /* in seconds */
714 uint32_t num_threads;
715 uint32_t flags;
716 uint32_t io_completed[NVME_TEST_MAX_THREADS];
717};
718
719enum nvme_io_test_flags {
720
721 /*
722 * Specifies whether dev_refthread/dev_relthread should be
723 * called during NVME_BIO_TEST. Ignored for other test
724 * types.
725 */
726 NVME_TEST_FLAG_REFTHREAD = 0x1,
727};
728
729struct nvme_pt_command {
730
731 /*
732 * cmd is used to specify a passthrough command to a controller or
733 * namespace.
734 *
735 * The following fields from cmd may be specified by the caller:
736 * * opc (opcode)
737 * * nsid (namespace id) - for admin commands only
738 * * cdw10-cdw15
739 *
740 * Remaining fields must be set to 0 by the caller.
741 */
742 struct nvme_command cmd;
743
744 /*
745 * cpl returns completion status for the passthrough command
746 * specified by cmd.
747 *
748 * The following fields will be filled out by the driver, for
749 * consumption by the caller:
750 * * cdw0
751 * * status (except for phase)
752 *
753 * Remaining fields will be set to 0 by the driver.
754 */
755 struct nvme_completion cpl;
756
757 /* buf is the data buffer associated with this passthrough command. */
758 void * buf;
759
760 /*
761 * len is the length of the data buffer associated with this
762 * passthrough command.
763 */
764 uint32_t len;
765
766 /*
767 * is_read = 1 if the passthrough command will read data into the
768 * supplied buffer.
769 *
770 * is_read = 0 if the passthrough command will write data into the
771 * supplied buffer.
772 */
773 uint32_t is_read;
774
775 /*
776 * driver_lock is used by the driver only. It must be set to 0
777 * by the caller.
778 */
779 struct mtx * driver_lock;
780};
781
782#define nvme_completion_is_error(cpl) \
783 ((cpl)->status.sc != 0 || (cpl)->status.sct != 0)
784
785#ifdef _KERNEL
786
787struct bio;
788
789struct nvme_namespace;
790struct nvme_controller;
791struct nvme_consumer;
792
793typedef void (*nvme_cb_fn_t)(void *, const struct nvme_completion *);
794
795typedef void *(*nvme_cons_ns_fn_t)(struct nvme_namespace *, void *);
796typedef void *(*nvme_cons_ctrlr_fn_t)(struct nvme_controller *);
797typedef void (*nvme_cons_async_fn_t)(void *, const struct nvme_completion *,
798 uint32_t, void *, uint32_t);
799typedef void (*nvme_cons_fail_fn_t)(void *);
800
801enum nvme_namespace_flags {
802 NVME_NS_DEALLOCATE_SUPPORTED = 0x1,
803 NVME_NS_FLUSH_SUPPORTED = 0x2,
804};
805
806int nvme_ctrlr_passthrough_cmd(struct nvme_controller *ctrlr,
807 struct nvme_pt_command *pt,
808 uint32_t nsid, int is_user_buffer,
809 int is_admin_cmd);
810
811/* Admin functions */
812void nvme_ctrlr_cmd_set_feature(struct nvme_controller *ctrlr,
813 uint8_t feature, uint32_t cdw11,
814 void *payload, uint32_t payload_size,
815 nvme_cb_fn_t cb_fn, void *cb_arg);
816void nvme_ctrlr_cmd_get_feature(struct nvme_controller *ctrlr,
817 uint8_t feature, uint32_t cdw11,
818 void *payload, uint32_t payload_size,
819 nvme_cb_fn_t cb_fn, void *cb_arg);
820void nvme_ctrlr_cmd_get_log_page(struct nvme_controller *ctrlr,
821 uint8_t log_page, uint32_t nsid,
822 void *payload, uint32_t payload_size,
823 nvme_cb_fn_t cb_fn, void *cb_arg);
824
825/* NVM I/O functions */
826int nvme_ns_cmd_write(struct nvme_namespace *ns, void *payload,
827 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
828 void *cb_arg);
829int nvme_ns_cmd_write_bio(struct nvme_namespace *ns, struct bio *bp,
830 nvme_cb_fn_t cb_fn, void *cb_arg);
831int nvme_ns_cmd_read(struct nvme_namespace *ns, void *payload,
832 uint64_t lba, uint32_t lba_count, nvme_cb_fn_t cb_fn,
833 void *cb_arg);
834int nvme_ns_cmd_read_bio(struct nvme_namespace *ns, struct bio *bp,
835 nvme_cb_fn_t cb_fn, void *cb_arg);
836int nvme_ns_cmd_deallocate(struct nvme_namespace *ns, void *payload,
837 uint8_t num_ranges, nvme_cb_fn_t cb_fn,
838 void *cb_arg);
839int nvme_ns_cmd_flush(struct nvme_namespace *ns, nvme_cb_fn_t cb_fn,
840 void *cb_arg);
841
842/* Registration functions */
843struct nvme_consumer * nvme_register_consumer(nvme_cons_ns_fn_t ns_fn,
844 nvme_cons_ctrlr_fn_t ctrlr_fn,
845 nvme_cons_async_fn_t async_fn,
846 nvme_cons_fail_fn_t fail_fn);
847void nvme_unregister_consumer(struct nvme_consumer *consumer);
848
849/* Controller helper functions */
850device_t nvme_ctrlr_get_device(struct nvme_controller *ctrlr);
851const struct nvme_controller_data *
852 nvme_ctrlr_get_data(struct nvme_controller *ctrlr);
853
854/* Namespace helper functions */
855uint32_t nvme_ns_get_max_io_xfer_size(struct nvme_namespace *ns);
856uint32_t nvme_ns_get_sector_size(struct nvme_namespace *ns);
857uint64_t nvme_ns_get_num_sectors(struct nvme_namespace *ns);
858uint64_t nvme_ns_get_size(struct nvme_namespace *ns);
859uint32_t nvme_ns_get_flags(struct nvme_namespace *ns);
860const char * nvme_ns_get_serial_number(struct nvme_namespace *ns);
861const char * nvme_ns_get_model_number(struct nvme_namespace *ns);
862const struct nvme_namespace_data *
863 nvme_ns_get_data(struct nvme_namespace *ns);
864
865int nvme_ns_bio_process(struct nvme_namespace *ns, struct bio *bp,
866 nvme_cb_fn_t cb_fn);
867
868#endif /* _KERNEL */
869
870#endif /* __NVME_H__ */
|