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1/*-
2 * Copyright (c) 2005 by David E. O'Brien <obrien@FreeBSD.org>.
3 * Copyright (c) 2003,2004 by Quinton Dolan <q@onthenet.com.au>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY
16 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
22 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id: if_nv.c,v 1.19 2004/08/12 14:00:05 q Exp $
28 */
29/*
30 * NVIDIA nForce MCP Networking Adapter driver
31 *
32 * This is a port of the NVIDIA MCP Linux ethernet driver distributed by NVIDIA
33 * through their web site.
34 *
35 * All mainstream nForce and nForce2 motherboards are supported. This module
36 * is as stable, sometimes more stable, than the linux version. (Recent
37 * Linux stability issues seem to be related to some issues with newer
38 * distributions using GCC 3.x, however this don't appear to effect FreeBSD
39 * 5.x).
40 *
41 * In accordance with the NVIDIA distribution license it is necessary to
42 * link this module against the nvlibnet.o binary object included in the
43 * Linux driver source distribution. The binary component is not modified in
44 * any way and is simply linked against a FreeBSD equivalent of the nvnet.c
45 * linux kernel module "wrapper".
46 *
47 * The Linux driver uses a common code API that is shared between Win32 and
48 * i386 Linux. This abstracts the low level driver functions and uses
49 * callbacks and hooks to access the underlying hardware device. By using
50 * this same API in a FreeBSD kernel module it is possible to support the
51 * hardware without breaching the Linux source distributions licensing
52 * requirements, or obtaining the hardware programming specifications.
53 *
54 * Although not conventional, it works, and given the relatively small
55 * amount of hardware centric code, it's hopefully no more buggy than its
56 * linux counterpart.
57 *
58 * NVIDIA now support the nForce3 AMD64 platform, however I have been
59 * unable to access such a system to verify support. However, the code is
60 * reported to work with little modification when compiled with the AMD64
61 * version of the NVIDIA Linux library. All that should be necessary to make
62 * the driver work is to link it directly into the kernel, instead of as a
63 * module, and apply the docs/amd64.diff patch in this source distribution to
64 * the NVIDIA Linux driver source.
65 *
66 * This driver should work on all versions of FreeBSD since 4.9/5.1 as well
67 * as recent versions of DragonFly.
68 *
69 * Written by Quinton Dolan <q@onthenet.com.au>
70 * Portions based on existing FreeBSD network drivers.
71 * NVIDIA API usage derived from distributed NVIDIA NVNET driver source files.
72 */
73
74#include <sys/cdefs.h>
75__FBSDID("$FreeBSD: head/sys/dev/nve/if_nve.c 158651 2006-05-16 14:37:58Z phk $");
75__FBSDID("$FreeBSD: head/sys/dev/nve/if_nve.c 158735 2006-05-18 23:19:44Z jhb $");
76
77#include <sys/param.h>
78#include <sys/systm.h>
79#include <sys/sockio.h>
80#include <sys/mbuf.h>
81#include <sys/malloc.h>
82#include <sys/kernel.h>
83#include <sys/socket.h>
84#include <sys/sysctl.h>
85#include <sys/queue.h>
86#include <sys/module.h>
87
88#include <net/if.h>
89#include <net/if_arp.h>
90#include <net/ethernet.h>
91#include <net/if_dl.h>
92#include <net/if_media.h>
93#include <net/if_types.h>
94#include <net/bpf.h>
95#include <net/if_vlan_var.h>
96
97#include <machine/bus.h>
98#include <machine/resource.h>
99
100#include <vm/vm.h> /* for vtophys */
101#include <vm/pmap.h> /* for vtophys */
102#include <sys/bus.h>
103#include <sys/rman.h>
104
105#include <dev/pci/pcireg.h>
106#include <dev/pci/pcivar.h>
107#include <dev/mii/mii.h>
108#include <dev/mii/miivar.h>
109#include "miibus_if.h"
110
111/* Include NVIDIA Linux driver header files */
112#include <contrib/dev/nve/nvenet_version.h>
113#define linux
114#include <contrib/dev/nve/basetype.h>
115#include <contrib/dev/nve/phy.h>
116#include "os+%DIKED-nve.h"
117#include <contrib/dev/nve/drvinfo.h>
118#include <contrib/dev/nve/adapter.h>
119#undef linux
120
121#include <dev/nve/if_nvereg.h>
122
123MODULE_DEPEND(nve, pci, 1, 1, 1);
124MODULE_DEPEND(nve, ether, 1, 1, 1);
125MODULE_DEPEND(nve, miibus, 1, 1, 1);
126
127static int nve_probe(device_t);
128static int nve_attach(device_t);
129static int nve_detach(device_t);
130static void nve_init(void *);
131static void nve_init_locked(struct nve_softc *);
132static void nve_stop(struct nve_softc *);
133static void nve_shutdown(device_t);
134static int nve_init_rings(struct nve_softc *);
135static void nve_free_rings(struct nve_softc *);
136
137static void nve_ifstart(struct ifnet *);
138static void nve_ifstart_locked(struct ifnet *);
139static int nve_ioctl(struct ifnet *, u_long, caddr_t);
140static void nve_intr(void *);
141static void nve_tick(void *);
142static void nve_setmulti(struct nve_softc *);
143static void nve_watchdog(struct ifnet *);
144static void nve_update_stats(struct nve_softc *);
145
146static int nve_ifmedia_upd(struct ifnet *);
147static void nve_ifmedia_upd_locked(struct ifnet *);
148static void nve_ifmedia_sts(struct ifnet *, struct ifmediareq *);
149static int nve_miibus_readreg(device_t, int, int);
150static void nve_miibus_writereg(device_t, int, int, int);
151
152static void nve_dmamap_cb(void *, bus_dma_segment_t *, int, int);
153static void nve_dmamap_tx_cb(void *, bus_dma_segment_t *, int, bus_size_t, int);
154
155static NV_SINT32 nve_osalloc(PNV_VOID, PMEMORY_BLOCK);
156static NV_SINT32 nve_osfree(PNV_VOID, PMEMORY_BLOCK);
157static NV_SINT32 nve_osallocex(PNV_VOID, PMEMORY_BLOCKEX);
158static NV_SINT32 nve_osfreeex(PNV_VOID, PMEMORY_BLOCKEX);
159static NV_SINT32 nve_osclear(PNV_VOID, PNV_VOID, NV_SINT32);
160static NV_SINT32 nve_osdelay(PNV_VOID, NV_UINT32);
161static NV_SINT32 nve_osallocrxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID *);
162static NV_SINT32 nve_osfreerxbuf(PNV_VOID, PMEMORY_BLOCK, PNV_VOID);
163static NV_SINT32 nve_ospackettx(PNV_VOID, PNV_VOID, NV_UINT32);
164static NV_SINT32 nve_ospacketrx(PNV_VOID, PNV_VOID, NV_UINT32, NV_UINT8 *, NV_UINT8);
165static NV_SINT32 nve_oslinkchg(PNV_VOID, NV_SINT32);
166static NV_SINT32 nve_osalloctimer(PNV_VOID, PNV_VOID *);
167static NV_SINT32 nve_osfreetimer(PNV_VOID, PNV_VOID);
168static NV_SINT32 nve_osinittimer(PNV_VOID, PNV_VOID, PTIMER_FUNC, PNV_VOID);
169static NV_SINT32 nve_ossettimer(PNV_VOID, PNV_VOID, NV_UINT32);
170static NV_SINT32 nve_oscanceltimer(PNV_VOID, PNV_VOID);
171
172static NV_SINT32 nve_ospreprocpkt(PNV_VOID, PNV_VOID, PNV_VOID *, NV_UINT8 *, NV_UINT8);
173static PNV_VOID nve_ospreprocpktnopq(PNV_VOID, PNV_VOID);
174static NV_SINT32 nve_osindicatepkt(PNV_VOID, PNV_VOID *, NV_UINT32);
175static NV_SINT32 nve_oslockalloc(PNV_VOID, NV_SINT32, PNV_VOID *);
176static NV_SINT32 nve_oslockacquire(PNV_VOID, NV_SINT32, PNV_VOID);
177static NV_SINT32 nve_oslockrelease(PNV_VOID, NV_SINT32, PNV_VOID);
178static PNV_VOID nve_osreturnbufvirt(PNV_VOID, PNV_VOID);
179
180static device_method_t nve_methods[] = {
181 /* Device interface */
182 DEVMETHOD(device_probe, nve_probe),
183 DEVMETHOD(device_attach, nve_attach),
184 DEVMETHOD(device_detach, nve_detach),
185 DEVMETHOD(device_shutdown, nve_shutdown),
186
187 /* Bus interface */
188 DEVMETHOD(bus_print_child, bus_generic_print_child),
189 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
190
191 /* MII interface */
192 DEVMETHOD(miibus_readreg, nve_miibus_readreg),
193 DEVMETHOD(miibus_writereg, nve_miibus_writereg),
194
195 {0, 0}
196};
197
198static driver_t nve_driver = {
199 "nve",
200 nve_methods,
201 sizeof(struct nve_softc)
202};
203
204static devclass_t nve_devclass;
205
206static int nve_pollinterval = 0;
207SYSCTL_INT(_hw, OID_AUTO, nve_pollinterval, CTLFLAG_RW,
208 &nve_pollinterval, 0, "delay between interface polls");
209
210DRIVER_MODULE(nve, pci, nve_driver, nve_devclass, 0, 0);
211DRIVER_MODULE(miibus, nve, miibus_driver, miibus_devclass, 0, 0);
212
213static struct nve_type nve_devs[] = {
214 {NVIDIA_VENDORID, NFORCE_MCPNET1_DEVICEID,
215 "NVIDIA nForce MCP Networking Adapter"},
216 {NVIDIA_VENDORID, NFORCE_MCPNET2_DEVICEID,
217 "NVIDIA nForce MCP2 Networking Adapter"},
218 {NVIDIA_VENDORID, NFORCE_MCPNET3_DEVICEID,
219 "NVIDIA nForce MCP3 Networking Adapter"},
220 {NVIDIA_VENDORID, NFORCE_MCPNET4_DEVICEID,
221 "NVIDIA nForce MCP4 Networking Adapter"},
222 {NVIDIA_VENDORID, NFORCE_MCPNET5_DEVICEID,
223 "NVIDIA nForce MCP5 Networking Adapter"},
224 {NVIDIA_VENDORID, NFORCE_MCPNET6_DEVICEID,
225 "NVIDIA nForce MCP6 Networking Adapter"},
226 {NVIDIA_VENDORID, NFORCE_MCPNET7_DEVICEID,
227 "NVIDIA nForce MCP7 Networking Adapter"},
228 {NVIDIA_VENDORID, NFORCE_MCPNET8_DEVICEID,
229 "NVIDIA nForce MCP8 Networking Adapter"},
230 {NVIDIA_VENDORID, NFORCE_MCPNET9_DEVICEID,
231 "NVIDIA nForce MCP9 Networking Adapter"},
232 {NVIDIA_VENDORID, NFORCE_MCPNET10_DEVICEID,
233 "NVIDIA nForce MCP10 Networking Adapter"},
234 {NVIDIA_VENDORID, NFORCE_MCPNET11_DEVICEID,
235 "NVIDIA nForce MCP11 Networking Adapter"},
236 {NVIDIA_VENDORID, NFORCE_MCPNET12_DEVICEID,
237 "NVIDIA nForce MCP12 Networking Adapter"},
238 {NVIDIA_VENDORID, NFORCE_MCPNET13_DEVICEID,
239 "NVIDIA nForce MCP13 Networking Adapter"},
240 {0, 0, NULL}
241};
242
243/* DMA MEM map callback function to get data segment physical address */
244static void
245nve_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nsegs, int error)
246{
247 if (error)
248 return;
249
250 KASSERT(nsegs == 1,
251 ("Too many DMA segments returned when mapping DMA memory"));
252 *(bus_addr_t *)arg = segs->ds_addr;
253}
254
255/* DMA RX map callback function to get data segment physical address */
256static void
257nve_dmamap_rx_cb(void *arg, bus_dma_segment_t * segs, int nsegs,
258 bus_size_t mapsize, int error)
259{
260 if (error)
261 return;
262 *(bus_addr_t *)arg = segs->ds_addr;
263}
264
265/*
266 * DMA TX buffer callback function to allocate fragment data segment
267 * addresses
268 */
269static void
270nve_dmamap_tx_cb(void *arg, bus_dma_segment_t * segs, int nsegs, bus_size_t mapsize, int error)
271{
272 struct nve_tx_desc *info;
273
274 info = arg;
275 if (error)
276 return;
277 KASSERT(nsegs < NV_MAX_FRAGS,
278 ("Too many DMA segments returned when mapping mbuf"));
279 info->numfrags = nsegs;
280 bcopy(segs, info->frags, nsegs * sizeof(bus_dma_segment_t));
281}
282
283/* Probe for supported hardware ID's */
284static int
285nve_probe(device_t dev)
286{
287 struct nve_type *t;
288
289 t = nve_devs;
290 /* Check for matching PCI DEVICE ID's */
291 while (t->name != NULL) {
292 if ((pci_get_vendor(dev) == t->vid_id) &&
293 (pci_get_device(dev) == t->dev_id)) {
294 device_set_desc(dev, t->name);
295 return (0);
296 }
297 t++;
298 }
299
300 return (ENXIO);
301}
302
303/* Attach driver and initialise hardware for use */
304static int
305nve_attach(device_t dev)
306{
307 u_char eaddr[ETHER_ADDR_LEN];
308 struct nve_softc *sc;
309 struct ifnet *ifp;
310 OS_API *osapi;
311 ADAPTER_OPEN_PARAMS OpenParams;
312 int error = 0, i, rid;
313
314 if (bootverbose)
315 device_printf(dev, "nvenetlib.o version %s\n", DRIVER_VERSION);
316
317 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - entry\n");
318
319 sc = device_get_softc(dev);
320
321 /* Allocate mutex */
322 mtx_init(&sc->mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
323 MTX_DEF);
324 callout_init_mtx(&sc->stat_callout, &sc->mtx, 0);
325
326 sc->dev = dev;
327
328 /* Preinitialize data structures */
329 bzero(&OpenParams, sizeof(ADAPTER_OPEN_PARAMS));
330
331 /* Enable bus mastering */
332 pci_enable_busmaster(dev);
333
334 /* Allocate memory mapped address space */
335 rid = NV_RID;
336 sc->res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 0, ~0, 1,
337 RF_ACTIVE);
338
339 if (sc->res == NULL) {
340 device_printf(dev, "couldn't map memory\n");
341 error = ENXIO;
342 goto fail;
343 }
344 sc->sc_st = rman_get_bustag(sc->res);
345 sc->sc_sh = rman_get_bushandle(sc->res);
346
347 /* Allocate interrupt */
348 rid = 0;
349 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
350 RF_SHAREABLE | RF_ACTIVE);
351
352 if (sc->irq == NULL) {
353 device_printf(dev, "couldn't map interrupt\n");
354 error = ENXIO;
355 goto fail;
356 }
357 /* Allocate DMA tags */
358 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
359 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES * NV_MAX_FRAGS,
360 NV_MAX_FRAGS, MCLBYTES, 0,
361 busdma_lock_mutex, &Giant,
362 &sc->mtag);
363 if (error) {
364 device_printf(dev, "couldn't allocate dma tag\n");
365 goto fail;
366 }
367 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
368 BUS_SPACE_MAXADDR, NULL, NULL,
369 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 1,
370 sizeof(struct nve_rx_desc) * RX_RING_SIZE, 0,
371 busdma_lock_mutex, &Giant,
372 &sc->rtag);
373 if (error) {
374 device_printf(dev, "couldn't allocate dma tag\n");
375 goto fail;
376 }
377 error = bus_dma_tag_create(NULL, 4, 0, BUS_SPACE_MAXADDR_32BIT,
378 BUS_SPACE_MAXADDR, NULL, NULL,
379 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 1,
380 sizeof(struct nve_tx_desc) * TX_RING_SIZE, 0,
381 busdma_lock_mutex, &Giant,
382 &sc->ttag);
383 if (error) {
384 device_printf(dev, "couldn't allocate dma tag\n");
385 goto fail;
386 }
387 /* Allocate DMA safe memory and get the DMA addresses. */
388 error = bus_dmamem_alloc(sc->ttag, (void **)&sc->tx_desc,
389 BUS_DMA_WAITOK, &sc->tmap);
390 if (error) {
391 device_printf(dev, "couldn't allocate dma memory\n");
392 goto fail;
393 }
394 bzero(sc->tx_desc, sizeof(struct nve_tx_desc) * TX_RING_SIZE);
395 error = bus_dmamap_load(sc->ttag, sc->tmap, sc->tx_desc,
396 sizeof(struct nve_tx_desc) * TX_RING_SIZE, nve_dmamap_cb,
397 &sc->tx_addr, 0);
398 if (error) {
399 device_printf(dev, "couldn't map dma memory\n");
400 goto fail;
401 }
402 error = bus_dmamem_alloc(sc->rtag, (void **)&sc->rx_desc,
403 BUS_DMA_WAITOK, &sc->rmap);
404 if (error) {
405 device_printf(dev, "couldn't allocate dma memory\n");
406 goto fail;
407 }
408 bzero(sc->rx_desc, sizeof(struct nve_rx_desc) * RX_RING_SIZE);
409 error = bus_dmamap_load(sc->rtag, sc->rmap, sc->rx_desc,
410 sizeof(struct nve_rx_desc) * RX_RING_SIZE, nve_dmamap_cb,
411 &sc->rx_addr, 0);
412 if (error) {
413 device_printf(dev, "couldn't map dma memory\n");
414 goto fail;
415 }
416 /* Initialize rings. */
417 if (nve_init_rings(sc)) {
418 device_printf(dev, "failed to init rings\n");
419 error = ENXIO;
420 goto fail;
421 }
422 /* Setup NVIDIA API callback routines */
423 osapi = &sc->osapi;
424 osapi->pOSCX = sc;
425 osapi->pfnAllocMemory = nve_osalloc;
426 osapi->pfnFreeMemory = nve_osfree;
427 osapi->pfnAllocMemoryEx = nve_osallocex;
428 osapi->pfnFreeMemoryEx = nve_osfreeex;
429 osapi->pfnClearMemory = nve_osclear;
430 osapi->pfnStallExecution = nve_osdelay;
431 osapi->pfnAllocReceiveBuffer = nve_osallocrxbuf;
432 osapi->pfnFreeReceiveBuffer = nve_osfreerxbuf;
433 osapi->pfnPacketWasSent = nve_ospackettx;
434 osapi->pfnPacketWasReceived = nve_ospacketrx;
435 osapi->pfnLinkStateHasChanged = nve_oslinkchg;
436 osapi->pfnAllocTimer = nve_osalloctimer;
437 osapi->pfnFreeTimer = nve_osfreetimer;
438 osapi->pfnInitializeTimer = nve_osinittimer;
439 osapi->pfnSetTimer = nve_ossettimer;
440 osapi->pfnCancelTimer = nve_oscanceltimer;
441 osapi->pfnPreprocessPacket = nve_ospreprocpkt;
442 osapi->pfnPreprocessPacketNopq = nve_ospreprocpktnopq;
443 osapi->pfnIndicatePackets = nve_osindicatepkt;
444 osapi->pfnLockAlloc = nve_oslockalloc;
445 osapi->pfnLockAcquire = nve_oslockacquire;
446 osapi->pfnLockRelease = nve_oslockrelease;
447 osapi->pfnReturnBufferVirtual = nve_osreturnbufvirt;
448
449 sc->linkup = FALSE;
450 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + FCS_LEN;
451
452 /* TODO - We don't support hardware offload yet */
453 sc->hwmode = 1;
454 sc->media = 0;
455
456 /* Set NVIDIA API startup parameters */
457 OpenParams.MaxDpcLoop = 2;
458 OpenParams.MaxRxPkt = RX_RING_SIZE;
459 OpenParams.MaxTxPkt = TX_RING_SIZE;
460 OpenParams.SentPacketStatusSuccess = 1;
461 OpenParams.SentPacketStatusFailure = 0;
462 OpenParams.MaxRxPktToAccumulate = 6;
463 OpenParams.ulPollInterval = nve_pollinterval;
464 OpenParams.SetForcedModeEveryNthRxPacket = 0;
465 OpenParams.SetForcedModeEveryNthTxPacket = 0;
466 OpenParams.RxForcedInterrupt = 0;
467 OpenParams.TxForcedInterrupt = 0;
468 OpenParams.pOSApi = osapi;
469 OpenParams.pvHardwareBaseAddress = rman_get_virtual(sc->res);
470 OpenParams.bASFEnabled = 0;
471 OpenParams.ulDescriptorVersion = sc->hwmode;
472 OpenParams.ulMaxPacketSize = sc->max_frame_size;
473 OpenParams.DeviceId = pci_get_device(dev);
474
475 /* Open NVIDIA Hardware API */
476 error = ADAPTER_Open(&OpenParams, (void **)&(sc->hwapi), &sc->phyaddr);
477 if (error) {
478 device_printf(dev,
479 "failed to open NVIDIA Hardware API: 0x%x\n", error);
480 goto fail;
481 }
482
483 /* TODO - Add support for MODE2 hardware offload */
484
485 bzero(&sc->adapterdata, sizeof(sc->adapterdata));
486
487 sc->adapterdata.ulMediaIF = sc->media;
488 sc->adapterdata.ulModeRegTxReadCompleteEnable = 1;
489 sc->hwapi->pfnSetCommonData(sc->hwapi->pADCX, &sc->adapterdata);
490
491 /* MAC is loaded backwards into h/w reg */
492 sc->hwapi->pfnGetNodeAddress(sc->hwapi->pADCX, sc->original_mac_addr);
493 for (i = 0; i < 6; i++) {
494 eaddr[i] = sc->original_mac_addr[5 - i];
495 }
496 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, eaddr);
497
498 /* Display ethernet address ,... */
499 device_printf(dev, "Ethernet address %6D\n", eaddr, ":");
500
501 /* Allocate interface structures */
502 ifp = sc->ifp = if_alloc(IFT_ETHER);
503 if (ifp == NULL) {
504 device_printf(dev, "can not if_alloc()\n");
505 error = ENOSPC;
506 goto fail;
507 }
508
509 /* Probe device for MII interface to PHY */
510 DEBUGOUT(NVE_DEBUG_INIT, "nve: do mii_phy_probe\n");
511 if (mii_phy_probe(dev, &sc->miibus, nve_ifmedia_upd, nve_ifmedia_sts)) {
512 device_printf(dev, "MII without any phy!\n");
513 error = ENXIO;
514 goto fail;
515 }
516
517 /* Setup interface parameters */
518 ifp->if_softc = sc;
519 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
521 ifp->if_ioctl = nve_ioctl;
522 ifp->if_output = ether_output;
523 ifp->if_start = nve_ifstart;
524 ifp->if_watchdog = nve_watchdog;
525 ifp->if_timer = 0;
526 ifp->if_init = nve_init;
527 ifp->if_mtu = ETHERMTU;
528 ifp->if_baudrate = IF_Mbps(100);
529 ifp->if_snd.ifq_maxlen = TX_RING_SIZE - 1;
530 ifp->if_capabilities |= IFCAP_VLAN_MTU;
531
532 /* Attach to OS's managers. */
533 ether_ifattach(ifp, eaddr);
534
535 /* Activate our interrupt handler. - attach last to avoid lock */
536 error = bus_setup_intr(sc->dev, sc->irq, INTR_TYPE_NET | INTR_MPSAFE,
537 nve_intr, sc, &sc->sc_ih);
538 if (error) {
539 device_printf(sc->dev, "couldn't set up interrupt handler\n");
540 goto fail;
541 }
542 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_attach - exit\n");
543
544fail:
545 if (error)
546 nve_detach(dev);
547
548 return (error);
549}
550
551/* Detach interface for module unload */
552static int
553nve_detach(device_t dev)
554{
555 struct nve_softc *sc = device_get_softc(dev);
556 struct ifnet *ifp;
557
558 KASSERT(mtx_initialized(&sc->mtx), ("mutex not initialized"));
559
560 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - entry\n");
561
562 ifp = sc->ifp;
563
564 if (device_is_attached(dev)) {
565 NVE_LOCK(sc);
566 nve_stop(sc);
567 NVE_UNLOCK(sc);
568 callout_drain(&sc->stat_callout);
569 ether_ifdetach(ifp);
570 }
571
572 if (sc->miibus)
573 device_delete_child(dev, sc->miibus);
574 bus_generic_detach(dev);
575
576 /* Reload unreversed address back into MAC in original state */
577 if (sc->original_mac_addr)
578 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX,
579 sc->original_mac_addr);
580
581 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnClose\n");
582 /* Detach from NVIDIA hardware API */
583 if (sc->hwapi->pfnClose)
584 sc->hwapi->pfnClose(sc->hwapi->pADCX, FALSE);
585 /* Release resources */
586 if (sc->sc_ih)
587 bus_teardown_intr(sc->dev, sc->irq, sc->sc_ih);
588 if (sc->irq)
589 bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->irq);
590 if (sc->res)
591 bus_release_resource(sc->dev, SYS_RES_MEMORY, NV_RID, sc->res);
592
593 nve_free_rings(sc);
594
595 if (sc->tx_desc) {
596 bus_dmamap_unload(sc->rtag, sc->rmap);
597 bus_dmamem_free(sc->rtag, sc->rx_desc, sc->rmap);
598 bus_dmamap_destroy(sc->rtag, sc->rmap);
599 }
600 if (sc->mtag)
601 bus_dma_tag_destroy(sc->mtag);
602 if (sc->ttag)
603 bus_dma_tag_destroy(sc->ttag);
604 if (sc->rtag)
605 bus_dma_tag_destroy(sc->rtag);
606
607 if (ifp)
608 if_free(ifp);
609 mtx_destroy(&sc->mtx);
610
611 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_detach - exit\n");
612
613 return (0);
614}
615
616/* Initialise interface and start it "RUNNING" */
617static void
618nve_init(void *xsc)
619{
620 struct nve_softc *sc = xsc;
621
622 NVE_LOCK(sc);
623 nve_init_locked(sc);
624 NVE_UNLOCK(sc);
625}
626
627static void
628nve_init_locked(struct nve_softc *sc)
629{
630 struct ifnet *ifp;
631 int error;
632
633 NVE_LOCK_ASSERT(sc);
634 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - entry (%d)\n", sc->linkup);
635
636 ifp = sc->ifp;
637
638 /* Do nothing if already running */
639 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
640 return;
641
642 nve_stop(sc);
643 DEBUGOUT(NVE_DEBUG_INIT, "nve: do pfnInit\n");
644
645 nve_ifmedia_upd_locked(ifp);
646
647 /* Setup Hardware interface and allocate memory structures */
648 error = sc->hwapi->pfnInit(sc->hwapi->pADCX,
649 0, /* force speed */
650 0, /* force full duplex */
651 0, /* force mode */
652 0, /* force async mode */
653 &sc->linkup);
654
655 if (error) {
656 device_printf(sc->dev,
657 "failed to start NVIDIA Hardware interface\n");
658 return;
659 }
660 /* Set the MAC address */
661 sc->hwapi->pfnSetNodeAddress(sc->hwapi->pADCX, IF_LLADDR(sc->ifp));
662 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
663 sc->hwapi->pfnStart(sc->hwapi->pADCX);
664
665 /* Setup multicast filter */
666 nve_setmulti(sc);
667
668 /* Update interface parameters */
669 ifp->if_drv_flags |= IFF_DRV_RUNNING;
670 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
671
672 callout_reset(&sc->stat_callout, hz, nve_tick, sc);
673
674 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init - exit\n");
675
676 return;
677}
678
679/* Stop interface activity ie. not "RUNNING" */
680static void
681nve_stop(struct nve_softc *sc)
682{
683 struct ifnet *ifp;
684
685 NVE_LOCK_ASSERT(sc);
686
687 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - entry\n");
688
689 ifp = sc->ifp;
690 ifp->if_timer = 0;
691
692 /* Cancel tick timer */
693 callout_stop(&sc->stat_callout);
694
695 /* Stop hardware activity */
696 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
697 sc->hwapi->pfnStop(sc->hwapi->pADCX, 0);
698
699 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: do pfnDeinit\n");
700 /* Shutdown interface and deallocate memory buffers */
701 if (sc->hwapi->pfnDeinit)
702 sc->hwapi->pfnDeinit(sc->hwapi->pADCX, 0);
703
704 sc->linkup = 0;
705 sc->cur_rx = 0;
706 sc->pending_rxs = 0;
707 sc->pending_txs = 0;
708
709 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
710
711 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_stop - exit\n");
712
713 return;
714}
715
716/* Shutdown interface for unload/reboot */
717static void
718nve_shutdown(device_t dev)
719{
720 struct nve_softc *sc;
721
722 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_shutdown\n");
723
724 sc = device_get_softc(dev);
725
726 /* Stop hardware activity */
727 NVE_LOCK(sc);
728 nve_stop(sc);
729 NVE_UNLOCK(sc);
730}
731
732/* Allocate TX ring buffers */
733static int
734nve_init_rings(struct nve_softc *sc)
735{
736 int error, i;
737
738 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - entry\n");
739
740 sc->cur_rx = sc->cur_tx = sc->pending_rxs = sc->pending_txs = 0;
741 /* Initialise RX ring */
742 for (i = 0; i < RX_RING_SIZE; i++) {
743 struct nve_rx_desc *desc = sc->rx_desc + i;
744 struct nve_map_buffer *buf = &desc->buf;
745
746 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
747 if (buf->mbuf == NULL) {
748 device_printf(sc->dev, "couldn't allocate mbuf\n");
749 nve_free_rings(sc);
750 return (ENOBUFS);
751 }
752 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
753 m_adj(buf->mbuf, ETHER_ALIGN);
754
755 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
756 if (error) {
757 device_printf(sc->dev, "couldn't create dma map\n");
758 nve_free_rings(sc);
759 return (error);
760 }
761 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
762 nve_dmamap_rx_cb, &desc->paddr, 0);
763 if (error) {
764 device_printf(sc->dev, "couldn't dma map mbuf\n");
765 nve_free_rings(sc);
766 return (error);
767 }
768 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
769
770 desc->buflength = buf->mbuf->m_len;
771 desc->vaddr = mtod(buf->mbuf, caddr_t);
772 }
773 bus_dmamap_sync(sc->rtag, sc->rmap,
774 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
775
776 /* Initialize TX ring */
777 for (i = 0; i < TX_RING_SIZE; i++) {
778 struct nve_tx_desc *desc = sc->tx_desc + i;
779 struct nve_map_buffer *buf = &desc->buf;
780
781 buf->mbuf = NULL;
782
783 error = bus_dmamap_create(sc->mtag, 0, &buf->map);
784 if (error) {
785 device_printf(sc->dev, "couldn't create dma map\n");
786 nve_free_rings(sc);
787 return (error);
788 }
789 }
790 bus_dmamap_sync(sc->ttag, sc->tmap,
791 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
792
793 DEBUGOUT(NVE_DEBUG_INIT, "nve: nve_init_rings - exit\n");
794
795 return (error);
796}
797
798/* Free the TX ring buffers */
799static void
800nve_free_rings(struct nve_softc *sc)
801{
802 int i;
803
804 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - entry\n");
805
806 for (i = 0; i < RX_RING_SIZE; i++) {
807 struct nve_rx_desc *desc = sc->rx_desc + i;
808 struct nve_map_buffer *buf = &desc->buf;
809
810 if (buf->mbuf) {
811 bus_dmamap_unload(sc->mtag, buf->map);
812 bus_dmamap_destroy(sc->mtag, buf->map);
813 m_freem(buf->mbuf);
814 }
815 buf->mbuf = NULL;
816 }
817
818 for (i = 0; i < TX_RING_SIZE; i++) {
819 struct nve_tx_desc *desc = sc->tx_desc + i;
820 struct nve_map_buffer *buf = &desc->buf;
821
822 if (buf->mbuf) {
823 bus_dmamap_unload(sc->mtag, buf->map);
824 bus_dmamap_destroy(sc->mtag, buf->map);
825 m_freem(buf->mbuf);
826 }
827 buf->mbuf = NULL;
828 }
829
830 DEBUGOUT(NVE_DEBUG_DEINIT, "nve: nve_free_rings - exit\n");
831}
832
833/* Main loop for sending packets from OS to interface */
834static void
835nve_ifstart(struct ifnet *ifp)
836{
837 struct nve_softc *sc = ifp->if_softc;
838
839 NVE_LOCK(sc);
840 nve_ifstart_locked(ifp);
841 NVE_UNLOCK(sc);
842}
843
844static void
845nve_ifstart_locked(struct ifnet *ifp)
846{
847 struct nve_softc *sc = ifp->if_softc;
848 struct nve_map_buffer *buf;
849 struct mbuf *m0, *m;
850 struct nve_tx_desc *desc;
851 ADAPTER_WRITE_DATA txdata;
852 int error, i;
853
854 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - entry\n");
855
856 NVE_LOCK_ASSERT(sc);
857
858 /* If link is down/busy or queue is empty do nothing */
859 if (ifp->if_drv_flags & IFF_DRV_OACTIVE ||
860 IFQ_DRV_IS_EMPTY(&ifp->if_snd))
861 return;
862
863 /* Transmit queued packets until sent or TX ring is full */
864 while (sc->pending_txs < TX_RING_SIZE) {
865 desc = sc->tx_desc + sc->cur_tx;
866 buf = &desc->buf;
867
868 /* Get next packet to send. */
869 IF_DEQUEUE(&ifp->if_snd, m0);
870
871 /* If nothing to send, return. */
872 if (m0 == NULL)
873 return;
874
875 /*
876 * On nForce4, the chip doesn't interrupt on transmit,
877 * so try to flush transmitted packets from the queue
878 * if it's getting large (see note in nve_watchdog).
879 */
880 if (sc->pending_txs > TX_RING_SIZE/2) {
881 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
882 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
883 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
884 }
885
886 /* Map MBUF for DMA access */
887 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m0,
888 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
889
890 if (error && error != EFBIG) {
891 m_freem(m0);
892 sc->tx_errors++;
893 continue;
894 }
895 /*
896 * Packet has too many fragments - defrag into new mbuf
897 * cluster
898 */
899 if (error) {
900 m = m_defrag(m0, M_DONTWAIT);
901 if (m == NULL) {
902 m_freem(m0);
903 sc->tx_errors++;
904 continue;
905 }
906 m0 = m;
907
908 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, m,
909 nve_dmamap_tx_cb, desc, BUS_DMA_NOWAIT);
910 if (error) {
911 m_freem(m);
912 sc->tx_errors++;
913 continue;
914 }
915 }
916 /* Do sync on DMA bounce buffer */
917 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREWRITE);
918
919 buf->mbuf = m0;
920 txdata.ulNumberOfElements = desc->numfrags;
921 txdata.pvID = (PVOID)desc;
922
923 /* Put fragments into API element list */
924 txdata.ulTotalLength = buf->mbuf->m_len;
925 for (i = 0; i < desc->numfrags; i++) {
926 txdata.sElement[i].ulLength =
927 (ulong)desc->frags[i].ds_len;
928 txdata.sElement[i].pPhysical =
929 (PVOID)desc->frags[i].ds_addr;
930 }
931
932 /* Send packet to Nvidia API for transmission */
933 error = sc->hwapi->pfnWrite(sc->hwapi->pADCX, &txdata);
934
935 switch (error) {
936 case ADAPTERERR_NONE:
937 /* Packet was queued in API TX queue successfully */
938 sc->pending_txs++;
939 sc->cur_tx = (sc->cur_tx + 1) % TX_RING_SIZE;
940 break;
941
942 case ADAPTERERR_TRANSMIT_QUEUE_FULL:
943 /* The API TX queue is full - requeue the packet */
944 device_printf(sc->dev,
945 "nve_ifstart: transmit queue is full\n");
946 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
947 bus_dmamap_unload(sc->mtag, buf->map);
948 IF_PREPEND(&ifp->if_snd, buf->mbuf);
949 buf->mbuf = NULL;
950 return;
951
952 default:
953 /* The API failed to queue/send the packet so dump it */
954 device_printf(sc->dev, "nve_ifstart: transmit error\n");
955 bus_dmamap_unload(sc->mtag, buf->map);
956 m_freem(buf->mbuf);
957 buf->mbuf = NULL;
958 sc->tx_errors++;
959 return;
960 }
961 /* Set watchdog timer. */
962 ifp->if_timer = 8;
963
964 /* Copy packet to BPF tap */
965 BPF_MTAP(ifp, m0);
966 }
967 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
968
969 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_ifstart - exit\n");
970}
971
972/* Handle IOCTL events */
973static int
974nve_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
975{
976 struct nve_softc *sc = ifp->if_softc;
977 struct ifreq *ifr = (struct ifreq *) data;
978 struct mii_data *mii;
979 int error = 0;
980
981 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - entry\n");
982
983 switch (command) {
984 case SIOCSIFMTU:
985 /* Set MTU size */
986 NVE_LOCK(sc);
987 if (ifp->if_mtu == ifr->ifr_mtu) {
988 NVE_UNLOCK(sc);
989 break;
990 }
991 if (ifr->ifr_mtu + ifp->if_hdrlen <= MAX_PACKET_SIZE_1518) {
992 ifp->if_mtu = ifr->ifr_mtu;
993 nve_stop(sc);
994 nve_init_locked(sc);
995 } else
996 error = EINVAL;
997 NVE_UNLOCK(sc);
998 break;
999
1000 case SIOCSIFFLAGS:
1001 /* Setup interface flags */
1002 NVE_LOCK(sc);
1003 if (ifp->if_flags & IFF_UP) {
1004 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1005 nve_init_locked(sc);
1006 NVE_UNLOCK(sc);
1007 break;
1008 }
1009 } else {
1010 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1011 nve_stop(sc);
1012 NVE_UNLOCK(sc);
1013 break;
1014 }
1015 }
1016 /* Handle IFF_PROMISC and IFF_ALLMULTI flags. */
1017 nve_setmulti(sc);
1018 NVE_UNLOCK(sc);
1019 break;
1020
1021 case SIOCADDMULTI:
1022 case SIOCDELMULTI:
1023 /* Setup multicast filter */
1024 NVE_LOCK(sc);
1025 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1026 nve_setmulti(sc);
1027 }
1028 NVE_UNLOCK(sc);
1029 break;
1030
1031 case SIOCGIFMEDIA:
1032 case SIOCSIFMEDIA:
1033 /* Get/Set interface media parameters */
1034 mii = device_get_softc(sc->miibus);
1035 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1036 break;
1037
1038 default:
1039 /* Everything else we forward to generic ether ioctl */
1040 error = ether_ioctl(ifp, (int)command, data);
1041 break;
1042 }
1043
1044 DEBUGOUT(NVE_DEBUG_IOCTL, "nve: nve_ioctl - exit\n");
1045
1046 return (error);
1047}
1048
1049/* Interrupt service routine */
1050static void
1051nve_intr(void *arg)
1052{
1053 struct nve_softc *sc = arg;
1054 struct ifnet *ifp = sc->ifp;
1055
1056 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - entry\n");
1057
1058 NVE_LOCK(sc);
1059 if (!ifp->if_flags & IFF_UP) {
1060 nve_stop(sc);
1061 NVE_UNLOCK(sc);
1062 return;
1063 }
1064 /* Handle interrupt event */
1065 if (sc->hwapi->pfnQueryInterrupt(sc->hwapi->pADCX)) {
1066 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
1067 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1068 }
1069 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1070 nve_ifstart_locked(ifp);
1071
1072 /* If no pending packets we don't need a timeout */
1073 if (sc->pending_txs == 0)
1074 sc->ifp->if_timer = 0;
1075 NVE_UNLOCK(sc);
1076
1077 DEBUGOUT(NVE_DEBUG_INTERRUPT, "nve: nve_intr - exit\n");
1078
1079 return;
1080}
1081
1082/* Setup multicast filters */
1083static void
1084nve_setmulti(struct nve_softc *sc)
1085{
1086 struct ifnet *ifp;
1087 struct ifmultiaddr *ifma;
1088 PACKET_FILTER hwfilter;
1089 int i;
1090 u_int8_t andaddr[6], oraddr[6];
1091
1092 NVE_LOCK_ASSERT(sc);
1093
1094 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - entry\n");
1095
1096 ifp = sc->ifp;
1097
1098 /* Initialize filter */
1099 hwfilter.ulFilterFlags = 0;
1100 for (i = 0; i < 6; i++) {
1101 hwfilter.acMulticastAddress[i] = 0;
1102 hwfilter.acMulticastMask[i] = 0;
1103 }
1104
1105 if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1106 /* Accept all packets */
1107 hwfilter.ulFilterFlags |= ACCEPT_ALL_PACKETS;
1108 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1109 return;
1110 }
1111 /* Setup multicast filter */
1112 IF_ADDR_LOCK(ifp);
1113 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1114 u_char *addrp;
1115
1116 if (ifma->ifma_addr->sa_family != AF_LINK)
1117 continue;
1118
1119 addrp = LLADDR((struct sockaddr_dl *) ifma->ifma_addr);
1120 for (i = 0; i < 6; i++) {
1121 u_int8_t mcaddr = addrp[i];
1122 andaddr[i] &= mcaddr;
1123 oraddr[i] |= mcaddr;
1124 }
1125 }
1126 IF_ADDR_UNLOCK(ifp);
1127 for (i = 0; i < 6; i++) {
1128 hwfilter.acMulticastAddress[i] = andaddr[i] & oraddr[i];
1129 hwfilter.acMulticastMask[i] = andaddr[i] | (~oraddr[i]);
1130 }
1131
1132 /* Send filter to NVIDIA API */
1133 sc->hwapi->pfnSetPacketFilter(sc->hwapi->pADCX, &hwfilter);
1134
1135 DEBUGOUT(NVE_DEBUG_RUNNING, "nve: nve_setmulti - exit\n");
1136
1137 return;
1138}
1139
1140/* Change the current media/mediaopts */
1141static int
1142nve_ifmedia_upd(struct ifnet *ifp)
1143{
1144 struct nve_softc *sc = ifp->if_softc;
1145
1146 NVE_LOCK(sc);
1147 nve_ifmedia_upd_locked(ifp);
1148 NVE_UNLOCK(sc);
1149 return (0);
1150}
1151
1152static void
1153nve_ifmedia_upd_locked(struct ifnet *ifp)
1154{
1155 struct nve_softc *sc = ifp->if_softc;
1156 struct mii_data *mii;
1157
1158 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_upd\n");
1159
1160 NVE_LOCK_ASSERT(sc);
1161 mii = device_get_softc(sc->miibus);
1162
1163 if (mii->mii_instance) {
1164 struct mii_softc *miisc;
1165 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1166 miisc = LIST_NEXT(miisc, mii_list)) {
1167 mii_phy_reset(miisc);
1168 }
1169 }
1170 mii_mediachg(mii);
1171}
1172
1173/* Update current miibus PHY status of media */
1174static void
1175nve_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1176{
1177 struct nve_softc *sc;
1178 struct mii_data *mii;
1179
1180 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_ifmedia_sts\n");
1181
1182 sc = ifp->if_softc;
1183 NVE_LOCK(sc);
1184 mii = device_get_softc(sc->miibus);
1185 mii_pollstat(mii);
1186 NVE_UNLOCK(sc);
1187
1188 ifmr->ifm_active = mii->mii_media_active;
1189 ifmr->ifm_status = mii->mii_media_status;
1190
1191 return;
1192}
1193
1194/* miibus tick timer - maintain link status */
1195static void
1196nve_tick(void *xsc)
1197{
1198 struct nve_softc *sc = xsc;
1199 struct mii_data *mii;
1200 struct ifnet *ifp;
1201
1202 NVE_LOCK_ASSERT(sc);
1203
1204 ifp = sc->ifp;
1205 nve_update_stats(sc);
1206
1207 mii = device_get_softc(sc->miibus);
1208 mii_tick(mii);
1209
1210 if (mii->mii_media_status & IFM_ACTIVE &&
1211 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1212 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1213 nve_ifstart_locked(ifp);
1214 }
1215 callout_reset(&sc->stat_callout, hz, nve_tick, sc);
1216
1217 return;
1218}
1219
1220/* Update ifnet data structure with collected interface stats from API */
1221static void
1222nve_update_stats(struct nve_softc *sc)
1223{
1224 struct ifnet *ifp = sc->ifp;
1225 ADAPTER_STATS stats;
1226
1227 NVE_LOCK_ASSERT(sc);
1228
1229 if (sc->hwapi) {
1230 sc->hwapi->pfnGetStatistics(sc->hwapi->pADCX, &stats);
1231
1232 ifp->if_ipackets = stats.ulSuccessfulReceptions;
1233 ifp->if_ierrors = stats.ulMissedFrames +
1234 stats.ulFailedReceptions +
1235 stats.ulCRCErrors +
1236 stats.ulFramingErrors +
1237 stats.ulOverFlowErrors;
1238
1239 ifp->if_opackets = stats.ulSuccessfulTransmissions;
1240 ifp->if_oerrors = sc->tx_errors +
1241 stats.ulFailedTransmissions +
1242 stats.ulRetryErrors +
1243 stats.ulUnderflowErrors +
1244 stats.ulLossOfCarrierErrors +
1245 stats.ulLateCollisionErrors;
1246
1247 ifp->if_collisions = stats.ulLateCollisionErrors;
1248 }
1249
1250 return;
1251}
1252
1253/* miibus Read PHY register wrapper - calls Nvidia API entry point */
1254static int
1255nve_miibus_readreg(device_t dev, int phy, int reg)
1256{
1257 struct nve_softc *sc = device_get_softc(dev);
1258 ULONG data;
1259
1260 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - entry\n");
1261
1262 ADAPTER_ReadPhy(sc->hwapi->pADCX, phy, reg, &data);
1263
1264 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_readreg - exit\n");
1265
1266 return (data);
1267}
1268
1269/* miibus Write PHY register wrapper - calls Nvidia API entry point */
1270static void
1271nve_miibus_writereg(device_t dev, int phy, int reg, int data)
1272{
1273 struct nve_softc *sc = device_get_softc(dev);
1274
1275 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - entry\n");
1276
1277 ADAPTER_WritePhy(sc->hwapi->pADCX, phy, reg, (ulong)data);
1278
1279 DEBUGOUT(NVE_DEBUG_MII, "nve: nve_miibus_writereg - exit\n");
1280
1281 return;
1282}
1283
1284/* Watchdog timer to prevent PHY lockups */
1285static void
1286nve_watchdog(struct ifnet *ifp)
1287{
1288 struct nve_softc *sc = ifp->if_softc;
1289 int pending_txs_start;
1290
1291 NVE_LOCK(sc);
1292
1293 /*
1294 * The nvidia driver blob defers tx completion notifications.
1295 * Thus, sometimes the watchdog timer will go off when the
1296 * tx engine is fine, but the tx completions are just deferred.
1297 * Try kicking the driver blob to clear out any pending tx
1286 * completions. If that clears up all the pending tx
1298 * completions. If that clears up any of the pending tx
1299 * operations, then just return without printing the warning
1288 * message or resetting the adapter.
1300 * message or resetting the adapter, as we can then conclude
1301 * the chip hasn't actually crashed (it's still sending packets).
1302 */
1303 pending_txs_start = sc->pending_txs;
1304 sc->hwapi->pfnDisableInterrupts(sc->hwapi->pADCX);
1305 sc->hwapi->pfnHandleInterrupt(sc->hwapi->pADCX);
1306 sc->hwapi->pfnEnableInterrupts(sc->hwapi->pADCX);
1293 if (sc->pending_txs == 0) {
1307 if (sc->pending_txs < pending_txs_start) {
1308 NVE_UNLOCK(sc);
1309 return;
1310 }
1311
1312 device_printf(sc->dev, "device timeout (%d)\n", sc->pending_txs);
1313
1314 sc->tx_errors++;
1315
1316 nve_stop(sc);
1317 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1318 nve_init_locked(sc);
1319
1320 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1321 nve_ifstart_locked(ifp);
1322 NVE_UNLOCK(sc);
1323
1324 return;
1325}
1326
1327/* --- Start of NVOSAPI interface --- */
1328
1329/* Allocate DMA enabled general use memory for API */
1330static NV_SINT32
1331nve_osalloc(PNV_VOID ctx, PMEMORY_BLOCK mem)
1332{
1333 struct nve_softc *sc;
1334 bus_addr_t mem_physical;
1335
1336 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc - %d\n", mem->uiLength);
1337
1338 sc = (struct nve_softc *)ctx;
1339
1340 mem->pLogical = (PVOID)contigmalloc(mem->uiLength, M_DEVBUF,
1341 M_NOWAIT | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
1342
1343 if (!mem->pLogical) {
1344 device_printf(sc->dev, "memory allocation failed\n");
1345 return (0);
1346 }
1347 memset(mem->pLogical, 0, (ulong)mem->uiLength);
1348 mem_physical = vtophys(mem->pLogical);
1349 mem->pPhysical = (PVOID)mem_physical;
1350
1351 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osalloc 0x%x/0x%x - %d\n",
1352 (uint)mem->pLogical, (uint)mem->pPhysical, (uint)mem->uiLength);
1353
1354 return (1);
1355}
1356
1357/* Free allocated memory */
1358static NV_SINT32
1359nve_osfree(PNV_VOID ctx, PMEMORY_BLOCK mem)
1360{
1361 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfree - 0x%x - %d\n",
1362 (uint)mem->pLogical, (uint) mem->uiLength);
1363
1364 contigfree(mem->pLogical, PAGE_SIZE, M_DEVBUF);
1365 return (1);
1366}
1367
1368/* Copied directly from nvnet.c */
1369static NV_SINT32
1370nve_osallocex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
1371{
1372 MEMORY_BLOCK mem_block;
1373
1374 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocex\n");
1375
1376 mem_block_ex->pLogical = NULL;
1377 mem_block_ex->uiLengthOrig = mem_block_ex->uiLength;
1378
1379 if ((mem_block_ex->AllocFlags & ALLOC_MEMORY_ALIGNED) &&
1380 (mem_block_ex->AlignmentSize > 1)) {
1381 DEBUGOUT(NVE_DEBUG_API, " aligning on %d\n",
1382 mem_block_ex->AlignmentSize);
1383 mem_block_ex->uiLengthOrig += mem_block_ex->AlignmentSize;
1384 }
1385 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1386
1387 if (nve_osalloc(ctx, &mem_block) == 0) {
1388 return (0);
1389 }
1390 mem_block_ex->pLogicalOrig = mem_block.pLogical;
1391 mem_block_ex->pPhysicalOrigLow = (unsigned long)mem_block.pPhysical;
1392 mem_block_ex->pPhysicalOrigHigh = 0;
1393
1394 mem_block_ex->pPhysical = mem_block.pPhysical;
1395 mem_block_ex->pLogical = mem_block.pLogical;
1396
1397 if (mem_block_ex->uiLength != mem_block_ex->uiLengthOrig) {
1398 unsigned int offset;
1399 offset = mem_block_ex->pPhysicalOrigLow &
1400 (mem_block_ex->AlignmentSize - 1);
1401
1402 if (offset) {
1403 mem_block_ex->pPhysical =
1404 (PVOID)((ulong)mem_block_ex->pPhysical +
1405 mem_block_ex->AlignmentSize - offset);
1406 mem_block_ex->pLogical =
1407 (PVOID)((ulong)mem_block_ex->pLogical +
1408 mem_block_ex->AlignmentSize - offset);
1409 } /* if (offset) */
1410 } /* if (mem_block_ex->uiLength != *mem_block_ex->uiLengthOrig) */
1411 return (1);
1412}
1413
1414/* Copied directly from nvnet.c */
1415static NV_SINT32
1416nve_osfreeex(PNV_VOID ctx, PMEMORY_BLOCKEX mem_block_ex)
1417{
1418 MEMORY_BLOCK mem_block;
1419
1420 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreeex\n");
1421
1422 mem_block.pLogical = mem_block_ex->pLogicalOrig;
1423 mem_block.pPhysical = (PVOID)((ulong)mem_block_ex->pPhysicalOrigLow);
1424 mem_block.uiLength = mem_block_ex->uiLengthOrig;
1425
1426 return (nve_osfree(ctx, &mem_block));
1427}
1428
1429/* Clear memory region */
1430static NV_SINT32
1431nve_osclear(PNV_VOID ctx, PNV_VOID mem, NV_SINT32 length)
1432{
1433 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osclear\n");
1434 memset(mem, 0, length);
1435 return (1);
1436}
1437
1438/* Sleep for a tick */
1439static NV_SINT32
1440nve_osdelay(PNV_VOID ctx, NV_UINT32 usec)
1441{
1442 DELAY(usec);
1443 return (1);
1444}
1445
1446/* Allocate memory for rx buffer */
1447static NV_SINT32
1448nve_osallocrxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID *id)
1449{
1450 struct nve_softc *sc = ctx;
1451 struct nve_rx_desc *desc;
1452 struct nve_map_buffer *buf;
1453 int error;
1454
1455 if (device_is_attached(sc->dev))
1456 NVE_LOCK_ASSERT(sc);
1457
1458 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osallocrxbuf\n");
1459
1460 if (sc->pending_rxs == RX_RING_SIZE) {
1461 device_printf(sc->dev, "rx ring buffer is full\n");
1462 goto fail;
1463 }
1464 desc = sc->rx_desc + sc->cur_rx;
1465 buf = &desc->buf;
1466
1467 if (buf->mbuf == NULL) {
1468 buf->mbuf = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1469 if (buf->mbuf == NULL) {
1470 device_printf(sc->dev, "failed to allocate memory\n");
1471 goto fail;
1472 }
1473 buf->mbuf->m_len = buf->mbuf->m_pkthdr.len = MCLBYTES;
1474 m_adj(buf->mbuf, ETHER_ALIGN);
1475
1476 error = bus_dmamap_load_mbuf(sc->mtag, buf->map, buf->mbuf,
1477 nve_dmamap_rx_cb, &desc->paddr, 0);
1478 if (error) {
1479 device_printf(sc->dev, "failed to dmamap mbuf\n");
1480 m_freem(buf->mbuf);
1481 buf->mbuf = NULL;
1482 goto fail;
1483 }
1484 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_PREREAD);
1485 desc->buflength = buf->mbuf->m_len;
1486 desc->vaddr = mtod(buf->mbuf, caddr_t);
1487 }
1488 sc->pending_rxs++;
1489 sc->cur_rx = (sc->cur_rx + 1) % RX_RING_SIZE;
1490
1491 mem->pLogical = (void *)desc->vaddr;
1492 mem->pPhysical = (void *)desc->paddr;
1493 mem->uiLength = desc->buflength;
1494 *id = (void *)desc;
1495
1496 return (1);
1497
1498fail:
1499 return (0);
1500}
1501
1502/* Free the rx buffer */
1503static NV_SINT32
1504nve_osfreerxbuf(PNV_VOID ctx, PMEMORY_BLOCK mem, PNV_VOID id)
1505{
1506 struct nve_softc *sc = ctx;
1507 struct nve_rx_desc *desc;
1508 struct nve_map_buffer *buf;
1509
1510 DEBUGOUT(NVE_DEBUG_API, "nve: nve_osfreerxbuf\n");
1511
1512 desc = (struct nve_rx_desc *) id;
1513 buf = &desc->buf;
1514
1515 if (buf->mbuf) {
1516 bus_dmamap_unload(sc->mtag, buf->map);
1517 bus_dmamap_destroy(sc->mtag, buf->map);
1518 m_freem(buf->mbuf);
1519 }
1520 sc->pending_rxs--;
1521 buf->mbuf = NULL;
1522
1523 return (1);
1524}
1525
1526/* This gets called by the Nvidia API after our TX packet has been sent */
1527static NV_SINT32
1528nve_ospackettx(PNV_VOID ctx, PNV_VOID id, NV_UINT32 success)
1529{
1530 struct nve_softc *sc = ctx;
1531 struct nve_map_buffer *buf;
1532 struct nve_tx_desc *desc = (struct nve_tx_desc *) id;
1533 struct ifnet *ifp;
1534
1535 NVE_LOCK_ASSERT(sc);
1536
1537 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospackettx\n");
1538
1539 ifp = sc->ifp;
1540 buf = &desc->buf;
1541 sc->pending_txs--;
1542
1543 /* Unload and free mbuf cluster */
1544 if (buf->mbuf == NULL)
1545 goto fail;
1546
1547 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTWRITE);
1548 bus_dmamap_unload(sc->mtag, buf->map);
1549 m_freem(buf->mbuf);
1550 buf->mbuf = NULL;
1551
1552 /* Send more packets if we have them */
1553 if (sc->pending_txs < TX_RING_SIZE)
1554 sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1555
1556 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->pending_txs < TX_RING_SIZE)
1557 nve_ifstart_locked(ifp);
1558
1559fail:
1560
1561 return (1);
1562}
1563
1564/* This gets called by the Nvidia API when a new packet has been received */
1565/* XXX What is newbuf used for? XXX */
1566static NV_SINT32
1567nve_ospacketrx(PNV_VOID ctx, PNV_VOID data, NV_UINT32 success, NV_UINT8 *newbuf,
1568 NV_UINT8 priority)
1569{
1570 struct nve_softc *sc = ctx;
1571 struct ifnet *ifp;
1572 struct nve_rx_desc *desc;
1573 struct nve_map_buffer *buf;
1574 ADAPTER_READ_DATA *readdata;
1575 struct mbuf *m;
1576
1577 NVE_LOCK_ASSERT(sc);
1578
1579 DEBUGOUT(NVE_DEBUG_API, "nve: nve_ospacketrx\n");
1580
1581 ifp = sc->ifp;
1582
1583 readdata = (ADAPTER_READ_DATA *) data;
1584 desc = readdata->pvID;
1585 buf = &desc->buf;
1586 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1587
1588 if (success) {
1589 /* Sync DMA bounce buffer. */
1590 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1591
1592 /* First mbuf in packet holds the ethernet and packet headers */
1593 buf->mbuf->m_pkthdr.rcvif = ifp;
1594 buf->mbuf->m_pkthdr.len = buf->mbuf->m_len =
1595 readdata->ulTotalLength;
1596
1597 bus_dmamap_unload(sc->mtag, buf->map);
1598
1599 /* Blat the mbuf pointer, kernel will free the mbuf cluster */
1600 m = buf->mbuf;
1601 buf->mbuf = NULL;
1602
1603 /* Give mbuf to OS. */
1604 NVE_UNLOCK(sc);
1605 (*ifp->if_input)(ifp, m);
1606 NVE_LOCK(sc);
1607 if (readdata->ulFilterMatch & ADREADFL_MULTICAST_MATCH)
1608 ifp->if_imcasts++;
1609
1610 } else {
1611 bus_dmamap_sync(sc->mtag, buf->map, BUS_DMASYNC_POSTREAD);
1612 bus_dmamap_unload(sc->mtag, buf->map);
1613 m_freem(buf->mbuf);
1614 buf->mbuf = NULL;
1615 }
1616
1617 sc->cur_rx = desc - sc->rx_desc;
1618 sc->pending_rxs--;
1619
1620 return (1);
1621}
1622
1623/* This gets called by NVIDIA API when the PHY link state changes */
1624static NV_SINT32
1625nve_oslinkchg(PNV_VOID ctx, NV_SINT32 enabled)
1626{
1627
1628 DEBUGOUT(NVE_DEBUG_API, "nve: nve_oslinkchg\n");
1629
1630 return (1);
1631}
1632
1633/* Setup a watchdog timer */
1634static NV_SINT32
1635nve_osalloctimer(PNV_VOID ctx, PNV_VOID *timer)
1636{
1637 struct nve_softc *sc = (struct nve_softc *)ctx;
1638
1639 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osalloctimer\n");
1640
1641 callout_init(&sc->ostimer, CALLOUT_MPSAFE);
1642 *timer = &sc->ostimer;
1643
1644 return (1);
1645}
1646
1647/* Free the timer */
1648static NV_SINT32
1649nve_osfreetimer(PNV_VOID ctx, PNV_VOID timer)
1650{
1651
1652 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osfreetimer\n");
1653
1654 callout_drain((struct callout *)timer);
1655
1656 return (1);
1657}
1658
1659/* Setup timer parameters */
1660static NV_SINT32
1661nve_osinittimer(PNV_VOID ctx, PNV_VOID timer, PTIMER_FUNC func, PNV_VOID parameters)
1662{
1663 struct nve_softc *sc = (struct nve_softc *)ctx;
1664
1665 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osinittimer\n");
1666
1667 sc->ostimer_func = func;
1668 sc->ostimer_params = parameters;
1669
1670 return (1);
1671}
1672
1673/* Set the timer to go off */
1674static NV_SINT32
1675nve_ossettimer(PNV_VOID ctx, PNV_VOID timer, NV_UINT32 delay)
1676{
1677 struct nve_softc *sc = ctx;
1678
1679 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ossettimer\n");
1680
1681 callout_reset((struct callout *)timer, delay, sc->ostimer_func,
1682 sc->ostimer_params);
1683
1684 return (1);
1685}
1686
1687/* Cancel the timer */
1688static NV_SINT32
1689nve_oscanceltimer(PNV_VOID ctx, PNV_VOID timer)
1690{
1691
1692 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_oscanceltimer\n");
1693
1694 callout_stop((struct callout *)timer);
1695
1696 return (1);
1697}
1698
1699static NV_SINT32
1700nve_ospreprocpkt(PNV_VOID ctx, PNV_VOID readdata, PNV_VOID *id,
1701 NV_UINT8 *newbuffer, NV_UINT8 priority)
1702{
1703
1704 /* Not implemented */
1705 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n");
1706
1707 return (1);
1708}
1709
1710static PNV_VOID
1711nve_ospreprocpktnopq(PNV_VOID ctx, PNV_VOID readdata)
1712{
1713
1714 /* Not implemented */
1715 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_ospreprocpkt\n");
1716
1717 return (NULL);
1718}
1719
1720static NV_SINT32
1721nve_osindicatepkt(PNV_VOID ctx, PNV_VOID *id, NV_UINT32 pktno)
1722{
1723
1724 /* Not implemented */
1725 DEBUGOUT(NVE_DEBUG_BROKEN, "nve: nve_osindicatepkt\n");
1726
1727 return (1);
1728}
1729
1730/* Allocate mutex context (already done in nve_attach) */
1731static NV_SINT32
1732nve_oslockalloc(PNV_VOID ctx, NV_SINT32 type, PNV_VOID *pLock)
1733{
1734 struct nve_softc *sc = (struct nve_softc *)ctx;
1735
1736 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockalloc\n");
1737
1738 *pLock = (void **)sc;
1739
1740 return (1);
1741}
1742
1743/* Obtain a spin lock */
1744static NV_SINT32
1745nve_oslockacquire(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
1746{
1747
1748 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockacquire\n");
1749
1750 return (1);
1751}
1752
1753/* Release lock */
1754static NV_SINT32
1755nve_oslockrelease(PNV_VOID ctx, NV_SINT32 type, PNV_VOID lock)
1756{
1757
1758 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_oslockrelease\n");
1759
1760 return (1);
1761}
1762
1763/* I have no idea what this is for */
1764static PNV_VOID
1765nve_osreturnbufvirt(PNV_VOID ctx, PNV_VOID readdata)
1766{
1767
1768 /* Not implemented */
1769 DEBUGOUT(NVE_DEBUG_LOCK, "nve: nve_osreturnbufvirt\n");
1770 panic("nve: nve_osreturnbufvirtual not implemented\n");
1771
1772 return (NULL);
1773}
1774
1775/* --- End on NVOSAPI interface --- */