1/* $FreeBSD: head/sys/dev/mc146818/mc146818reg.h 59868 2000-05-01 19:54:26Z peter $ */
2/* $NetBSD: mc146818reg.h,v 1.2 1997/03/12 06:53:42 cgd Exp $ */
3
| |
4/*
5 * Copyright (c) 1995 Carnegie-Mellon University.
6 * All rights reserved.
7 *
8 * Permission to use, copy, modify and distribute this software and
9 * its documentation is hereby granted, provided that both the copyright
10 * notice and this permission notice appear in all copies of the
11 * software, derivative works or modified versions, and any portions
12 * thereof, and that both notices appear in supporting documentation.
13 *
14 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
15 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
16 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
17 *
18 * Carnegie Mellon requests users of this software to return to
19 *
20 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
21 * School of Computer Science
22 * Carnegie Mellon University
23 * Pittsburgh PA 15213-3890
24 *
25 * any improvements or extensions that they make and grant Carnegie the
26 * rights to redistribute these changes.
| 1/*
2 * Copyright (c) 1995 Carnegie-Mellon University.
3 * All rights reserved.
4 *
5 * Permission to use, copy, modify and distribute this software and
6 * its documentation is hereby granted, provided that both the copyright
7 * notice and this permission notice appear in all copies of the
8 * software, derivative works or modified versions, and any portions
9 * thereof, and that both notices appear in supporting documentation.
10 *
11 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
12 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
13 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
14 *
15 * Carnegie Mellon requests users of this software to return to
16 *
17 * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
18 * School of Computer Science
19 * Carnegie Mellon University
20 * Pittsburgh PA 15213-3890
21 *
22 * any improvements or extensions that they make and grant Carnegie the
23 * rights to redistribute these changes.
|
| 24 *
25 * from: NetBSD: mc146818reg.h,v 1.5 2003/11/02 11:07:45 wiz Exp
26 *
27 * $FreeBSD: head/sys/dev/mc146818/mc146818reg.h 137821 2004-11-17 16:37:25Z marius $
|
27 */
28
29/*
30 * Definitions for the Motorola MC146818A Real Time Clock.
| 28 */
29
30/*
31 * Definitions for the Motorola MC146818A Real Time Clock.
|
31 * They also apply for the (compatible) Dallas Semicontuctor DS1287A RTC.
| 32 * They also apply for the (compatible) Dallas Semiconductor DS1287A RTC.
|
32 *
33 * Though there are undoubtedly other (better) sources, this material was
34 * culled from the DEC "KN121 System Module Programmer's Reference
35 * Information."
36 *
37 * The MC146818A has 16 registers. The first 10 contain time-of-year
38 * and alarm data. The rest contain various control and status bits.
39 *
40 * To read or write the registers, one writes the register number to
41 * the RTC's control port, then either reads from or writes the new
42 * data to the RTC's data port. Since the locations of these ports
43 * and the method used to access them can be machine-dependent, the
44 * low-level details of reading and writing the RTC's registers are
45 * handled by machine-specific functions.
46 *
47 * The time-of-year and alarm data can be expressed in either binary
48 * or BCD, and they are selected by a bit in register B.
49 *
50 * The "hour" time-of-year and alarm fields can either be expressed in
51 * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the
52 * hour fields can have the values: 1-12 and 81-92 (the latter being
53 * PM). If the 24-hour format is chosen, they can have the values
54 * 0-24. The hour format is selectable by a bit in register B.
55 * (XXX IS AM/PM MODE DESCRIPTION CORRECT?)
56 *
57 * It is assumed the if systems are going to use BCD (rather than
58 * binary) mode, or AM/PM hour format, they'll do the appropriate
59 * conversions in machine-dependent code. Also, if the clock is
60 * switched between BCD and binary mode, or between AM/PM mode and
61 * 24-hour mode, the time-of-day and alarm registers are NOT
62 * automatically reset; they must be reprogrammed with correct values.
63 */
64
65/*
66 * The registers, and the bits within each register.
67 */
68
69#define MC_SEC 0x0 /* Time of year: seconds (0-59) */
70#define MC_ASEC 0x1 /* Alarm: seconds */
71#define MC_MIN 0x2 /* Time of year: minutes (0-59) */
72#define MC_AMIN 0x3 /* Alarm: minutes */
73#define MC_HOUR 0x4 /* Time of year: hour (see above) */
74#define MC_AHOUR 0x5 /* Alarm: hour */
75#define MC_DOW 0x6 /* Time of year: day of week (1-7) */
76#define MC_DOM 0x7 /* Time of year: day of month (1-31) */
77#define MC_MONTH 0x8 /* Time of year: month (1-12) */
78#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */
79
80#define MC_REGA 0xa /* Control register A */
81
82#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */
83#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */
84#define MC_REGA_UIP 0x80 /* Update in progress; read only. */
85
86#define MC_REGB 0xb /* Control register B */
87
88#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */
89#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */
90#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */
91#define MC_REGB_SQWE 0x08 /* Square Wave Enable */
92#define MC_REGB_UIE 0x10 /* Update End interrupt enable */
93#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */
94#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */
95#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */
96
97#define MC_REGC 0xc /* Control register C */
98
99/* MC_REGC_UNUSED 0x0f UNUSED */
100#define MC_REGC_UF 0x10 /* Update End interrupt flag */
101#define MC_REGC_AF 0x20 /* Alarm interrupt flag */
102#define MC_REGC_PF 0x40 /* Periodic interrupt flag */
103#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */
104
105#define MC_REGD 0xd /* Control register D */
106
107/* MC_REGD_UNUSED 0x7f UNUSED */
108#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */
109
110
111#define MC_NREGS 0xe /* 14 registers; CMOS follows */
112#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */
113
114#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */
115#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */
116
117/*
118 * Periodic Interrupt Rate Select constants (Control register A)
119 */
120#define MC_RATE_NONE 0x0 /* No periodic interrupt */
121#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */
122#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */
123#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */
124#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */
125#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */
126#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */
127#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */
128#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */
129#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */
130#define MC_RATE_64_Hz 0xa /* 15.625 ms period */
131#define MC_RATE_32_Hz 0xb /* 31.25 ms period */
132#define MC_RATE_16_Hz 0xc /* 62.5 ms period */
133#define MC_RATE_8_Hz 0xd /* 125 ms period */
134#define MC_RATE_4_Hz 0xe /* 250 ms period */
135#define MC_RATE_2_Hz 0xf /* 500 ms period */
136
137/*
138 * Time base (divisor select) constants (Control register A)
139 */
140#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */
141#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */
142#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */
143#define MC_BASE_NONE 0x60 /* actually, both of these reset */
144#define MC_BASE_RESET 0x70
| 33 *
34 * Though there are undoubtedly other (better) sources, this material was
35 * culled from the DEC "KN121 System Module Programmer's Reference
36 * Information."
37 *
38 * The MC146818A has 16 registers. The first 10 contain time-of-year
39 * and alarm data. The rest contain various control and status bits.
40 *
41 * To read or write the registers, one writes the register number to
42 * the RTC's control port, then either reads from or writes the new
43 * data to the RTC's data port. Since the locations of these ports
44 * and the method used to access them can be machine-dependent, the
45 * low-level details of reading and writing the RTC's registers are
46 * handled by machine-specific functions.
47 *
48 * The time-of-year and alarm data can be expressed in either binary
49 * or BCD, and they are selected by a bit in register B.
50 *
51 * The "hour" time-of-year and alarm fields can either be expressed in
52 * AM/PM format, or in 24-hour format. If AM/PM format is chosen, the
53 * hour fields can have the values: 1-12 and 81-92 (the latter being
54 * PM). If the 24-hour format is chosen, they can have the values
55 * 0-24. The hour format is selectable by a bit in register B.
56 * (XXX IS AM/PM MODE DESCRIPTION CORRECT?)
57 *
58 * It is assumed the if systems are going to use BCD (rather than
59 * binary) mode, or AM/PM hour format, they'll do the appropriate
60 * conversions in machine-dependent code. Also, if the clock is
61 * switched between BCD and binary mode, or between AM/PM mode and
62 * 24-hour mode, the time-of-day and alarm registers are NOT
63 * automatically reset; they must be reprogrammed with correct values.
64 */
65
66/*
67 * The registers, and the bits within each register.
68 */
69
70#define MC_SEC 0x0 /* Time of year: seconds (0-59) */
71#define MC_ASEC 0x1 /* Alarm: seconds */
72#define MC_MIN 0x2 /* Time of year: minutes (0-59) */
73#define MC_AMIN 0x3 /* Alarm: minutes */
74#define MC_HOUR 0x4 /* Time of year: hour (see above) */
75#define MC_AHOUR 0x5 /* Alarm: hour */
76#define MC_DOW 0x6 /* Time of year: day of week (1-7) */
77#define MC_DOM 0x7 /* Time of year: day of month (1-31) */
78#define MC_MONTH 0x8 /* Time of year: month (1-12) */
79#define MC_YEAR 0x9 /* Time of year: year in century (0-99) */
80
81#define MC_REGA 0xa /* Control register A */
82
83#define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */
84#define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */
85#define MC_REGA_UIP 0x80 /* Update in progress; read only. */
86
87#define MC_REGB 0xb /* Control register B */
88
89#define MC_REGB_DSE 0x01 /* Daylight Savings Enable */
90#define MC_REGB_24HR 0x02 /* 24-hour mode (AM/PM mode when clear) */
91#define MC_REGB_BINARY 0x04 /* Binary mode (BCD mode when clear) */
92#define MC_REGB_SQWE 0x08 /* Square Wave Enable */
93#define MC_REGB_UIE 0x10 /* Update End interrupt enable */
94#define MC_REGB_AIE 0x20 /* Alarm interrupt enable */
95#define MC_REGB_PIE 0x40 /* Periodic interrupt enable */
96#define MC_REGB_SET 0x80 /* Allow time to be set; stops updates */
97
98#define MC_REGC 0xc /* Control register C */
99
100/* MC_REGC_UNUSED 0x0f UNUSED */
101#define MC_REGC_UF 0x10 /* Update End interrupt flag */
102#define MC_REGC_AF 0x20 /* Alarm interrupt flag */
103#define MC_REGC_PF 0x40 /* Periodic interrupt flag */
104#define MC_REGC_IRQF 0x80 /* Interrupt request pending flag */
105
106#define MC_REGD 0xd /* Control register D */
107
108/* MC_REGD_UNUSED 0x7f UNUSED */
109#define MC_REGD_VRT 0x80 /* Valid RAM and Time bit */
110
111
112#define MC_NREGS 0xe /* 14 registers; CMOS follows */
113#define MC_NTODREGS 0xa /* 10 of those regs are for TOD and alarm */
114
115#define MC_NVRAM_START 0xe /* start of NVRAM: offset 14 */
116#define MC_NVRAM_SIZE 50 /* 50 bytes of NVRAM */
117
118/*
119 * Periodic Interrupt Rate Select constants (Control register A)
120 */
121#define MC_RATE_NONE 0x0 /* No periodic interrupt */
122#define MC_RATE_1 0x1 /* 256 Hz if MC_BASE_32_KHz, else 32768 Hz */
123#define MC_RATE_2 0x2 /* 128 Hz if MC_BASE_32_KHz, else 16384 Hz */
124#define MC_RATE_8192_Hz 0x3 /* 122.070 us period */
125#define MC_RATE_4096_Hz 0x4 /* 244.141 us period */
126#define MC_RATE_2048_Hz 0x5 /* 488.281 us period */
127#define MC_RATE_1024_Hz 0x6 /* 976.562 us period */
128#define MC_RATE_512_Hz 0x7 /* 1.953125 ms period */
129#define MC_RATE_256_Hz 0x8 /* 3.90625 ms period */
130#define MC_RATE_128_Hz 0x9 /* 7.8125 ms period */
131#define MC_RATE_64_Hz 0xa /* 15.625 ms period */
132#define MC_RATE_32_Hz 0xb /* 31.25 ms period */
133#define MC_RATE_16_Hz 0xc /* 62.5 ms period */
134#define MC_RATE_8_Hz 0xd /* 125 ms period */
135#define MC_RATE_4_Hz 0xe /* 250 ms period */
136#define MC_RATE_2_Hz 0xf /* 500 ms period */
137
138/*
139 * Time base (divisor select) constants (Control register A)
140 */
141#define MC_BASE_4_MHz 0x00 /* 4MHz crystal */
142#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */
143#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */
144#define MC_BASE_NONE 0x60 /* actually, both of these reset */
145#define MC_BASE_RESET 0x70
|
145
146/*
147 * A collection of TOD/Alarm registers.
148 */
149typedef u_int mc_todregs[MC_NTODREGS];
150
151/*
152 * Get all of the TOD/Alarm registers
153 * Must be called at splhigh(), and with the RTC properly set up.
154 */
155#define MC146818_GETTOD(dev, regs) \
156 do { \
157 int i; \
158 \
159 /* update in progress; spin loop */ \
160 while (MCCLOCK_READ(dev, MC_REGA) & MC_REGA_UIP) \
161 ; \
162 \
163 /* read all of the tod/alarm regs */ \
164 for (i = 0; i < MC_NTODREGS; i++) \
165 (*regs)[i] = MCCLOCK_READ(dev, i); \
166 } while (0);
167
168/*
169 * Set all of the TOD/Alarm registers
170 * Must be called at splhigh(), and with the RTC properly set up.
171 */
172#define MC146818_PUTTOD(dev, regs) \
173 do { \
174 int i; \
175 \
176 /* stop updates while setting */ \
177 MCCLOCK_WRITE(dev, MC_REGB, \
178 MCCLOCK_READ(dev, MC_REGB) | MC_REGB_SET); \
179 \
180 /* write all of the tod/alarm regs */ \
181 for (i = 0; i < MC_NTODREGS; i++) \
182 MCCLOCK_WRITE(dev, i, (*regs)[i]); \
183 \
184 /* reenable updates */ \
185 MCCLOCK_WRITE(dev, MC_REGB, \
186 MCCLOCK_READ(dev, MC_REGB) & ~MC_REGB_SET); \
187 } while (0);
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