| lancereg.h (155093) | lancereg.h (158663) |
|---|---|
| 1/* $NetBSD: lancereg.h,v 1.12 2005/12/11 12:21:27 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and Jason R. Thorpe. --- 106 unchanged lines hidden (view full) --- 115 * 116 * 32-bit software model (ILACC) am79900reg.h 117 * 118 * Note that the vast majority of the registers described in this file 119 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are 120 * valid on the LANCE. 121 */ 122 | 1/* $NetBSD: lancereg.h,v 1.12 2005/12/11 12:21:27 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum and Jason R. Thorpe. --- 106 unchanged lines hidden (view full) --- 115 * 116 * 32-bit software model (ILACC) am79900reg.h 117 * 118 * Note that the vast majority of the registers described in this file 119 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are 120 * valid on the LANCE. 121 */ 122 |
| 123/* $FreeBSD: head/sys/dev/le/lancereg.h 155093 2006-01-31 14:48:58Z marius $ */ | 123/* $FreeBSD: head/sys/dev/le/lancereg.h 158663 2006-05-16 21:04:01Z marius $ */ |
| 124 125#ifndef _DEV_LE_LANCEREG_H_ 126#define _DEV_LE_LANCEREG_H_ 127 128#define LEBLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 129/* LEMINSIZE should be ETHER_MIN_LEN when LE_MODE_DTCR is set. */ 130#define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN) 131 --- 360 unchanged lines hidden (view full) --- 492#define LE_B19_EDO 0x0001 /* EEPROM data out */ 493 494/* bus configuration register 20 (bcr20) */ 495#define LE_B20_APERREN 0x0400 /* Advanced parity error handling */ 496#define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */ 497#define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */ 498#define LE_B20_SSTYLE 0x0007 /* Software Style */ 499#define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */ | 124 125#ifndef _DEV_LE_LANCEREG_H_ 126#define _DEV_LE_LANCEREG_H_ 127 128#define LEBLEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 129/* LEMINSIZE should be ETHER_MIN_LEN when LE_MODE_DTCR is set. */ 130#define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN) 131 --- 360 unchanged lines hidden (view full) --- 492#define LE_B19_EDO 0x0001 /* EEPROM data out */ 493 494/* bus configuration register 20 (bcr20) */ 495#define LE_B20_APERREN 0x0400 /* Advanced parity error handling */ 496#define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */ 497#define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */ 498#define LE_B20_SSTYLE 0x0007 /* Software Style */ 499#define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */ |
| 500#define LE_B20_SSTYPE_ILACC 1 /* ILACC (32-bit) */ | 500#define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */ |
| 501#define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */ 502#define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */ 503 504/* bus configuration register 25 (bcr25) */ 505#define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */ 506 507/* bus configuration register 26 (bcr26) */ 508#define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */ --- 111 unchanged lines hidden --- | 501#define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */ 502#define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */ 503 504/* bus configuration register 25 (bcr25) */ 505#define LE_B25_SRAM_SIZE 0x00ff /* SRAM size */ 506 507/* bus configuration register 26 (bcr26) */ 508#define LE_B26_SRAM_BND 0x00ff /* SRAM boundary */ --- 111 unchanged lines hidden --- |