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i40e_adminq_cmd.h (291248) i40e_adminq_cmd.h (292095)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2013-2014, Intel Corporation
3 Copyright (c) 2013-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: stable/10/sys/dev/ixl/i40e_adminq_cmd.h 291248 2015-11-24 11:09:39Z smh $*/
33/*$FreeBSD: stable/10/sys/dev/ixl/i40e_adminq_cmd.h 292095 2015-12-11 12:20:58Z smh $*/
34
35#ifndef _I40E_ADMINQ_CMD_H_
36#define _I40E_ADMINQ_CMD_H_
37
38/* This header file defines the i40e Admin Queue commands and is shared between
39 * i40e Firmware and Software.
40 *
41 * This file needs to comply with the Linux Kernel coding style.
42 */
43
44#define I40E_FW_API_VERSION_MAJOR 0x0001
34
35#ifndef _I40E_ADMINQ_CMD_H_
36#define _I40E_ADMINQ_CMD_H_
37
38/* This header file defines the i40e Admin Queue commands and is shared between
39 * i40e Firmware and Software.
40 *
41 * This file needs to comply with the Linux Kernel coding style.
42 */
43
44#define I40E_FW_API_VERSION_MAJOR 0x0001
45#define I40E_FW_API_VERSION_MINOR 0x0002
45#define I40E_FW_API_VERSION_MINOR 0x0004
46
47struct i40e_aq_desc {
48 __le16 flags;
49 __le16 opcode;
50 __le16 datalen;
51 __le16 retval;
52 __le32 cookie_high;
53 __le32 cookie_low;

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135
136 /* resource ownership */
137 i40e_aqc_opc_request_resource = 0x0008,
138 i40e_aqc_opc_release_resource = 0x0009,
139
140 i40e_aqc_opc_list_func_capabilities = 0x000A,
141 i40e_aqc_opc_list_dev_capabilities = 0x000B,
142
46
47struct i40e_aq_desc {
48 __le16 flags;
49 __le16 opcode;
50 __le16 datalen;
51 __le16 retval;
52 __le32 cookie_high;
53 __le32 cookie_low;

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135
136 /* resource ownership */
137 i40e_aqc_opc_request_resource = 0x0008,
138 i40e_aqc_opc_release_resource = 0x0009,
139
140 i40e_aqc_opc_list_func_capabilities = 0x000A,
141 i40e_aqc_opc_list_dev_capabilities = 0x000B,
142
143 i40e_aqc_opc_set_cppm_configuration = 0x0103,
144 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
145 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
146
147 /* LAA */
143 /* LAA */
148 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */
149 i40e_aqc_opc_mac_address_read = 0x0107,
150 i40e_aqc_opc_mac_address_write = 0x0108,
151
152 /* PXE */
153 i40e_aqc_opc_clear_pxe_mode = 0x0110,
154
155 /* internal switch commands */
156 i40e_aqc_opc_get_switch_config = 0x0200,

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265 i40e_aqc_opc_lldp_start = 0x0A06,
266 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
267 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
268 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
269
270 /* Tunnel commands */
271 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
272 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
144 i40e_aqc_opc_mac_address_read = 0x0107,
145 i40e_aqc_opc_mac_address_write = 0x0108,
146
147 /* PXE */
148 i40e_aqc_opc_clear_pxe_mode = 0x0110,
149
150 /* internal switch commands */
151 i40e_aqc_opc_get_switch_config = 0x0200,

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260 i40e_aqc_opc_lldp_start = 0x0A06,
261 i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07,
262 i40e_aqc_opc_lldp_set_local_mib = 0x0A08,
263 i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
264
265 /* Tunnel commands */
266 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
267 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
273 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
274
275 /* Async Events */
276 i40e_aqc_opc_event_lan_overflow = 0x1001,
277
278 /* OEM commands */
279 i40e_aqc_opc_oem_parameter_change = 0xFE00,
280 i40e_aqc_opc_oem_device_status_change = 0xFE01,
281 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
282 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
283
284 /* debug commands */
268
269 /* Async Events */
270 i40e_aqc_opc_event_lan_overflow = 0x1001,
271
272 /* OEM commands */
273 i40e_aqc_opc_oem_parameter_change = 0xFE00,
274 i40e_aqc_opc_oem_device_status_change = 0xFE01,
275 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
276 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
277
278 /* debug commands */
285 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
286 i40e_aqc_opc_debug_set_mode = 0xFF01,
287 i40e_aqc_opc_debug_read_reg = 0xFF03,
288 i40e_aqc_opc_debug_write_reg = 0xFF04,
289 i40e_aqc_opc_debug_modify_reg = 0xFF07,
290 i40e_aqc_opc_debug_dump_internals = 0xFF08,
291};
292
293/* command structures and indirect data structures */
294

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512
513/* Manage MAC Address Read Command (indirect 0x0107) */
514struct i40e_aqc_mac_address_read {
515 __le16 command_flags;
516#define I40E_AQC_LAN_ADDR_VALID 0x10
517#define I40E_AQC_SAN_ADDR_VALID 0x20
518#define I40E_AQC_PORT_ADDR_VALID 0x40
519#define I40E_AQC_WOL_ADDR_VALID 0x80
279 i40e_aqc_opc_debug_read_reg = 0xFF03,
280 i40e_aqc_opc_debug_write_reg = 0xFF04,
281 i40e_aqc_opc_debug_modify_reg = 0xFF07,
282 i40e_aqc_opc_debug_dump_internals = 0xFF08,
283};
284
285/* command structures and indirect data structures */
286

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504
505/* Manage MAC Address Read Command (indirect 0x0107) */
506struct i40e_aqc_mac_address_read {
507 __le16 command_flags;
508#define I40E_AQC_LAN_ADDR_VALID 0x10
509#define I40E_AQC_SAN_ADDR_VALID 0x20
510#define I40E_AQC_PORT_ADDR_VALID 0x40
511#define I40E_AQC_WOL_ADDR_VALID 0x80
520#define I40E_AQC_ADDR_VALID_MASK 0xf0
512#define I40E_AQC_MC_MAG_EN_VALID 0x100
513#define I40E_AQC_ADDR_VALID_MASK 0x1F0
521 u8 reserved[6];
522 __le32 addr_high;
523 __le32 addr_low;
524};
525
526I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
527
528struct i40e_aqc_mac_address_read_data {

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535I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
536
537/* Manage MAC Address Write Command (0x0108) */
538struct i40e_aqc_mac_address_write {
539 __le16 command_flags;
540#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
541#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
542#define I40E_AQC_WRITE_TYPE_PORT 0x8000
514 u8 reserved[6];
515 __le32 addr_high;
516 __le32 addr_low;
517};
518
519I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
520
521struct i40e_aqc_mac_address_read_data {

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528I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
529
530/* Manage MAC Address Write Command (0x0108) */
531struct i40e_aqc_mac_address_write {
532 __le16 command_flags;
533#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
534#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
535#define I40E_AQC_WRITE_TYPE_PORT 0x8000
543#define I40E_AQC_WRITE_TYPE_MASK 0xc000
536#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
537#define I40E_AQC_WRITE_TYPE_MASK 0xC000
538
544 __le16 mac_sah;
545 __le32 mac_sal;
546 u8 reserved[8];
547};
548
549I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
550
551/* PXE commands (0x011x) */

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1071#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1072#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1073#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1074#define I40E_AQC_SET_VSI_DEFAULT 0x08
1075#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1076 __le16 seid;
1077#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1078 __le16 vlan_tag;
539 __le16 mac_sah;
540 __le32 mac_sal;
541 u8 reserved[8];
542};
543
544I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
545
546/* PXE commands (0x011x) */

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1066#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1067#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1068#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1069#define I40E_AQC_SET_VSI_DEFAULT 0x08
1070#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1071 __le16 seid;
1072#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1073 __le16 vlan_tag;
1074#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1079#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1080 u8 reserved[8];
1081};
1082
1083I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1084
1085/* Add S/E-tag command (direct 0x0255)
1086 * Uses generic i40e_aqc_add_remove_tag_completion for completion

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2065#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2066#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2067#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2068#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2069#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2070#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2071#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2072#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
1075#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1076 u8 reserved[8];
1077};
1078
1079I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1080
1081/* Add S/E-tag command (direct 0x0255)
1082 * Uses generic i40e_aqc_add_remove_tag_completion for completion

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2061#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8
2062#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT)
2063#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0
2064#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT)
2065#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3
2066#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT)
2067#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8
2068#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT)
2069#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8
2070#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT)
2071#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xA
2072#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT)
2073#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10
2074#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT)
2073struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2074 u8 reserved1;
2075 u8 oper_num_tc;
2076 u8 oper_prio_tc[4];
2077 u8 reserved2;
2078 u8 oper_tc_bw[8];
2079 u8 oper_pfc_en;
2080 u8 reserved3;

--- 249 unchanged lines hidden --- 		2075struct i40e_aqc_get_cee_dcb_cfg_v1_resp {
2076 u8 reserved1;
2077 u8 oper_num_tc;
2078 u8 oper_prio_tc[4];
2079 u8 reserved2;
2080 u8 oper_tc_bw[8];
2081 u8 oper_pfc_en;
2082 u8 reserved3;

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