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ixgbe_type.h (230775) ixgbe_type.h (238149)
1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 230775 2012-01-30 16:42:02Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_type.h 238149 2012-07-05 20:51:44Z jfv $*/
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40
41/* Vendor ID */

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61#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
62#define IXGBE_DEV_ID_82599_CX4 0x10F9
63#define IXGBE_DEV_ID_82599_SFP 0x10FB
64#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
65#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
66#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
67#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
68#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
34
35#ifndef _IXGBE_TYPE_H_
36#define _IXGBE_TYPE_H_
37
38#include "ixgbe_osdep.h"
39
40
41/* Vendor ID */

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61#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
62#define IXGBE_DEV_ID_82599_CX4 0x10F9
63#define IXGBE_DEV_ID_82599_SFP 0x10FB
64#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
65#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
66#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A
67#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
68#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
69#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
69#define IXGBE_DEV_ID_82599EN_SFP 0x1557
70#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
71#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
72#define IXGBE_DEV_ID_82599_VF 0x10ED
73#define IXGBE_DEV_ID_X540_VF 0x1515
74#define IXGBE_DEV_ID_X540T 0x1528
70#define IXGBE_DEV_ID_82599EN_SFP 0x1557
71#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
72#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
73#define IXGBE_DEV_ID_82599_VF 0x10ED
74#define IXGBE_DEV_ID_X540_VF 0x1515
75#define IXGBE_DEV_ID_X540T 0x1528
76#define IXGBE_DEV_ID_X540T1 0x1560
75
76/* General Registers */
77#define IXGBE_CTRL 0x00000
78#define IXGBE_STATUS 0x00008
79#define IXGBE_CTRL_EXT 0x00018
80#define IXGBE_ESDP 0x00020
81#define IXGBE_EODSDP 0x00028
82#define IXGBE_I2CCTL 0x00028

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113#define IXGBE_VPDDIAG0 0x10204
114#define IXGBE_VPDDIAG1 0x10208
115
116/* I2CCTL Bit Masks */
117#define IXGBE_I2C_CLK_IN 0x00000001
118#define IXGBE_I2C_CLK_OUT 0x00000002
119#define IXGBE_I2C_DATA_IN 0x00000004
120#define IXGBE_I2C_DATA_OUT 0x00000008
77
78/* General Registers */
79#define IXGBE_CTRL 0x00000
80#define IXGBE_STATUS 0x00008
81#define IXGBE_CTRL_EXT 0x00018
82#define IXGBE_ESDP 0x00020
83#define IXGBE_EODSDP 0x00028
84#define IXGBE_I2CCTL 0x00028

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115#define IXGBE_VPDDIAG0 0x10204
116#define IXGBE_VPDDIAG1 0x10208
117
118/* I2CCTL Bit Masks */
119#define IXGBE_I2C_CLK_IN 0x00000001
120#define IXGBE_I2C_CLK_OUT 0x00000002
121#define IXGBE_I2C_DATA_IN 0x00000004
122#define IXGBE_I2C_DATA_OUT 0x00000008
123#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
121
124
125
122/* Interrupt Registers */
123#define IXGBE_EICR 0x00800
124#define IXGBE_EICS 0x00808
125#define IXGBE_EIMS 0x00880
126#define IXGBE_EIMC 0x00888
127#define IXGBE_EIAC 0x00810
128#define IXGBE_EIAM 0x00890
129#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)

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827
828#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
829#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
830#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
831#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
832#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
833#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
834 IXGBE_GCR_EXT_VT_MODE_64)
126/* Interrupt Registers */
127#define IXGBE_EICR 0x00800
128#define IXGBE_EICS 0x00808
129#define IXGBE_EIMS 0x00880
130#define IXGBE_EIMC 0x00888
131#define IXGBE_EIAC 0x00810
132#define IXGBE_EIAM 0x00890
133#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)

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831
832#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
833#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
834#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
835#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
836#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
837#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
838 IXGBE_GCR_EXT_VT_MODE_64)
839#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003
835/* Time Sync Registers */
836#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
837#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
838#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
839#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
840#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
841#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
842#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */

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847#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
848#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
849#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
850#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
851#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
852#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
853#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
854#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
840/* Time Sync Registers */
841#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
842#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
843#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
844#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
845#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
846#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
847#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */

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852#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
853#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */
854#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */
855#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */
856#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */
857#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */
858#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */
859#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */
860#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */
861#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */
855#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
856#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
857#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
858#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
859#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
860#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
861
862/* Diagnostic Registers */

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1066
1067#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1068#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1069#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1070#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */
1071#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */
1072#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */
1073#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */
862#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */
863#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */
864#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
865#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
866#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
867#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
868
869/* Diagnostic Registers */

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1073
1074#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
1075#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
1076#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
1077#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */
1078#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */
1079#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */
1080#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */
1074#define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* Rx wr Desc Relax Order */
1075#define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* Rx Split Header RO */
1081#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
1082#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
1076
1077#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1078#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1079#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1080#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1083
1084#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
1085#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
1086#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
1087#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
1081#define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
1088#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
1089#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
1090#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
1082#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1083
1084/* MSCA Bit Masks */
1085#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */
1086#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1087#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */
1088#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */
1089#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */

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1377#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1378#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1379#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1380#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1381#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1382#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1383#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1384#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
1091#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
1092
1093/* MSCA Bit Masks */
1094#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */
1095#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1096#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */
1097#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */
1098#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */

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1386#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1387#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1388#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1389#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1390#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1391#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1392#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1393#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */
1394#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */
1385#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1386#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1387#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1388#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1389#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1390#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1391#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1392#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1393
1394/* Extended Interrupt Cause Set */
1395#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1396#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1397#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1398#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1399#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1400#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1401#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1395#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1396#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1397#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1398#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1399#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1400#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1401#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1402#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1403
1404/* Extended Interrupt Cause Set */
1405#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1406#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1407#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1408#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1409#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1410#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1411#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1412#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1402#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1403#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1404#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1405#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1406#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1407#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1408#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1409#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1410
1411/* Extended Interrupt Mask Set */
1412#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1413#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1414#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1415#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1416#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1417#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1418#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1419#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
1413#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1414#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1415#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1416#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1417#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1418#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1419#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1420#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1421
1422/* Extended Interrupt Mask Set */
1423#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1424#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1425#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1426#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1427#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1428#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1429#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1430#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */
1431#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1420#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1421#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1422#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1423#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1424#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1425#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1426#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1427#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1428
1429/* Extended Interrupt Mask Clear */
1430#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1431#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1432#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1433#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1434#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1435#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1436#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1432#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1433#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1434#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1435#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1436#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1437#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1438#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1439#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1440
1441/* Extended Interrupt Mask Clear */
1442#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1443#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1444#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1445#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1446#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1447#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1448#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1449#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */
1437#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1438#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1439#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1440#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1441#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1442#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1443#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1444#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

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1514
1515/* ETYPE Queue Filter/Select Bit Masks */
1516#define IXGBE_MAX_ETQF_FILTERS 8
1517#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
1518#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1519#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1520#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1521#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1450#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1451#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1452#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1453#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1454#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1455#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1456#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1457#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */

--- 69 unchanged lines hidden (view full) ---

1527
1528/* ETYPE Queue Filter/Select Bit Masks */
1529#define IXGBE_MAX_ETQF_FILTERS 8
1530#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
1531#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1532#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1533#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1534#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1535#define IXGBE_ETQF_POOL_SHIFT 20
1522
1523#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1524#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1525#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1526#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1527
1528/*
1529 * ETQF filter list: one static filter per filter consumer. This is

--- 38 unchanged lines hidden (view full) ---

1568/* ESDP Bit Masks */
1569#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1570#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1571#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1572#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1573#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1574#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1575#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1536
1537#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1538#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1539#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1540#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1541
1542/*
1543 * ETQF filter list: one static filter per filter consumer. This is

--- 38 unchanged lines hidden (view full) ---

1582/* ESDP Bit Masks */
1583#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1584#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1585#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1586#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1587#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1588#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1589#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1576#define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
1590#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */
1591#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */
1592#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */
1593#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */
1594#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */
1577#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1595#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1596#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */
1597#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */
1598#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */
1599#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */
1578
1600
1601
1579/* LEDCTL Bit Masks */
1580#define IXGBE_LED_IVRT_BASE 0x00000040
1581#define IXGBE_LED_BLINK_BASE 0x00000080
1582#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1583#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1584#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1585#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1586#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)

--- 185 unchanged lines hidden (view full) ---

1772#define IXGBE_PBANUM1_PTR 0x16
1773#define IXGBE_ALT_MAC_ADDR_PTR 0x37
1774#define IXGBE_FREE_SPACE_PTR 0X3E
1775
1776#define IXGBE_SAN_MAC_ADDR_PTR 0x28
1777#define IXGBE_DEVICE_CAPS 0x2C
1778#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1779#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1602/* LEDCTL Bit Masks */
1603#define IXGBE_LED_IVRT_BASE 0x00000040
1604#define IXGBE_LED_BLINK_BASE 0x00000080
1605#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1606#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1607#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1608#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1609#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)

--- 185 unchanged lines hidden (view full) ---

1795#define IXGBE_PBANUM1_PTR 0x16
1796#define IXGBE_ALT_MAC_ADDR_PTR 0x37
1797#define IXGBE_FREE_SPACE_PTR 0X3E
1798
1799#define IXGBE_SAN_MAC_ADDR_PTR 0x28
1800#define IXGBE_DEVICE_CAPS 0x2C
1801#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
1802#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1803#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
1780#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1804#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1805#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
1781
1782/* MSI-X capability fields masks */
1783#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1784
1785/* Legacy EEPROM word offsets */
1786#define IXGBE_ISCSI_BOOT_CAPS 0x0033
1787#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1788#define IXGBE_ISCSI_SETUP_PORT_1 0x0034

--- 78 unchanged lines hidden (view full) ---

1867#define IXGBE_PCI_LINK_WIDTH 0x3F0
1868#define IXGBE_PCI_LINK_WIDTH_1 0x10
1869#define IXGBE_PCI_LINK_WIDTH_2 0x20
1870#define IXGBE_PCI_LINK_WIDTH_4 0x40
1871#define IXGBE_PCI_LINK_WIDTH_8 0x80
1872#define IXGBE_PCI_LINK_SPEED 0xF
1873#define IXGBE_PCI_LINK_SPEED_2500 0x1
1874#define IXGBE_PCI_LINK_SPEED_5000 0x2
1806
1807/* MSI-X capability fields masks */
1808#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1809
1810/* Legacy EEPROM word offsets */
1811#define IXGBE_ISCSI_BOOT_CAPS 0x0033
1812#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1813#define IXGBE_ISCSI_SETUP_PORT_1 0x0034

--- 78 unchanged lines hidden (view full) ---

1892#define IXGBE_PCI_LINK_WIDTH 0x3F0
1893#define IXGBE_PCI_LINK_WIDTH_1 0x10
1894#define IXGBE_PCI_LINK_WIDTH_2 0x20
1895#define IXGBE_PCI_LINK_WIDTH_4 0x40
1896#define IXGBE_PCI_LINK_WIDTH_8 0x80
1897#define IXGBE_PCI_LINK_SPEED 0xF
1898#define IXGBE_PCI_LINK_SPEED_2500 0x1
1899#define IXGBE_PCI_LINK_SPEED_5000 0x2
1900#define IXGBE_PCI_LINK_SPEED_8000 0x3
1875#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1876#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1877#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1878
1879/* Number of 100 microseconds we wait for PCI Express master disable */
1880#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1881
1882/* Check whether address is multicast. This is little-endian specific check.*/

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1929#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1930#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */
1931#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */
1932#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */
1933#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */
1934#define IXGBE_RXDCTL_RLPML_EN 0x00008000
1935#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1936
1901#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1902#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1903#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1904
1905/* Number of 100 microseconds we wait for PCI Express master disable */
1906#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1907
1908/* Check whether address is multicast. This is little-endian specific check.*/

--- 46 unchanged lines hidden (view full) ---

1955#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1956#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */
1957#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */
1958#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */
1959#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */
1960#define IXGBE_RXDCTL_RLPML_EN 0x00008000
1961#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1962
1963#define IXGBE_TSAUXC_EN_CLK 0x00000004
1964#define IXGBE_TSAUXC_SYNCLK 0x00000008
1965#define IXGBE_TSAUXC_SDP0_INT 0x00000040
1966
1937#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1938#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
1939
1940#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1941#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1942#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
1943#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
1944#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04

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1972#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1973/* Receive Priority Flow Control Enable */
1974#define IXGBE_FCTRL_RPFCE 0x00004000
1975#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1976#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1977#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1978#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1979#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1967#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
1968#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */
1969
1970#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
1971#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
1972#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
1973#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
1974#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04

--- 27 unchanged lines hidden (view full) ---

2002#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
2003/* Receive Priority Flow Control Enable */
2004#define IXGBE_FCTRL_RPFCE 0x00004000
2005#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
2006#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
2007#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
2008#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
2009#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1980#define IXGBE_MFLCN_RPFCM 0x00000004 /* Receive Priority FC Mode */
1981#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF0 /* Rx Priority FC bitmap mask */
2010#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */
1982#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
1983
1984/* Multiple Receive Queue Control */
1985#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1986#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1987#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1988#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1989#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */

--- 518 unchanged lines hidden (view full) ---

2508#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2509#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2510#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2511#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2512#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2513#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2514#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2515#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2011#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */
2012
2013/* Multiple Receive Queue Control */
2014#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
2015#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
2016#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
2017#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
2018#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */

--- 518 unchanged lines hidden (view full) ---

2537#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2538#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2539#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2540#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2541#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2542#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2543#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2544#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2545#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000
2516
2517/* Flow Control Data Sheet defined values
2518 * Calculation and defines taken from 802.1bb Annex O
2519 */
2520
2521/* BitTimes (BT) conversion */
2546
2547/* Flow Control Data Sheet defined values
2548 * Calculation and defines taken from 802.1bb Annex O
2549 */
2550
2551/* BitTimes (BT) conversion */
2522#define IXGBE_BT2KB(BT) ((BT + 1023) / (8 * 1024))
2552#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2523#define IXGBE_B2BT(BT) (BT * 8)
2524
2525/* Calculate Delay to respond to PFC */
2526#define IXGBE_PFC_D 672
2527
2528/* Calculate Cable Delay */
2529#define IXGBE_CABLE_DC 5556 /* Delay Copper */
2530#define IXGBE_CABLE_DO 5000 /* Delay Optical */

--- 14 unchanged lines hidden (view full) ---

2545
2546/* Calculate Delay incurred from higher layer */
2547#define IXGBE_HD 6144
2548
2549/* Calculate PCI Bus delay for low thresholds */
2550#define IXGBE_PCI_DELAY 10000
2551
2552/* Calculate X540 delay value in bit times */
2553#define IXGBE_B2BT(BT) (BT * 8)
2554
2555/* Calculate Delay to respond to PFC */
2556#define IXGBE_PFC_D 672
2557
2558/* Calculate Cable Delay */
2559#define IXGBE_CABLE_DC 5556 /* Delay Copper */
2560#define IXGBE_CABLE_DO 5000 /* Delay Optical */

--- 14 unchanged lines hidden (view full) ---

2575
2576/* Calculate Delay incurred from higher layer */
2577#define IXGBE_HD 6144
2578
2579/* Calculate PCI Bus delay for low thresholds */
2580#define IXGBE_PCI_DELAY 10000
2581
2582/* Calculate X540 delay value in bit times */
2553#define IXGBE_FILL_RATE (36 / 25)
2583#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2584 ((36 * \
2585 (IXGBE_B2BT(_max_frame_link) + \
2586 IXGBE_PFC_D + \
2587 (2 * IXGBE_CABLE_DC) + \
2588 (2 * IXGBE_ID_X540) + \
2589 IXGBE_HD) / 25 + 1) + \
2590 2 * IXGBE_B2BT(_max_frame_tc))
2554
2591
2555#define IXGBE_DV_X540(LINK, TC) (IXGBE_FILL_RATE * \
2556 (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
2557 (2 * IXGBE_CABLE_DC) + \
2558 (2 * IXGBE_ID_X540) + \
2559 IXGBE_HD + IXGBE_B2BT(TC)))
2560
2561/* Calculate 82599, 82598 delay value in bit times */
2592/* Calculate 82599, 82598 delay value in bit times */
2562#define IXGBE_DV(LINK, TC) (IXGBE_FILL_RATE * \
2563 (IXGBE_B2BT(LINK) + IXGBE_PFC_D + \
2564 (2 * IXGBE_CABLE_DC) + (2 * IXGBE_ID) + \
2565 IXGBE_HD + IXGBE_B2BT(TC)))
2593#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2594 ((36 * \
2595 (IXGBE_B2BT(_max_frame_link) + \
2596 IXGBE_PFC_D + \
2597 (2 * IXGBE_CABLE_DC) + \
2598 (2 * IXGBE_ID) + \
2599 IXGBE_HD) / 25 + 1) + \
2600 2 * IXGBE_B2BT(_max_frame_tc))
2566
2567/* Calculate low threshold delay values */
2601
2602/* Calculate low threshold delay values */
2568#define IXGBE_LOW_DV_X540(TC) (2 * IXGBE_B2BT(TC) + \
2569 (IXGBE_FILL_RATE * IXGBE_PCI_DELAY))
2570#define IXGBE_LOW_DV(TC) (2 * IXGBE_LOW_DV_X540(TC))
2603#define IXGBE_LOW_DV_X540(_max_frame_tc) \
2604 (2 * IXGBE_B2BT(_max_frame_tc) + \
2605 (36 * IXGBE_PCI_DELAY / 25) + 1)
2606#define IXGBE_LOW_DV(_max_frame_tc) \
2607 (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2571
2572/* Software ATR hash keys */
2573#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2574#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2575
2576/* Software ATR input stream values and masks */
2577#define IXGBE_ATR_HASH_MASK 0x7fff
2578#define IXGBE_ATR_L4TYPE_MASK 0x3

--- 127 unchanged lines hidden (view full) ---

2706 ixgbe_sfp_type_da_cu_core0 = 3,
2707 ixgbe_sfp_type_da_cu_core1 = 4,
2708 ixgbe_sfp_type_srlr_core0 = 5,
2709 ixgbe_sfp_type_srlr_core1 = 6,
2710 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2711 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2712 ixgbe_sfp_type_1g_cu_core0 = 9,
2713 ixgbe_sfp_type_1g_cu_core1 = 10,
2608
2609/* Software ATR hash keys */
2610#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2611#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2612
2613/* Software ATR input stream values and masks */
2614#define IXGBE_ATR_HASH_MASK 0x7fff
2615#define IXGBE_ATR_L4TYPE_MASK 0x3

--- 127 unchanged lines hidden (view full) ---

2743 ixgbe_sfp_type_da_cu_core0 = 3,
2744 ixgbe_sfp_type_da_cu_core1 = 4,
2745 ixgbe_sfp_type_srlr_core0 = 5,
2746 ixgbe_sfp_type_srlr_core1 = 6,
2747 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2748 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2749 ixgbe_sfp_type_1g_cu_core0 = 9,
2750 ixgbe_sfp_type_1g_cu_core1 = 10,
2751 ixgbe_sfp_type_1g_sx_core0 = 11,
2752 ixgbe_sfp_type_1g_sx_core1 = 12,
2714 ixgbe_sfp_type_not_present = 0xFFFE,
2715 ixgbe_sfp_type_unknown = 0xFFFF
2716};
2717
2718enum ixgbe_media_type {
2719 ixgbe_media_type_unknown = 0,
2720 ixgbe_media_type_fiber,
2721 ixgbe_media_type_copper,

--- 33 unchanged lines hidden (view full) ---

2755 ixgbe_bus_speed_unknown = 0,
2756 ixgbe_bus_speed_33 = 33,
2757 ixgbe_bus_speed_66 = 66,
2758 ixgbe_bus_speed_100 = 100,
2759 ixgbe_bus_speed_120 = 120,
2760 ixgbe_bus_speed_133 = 133,
2761 ixgbe_bus_speed_2500 = 2500,
2762 ixgbe_bus_speed_5000 = 5000,
2753 ixgbe_sfp_type_not_present = 0xFFFE,
2754 ixgbe_sfp_type_unknown = 0xFFFF
2755};
2756
2757enum ixgbe_media_type {
2758 ixgbe_media_type_unknown = 0,
2759 ixgbe_media_type_fiber,
2760 ixgbe_media_type_copper,

--- 33 unchanged lines hidden (view full) ---

2794 ixgbe_bus_speed_unknown = 0,
2795 ixgbe_bus_speed_33 = 33,
2796 ixgbe_bus_speed_66 = 66,
2797 ixgbe_bus_speed_100 = 100,
2798 ixgbe_bus_speed_120 = 120,
2799 ixgbe_bus_speed_133 = 133,
2800 ixgbe_bus_speed_2500 = 2500,
2801 ixgbe_bus_speed_5000 = 5000,
2802 ixgbe_bus_speed_8000 = 8000,
2763 ixgbe_bus_speed_reserved
2764};
2765
2766/* PCI bus widths */
2767enum ixgbe_bus_width {
2768 ixgbe_bus_width_unknown = 0,
2769 ixgbe_bus_width_pcie_x1 = 1,
2770 ixgbe_bus_width_pcie_x2 = 2,

--- 20 unchanged lines hidden (view full) ---

2791
2792 u16 func;
2793 u16 lan_id;
2794};
2795
2796/* Flow control parameters */
2797struct ixgbe_fc_info {
2798 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
2803 ixgbe_bus_speed_reserved
2804};
2805
2806/* PCI bus widths */
2807enum ixgbe_bus_width {
2808 ixgbe_bus_width_unknown = 0,
2809 ixgbe_bus_width_pcie_x1 = 1,
2810 ixgbe_bus_width_pcie_x2 = 2,

--- 20 unchanged lines hidden (view full) ---

2831
2832 u16 func;
2833 u16 lan_id;
2834};
2835
2836/* Flow control parameters */
2837struct ixgbe_fc_info {
2838 u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */
2799 u32 low_water; /* Flow Control Low-water */
2839 u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */
2800 u16 pause_time; /* Flow Control Pause timer */
2801 bool send_xon; /* Flow control send XON */
2802 bool strict_ieee; /* Strict IEEE mode */
2803 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2804 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2805 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2806 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2807};

--- 142 unchanged lines hidden (view full) ---

2950 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2951
2952 /* RAR, Multicast, VLAN */
2953 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2954 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
2955 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2956 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
2957 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2840 u16 pause_time; /* Flow Control Pause timer */
2841 bool send_xon; /* Flow control send XON */
2842 bool strict_ieee; /* Strict IEEE mode */
2843 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2844 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2845 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2846 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2847};

--- 142 unchanged lines hidden (view full) ---

2990 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2991
2992 /* RAR, Multicast, VLAN */
2993 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2994 s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *);
2995 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2996 s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32);
2997 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2998 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
2958 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2959 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2960 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2961 ixgbe_mc_addr_itr);
2962 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
2963 ixgbe_mc_addr_itr, bool clear);
2964 s32 (*enable_mc)(struct ixgbe_hw *);
2965 s32 (*disable_mc)(struct ixgbe_hw *);
2966 s32 (*clear_vfta)(struct ixgbe_hw *);
2967 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2968 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
2969 s32 (*init_uta_tables)(struct ixgbe_hw *);
2970 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
2971 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
2972
2973 /* Flow Control */
2999 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3000 s32 (*init_rx_addrs)(struct ixgbe_hw *);
3001 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3002 ixgbe_mc_addr_itr);
3003 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
3004 ixgbe_mc_addr_itr, bool clear);
3005 s32 (*enable_mc)(struct ixgbe_hw *);
3006 s32 (*disable_mc)(struct ixgbe_hw *);
3007 s32 (*clear_vfta)(struct ixgbe_hw *);
3008 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
3009 s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, bool *);
3010 s32 (*init_uta_tables)(struct ixgbe_hw *);
3011 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3012 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3013
3014 /* Flow Control */
2974 s32 (*fc_enable)(struct ixgbe_hw *, s32);
3015 s32 (*fc_enable)(struct ixgbe_hw *);
2975
2976 /* Manageability interface */
2977 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
2978};
2979
2980struct ixgbe_phy_operations {
2981 s32 (*identify)(struct ixgbe_hw *);
2982 s32 (*identify_sfp)(struct ixgbe_hw *);

--- 39 unchanged lines hidden (view full) ---

3022 s32 mc_filter_type;
3023 u32 mcft_size;
3024 u32 vft_size;
3025 u32 num_rar_entries;
3026 u32 rar_highwater;
3027 u32 rx_pb_size;
3028 u32 max_tx_queues;
3029 u32 max_rx_queues;
3016
3017 /* Manageability interface */
3018 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
3019};
3020
3021struct ixgbe_phy_operations {
3022 s32 (*identify)(struct ixgbe_hw *);
3023 s32 (*identify_sfp)(struct ixgbe_hw *);

--- 39 unchanged lines hidden (view full) ---

3063 s32 mc_filter_type;
3064 u32 mcft_size;
3065 u32 vft_size;
3066 u32 num_rar_entries;
3067 u32 rar_highwater;
3068 u32 rx_pb_size;
3069 u32 max_tx_queues;
3070 u32 max_rx_queues;
3030 u32 max_msix_vectors;
3031 bool msix_vectors_from_pcie;
3032 u32 orig_autoc;
3071 u32 orig_autoc;
3033 bool arc_subsystem_valid;
3072 u8 san_mac_rar_index;
3034 u32 orig_autoc2;
3073 u32 orig_autoc2;
3074 u16 max_msix_vectors;
3075 bool arc_subsystem_valid;
3035 bool orig_link_settings_stored;
3036 bool autotry_restart;
3037 u8 flags;
3038};
3039
3040struct ixgbe_phy_info {
3041 struct ixgbe_phy_operations ops;
3042 enum ixgbe_phy_type type;

--- 54 unchanged lines hidden (view full) ---

3097 struct ixgbe_mbx_info mbx;
3098 u16 device_id;
3099 u16 vendor_id;
3100 u16 subsystem_device_id;
3101 u16 subsystem_vendor_id;
3102 u8 revision_id;
3103 bool adapter_stopped;
3104 bool force_full_reset;
3076 bool orig_link_settings_stored;
3077 bool autotry_restart;
3078 u8 flags;
3079};
3080
3081struct ixgbe_phy_info {
3082 struct ixgbe_phy_operations ops;
3083 enum ixgbe_phy_type type;

--- 54 unchanged lines hidden (view full) ---

3138 struct ixgbe_mbx_info mbx;
3139 u16 device_id;
3140 u16 vendor_id;
3141 u16 subsystem_device_id;
3142 u16 subsystem_vendor_id;
3143 u8 revision_id;
3144 bool adapter_stopped;
3145 bool force_full_reset;
3146 bool allow_unsupported_sfp;
3105};
3106
3107#define ixgbe_call_func(hw, func, params, error) \
3108 (func != NULL) ? func params : error
3109
3110
3111/* Error Codes */
3112#define IXGBE_SUCCESS 0

--- 20 unchanged lines hidden (view full) ---

3133#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
3134#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
3135#define IXGBE_ERR_FDIR_REINIT_FAILED -23
3136#define IXGBE_ERR_EEPROM_VERSION -24
3137#define IXGBE_ERR_NO_SPACE -25
3138#define IXGBE_ERR_OVERTEMP -26
3139#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3140#define IXGBE_ERR_FC_NOT_SUPPORTED -28
3147};
3148
3149#define ixgbe_call_func(hw, func, params, error) \
3150 (func != NULL) ? func params : error
3151
3152
3153/* Error Codes */
3154#define IXGBE_SUCCESS 0

--- 20 unchanged lines hidden (view full) ---

3175#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
3176#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
3177#define IXGBE_ERR_FDIR_REINIT_FAILED -23
3178#define IXGBE_ERR_EEPROM_VERSION -24
3179#define IXGBE_ERR_NO_SPACE -25
3180#define IXGBE_ERR_OVERTEMP -26
3181#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3182#define IXGBE_ERR_FC_NOT_SUPPORTED -28
3141#define IXGBE_ERR_FLOW_CONTROL -29
3142#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3143#define IXGBE_ERR_PBA_SECTION -31
3144#define IXGBE_ERR_INVALID_ARGUMENT -32
3145#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3146#define IXGBE_ERR_OUT_OF_MEM -34
3147
3148#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3149
3150
3151#endif /* _IXGBE_TYPE_H_ */
3183#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3184#define IXGBE_ERR_PBA_SECTION -31
3185#define IXGBE_ERR_INVALID_ARGUMENT -32
3186#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3187#define IXGBE_ERR_OUT_OF_MEM -34
3188
3189#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3190
3191
3192#endif /* _IXGBE_TYPE_H_ */