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ixgbe_82598.c (230775) ixgbe_82598.c (238149)
1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 230775 2012-01-30 16:42:02Z jfv $*/
33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82598.c 238149 2012-07-05 20:51:44Z jfv $*/
34
35#include "ixgbe_type.h"
36#include "ixgbe_82598.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,

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99 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
100out:
101 /* disable completion timeout resend */
102 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
103 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
104}
105
106/**
34
35#include "ixgbe_type.h"
36#include "ixgbe_82598.h"
37#include "ixgbe_api.h"
38#include "ixgbe_common.h"
39#include "ixgbe_phy.h"
40
41static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,

--- 57 unchanged lines hidden (view full) ---

99 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
100out:
101 /* disable completion timeout resend */
102 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
103 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
104}
105
106/**
107 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
108 * @hw: pointer to hardware structure
109 *
110 * Read PCIe configuration space, and get the MSI-X vector count from
111 * the capabilities table.
112 **/
113u32 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
114{
115 u32 msix_count = 18;
116
117 DEBUGFUNC("ixgbe_get_pcie_msix_count_82598");
118
119 if (hw->mac.msix_vectors_from_pcie) {
120 msix_count = IXGBE_READ_PCIE_WORD(hw,
121 IXGBE_PCIE_MSIX_82598_CAPS);
122 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
123
124 /* MSI-X count is zero-based in HW, so increment to give
125 * proper value */
126 msix_count++;
127 }
128 return msix_count;
129}
130
131/**
132 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
133 * @hw: pointer to hardware structure
134 *
135 * Initialize the function pointers and assign the MAC type for 82598.
136 * Does not touch the hardware.
137 **/
138s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
139{

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171 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
172
173 mac->mcft_size = 128;
174 mac->vft_size = 128;
175 mac->num_rar_entries = 16;
176 mac->rx_pb_size = 512;
177 mac->max_tx_queues = 32;
178 mac->max_rx_queues = 64;
107 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
108 * @hw: pointer to hardware structure
109 *
110 * Initialize the function pointers and assign the MAC type for 82598.
111 * Does not touch the hardware.
112 **/
113s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
114{

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146 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
147
148 mac->mcft_size = 128;
149 mac->vft_size = 128;
150 mac->num_rar_entries = 16;
151 mac->rx_pb_size = 512;
152 mac->max_tx_queues = 32;
153 mac->max_rx_queues = 64;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
154 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
180
181 /* SFP+ Module */
182 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
183
184 /* Link */
185 mac->ops.check_link = &ixgbe_check_mac_link_82598;
186 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
187 mac->ops.flap_tx_laser = NULL;

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275 DEBUGFUNC("ixgbe_start_hw_82598");
276
277 ret_val = ixgbe_start_hw_generic(hw);
278
279 /* Disable relaxed ordering */
280 for (i = 0; ((i < hw->mac.max_tx_queues) &&
281 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
282 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
155
156 /* SFP+ Module */
157 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
158
159 /* Link */
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;

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250 DEBUGFUNC("ixgbe_start_hw_82598");
251
252 ret_val = ixgbe_start_hw_generic(hw);
253
254 /* Disable relaxed ordering */
255 for (i = 0; ((i < hw->mac.max_tx_queues) &&
256 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
257 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
283 regval &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
258 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
284 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
285 }
286
287 for (i = 0; ((i < hw->mac.max_rx_queues) &&
288 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
289 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
259 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
260 }
261
262 for (i = 0; ((i < hw->mac.max_rx_queues) &&
263 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
264 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
290 regval &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
291 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
265 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
266 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
292 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
293 }
294
295 /* set the completion timeout for interface */
296 if (ret_val == IXGBE_SUCCESS)
297 ixgbe_set_pcie_completion_timeout(hw);
298
299 return ret_val;

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411 }
412out:
413 return media_type;
414}
415
416/**
417 * ixgbe_fc_enable_82598 - Enable flow control
418 * @hw: pointer to hardware structure
267 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
268 }
269
270 /* set the completion timeout for interface */
271 if (ret_val == IXGBE_SUCCESS)
272 ixgbe_set_pcie_completion_timeout(hw);
273
274 return ret_val;

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386 }
387out:
388 return media_type;
389}
390
391/**
392 * ixgbe_fc_enable_82598 - Enable flow control
393 * @hw: pointer to hardware structure
419 * @packetbuf_num: packet buffer number (0-7)
420 *
421 * Enable flow control according to the current settings.
422 **/
394 *
395 * Enable flow control according to the current settings.
396 **/
423s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
397s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
424{
425 s32 ret_val = IXGBE_SUCCESS;
426 u32 fctrl_reg;
427 u32 rmcs_reg;
428 u32 reg;
398{
399 s32 ret_val = IXGBE_SUCCESS;
400 u32 fctrl_reg;
401 u32 rmcs_reg;
402 u32 reg;
403 u32 fcrtl, fcrth;
429 u32 link_speed = 0;
404 u32 link_speed = 0;
405 int i;
430 bool link_up;
431
432 DEBUGFUNC("ixgbe_fc_enable_82598");
433
406 bool link_up;
407
408 DEBUGFUNC("ixgbe_fc_enable_82598");
409
410 /* Validate the water mark configuration */
411 if (!hw->fc.pause_time) {
412 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
413 goto out;
414 }
415
416 /* Low water mark of zero causes XOFF floods */
417 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
418 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
419 hw->fc.high_water[i]) {
420 if (!hw->fc.low_water[i] ||
421 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
422 DEBUGOUT("Invalid water mark configuration\n");
423 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
424 goto out;
425 }
426 }
427 }
428
434 /*
435 * On 82598 having Rx FC on causes resets while doing 1G
436 * so if it's on turn it off once we know link_speed. For
437 * more details see 82598 Specification update.
438 */
439 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
440 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
441 switch (hw->fc.requested_mode) {

--- 5 unchanged lines hidden (view full) ---

447 break;
448 default:
449 /* no change */
450 break;
451 }
452 }
453
454 /* Negotiate the fc mode to use */
429 /*
430 * On 82598 having Rx FC on causes resets while doing 1G
431 * so if it's on turn it off once we know link_speed. For
432 * more details see 82598 Specification update.
433 */
434 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
435 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
436 switch (hw->fc.requested_mode) {

--- 5 unchanged lines hidden (view full) ---

442 break;
443 default:
444 /* no change */
445 break;
446 }
447 }
448
449 /* Negotiate the fc mode to use */
455 ret_val = ixgbe_fc_autoneg(hw);
456 if (ret_val == IXGBE_ERR_FLOW_CONTROL)
457 goto out;
450 ixgbe_fc_autoneg(hw);
458
459 /* Disable any previous flow control settings */
460 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
461 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
462
463 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
464 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
465

--- 45 unchanged lines hidden (view full) ---

511 }
512
513 /* Set 802.3x based flow control settings. */
514 fctrl_reg |= IXGBE_FCTRL_DPF;
515 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
516 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
517
518 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
451
452 /* Disable any previous flow control settings */
453 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
454 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
455
456 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
457 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
458

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504 }
505
506 /* Set 802.3x based flow control settings. */
507 fctrl_reg |= IXGBE_FCTRL_DPF;
508 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
509 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
510
511 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
519 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
520 reg = hw->fc.low_water << 6;
521 if (hw->fc.send_xon)
522 reg |= IXGBE_FCRTL_XONE;
512 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
513 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
514 hw->fc.high_water[i]) {
515 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
516 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
517 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
518 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
519 } else {
520 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
521 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
522 }
523
523
524 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
525
526 reg = hw->fc.high_water[packetbuf_num] << 6;
527 reg |= IXGBE_FCRTH_FCEN;
528
529 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
530 }
531
532 /* Configure pause time (2 TCs per register) */
524 }
525
526 /* Configure pause time (2 TCs per register) */
533 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
534 if ((packetbuf_num & 1) == 0)
535 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
536 else
537 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
538 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
527 reg = hw->fc.pause_time * 0x00010001;
528 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
529 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
539
530
540 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
531 /* Configure flow control refresh threshold value */
532 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
541
542out:
543 return ret_val;
544}
545
546/**
547 * ixgbe_start_mac_link_82598 - Configures MAC link settings
548 * @hw: pointer to hardware structure

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1320 u32 i;
1321
1322 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1323
1324 /* Enable relaxed ordering */
1325 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1326 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1327 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
533
534out:
535 return ret_val;
536}
537
538/**
539 * ixgbe_start_mac_link_82598 - Configures MAC link settings
540 * @hw: pointer to hardware structure

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1312 u32 i;
1313
1314 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1315
1316 /* Enable relaxed ordering */
1317 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1318 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1319 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1328 regval |= IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1320 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1329 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1330 }
1331
1332 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1333 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1334 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1321 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1322 }
1323
1324 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1325 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1326 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1335 regval |= (IXGBE_DCA_RXCTRL_DESC_WRO_EN |
1336 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
1327 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
1328 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
1337 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1338 }
1339
1340}
1341
1342/**
1343 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1344 * @hw: pointer to hardware structure

--- 38 unchanged lines hidden --- 		1329 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1330 }
1331
1332}
1333
1334/**
1335 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1336 * @hw: pointer to hardware structure

--- 38 unchanged lines hidden ---