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ispvar.h (64087) ispvar.h (65140)
1/* $FreeBSD: head/sys/dev/isp/ispvar.h 64087 2000-08-01 06:10:21Z mjacob $ */
1/* $FreeBSD: head/sys/dev/isp/ispvar.h 65140 2000-08-27 23:38:44Z mjacob $ */
2/*
3 * Soft Definitions for for Qlogic ISP SCSI adapters.
4 *
5 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob
6 * NASA/Ames Research Center
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without

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148#define QENTRY_LEN 64
149/* Both request and result queue length must be a power of two */
150#define RQUEST_QUEUE_LEN(x) MAXISPREQUEST(x)
151#define RESULT_QUEUE_LEN(x) \
152 (((MAXISPREQUEST(x) >> 2) < 64)? 64 : MAXISPREQUEST(x) >> 2)
153#define ISP_QUEUE_ENTRY(q, idx) ((q) + ((idx) * QENTRY_LEN))
154#define ISP_QUEUE_SIZE(n) ((n) * QENTRY_LEN)
155#define ISP_NXT_QENTRY(idx, qlen) (((idx) + 1) & ((qlen)-1))
2/*
3 * Soft Definitions for for Qlogic ISP SCSI adapters.
4 *
5 * Copyright (c) 1997, 1998, 1999 by Matthew Jacob
6 * NASA/Ames Research Center
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without

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148#define QENTRY_LEN 64
149/* Both request and result queue length must be a power of two */
150#define RQUEST_QUEUE_LEN(x) MAXISPREQUEST(x)
151#define RESULT_QUEUE_LEN(x) \
152 (((MAXISPREQUEST(x) >> 2) < 64)? 64 : MAXISPREQUEST(x) >> 2)
153#define ISP_QUEUE_ENTRY(q, idx) ((q) + ((idx) * QENTRY_LEN))
154#define ISP_QUEUE_SIZE(n) ((n) * QENTRY_LEN)
155#define ISP_NXT_QENTRY(idx, qlen) (((idx) + 1) & ((qlen)-1))
156#define ISP_QAVAIL(in, out, qlen) \
156#define ISP_QFREE(in, out, qlen) \
157 ((in == out)? (qlen - 1) : ((in > out)? \
158 ((qlen - 1) - (in - out)) : (out - in - 1)))
157 ((in == out)? (qlen - 1) : ((in > out)? \
158 ((qlen - 1) - (in - out)) : (out - in - 1)))
159#define ISP_QAVAIL(isp) \
160 ISP_QFREE(isp->isp_reqidx, isp->isp_reqodx, RQUEST_QUEUE_LEN(isp))
159
160#define ISP_ADD_REQUEST(isp, iptr) \
161 MEMORYBARRIER(isp, SYNC_REQUEST, iptr, QENTRY_LEN); \
162 ISP_WRITE(isp, INMAILBOX4, iptr); \
163 isp->isp_reqidx = iptr
164
165/*
166 * SCSI Specific Host Adapter Parameters- per bus, per target

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171 isp_req_ack_active_neg : 1,
172 isp_data_line_active_neg: 1,
173 isp_cmd_dma_burst_enable: 1,
174 isp_data_dma_burst_enabl: 1,
175 isp_fifo_threshold : 3,
176 isp_ultramode : 1,
177 isp_diffmode : 1,
178 isp_lvdmode : 1,
161
162#define ISP_ADD_REQUEST(isp, iptr) \
163 MEMORYBARRIER(isp, SYNC_REQUEST, iptr, QENTRY_LEN); \
164 ISP_WRITE(isp, INMAILBOX4, iptr); \
165 isp->isp_reqidx = iptr
166
167/*
168 * SCSI Specific Host Adapter Parameters- per bus, per target

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173 isp_req_ack_active_neg : 1,
174 isp_data_line_active_neg: 1,
175 isp_cmd_dma_burst_enable: 1,
176 isp_data_dma_burst_enabl: 1,
177 isp_fifo_threshold : 3,
178 isp_ultramode : 1,
179 isp_diffmode : 1,
180 isp_lvdmode : 1,
179 : 1,
181 isp_fast_mttr : 1, /* fast sram */
180 isp_initiator_id : 4,
181 isp_async_data_setup : 4;
182 u_int16_t isp_selection_timeout;
183 u_int16_t isp_max_queue_depth;
184 u_int8_t isp_tag_aging;
185 u_int8_t isp_bus_reset_delay;
186 u_int8_t isp_retry_count;
187 u_int8_t isp_retry_delay;

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206#define DPARM_DISC 0x8000
207#define DPARM_PARITY 0x4000
208#define DPARM_WIDE 0x2000
209#define DPARM_SYNC 0x1000
210#define DPARM_TQING 0x0800
211#define DPARM_ARQ 0x0400
212#define DPARM_QFRZ 0x0200
213#define DPARM_RENEG 0x0100
182 isp_initiator_id : 4,
183 isp_async_data_setup : 4;
184 u_int16_t isp_selection_timeout;
185 u_int16_t isp_max_queue_depth;
186 u_int8_t isp_tag_aging;
187 u_int8_t isp_bus_reset_delay;
188 u_int8_t isp_retry_count;
189 u_int8_t isp_retry_delay;

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208#define DPARM_DISC 0x8000
209#define DPARM_PARITY 0x4000
210#define DPARM_WIDE 0x2000
211#define DPARM_SYNC 0x1000
212#define DPARM_TQING 0x0800
213#define DPARM_ARQ 0x0400
214#define DPARM_QFRZ 0x0200
215#define DPARM_RENEG 0x0100
214#define DPARM_NARROW 0x0080 /* Possibly only available with >= 7.55 fw */
215#define DPARM_ASYNC 0x0040 /* Possibly only available with >= 7.55 fw */
216#define DPARM_NARROW 0x0080
217#define DPARM_ASYNC 0x0040
218#define DPARM_PPR 0x0020
216#define DPARM_DEFAULT (0xFF00 & ~DPARM_QFRZ)
217#define DPARM_SAFE_DFLT (DPARM_DEFAULT & ~(DPARM_WIDE|DPARM_SYNC|DPARM_TQING))
218
219
220/* technically, not really correct, as they need to be rated based upon clock */
219#define DPARM_DEFAULT (0xFF00 & ~DPARM_QFRZ)
220#define DPARM_SAFE_DFLT (DPARM_DEFAULT & ~(DPARM_WIDE|DPARM_SYNC|DPARM_TQING))
221
222
223/* technically, not really correct, as they need to be rated based upon clock */
221#define ISP_40M_SYNCPARMS 0x080a
222#define ISP_20M_SYNCPARMS 0x080c
224#define ISP_80M_SYNCPARMS 0x0c09
225#define ISP_40M_SYNCPARMS 0x0c0a
226#define ISP_20M_SYNCPARMS 0x0c0c
227#define ISP_20M_SYNCPARMS_1040 0x080c
223#define ISP_10M_SYNCPARMS 0x0c19
224#define ISP_08M_SYNCPARMS 0x0c25
225#define ISP_05M_SYNCPARMS 0x0c32
226#define ISP_04M_SYNCPARMS 0x0c41
227
228/*
229 * Fibre Channel Specifics
230 */

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299#define TOPO_FL_PORT 1
300#define TOPO_N_PORT 2
301#define TOPO_F_PORT 3
302#define TOPO_PTP_STUB 4
303
304/*
305 * Soft Structure per host adapter
306 */
228#define ISP_10M_SYNCPARMS 0x0c19
229#define ISP_08M_SYNCPARMS 0x0c25
230#define ISP_05M_SYNCPARMS 0x0c32
231#define ISP_04M_SYNCPARMS 0x0c41
232
233/*
234 * Fibre Channel Specifics
235 */

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304#define TOPO_FL_PORT 1
305#define TOPO_N_PORT 2
306#define TOPO_F_PORT 3
307#define TOPO_PTP_STUB 4
308
309/*
310 * Soft Structure per host adapter
311 */
307struct ispsoftc {
312typedef struct ispsoftc {
308 /*
309 * Platform (OS) specific data
310 */
311 struct isposinfo isp_osinfo;
312
313 /*
314 * Pointer to bus specific functions and data
315 */

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325 u_int16_t isp_romfw_rev[3]; /* PROM F/W revision */
326 u_int16_t isp_maxcmds; /* max possible I/O cmds */
327 u_int8_t isp_type; /* HBA Chip Type */
328 u_int8_t isp_revision; /* HBA Chip H/W Revision */
329 u_int32_t isp_maxluns; /* maximum luns supported */
330
331 u_int32_t
332 isp_touched : 1, /* board ever seen? */
313 /*
314 * Platform (OS) specific data
315 */
316 struct isposinfo isp_osinfo;
317
318 /*
319 * Pointer to bus specific functions and data
320 */

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330 u_int16_t isp_romfw_rev[3]; /* PROM F/W revision */
331 u_int16_t isp_maxcmds; /* max possible I/O cmds */
332 u_int8_t isp_type; /* HBA Chip Type */
333 u_int8_t isp_revision; /* HBA Chip H/W Revision */
334 u_int32_t isp_maxluns; /* maximum luns supported */
335
336 u_int32_t
337 isp_touched : 1, /* board ever seen? */
333 isp_fast_mttr : 1, /* fast sram */
334 isp_bustype : 1, /* SBus or PCI */
335 : 1,
338 : 1,
339 isp_bustype : 1, /* SBus or PCI */
340 isp_loaded_fw : 1, /* loaded firmware */
336 isp_dblev : 12, /* debug log mask */
337 isp_clock : 8, /* input clock */
338 isp_confopts : 8; /* config options */
339
340 /*
341 * Volatile state
342 */
343

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361
362 /*
363 * request/result queue pointers and dma handles for them.
364 */
365 caddr_t isp_rquest;
366 caddr_t isp_result;
367 u_int32_t isp_rquest_dma;
368 u_int32_t isp_result_dma;
341 isp_dblev : 12, /* debug log mask */
342 isp_clock : 8, /* input clock */
343 isp_confopts : 8; /* config options */
344
345 /*
346 * Volatile state
347 */
348

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366
367 /*
368 * request/result queue pointers and dma handles for them.
369 */
370 caddr_t isp_rquest;
371 caddr_t isp_result;
372 u_int32_t isp_rquest_dma;
373 u_int32_t isp_result_dma;
369};
374} ispsoftc_t;
370
371#define SDPARAM(isp) ((sdparam *) (isp)->isp_param)
372#define FCPARAM(isp) ((fcparam *) (isp)->isp_param)
373
374/*
375 * ISP Driver Run States
376 */
377#define ISP_NILSTATE 0

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376#define SDPARAM(isp) ((sdparam *) (isp)->isp_param)
377#define FCPARAM(isp) ((fcparam *) (isp)->isp_param)
378
379/*
380 * ISP Driver Run States
381 */
382#define ISP_NILSTATE 0

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