| ispreg.h (163899) | ispreg.h (166929) |
|---|---|
| 1/* $FreeBSD: head/sys/dev/isp/ispreg.h 163899 2006-11-02 03:21:32Z mjacob $ */ | 1/* $FreeBSD: head/sys/dev/isp/ispreg.h 166929 2007-02-23 21:59:21Z mjacob $ */ |
| 2/*- 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997-2006 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without --- 394 unchanged lines hidden (view full) --- 404#define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 405#define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */ 406#define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 407#define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */ 408#define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */ 409 410/* BIU2400_HCCR definitions */ 411 | 2/*- 3 * Machine Independent (well, as best as possible) register 4 * definitions for Qlogic ISP SCSI adapters. 5 * 6 * Copyright (c) 1997-2006 by Matthew Jacob 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without --- 394 unchanged lines hidden (view full) --- 404#define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */ 405#define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */ 406#define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */ 407#define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */ 408#define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */ 409 410/* BIU2400_HCCR definitions */ 411 |
| 412#define HCCR_2400_CMD_NOP (0x0 << 28) 413#define HCCR_2400_CMD_RESET (0x1 << 28) 414#define HCCR_2400_CMD_CLEAR_RESET (0x2 << 28) 415#define HCCR_2400_CMD_PAUSE (0x3 << 28) 416#define HCCR_2400_CMD_RELEASE (0x4 << 28) 417#define HCCR_2400_CMD_SET_HOST_INT (0x5 << 28) 418#define HCCR_2400_CMD_CLEAR_HOST_INT (0x6 << 28) 419#define HCCR_2400_CMD_CLEAR_RISC_INT (0xA << 28) | 412#define HCCR_2400_CMD_NOP 0x00000000 413#define HCCR_2400_CMD_RESET 0x10000000 414#define HCCR_2400_CMD_CLEAR_RESET 0x20000000 415#define HCCR_2400_CMD_PAUSE 0x30000000 416#define HCCR_2400_CMD_RELEASE 0x40000000 417#define HCCR_2400_CMD_SET_HOST_INT 0x50000000 418#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 419#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 |
| 420 421#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 422#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 423#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 424 425 426/* 427 * Mailbox Block Register Offsets --- 751 unchanged lines hidden --- | 420 421#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 422#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 423#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 424 425 426/* 427 * Mailbox Block Register Offsets --- 751 unchanged lines hidden --- |