Deleted Added
sdiff udiff text old ( 290785 ) new ( 291500 )
full compact
ispreg.h (290785) ispreg.h (291500)
1/* $FreeBSD: stable/10/sys/dev/isp/ispreg.h 290785 2015-11-13 19:42:55Z mav $ */
1/* $FreeBSD: stable/10/sys/dev/isp/ispreg.h 291500 2015-11-30 21:30:18Z mav $ */
2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29/*
30 * Machine Independent (well, as best as possible) register
31 * definitions for Qlogic ISP SCSI adapters.
32 */
33#ifndef _ISPREG_H
34#define _ISPREG_H
35
36/*
37 * Hardware definitions for the Qlogic ISP registers.
38 */
39
40/*
41 * This defines types of access to various registers.
42 *
43 * R: Read Only
44 * W: Write Only
45 * RW: Read/Write
46 *
47 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only
48 * if RISC processor in ISP is paused.
49 */
50
51/*
52 * Offsets for various register blocks.
53 *
54 * Sad but true, different architectures have different offsets.
55 *
56 * Don't be alarmed if none of this makes sense. The original register
57 * layout set some defines in a certain pattern. Everything else has been
58 * grafted on since. For example, the ISP1080 manual will state that DMA
59 * registers start at 0x80 from the base of the register address space.
60 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
61 * to start at offset 0x60 because the DMA registers are all defined to
62 * be DMA_BLOCK+0x20 and so on. Clear?
63 */
64
65#define BIU_REGS_OFF 0x00
66
67#define PCI_MBOX_REGS_OFF 0x70
68#define PCI_MBOX_REGS2100_OFF 0x10
69#define PCI_MBOX_REGS2300_OFF 0x40
70#define PCI_MBOX_REGS2400_OFF 0x80
71#define SBUS_MBOX_REGS_OFF 0x80
72
73#define PCI_SXP_REGS_OFF 0x80
74#define SBUS_SXP_REGS_OFF 0x200
75
76#define PCI_RISC_REGS_OFF 0x80
77#define SBUS_RISC_REGS_OFF 0x400
78
79/* Bless me! Chip designers have putzed it again! */
80#define ISP1080_DMA_REGS_OFF 0x60
81#define DMA_REGS_OFF 0x00 /* same as BIU block */
82
83#define SBUS_REGSIZE 0x450
84#define PCI_REGSIZE 0x100
85
86/*
87 * NB: The *_BLOCK definitions have no specific hardware meaning.
88 * They serve simply to note to the MD layer which block of
89 * registers offsets are being accessed.
90 */
91#define _NREG_BLKS 5
92#define _BLK_REG_SHFT 13
93#define _BLK_REG_MASK (7 << _BLK_REG_SHFT)
94#define BIU_BLOCK (0 << _BLK_REG_SHFT)
95#define MBOX_BLOCK (1 << _BLK_REG_SHFT)
96#define SXP_BLOCK (2 << _BLK_REG_SHFT)
97#define RISC_BLOCK (3 << _BLK_REG_SHFT)
98#define DMA_BLOCK (4 << _BLK_REG_SHFT)
99
100/*
101 * Bus Interface Block Register Offsets
102 */
103
104#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
105#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
106#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
107#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
108#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
109#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
110#define BIU2100_CSR (BIU_BLOCK+0x6)
111#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
112#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
113#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
114#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
115/*
116 * These are specific to the 2300.
117 */
118#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */
119#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */
120#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */
121#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */
122
123#define BIU_R2HSTSLO (BIU_BLOCK+0x18)
124#define BIU_R2HSTSHI (BIU_BLOCK+0x1A)
125
126#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
127#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
128#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
129#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
130#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
131#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
132#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
133#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
134#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
135#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
136#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
137#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
138#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
139#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
140#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
141#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
142
143/* fifo command stuff- mostly for SPI */
144#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
145#define RDMA2100_CONTROL DFIFO_COMMAND
146#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
147
148/*
149 * Putzed DMA register layouts.
150 */
151#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
152#define CDMA2100_CONTROL CDMA_CONF
153#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
154#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
155#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
156#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
157#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
158#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
159#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
160#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
161
162#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
163#define TDMA2100_CONTROL DDMA_CONF
164#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
165#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
166#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
167#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
168#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
169#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
170#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
171/* these are for the 1040A cards */
172#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
173#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
174
175
176/*
177 * Bus Interface Block Register Definitions
178 */
179/* BUS CONFIGURATION REGISTER #0 */
180#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */
181/* BUS CONFIGURATION REGISTER #1 */
182
183#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */
184#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */
185
186#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */
187#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */
188#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */
189#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */
190#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */
191#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */
192#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */
193#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */
194#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */
195#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
196#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
197
198#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
199#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
200#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
201
202/* ISP2100 Bus Control/Status Register */
203
204#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */
205#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */
206#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */
207#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */
208#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */
209#define BIU2100_NVRAM_OFFSET (1 << 14)
210#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */
211#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */
212#define BIU2100_SOFT_RESET 0x01
213/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */
214
215
216/* BUS CONTROL REGISTER */
217#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */
218#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */
219#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */
220#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */
221#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */
222#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */
223
224#define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)
225
226#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000
227#define BIU2100_ICR_ENA_FPM_INT 0x0020
228#define BIU2100_ICR_ENA_FB_INT 0x0010
229#define BIU2100_ICR_ENA_RISC_INT 0x0008
230#define BIU2100_ICR_ENA_CDMA_INT 0x0004
231#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002
232#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
233#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
234
235#define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)
236
237/* BUS STATUS REGISTER */
238#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */
239#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */
240#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */
241#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */
242#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */
243
244#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
245#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
246#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
247#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
248#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
249#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
250#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
251
252#define INT_PENDING_MASK(isp) \
253 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \
254 (BIU_ISR_RISC_INT))
255
256/* BUS SEMAPHORE REGISTER */
257#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
258#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
259
260/* NVRAM SEMAPHORE REGISTER */
261#define BIU_NVRAM_CLOCK 0x0001
262#define BIU_NVRAM_SELECT 0x0002
263#define BIU_NVRAM_DATAOUT 0x0004
264#define BIU_NVRAM_DATAIN 0x0008
265#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */
266#define ISP_NVRAM_READ 6
267
268/* COMNMAND && DATA DMA CONFIGURATION REGISTER */
269#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */
270#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */
271#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */
272#define DMA_DMA_DIRECTION 0x0001 /*
273 * Set DMA direction:
274 * 0 - DMA FIFO to host
275 * 1 - Host to DMA FIFO
276 */
277
278/* COMMAND && DATA DMA CONTROL REGISTER */
279#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */
280#define DMA_CNTRL_CLEAR_CHAN 0x0008 /*
281 * Clear FIFO and DMA Channel,
282 * reset DMA registers
283 */
284#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */
285#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */
286#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */
287
288/*
289 * Variants of same for 2100
290 */
291#define DMA_CNTRL2100_CLEAR_CHAN 0x0004
292#define DMA_CNTRL2100_RESET_INT 0x0002
293
294
295
296/* DMA STATUS REGISTER */
297#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */
298#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */
299#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */
300#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */
301#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */
302#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */
303
304#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */
305#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */
306#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */
307#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */
308#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */
309#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */
310#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */
311#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */
312#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */
313#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */
314#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */
315
316/* DMA Status Register, pipeline status bits */
317#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */
318#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */
319#define DMA_SBUS_PIPE_STAGE1 0x0040 /*
320 * Pipeline stage 1 Loaded,
321 * stage 2 empty
322 */
323#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */
324#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */
325#define DMA_PCI_PIPE_STAGE1 0x0001 /*
326 * Pipeline stage 1 Loaded,
327 * stage 2 empty
328 */
329#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */
330
331/* DMA Status Register, channel status bits */
332#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */
333#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */
334#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */
335#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */
336#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */
337#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */
338#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */
339
340
341/* DMA FIFO STATUS REGISTER */
342#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */
343#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */
344#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */
345#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */
346
347/*
348 * 2400 Interface Offsets and Register Definitions
349 *
350 * The 2400 looks quite different in terms of registers from other QLogic cards.
351 * It is getting to be a genuine pain and challenge to keep the same model
352 * for all.
353 */
354#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00)
355#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04)
356#define BIU2400_CSR (BIU_BLOCK+0x08)
357#define BIU2400_ICR (BIU_BLOCK+0x0C)
358#define BIU2400_ISR (BIU_BLOCK+0x10)
359
360#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
361#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
362#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
363#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
364
365#define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
366#define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */
367
368#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
369#define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */
370
371#define BIU2400_R2HSTSLO (BIU_BLOCK+0x44)
372#define BIU2400_R2HSTSHI (BIU_BLOCK+0x46)
373
374#define BIU2400_HCCR (BIU_BLOCK+0x48)
375#define BIU2400_GPIOD (BIU_BLOCK+0x4C)
376#define BIU2400_GPIOE (BIU_BLOCK+0x50)
377#define BIU2400_HSEMA (BIU_BLOCK+0x58)
378
379/* BIU2400_FLASH_ADDR definitions */
380#define BIU2400_FLASH_DFLAG (1 << 30)
381
382/* BIU2400_CSR definitions */
383#define BIU2400_NVERR (1 << 18)
384#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */
385#define BIU2400_DMA_STOP (1 << 16)
386#define BIU2400_FUNCTION (1 << 15) /* RO */
387#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
388#define BIU2400_CSR_64BIT (1 << 2) /* RO */
389#define BIU2400_FLASH_ENABLE (1 << 1)
390#define BIU2400_SOFT_RESET (1 << 0)
391
392/* BIU2400_ICR definitions */
393#define BIU2400_ICR_ENA_RISC_INT 0x8
394#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
395
396/* BIU2400_ISR definitions */
397#define BIU2400_ISR_RISC_INT 0x8
398
399/* BIU2400_HCCR definitions */
400
401#define HCCR_2400_CMD_NOP 0x00000000
402#define HCCR_2400_CMD_RESET 0x10000000
403#define HCCR_2400_CMD_CLEAR_RESET 0x20000000
404#define HCCR_2400_CMD_PAUSE 0x30000000
405#define HCCR_2400_CMD_RELEASE 0x40000000
406#define HCCR_2400_CMD_SET_HOST_INT 0x50000000
407#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000
408#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000
409
410#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
411#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */
412#define HCCR_2400_RISC_RESET (1 << 5) /* RO */
413
414
415/*
416 * Mailbox Block Register Offsets
417 */
418
419#define INMAILBOX0 (MBOX_BLOCK+0x0)
420#define INMAILBOX1 (MBOX_BLOCK+0x2)
421#define INMAILBOX2 (MBOX_BLOCK+0x4)
422#define INMAILBOX3 (MBOX_BLOCK+0x6)
423#define INMAILBOX4 (MBOX_BLOCK+0x8)
424#define INMAILBOX5 (MBOX_BLOCK+0xA)
425#define INMAILBOX6 (MBOX_BLOCK+0xC)
426#define INMAILBOX7 (MBOX_BLOCK+0xE)
427
428#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
429#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
430#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
431#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
432#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
433#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
434#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
435#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
436
437/*
438 * Strictly speaking, it's
439 * SCSI && 2100 : 8 MBOX registers
440 * 2200: 24 MBOX registers
441 * 2300/2400: 32 MBOX registers
442 */
443#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1))
444#define ISP_NMBOX(isp) ((IS_24XX(isp) || IS_23XX(isp))? 32 : (IS_2200(isp) ? 24 : 8))
445#define ISP_NMBOX_BMASK(isp) \
446 ((IS_24XX(isp) || IS_23XX(isp))? 0xffffffff : (IS_2200(isp)? 0x00ffffff : 0xff))
447#define MAX_MAILBOX 32
448/* if timeout == 0, then default timeout is picked */
449#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */
450typedef struct {
451 uint16_t param[MAX_MAILBOX];
452 uint32_t ibits; /* bits to add for register copyin */
453 uint32_t obits; /* bits to add for register copyout */
454 uint32_t ibitm; /* bits to mask for register copyin */
455 uint32_t obitm; /* bits to mask for register copyout */
2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 */
29/*
30 * Machine Independent (well, as best as possible) register
31 * definitions for Qlogic ISP SCSI adapters.
32 */
33#ifndef _ISPREG_H
34#define _ISPREG_H
35
36/*
37 * Hardware definitions for the Qlogic ISP registers.
38 */
39
40/*
41 * This defines types of access to various registers.
42 *
43 * R: Read Only
44 * W: Write Only
45 * RW: Read/Write
46 *
47 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only
48 * if RISC processor in ISP is paused.
49 */
50
51/*
52 * Offsets for various register blocks.
53 *
54 * Sad but true, different architectures have different offsets.
55 *
56 * Don't be alarmed if none of this makes sense. The original register
57 * layout set some defines in a certain pattern. Everything else has been
58 * grafted on since. For example, the ISP1080 manual will state that DMA
59 * registers start at 0x80 from the base of the register address space.
60 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
61 * to start at offset 0x60 because the DMA registers are all defined to
62 * be DMA_BLOCK+0x20 and so on. Clear?
63 */
64
65#define BIU_REGS_OFF 0x00
66
67#define PCI_MBOX_REGS_OFF 0x70
68#define PCI_MBOX_REGS2100_OFF 0x10
69#define PCI_MBOX_REGS2300_OFF 0x40
70#define PCI_MBOX_REGS2400_OFF 0x80
71#define SBUS_MBOX_REGS_OFF 0x80
72
73#define PCI_SXP_REGS_OFF 0x80
74#define SBUS_SXP_REGS_OFF 0x200
75
76#define PCI_RISC_REGS_OFF 0x80
77#define SBUS_RISC_REGS_OFF 0x400
78
79/* Bless me! Chip designers have putzed it again! */
80#define ISP1080_DMA_REGS_OFF 0x60
81#define DMA_REGS_OFF 0x00 /* same as BIU block */
82
83#define SBUS_REGSIZE 0x450
84#define PCI_REGSIZE 0x100
85
86/*
87 * NB: The *_BLOCK definitions have no specific hardware meaning.
88 * They serve simply to note to the MD layer which block of
89 * registers offsets are being accessed.
90 */
91#define _NREG_BLKS 5
92#define _BLK_REG_SHFT 13
93#define _BLK_REG_MASK (7 << _BLK_REG_SHFT)
94#define BIU_BLOCK (0 << _BLK_REG_SHFT)
95#define MBOX_BLOCK (1 << _BLK_REG_SHFT)
96#define SXP_BLOCK (2 << _BLK_REG_SHFT)
97#define RISC_BLOCK (3 << _BLK_REG_SHFT)
98#define DMA_BLOCK (4 << _BLK_REG_SHFT)
99
100/*
101 * Bus Interface Block Register Offsets
102 */
103
104#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
105#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
106#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
107#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
108#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
109#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
110#define BIU2100_CSR (BIU_BLOCK+0x6)
111#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
112#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
113#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
114#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
115/*
116 * These are specific to the 2300.
117 */
118#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */
119#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */
120#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */
121#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */
122
123#define BIU_R2HSTSLO (BIU_BLOCK+0x18)
124#define BIU_R2HSTSHI (BIU_BLOCK+0x1A)
125
126#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
127#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
128#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
129#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
130#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
131#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
132#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
133#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
134#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
135#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
136#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
137#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
138#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
139#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
140#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
141#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
142
143/* fifo command stuff- mostly for SPI */
144#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
145#define RDMA2100_CONTROL DFIFO_COMMAND
146#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
147
148/*
149 * Putzed DMA register layouts.
150 */
151#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
152#define CDMA2100_CONTROL CDMA_CONF
153#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
154#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
155#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
156#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
157#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
158#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
159#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
160#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
161
162#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
163#define TDMA2100_CONTROL DDMA_CONF
164#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
165#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
166#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
167#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
168#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
169#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
170#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
171/* these are for the 1040A cards */
172#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
173#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
174
175
176/*
177 * Bus Interface Block Register Definitions
178 */
179/* BUS CONFIGURATION REGISTER #0 */
180#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */
181/* BUS CONFIGURATION REGISTER #1 */
182
183#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */
184#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */
185
186#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */
187#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */
188#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */
189#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */
190#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */
191#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */
192#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */
193#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */
194#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */
195#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
196#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
197
198#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
199#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
200#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
201
202/* ISP2100 Bus Control/Status Register */
203
204#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */
205#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */
206#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */
207#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */
208#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */
209#define BIU2100_NVRAM_OFFSET (1 << 14)
210#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */
211#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */
212#define BIU2100_SOFT_RESET 0x01
213/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */
214
215
216/* BUS CONTROL REGISTER */
217#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */
218#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */
219#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */
220#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */
221#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */
222#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */
223
224#define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)
225
226#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000
227#define BIU2100_ICR_ENA_FPM_INT 0x0020
228#define BIU2100_ICR_ENA_FB_INT 0x0010
229#define BIU2100_ICR_ENA_RISC_INT 0x0008
230#define BIU2100_ICR_ENA_CDMA_INT 0x0004
231#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002
232#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
233#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
234
235#define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)
236
237/* BUS STATUS REGISTER */
238#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */
239#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */
240#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */
241#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */
242#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */
243
244#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
245#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
246#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
247#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
248#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
249#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
250#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
251
252#define INT_PENDING_MASK(isp) \
253 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \
254 (BIU_ISR_RISC_INT))
255
256/* BUS SEMAPHORE REGISTER */
257#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
258#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
259
260/* NVRAM SEMAPHORE REGISTER */
261#define BIU_NVRAM_CLOCK 0x0001
262#define BIU_NVRAM_SELECT 0x0002
263#define BIU_NVRAM_DATAOUT 0x0004
264#define BIU_NVRAM_DATAIN 0x0008
265#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */
266#define ISP_NVRAM_READ 6
267
268/* COMNMAND && DATA DMA CONFIGURATION REGISTER */
269#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */
270#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */
271#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */
272#define DMA_DMA_DIRECTION 0x0001 /*
273 * Set DMA direction:
274 * 0 - DMA FIFO to host
275 * 1 - Host to DMA FIFO
276 */
277
278/* COMMAND && DATA DMA CONTROL REGISTER */
279#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */
280#define DMA_CNTRL_CLEAR_CHAN 0x0008 /*
281 * Clear FIFO and DMA Channel,
282 * reset DMA registers
283 */
284#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */
285#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */
286#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */
287
288/*
289 * Variants of same for 2100
290 */
291#define DMA_CNTRL2100_CLEAR_CHAN 0x0004
292#define DMA_CNTRL2100_RESET_INT 0x0002
293
294
295
296/* DMA STATUS REGISTER */
297#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */
298#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */
299#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */
300#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */
301#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */
302#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */
303
304#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */
305#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */
306#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */
307#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */
308#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */
309#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */
310#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */
311#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */
312#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */
313#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */
314#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */
315
316/* DMA Status Register, pipeline status bits */
317#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */
318#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */
319#define DMA_SBUS_PIPE_STAGE1 0x0040 /*
320 * Pipeline stage 1 Loaded,
321 * stage 2 empty
322 */
323#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */
324#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */
325#define DMA_PCI_PIPE_STAGE1 0x0001 /*
326 * Pipeline stage 1 Loaded,
327 * stage 2 empty
328 */
329#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */
330
331/* DMA Status Register, channel status bits */
332#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */
333#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */
334#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */
335#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */
336#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */
337#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */
338#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */
339
340
341/* DMA FIFO STATUS REGISTER */
342#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */
343#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */
344#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */
345#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */
346
347/*
348 * 2400 Interface Offsets and Register Definitions
349 *
350 * The 2400 looks quite different in terms of registers from other QLogic cards.
351 * It is getting to be a genuine pain and challenge to keep the same model
352 * for all.
353 */
354#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00)
355#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04)
356#define BIU2400_CSR (BIU_BLOCK+0x08)
357#define BIU2400_ICR (BIU_BLOCK+0x0C)
358#define BIU2400_ISR (BIU_BLOCK+0x10)
359
360#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
361#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
362#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
363#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
364
365#define BIU2400_PRI_REQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
366#define BIU2400_PRI_REQOUTP (BIU_BLOCK+0x30) /* Priority Request Q Out */
367
368#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
369#define BIU2400_ATIO_RSPOUTP (BIU_BLOCK+0x40) /* ATIO Queue Out */
370
371#define BIU2400_R2HSTSLO (BIU_BLOCK+0x44)
372#define BIU2400_R2HSTSHI (BIU_BLOCK+0x46)
373
374#define BIU2400_HCCR (BIU_BLOCK+0x48)
375#define BIU2400_GPIOD (BIU_BLOCK+0x4C)
376#define BIU2400_GPIOE (BIU_BLOCK+0x50)
377#define BIU2400_HSEMA (BIU_BLOCK+0x58)
378
379/* BIU2400_FLASH_ADDR definitions */
380#define BIU2400_FLASH_DFLAG (1 << 30)
381
382/* BIU2400_CSR definitions */
383#define BIU2400_NVERR (1 << 18)
384#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */
385#define BIU2400_DMA_STOP (1 << 16)
386#define BIU2400_FUNCTION (1 << 15) /* RO */
387#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
388#define BIU2400_CSR_64BIT (1 << 2) /* RO */
389#define BIU2400_FLASH_ENABLE (1 << 1)
390#define BIU2400_SOFT_RESET (1 << 0)
391
392/* BIU2400_ICR definitions */
393#define BIU2400_ICR_ENA_RISC_INT 0x8
394#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
395
396/* BIU2400_ISR definitions */
397#define BIU2400_ISR_RISC_INT 0x8
398
399/* BIU2400_HCCR definitions */
400
401#define HCCR_2400_CMD_NOP 0x00000000
402#define HCCR_2400_CMD_RESET 0x10000000
403#define HCCR_2400_CMD_CLEAR_RESET 0x20000000
404#define HCCR_2400_CMD_PAUSE 0x30000000
405#define HCCR_2400_CMD_RELEASE 0x40000000
406#define HCCR_2400_CMD_SET_HOST_INT 0x50000000
407#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000
408#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000
409
410#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
411#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */
412#define HCCR_2400_RISC_RESET (1 << 5) /* RO */
413
414
415/*
416 * Mailbox Block Register Offsets
417 */
418
419#define INMAILBOX0 (MBOX_BLOCK+0x0)
420#define INMAILBOX1 (MBOX_BLOCK+0x2)
421#define INMAILBOX2 (MBOX_BLOCK+0x4)
422#define INMAILBOX3 (MBOX_BLOCK+0x6)
423#define INMAILBOX4 (MBOX_BLOCK+0x8)
424#define INMAILBOX5 (MBOX_BLOCK+0xA)
425#define INMAILBOX6 (MBOX_BLOCK+0xC)
426#define INMAILBOX7 (MBOX_BLOCK+0xE)
427
428#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
429#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
430#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
431#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
432#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
433#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
434#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
435#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
436
437/*
438 * Strictly speaking, it's
439 * SCSI && 2100 : 8 MBOX registers
440 * 2200: 24 MBOX registers
441 * 2300/2400: 32 MBOX registers
442 */
443#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1))
444#define ISP_NMBOX(isp) ((IS_24XX(isp) || IS_23XX(isp))? 32 : (IS_2200(isp) ? 24 : 8))
445#define ISP_NMBOX_BMASK(isp) \
446 ((IS_24XX(isp) || IS_23XX(isp))? 0xffffffff : (IS_2200(isp)? 0x00ffffff : 0xff))
447#define MAX_MAILBOX 32
448/* if timeout == 0, then default timeout is picked */
449#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */
450typedef struct {
451 uint16_t param[MAX_MAILBOX];
452 uint32_t ibits; /* bits to add for register copyin */
453 uint32_t obits; /* bits to add for register copyout */
454 uint32_t ibitm; /* bits to mask for register copyin */
455 uint32_t obitm; /* bits to mask for register copyout */
456 uint32_t
457 lineno : 16,
458 : 12,
459 logval : 4;
456 uint32_t logval; /* Bitmask of status codes to log */
460 uint32_t timeout;
457 uint32_t timeout;
458 uint32_t lineno;
461 const char *func;
462} mbreg_t;
463#define MBSINIT(mbxp, code, loglev, timo) \
464 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \
465 (mbxp)->ibitm = ~0; \
466 (mbxp)->obitm = ~0; \
467 (mbxp)->param[0] = code; \
468 (mbxp)->lineno = __LINE__; \
469 (mbxp)->func = __func__; \
470 (mbxp)->logval = loglev; \
471 (mbxp)->timeout = timo
472
473
474/*
475 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
476 * NB: The RISC processor must be paused and the appropriate register
477 * bank selected via BIU2100_CSR bits.
478 */
479
480#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
481#define FPM_SOFT_RESET 0x0100
482
483#define FBM_CMD (BIU_BLOCK + 0xB8)
484#define FBMCMD_FIFO_RESET_ALL 0xA000
485
486
487/*
488 * SXP Block Register Offsets
489 */
490#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
491#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
492#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
493#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
494#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
495#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
496#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
497#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
498#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
499#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
500#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
501#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
502#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
503#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
504#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
505#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
506#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
507#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
508#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
509#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
510#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
511#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
512#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
513#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
514#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
515#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
516#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
517#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
518#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
519#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
520#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
521#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
522#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
523#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
524#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
525#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
526#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
527#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
528#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
529
530/* for 1080/1280/1240 only */
531#define SXP_BANK1_SELECT 0x100
532
533
534/* SXP CONF1 REGISTER */
535#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */
536#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */
537#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */
538#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */
539#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */
540
541/* SXP CONF2 REGISTER */
542#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */
543#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */
544#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */
545#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */
546#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */
547#define SXP_CONF2_SELECT 0x0001 /* Enable selection */
548
549/* SXP INTERRUPT REGISTER */
550#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */
551#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */
552#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */
553#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */
554#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */
555#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */
556#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */
557#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */
558#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */
559#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */
560
561
562/* SXP GROSS ERROR REGISTER */
563#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */
564#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */
565#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */
566#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */
567#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */
568#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */
569#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */
570
571/* SXP EXCEPTION REGISTER */
572#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */
573#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */
574#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */
575#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */
576#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */
577#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */
578#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */
579#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */
580#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */
581#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */
582
583 /* SXP OVERRIDE REGISTER */
584#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */
585#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */
586#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */
587#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */
588#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */
589#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */
590#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */
591#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */
592#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */
593#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */
594#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */
595#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */
596#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */
597
598/* SXP COMMANDS */
599#define SXP_RESET_BUS_CMD 0x300b
600
601/* SXP SCSI ID REGISTER */
602#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */
603#define SXP_SELECT_ID 0x000F /* Select id */
604
605/* SXP DEV CONFIG1 REGISTER */
606#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */
607#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */
608#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */
609
610
611/* SXP DEV CONFIG2 REGISTER */
612#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */
613#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */
614#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */
615#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */
616#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */
617
618
619/* SXP PHASE POINTER REGISTER */
620#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */
621#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */
622#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */
623#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */
624
625
626/* SXP FIFO STATUS REGISTER */
627#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */
628#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */
629#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */
630#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */
631
632
633/* SXP CONTROL PINS REGISTER */
634#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */
635#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */
636#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */
637#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */
638#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */
639#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */
640#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */
641#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */
642#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */
643#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */
644#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */
645#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */
646
647/*
648 * Set the hold time for the SCSI Bus Reset to be 250 ms
649 */
650#define SXP_SCSI_BUS_RESET_HOLD_TIME 250
651
652/* SXP DIFF PINS REGISTER */
653#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */
654#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */
655#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */
656#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */
657#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
658#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
659
660/* Ultra2 only */
661#define SXP_PINS_LVD_MODE 0x1000
662#define SXP_PINS_HVD_MODE 0x0800
663#define SXP_PINS_SE_MODE 0x0400
664#define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE)
665
666/* The above have to be put together with the DIFFM pin to make sense */
667#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE)
668#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE)
669#define ISP1080_SE_MODE (SXP_PINS_SE_MODE)
670#define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE)
671
672/*
673 * RISC and Host Command and Control Block Register Offsets
674 */
675
676#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
677#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
678#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
679#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
680#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
681#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
682#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
683#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
684#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
685#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
686#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
687#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
688#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
689#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
690#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
691#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
692#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
693#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
694#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
695#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
696#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
697#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
698#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
699#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
700#define RISC_MTR2100 RISC_BLOCK+0x30
701
702#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
703#define DUAL_BANK 8
704#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
705#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
706#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
707#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
708#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
709#define TCR RISC_BLOCK+0x46 /* W : Test Control */
710#define TMR RISC_BLOCK+0x48 /* W : Test Mode */
711
712
713/* PROCESSOR STATUS REGISTER */
714#define RISC_PSR_FORCE_TRUE 0x8000
715#define RISC_PSR_LOOP_COUNT_DONE 0x4000
716#define RISC_PSR_RISC_INT 0x2000
717#define RISC_PSR_TIMER_ROLLOVER 0x1000
718#define RISC_PSR_ALU_OVERFLOW 0x0800
719#define RISC_PSR_ALU_MSB 0x0400
720#define RISC_PSR_ALU_CARRY 0x0200
721#define RISC_PSR_ALU_ZERO 0x0100
722
723#define RISC_PSR_PCI_ULTRA 0x0080
724#define RISC_PSR_SBUS_ULTRA 0x0020
725
726#define RISC_PSR_DMA_INT 0x0010
727#define RISC_PSR_SXP_INT 0x0008
728#define RISC_PSR_HOST_INT 0x0004
729#define RISC_PSR_INT_PENDING 0x0002
730#define RISC_PSR_FORCE_FALSE 0x0001
731
732
733/* Host Command and Control */
734#define HCCR_CMD_NOP 0x0000 /* NOP */
735#define HCCR_CMD_RESET 0x1000 /* Reset RISC */
736#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
737#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
738#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
739#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /*
740 * Disable RISC pause on FPM
741 * parity error.
742 */
743#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
744#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
745#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
746#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */
747#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */
748#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */
749#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */
750#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */
751
752
753#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400
754#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200
755#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100
756#define ISP2100_HCCR_PARITY 0x0001
757
758#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */
759#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */
760#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */
761
762#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */
763#define HCCR_RESET 0x0040 /* R : reset in progress */
764#define HCCR_PAUSE 0x0020 /* R : RISC paused */
765
766#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
767
768/*
769 * Defines for Interrupts
770 */
771#define ISP_INTS_ENABLED(isp) \
772 ((IS_SCSI(isp))? \
773 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \
774 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \
775 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK)))
776
777#define ISP_ENABLE_INTS(isp) \
778 (IS_SCSI(isp) ? \
779 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \
780 (IS_24XX(isp) ? \
781 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \
782 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK))))
783
784#define ISP_DISABLE_INTS(isp) \
785 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0)
786
787/*
788 * NVRAM Definitions (PCI cards only)
789 */
790
791#define ISPBSMX(c, byte, shift, mask) \
792 (((c)[(byte)] >> (shift)) & (mask))
793/*
794 * Qlogic 1020/1040 NVRAM is an array of 128 bytes.
795 *
796 * Some portion of the front of this is for general host adapter properties
797 * This is followed by an array of per-target parameters, and is tailed off
798 * with a checksum xor byte at offset 127. For non-byte entities data is
799 * stored in Little Endian order.
800 */
801
802#define ISP_NVRAM_SIZE 128
803
804#define ISP_NVRAM_VERSION(c) (c)[4]
805#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
806#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
807#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01)
808#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f)
809#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6]
810#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7]
811#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8]
812#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f)
813#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01)
814#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01)
815#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01)
816#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01)
817#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10]
818#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01)
819#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01)
820#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01)
821#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01)
822#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01)
823#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01)
824#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01)
825#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01)
826#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8))
827#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8))
828#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01)
829#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01)
830#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01)
831#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01)
832#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01)
833#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01)
834
835#define ISP_NVRAM_TARGOFF 28
836#define ISP_NVRAM_TARGSIZE 6
837#define _IxT(tgt, tidx) \
838 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx))
839#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01)
840#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01)
841#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01)
842#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01)
843#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01)
844#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01)
845#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01)
846#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01)
847#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff)
848#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff)
849#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
850#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
851#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
852
853/*
854 * Qlogic 1080/1240 NVRAM is an array of 256 bytes.
855 *
856 * Some portion of the front of this is for general host adapter properties
857 * This is followed by an array of per-target parameters, and is tailed off
858 * with a checksum xor byte at offset 256. For non-byte entities data is
859 * stored in Little Endian order.
860 */
861
862#define ISP1080_NVRAM_SIZE 256
863
864#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c)
865
866/* Offset 5 */
867/*
868 uint8_t bios_configuration_mode :2;
869 uint8_t bios_disable :1;
870 uint8_t selectable_scsi_boot_enable :1;
871 uint8_t cd_rom_boot_enable :1;
872 uint8_t disable_loading_risc_code :1;
873 uint8_t enable_64bit_addressing :1;
874 uint8_t unused_7 :1;
875 */
876
877/* Offsets 6, 7 */
878/*
879 uint8_t boot_lun_number :5;
880 uint8_t scsi_bus_number :1;
881 uint8_t unused_6 :1;
882 uint8_t unused_7 :1;
883 uint8_t boot_target_number :4;
884 uint8_t unused_12 :1;
885 uint8_t unused_13 :1;
886 uint8_t unused_14 :1;
887 uint8_t unused_15 :1;
888 */
889
890#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01)
891
892#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01)
893#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f)
894
895#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01)
896#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03)
897#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03)
898
899#define ISP1080_ISP_PARAMETER(c) \
900 (((c)[18]) | ((c)[19] << 8))
901
902#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01)
903#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01)
904
905#define ISP1080_BUS1_OFF 112
906
907#define ISP1080_NVRAM_INITIATOR_ID(c, b) \
908 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
909#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \
910 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
911#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \
912 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
913#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \
914 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]
915
916#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \
917 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
918#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \
919 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
920#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \
921 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
922#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \
923 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
924 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
925#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \
926 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
927 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))
928
929#define ISP1080_NVRAM_TARGOFF(b) \
930 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
931#define ISP1080_NVRAM_TARGSIZE 6
932#define _IxT8(tgt, tidx, b) \
933 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
934
935#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \
936 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
937#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \
938 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
939#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \
940 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
941#define ISP1080_NVRAM_TGT_TQING(c, t, b) \
942 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
943#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \
944 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
945#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \
946 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
947#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \
948 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
949#define ISP1080_NVRAM_TGT_DISC(c, t, b) \
950 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
951#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
952 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
953#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
954 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
955#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
956 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
957#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
958 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
959#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
960 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
961
962#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE
963#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE
964#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD
965#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT
966#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE
967#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE
968#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER
969#define ISP12160_FAST_POST ISP1080_FAST_POST
970#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION
971
972#define ISP12160_NVRAM_INITIATOR_ID \
973 ISP1080_NVRAM_INITIATOR_ID
974#define ISP12160_NVRAM_BUS_RESET_DELAY \
975 ISP1080_NVRAM_BUS_RESET_DELAY
976#define ISP12160_NVRAM_BUS_RETRY_COUNT \
977 ISP1080_NVRAM_BUS_RETRY_COUNT
978#define ISP12160_NVRAM_BUS_RETRY_DELAY \
979 ISP1080_NVRAM_BUS_RETRY_DELAY
980#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \
981 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME
982#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \
983 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION
984#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \
985 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION
986#define ISP12160_NVRAM_SELECTION_TIMEOUT \
987 ISP1080_NVRAM_SELECTION_TIMEOUT
988#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \
989 ISP1080_NVRAM_MAX_QUEUE_DEPTH
990
991
992#define ISP12160_BUS0_OFF 24
993#define ISP12160_BUS1_OFF 136
994
995#define ISP12160_NVRAM_TARGOFF(b) \
996 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16)
997
998#define ISP12160_NVRAM_TARGSIZE 6
999#define _IxT16(tgt, tidx, b) \
1000 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
1001
1002#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \
1003 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01)
1004#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \
1005 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01)
1006#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \
1007 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01)
1008#define ISP12160_NVRAM_TGT_TQING(c, t, b) \
1009 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01)
1010#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \
1011 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01)
1012#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \
1013 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01)
1014#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \
1015 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01)
1016#define ISP12160_NVRAM_TGT_DISC(c, t, b) \
1017 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01)
1018
1019#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
1020 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff)
1021#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
1022 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff)
1023
1024#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
1025 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f)
1026#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
1027 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01)
1028
1029#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \
1030 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f)
1031#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \
1032 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03)
1033#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \
1034 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01)
1035
1036/*
1037 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes.
1038 *
1039 * Some portion of the front of this is for general RISC engine parameters,
1040 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
1041 *
1042 * This is followed by some general host adapter parameters, and ends with
1043 * a checksum xor byte at offset 255. For non-byte entities data is stored
1044 * in Little Endian order.
1045 */
1046#define ISP2100_NVRAM_SIZE 256
1047/* ISP_NVRAM_VERSION is in same overall place */
1048#define ISP2100_NVRAM_RISCVER(c) (c)[6]
1049#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8))
1050#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8))
1051#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8))
1052#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1053#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16]
1054#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17]
1055
1056#define ISP2100_NVRAM_PORT_NAME(c) (\
1057 (((uint64_t)(c)[18]) << 56) | \
1058 (((uint64_t)(c)[19]) << 48) | \
1059 (((uint64_t)(c)[20]) << 40) | \
1060 (((uint64_t)(c)[21]) << 32) | \
1061 (((uint64_t)(c)[22]) << 24) | \
1062 (((uint64_t)(c)[23]) << 16) | \
1063 (((uint64_t)(c)[24]) << 8) | \
1064 (((uint64_t)(c)[25]) << 0))
1065
1066#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8))
1067#define ISP2100_NVRAM_TOV(c) ((c)[29])
1068
1069#define ISP2100_NVRAM_NODE_NAME(c) (\
1070 (((uint64_t)(c)[30]) << 56) | \
1071 (((uint64_t)(c)[31]) << 48) | \
1072 (((uint64_t)(c)[32]) << 40) | \
1073 (((uint64_t)(c)[33]) << 32) | \
1074 (((uint64_t)(c)[34]) << 24) | \
1075 (((uint64_t)(c)[35]) << 16) | \
1076 (((uint64_t)(c)[36]) << 8) | \
1077 (((uint64_t)(c)[37]) << 0))
1078
1079#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8))
1080
1081#define ISP2100_RACC_TIMER(c) (c)[40]
1082#define ISP2100_IDELAY_TIMER(c) (c)[41]
1083
1084#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8))
1085
1086#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8))
1087
1088#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8))
1089#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01)
1090#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01)
1091#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01)
1092#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01)
1093#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01)
1094#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01)
1095
1096#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\
1097 (((uint64_t)(c)[72]) << 56) | \
1098 (((uint64_t)(c)[73]) << 48) | \
1099 (((uint64_t)(c)[74]) << 40) | \
1100 (((uint64_t)(c)[75]) << 32) | \
1101 (((uint64_t)(c)[76]) << 24) | \
1102 (((uint64_t)(c)[77]) << 16) | \
1103 (((uint64_t)(c)[78]) << 8) | \
1104 (((uint64_t)(c)[79]) << 0))
1105
1106#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80]
1107#define ISP2100_RESET_DELAY(c) (c)[81]
1108
1109#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8))
1110
1111/*
1112 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum.
1113 */
1114#define ISP2400_NVRAM_PORT0_ADDR 0x80
1115#define ISP2400_NVRAM_PORT1_ADDR 0x180
1116#define ISP2400_NVRAM_SIZE 512
1117
1118#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8))
1119#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8))
1120#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1121#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8))
1122#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8))
1123
1124#define ISP2400_NVRAM_PORT_NAME(c) (\
1125 (((uint64_t)(c)[20]) << 56) | \
1126 (((uint64_t)(c)[21]) << 48) | \
1127 (((uint64_t)(c)[22]) << 40) | \
1128 (((uint64_t)(c)[23]) << 32) | \
1129 (((uint64_t)(c)[24]) << 24) | \
1130 (((uint64_t)(c)[25]) << 16) | \
1131 (((uint64_t)(c)[26]) << 8) | \
1132 (((uint64_t)(c)[27]) << 0))
1133
1134#define ISP2400_NVRAM_NODE_NAME(c) (\
1135 (((uint64_t)(c)[28]) << 56) | \
1136 (((uint64_t)(c)[29]) << 48) | \
1137 (((uint64_t)(c)[30]) << 40) | \
1138 (((uint64_t)(c)[31]) << 32) | \
1139 (((uint64_t)(c)[32]) << 24) | \
1140 (((uint64_t)(c)[33]) << 16) | \
1141 (((uint64_t)(c)[34]) << 8) | \
1142 (((uint64_t)(c)[35]) << 0))
1143
1144#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8))
1145#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8))
1146#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8))
1147#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8))
1148
1149#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \
1150 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24))
1151#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \
1152 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24))
1153#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
1154 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))
1155
1156/*
1157 * Firmware Crash Dump
1158 *
1159 * QLogic needs specific information format when they look at firmware crashes.
1160 *
1161 * This is incredibly kernel memory consumptive (to say the least), so this
1162 * code is only compiled in when needed.
1163 */
1164
1165#define QLA2200_RISC_IMAGE_DUMP_SIZE \
1166 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1167 (352 * sizeof (uint16_t)) + /* RISC registers */ \
1168 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */
1169#define QLA2300_RISC_IMAGE_DUMP_SIZE \
1170 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1171 (464 * sizeof (uint16_t)) + /* RISC registers */ \
1172 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \
1173 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \
1174 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */
1175/* the larger of the two */
1176#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE
1177#endif /* _ISPREG_H */
459 const char *func;
460} mbreg_t;
461#define MBSINIT(mbxp, code, loglev, timo) \
462 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \
463 (mbxp)->ibitm = ~0; \
464 (mbxp)->obitm = ~0; \
465 (mbxp)->param[0] = code; \
466 (mbxp)->lineno = __LINE__; \
467 (mbxp)->func = __func__; \
468 (mbxp)->logval = loglev; \
469 (mbxp)->timeout = timo
470
471
472/*
473 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
474 * NB: The RISC processor must be paused and the appropriate register
475 * bank selected via BIU2100_CSR bits.
476 */
477
478#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
479#define FPM_SOFT_RESET 0x0100
480
481#define FBM_CMD (BIU_BLOCK + 0xB8)
482#define FBMCMD_FIFO_RESET_ALL 0xA000
483
484
485/*
486 * SXP Block Register Offsets
487 */
488#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
489#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
490#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
491#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
492#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
493#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
494#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
495#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
496#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
497#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
498#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
499#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
500#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
501#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
502#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
503#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
504#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
505#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
506#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
507#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
508#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
509#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
510#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
511#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
512#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
513#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
514#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
515#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
516#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
517#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
518#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
519#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
520#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
521#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
522#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
523#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
524#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
525#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
526#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
527
528/* for 1080/1280/1240 only */
529#define SXP_BANK1_SELECT 0x100
530
531
532/* SXP CONF1 REGISTER */
533#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */
534#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */
535#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */
536#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */
537#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */
538
539/* SXP CONF2 REGISTER */
540#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */
541#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */
542#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */
543#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */
544#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */
545#define SXP_CONF2_SELECT 0x0001 /* Enable selection */
546
547/* SXP INTERRUPT REGISTER */
548#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */
549#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */
550#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */
551#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */
552#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */
553#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */
554#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */
555#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */
556#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */
557#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */
558
559
560/* SXP GROSS ERROR REGISTER */
561#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */
562#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */
563#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */
564#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */
565#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */
566#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */
567#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */
568
569/* SXP EXCEPTION REGISTER */
570#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */
571#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */
572#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */
573#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */
574#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */
575#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */
576#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */
577#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */
578#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */
579#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */
580
581 /* SXP OVERRIDE REGISTER */
582#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */
583#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */
584#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */
585#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */
586#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */
587#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */
588#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */
589#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */
590#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */
591#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */
592#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */
593#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */
594#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */
595
596/* SXP COMMANDS */
597#define SXP_RESET_BUS_CMD 0x300b
598
599/* SXP SCSI ID REGISTER */
600#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */
601#define SXP_SELECT_ID 0x000F /* Select id */
602
603/* SXP DEV CONFIG1 REGISTER */
604#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */
605#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */
606#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */
607
608
609/* SXP DEV CONFIG2 REGISTER */
610#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */
611#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */
612#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */
613#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */
614#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */
615
616
617/* SXP PHASE POINTER REGISTER */
618#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */
619#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */
620#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */
621#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */
622
623
624/* SXP FIFO STATUS REGISTER */
625#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */
626#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */
627#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */
628#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */
629
630
631/* SXP CONTROL PINS REGISTER */
632#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */
633#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */
634#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */
635#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */
636#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */
637#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */
638#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */
639#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */
640#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */
641#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */
642#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */
643#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */
644
645/*
646 * Set the hold time for the SCSI Bus Reset to be 250 ms
647 */
648#define SXP_SCSI_BUS_RESET_HOLD_TIME 250
649
650/* SXP DIFF PINS REGISTER */
651#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */
652#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */
653#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */
654#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */
655#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
656#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
657
658/* Ultra2 only */
659#define SXP_PINS_LVD_MODE 0x1000
660#define SXP_PINS_HVD_MODE 0x0800
661#define SXP_PINS_SE_MODE 0x0400
662#define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE)
663
664/* The above have to be put together with the DIFFM pin to make sense */
665#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE)
666#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE)
667#define ISP1080_SE_MODE (SXP_PINS_SE_MODE)
668#define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE)
669
670/*
671 * RISC and Host Command and Control Block Register Offsets
672 */
673
674#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
675#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
676#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
677#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
678#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
679#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
680#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
681#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
682#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
683#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
684#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
685#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
686#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
687#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
688#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
689#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
690#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
691#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
692#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
693#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
694#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
695#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
696#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
697#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
698#define RISC_MTR2100 RISC_BLOCK+0x30
699
700#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
701#define DUAL_BANK 8
702#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
703#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
704#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
705#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
706#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
707#define TCR RISC_BLOCK+0x46 /* W : Test Control */
708#define TMR RISC_BLOCK+0x48 /* W : Test Mode */
709
710
711/* PROCESSOR STATUS REGISTER */
712#define RISC_PSR_FORCE_TRUE 0x8000
713#define RISC_PSR_LOOP_COUNT_DONE 0x4000
714#define RISC_PSR_RISC_INT 0x2000
715#define RISC_PSR_TIMER_ROLLOVER 0x1000
716#define RISC_PSR_ALU_OVERFLOW 0x0800
717#define RISC_PSR_ALU_MSB 0x0400
718#define RISC_PSR_ALU_CARRY 0x0200
719#define RISC_PSR_ALU_ZERO 0x0100
720
721#define RISC_PSR_PCI_ULTRA 0x0080
722#define RISC_PSR_SBUS_ULTRA 0x0020
723
724#define RISC_PSR_DMA_INT 0x0010
725#define RISC_PSR_SXP_INT 0x0008
726#define RISC_PSR_HOST_INT 0x0004
727#define RISC_PSR_INT_PENDING 0x0002
728#define RISC_PSR_FORCE_FALSE 0x0001
729
730
731/* Host Command and Control */
732#define HCCR_CMD_NOP 0x0000 /* NOP */
733#define HCCR_CMD_RESET 0x1000 /* Reset RISC */
734#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
735#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
736#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
737#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /*
738 * Disable RISC pause on FPM
739 * parity error.
740 */
741#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
742#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
743#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
744#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */
745#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */
746#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */
747#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */
748#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */
749
750
751#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400
752#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200
753#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100
754#define ISP2100_HCCR_PARITY 0x0001
755
756#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */
757#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */
758#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */
759
760#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */
761#define HCCR_RESET 0x0040 /* R : reset in progress */
762#define HCCR_PAUSE 0x0020 /* R : RISC paused */
763
764#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
765
766/*
767 * Defines for Interrupts
768 */
769#define ISP_INTS_ENABLED(isp) \
770 ((IS_SCSI(isp))? \
771 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \
772 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \
773 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK)))
774
775#define ISP_ENABLE_INTS(isp) \
776 (IS_SCSI(isp) ? \
777 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \
778 (IS_24XX(isp) ? \
779 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \
780 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK))))
781
782#define ISP_DISABLE_INTS(isp) \
783 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0)
784
785/*
786 * NVRAM Definitions (PCI cards only)
787 */
788
789#define ISPBSMX(c, byte, shift, mask) \
790 (((c)[(byte)] >> (shift)) & (mask))
791/*
792 * Qlogic 1020/1040 NVRAM is an array of 128 bytes.
793 *
794 * Some portion of the front of this is for general host adapter properties
795 * This is followed by an array of per-target parameters, and is tailed off
796 * with a checksum xor byte at offset 127. For non-byte entities data is
797 * stored in Little Endian order.
798 */
799
800#define ISP_NVRAM_SIZE 128
801
802#define ISP_NVRAM_VERSION(c) (c)[4]
803#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
804#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
805#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01)
806#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f)
807#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6]
808#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7]
809#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8]
810#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f)
811#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01)
812#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01)
813#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01)
814#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01)
815#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10]
816#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01)
817#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01)
818#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01)
819#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01)
820#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01)
821#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01)
822#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01)
823#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01)
824#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8))
825#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8))
826#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01)
827#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01)
828#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01)
829#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01)
830#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01)
831#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01)
832
833#define ISP_NVRAM_TARGOFF 28
834#define ISP_NVRAM_TARGSIZE 6
835#define _IxT(tgt, tidx) \
836 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx))
837#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01)
838#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01)
839#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01)
840#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01)
841#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01)
842#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01)
843#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01)
844#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01)
845#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff)
846#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff)
847#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
848#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
849#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
850
851/*
852 * Qlogic 1080/1240 NVRAM is an array of 256 bytes.
853 *
854 * Some portion of the front of this is for general host adapter properties
855 * This is followed by an array of per-target parameters, and is tailed off
856 * with a checksum xor byte at offset 256. For non-byte entities data is
857 * stored in Little Endian order.
858 */
859
860#define ISP1080_NVRAM_SIZE 256
861
862#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c)
863
864/* Offset 5 */
865/*
866 uint8_t bios_configuration_mode :2;
867 uint8_t bios_disable :1;
868 uint8_t selectable_scsi_boot_enable :1;
869 uint8_t cd_rom_boot_enable :1;
870 uint8_t disable_loading_risc_code :1;
871 uint8_t enable_64bit_addressing :1;
872 uint8_t unused_7 :1;
873 */
874
875/* Offsets 6, 7 */
876/*
877 uint8_t boot_lun_number :5;
878 uint8_t scsi_bus_number :1;
879 uint8_t unused_6 :1;
880 uint8_t unused_7 :1;
881 uint8_t boot_target_number :4;
882 uint8_t unused_12 :1;
883 uint8_t unused_13 :1;
884 uint8_t unused_14 :1;
885 uint8_t unused_15 :1;
886 */
887
888#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01)
889
890#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01)
891#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f)
892
893#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01)
894#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03)
895#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03)
896
897#define ISP1080_ISP_PARAMETER(c) \
898 (((c)[18]) | ((c)[19] << 8))
899
900#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01)
901#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01)
902
903#define ISP1080_BUS1_OFF 112
904
905#define ISP1080_NVRAM_INITIATOR_ID(c, b) \
906 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
907#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \
908 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
909#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \
910 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
911#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \
912 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]
913
914#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \
915 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
916#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \
917 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
918#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \
919 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
920#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \
921 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
922 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
923#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \
924 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
925 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))
926
927#define ISP1080_NVRAM_TARGOFF(b) \
928 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
929#define ISP1080_NVRAM_TARGSIZE 6
930#define _IxT8(tgt, tidx, b) \
931 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
932
933#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \
934 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
935#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \
936 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
937#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \
938 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
939#define ISP1080_NVRAM_TGT_TQING(c, t, b) \
940 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
941#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \
942 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
943#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \
944 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
945#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \
946 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
947#define ISP1080_NVRAM_TGT_DISC(c, t, b) \
948 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
949#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
950 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
951#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
952 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
953#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
954 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
955#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
956 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
957#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
958 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
959
960#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE
961#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE
962#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD
963#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT
964#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE
965#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE
966#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER
967#define ISP12160_FAST_POST ISP1080_FAST_POST
968#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION
969
970#define ISP12160_NVRAM_INITIATOR_ID \
971 ISP1080_NVRAM_INITIATOR_ID
972#define ISP12160_NVRAM_BUS_RESET_DELAY \
973 ISP1080_NVRAM_BUS_RESET_DELAY
974#define ISP12160_NVRAM_BUS_RETRY_COUNT \
975 ISP1080_NVRAM_BUS_RETRY_COUNT
976#define ISP12160_NVRAM_BUS_RETRY_DELAY \
977 ISP1080_NVRAM_BUS_RETRY_DELAY
978#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \
979 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME
980#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \
981 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION
982#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \
983 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION
984#define ISP12160_NVRAM_SELECTION_TIMEOUT \
985 ISP1080_NVRAM_SELECTION_TIMEOUT
986#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \
987 ISP1080_NVRAM_MAX_QUEUE_DEPTH
988
989
990#define ISP12160_BUS0_OFF 24
991#define ISP12160_BUS1_OFF 136
992
993#define ISP12160_NVRAM_TARGOFF(b) \
994 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16)
995
996#define ISP12160_NVRAM_TARGSIZE 6
997#define _IxT16(tgt, tidx, b) \
998 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
999
1000#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \
1001 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01)
1002#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \
1003 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01)
1004#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \
1005 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01)
1006#define ISP12160_NVRAM_TGT_TQING(c, t, b) \
1007 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01)
1008#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \
1009 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01)
1010#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \
1011 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01)
1012#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \
1013 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01)
1014#define ISP12160_NVRAM_TGT_DISC(c, t, b) \
1015 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01)
1016
1017#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
1018 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff)
1019#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
1020 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff)
1021
1022#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
1023 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f)
1024#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
1025 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01)
1026
1027#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \
1028 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f)
1029#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \
1030 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03)
1031#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \
1032 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01)
1033
1034/*
1035 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes.
1036 *
1037 * Some portion of the front of this is for general RISC engine parameters,
1038 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
1039 *
1040 * This is followed by some general host adapter parameters, and ends with
1041 * a checksum xor byte at offset 255. For non-byte entities data is stored
1042 * in Little Endian order.
1043 */
1044#define ISP2100_NVRAM_SIZE 256
1045/* ISP_NVRAM_VERSION is in same overall place */
1046#define ISP2100_NVRAM_RISCVER(c) (c)[6]
1047#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8))
1048#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8))
1049#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8))
1050#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1051#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16]
1052#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17]
1053
1054#define ISP2100_NVRAM_PORT_NAME(c) (\
1055 (((uint64_t)(c)[18]) << 56) | \
1056 (((uint64_t)(c)[19]) << 48) | \
1057 (((uint64_t)(c)[20]) << 40) | \
1058 (((uint64_t)(c)[21]) << 32) | \
1059 (((uint64_t)(c)[22]) << 24) | \
1060 (((uint64_t)(c)[23]) << 16) | \
1061 (((uint64_t)(c)[24]) << 8) | \
1062 (((uint64_t)(c)[25]) << 0))
1063
1064#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8))
1065#define ISP2100_NVRAM_TOV(c) ((c)[29])
1066
1067#define ISP2100_NVRAM_NODE_NAME(c) (\
1068 (((uint64_t)(c)[30]) << 56) | \
1069 (((uint64_t)(c)[31]) << 48) | \
1070 (((uint64_t)(c)[32]) << 40) | \
1071 (((uint64_t)(c)[33]) << 32) | \
1072 (((uint64_t)(c)[34]) << 24) | \
1073 (((uint64_t)(c)[35]) << 16) | \
1074 (((uint64_t)(c)[36]) << 8) | \
1075 (((uint64_t)(c)[37]) << 0))
1076
1077#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8))
1078
1079#define ISP2100_RACC_TIMER(c) (c)[40]
1080#define ISP2100_IDELAY_TIMER(c) (c)[41]
1081
1082#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8))
1083
1084#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8))
1085
1086#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8))
1087#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01)
1088#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01)
1089#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01)
1090#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01)
1091#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01)
1092#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01)
1093
1094#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\
1095 (((uint64_t)(c)[72]) << 56) | \
1096 (((uint64_t)(c)[73]) << 48) | \
1097 (((uint64_t)(c)[74]) << 40) | \
1098 (((uint64_t)(c)[75]) << 32) | \
1099 (((uint64_t)(c)[76]) << 24) | \
1100 (((uint64_t)(c)[77]) << 16) | \
1101 (((uint64_t)(c)[78]) << 8) | \
1102 (((uint64_t)(c)[79]) << 0))
1103
1104#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80]
1105#define ISP2100_RESET_DELAY(c) (c)[81]
1106
1107#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8))
1108
1109/*
1110 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum.
1111 */
1112#define ISP2400_NVRAM_PORT0_ADDR 0x80
1113#define ISP2400_NVRAM_PORT1_ADDR 0x180
1114#define ISP2400_NVRAM_SIZE 512
1115
1116#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8))
1117#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8))
1118#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1119#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8))
1120#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8))
1121
1122#define ISP2400_NVRAM_PORT_NAME(c) (\
1123 (((uint64_t)(c)[20]) << 56) | \
1124 (((uint64_t)(c)[21]) << 48) | \
1125 (((uint64_t)(c)[22]) << 40) | \
1126 (((uint64_t)(c)[23]) << 32) | \
1127 (((uint64_t)(c)[24]) << 24) | \
1128 (((uint64_t)(c)[25]) << 16) | \
1129 (((uint64_t)(c)[26]) << 8) | \
1130 (((uint64_t)(c)[27]) << 0))
1131
1132#define ISP2400_NVRAM_NODE_NAME(c) (\
1133 (((uint64_t)(c)[28]) << 56) | \
1134 (((uint64_t)(c)[29]) << 48) | \
1135 (((uint64_t)(c)[30]) << 40) | \
1136 (((uint64_t)(c)[31]) << 32) | \
1137 (((uint64_t)(c)[32]) << 24) | \
1138 (((uint64_t)(c)[33]) << 16) | \
1139 (((uint64_t)(c)[34]) << 8) | \
1140 (((uint64_t)(c)[35]) << 0))
1141
1142#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8))
1143#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8))
1144#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8))
1145#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8))
1146
1147#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \
1148 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24))
1149#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \
1150 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24))
1151#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
1152 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))
1153
1154/*
1155 * Firmware Crash Dump
1156 *
1157 * QLogic needs specific information format when they look at firmware crashes.
1158 *
1159 * This is incredibly kernel memory consumptive (to say the least), so this
1160 * code is only compiled in when needed.
1161 */
1162
1163#define QLA2200_RISC_IMAGE_DUMP_SIZE \
1164 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1165 (352 * sizeof (uint16_t)) + /* RISC registers */ \
1166 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */
1167#define QLA2300_RISC_IMAGE_DUMP_SIZE \
1168 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1169 (464 * sizeof (uint16_t)) + /* RISC registers */ \
1170 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \
1171 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \
1172 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */
1173/* the larger of the two */
1174#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE
1175#endif /* _ISPREG_H */