414/* BIU2400_HCCR definitions */ 415 416#define HCCR_2400_CMD_NOP 0x00000000 417#define HCCR_2400_CMD_RESET 0x10000000 418#define HCCR_2400_CMD_CLEAR_RESET 0x20000000 419#define HCCR_2400_CMD_PAUSE 0x30000000 420#define HCCR_2400_CMD_RELEASE 0x40000000 421#define HCCR_2400_CMD_SET_HOST_INT 0x50000000 422#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 423#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 424 425#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 426#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 427#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 428 429 430/* 431 * Mailbox Block Register Offsets 432 */ 433 434#define INMAILBOX0 (MBOX_BLOCK+0x0) 435#define INMAILBOX1 (MBOX_BLOCK+0x2) 436#define INMAILBOX2 (MBOX_BLOCK+0x4) 437#define INMAILBOX3 (MBOX_BLOCK+0x6) 438#define INMAILBOX4 (MBOX_BLOCK+0x8) 439#define INMAILBOX5 (MBOX_BLOCK+0xA) 440#define INMAILBOX6 (MBOX_BLOCK+0xC) 441#define INMAILBOX7 (MBOX_BLOCK+0xE) 442 443#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 444#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 445#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 446#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 447#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 448#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 449#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 450#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 451 452/* 453 * Strictly speaking, it's 454 * SCSI && 2100 : 8 MBOX registers 455 * 2200: 24 MBOX registers 456 * 2300/2400: 32 MBOX registers 457 */ 458#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 459#define ISP_NMBOX(isp) ((IS_24XX(isp) || IS_23XX(isp))? 32 : (IS_2200(isp) ? 24 : 8)) 460#define ISP_NMBOX_BMASK(isp) \ 461 ((IS_24XX(isp) || IS_23XX(isp))? 0xffffffff : (IS_2200(isp)? 0x00ffffff : 0xff)) 462#define MAX_MAILBOX 32 463/* if timeout == 0, then default timeout is picked */ 464#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 465typedef struct { 466 uint16_t param[MAX_MAILBOX]; 467 uint32_t ibits; /* bits to add for register copyin */ 468 uint32_t obits; /* bits to add for register copyout */ 469 uint32_t ibitm; /* bits to mask for register copyin */ 470 uint32_t obitm; /* bits to mask for register copyout */ 471 uint32_t 472 lineno : 16, 473 : 12, 474 logval : 4; 475 uint32_t timeout; 476 const char *func; 477} mbreg_t; 478#define MBSINIT(mbxp, code, loglev, timo) \ 479 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \ 480 (mbxp)->ibitm = ~0; \ 481 (mbxp)->obitm = ~0; \ 482 (mbxp)->param[0] = code; \ 483 (mbxp)->lineno = __LINE__; \ 484 (mbxp)->func = __func__; \ 485 (mbxp)->logval = loglev; \ 486 (mbxp)->timeout = timo 487 488 489/* 490 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 491 * NB: The RISC processor must be paused and the appropriate register 492 * bank selected via BIU2100_CSR bits. 493 */ 494 495#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 496#define FPM_SOFT_RESET 0x0100 497 498#define FBM_CMD (BIU_BLOCK + 0xB8) 499#define FBMCMD_FIFO_RESET_ALL 0xA000 500 501 502/* 503 * SXP Block Register Offsets 504 */ 505#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 506#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 507#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 508#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 509#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 510#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 511#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 512#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 513#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 514#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 515#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 516#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 517#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 518#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 519#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 520#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 521#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 522#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 523#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 524#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 525#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 526#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 527#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 528#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 529#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 530#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 531#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 532#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 533#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 534#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 535#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 536#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 537#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 538#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 539#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 540#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 541#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 542#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 543#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 544 545/* for 1080/1280/1240 only */ 546#define SXP_BANK1_SELECT 0x100 547 548 549/* SXP CONF1 REGISTER */ 550#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 551#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 552#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 553#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 554#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 555 556/* SXP CONF2 REGISTER */ 557#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 558#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 559#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 560#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 561#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 562#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 563 564/* SXP INTERRUPT REGISTER */ 565#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 566#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 567#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 568#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 569#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 570#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 571#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 572#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 573#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 574#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 575 576 577/* SXP GROSS ERROR REGISTER */ 578#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 579#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 580#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 581#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 582#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 583#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 584#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 585 586/* SXP EXCEPTION REGISTER */ 587#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 588#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 589#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 590#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 591#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 592#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 593#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 594#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 595#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 596#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 597 598 /* SXP OVERRIDE REGISTER */ 599#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 600#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 601#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 602#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 603#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 604#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 605#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 606#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 607#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 608#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 609#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 610#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 611#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 612 613/* SXP COMMANDS */ 614#define SXP_RESET_BUS_CMD 0x300b 615 616/* SXP SCSI ID REGISTER */ 617#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 618#define SXP_SELECT_ID 0x000F /* Select id */ 619 620/* SXP DEV CONFIG1 REGISTER */ 621#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 622#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 623#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 624 625 626/* SXP DEV CONFIG2 REGISTER */ 627#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 628#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 629#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 630#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 631#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 632 633 634/* SXP PHASE POINTER REGISTER */ 635#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 636#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 637#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 638#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 639 640 641/* SXP FIFO STATUS REGISTER */ 642#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 643#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 644#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 645#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 646 647 648/* SXP CONTROL PINS REGISTER */ 649#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 650#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 651#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 652#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 653#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 654#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 655#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 656#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 657#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 658#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 659#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 660#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 661 662/* 663 * Set the hold time for the SCSI Bus Reset to be 250 ms 664 */ 665#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 666 667/* SXP DIFF PINS REGISTER */ 668#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 669#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 670#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 671#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 672#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 673#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 674 675/* Ultra2 only */ 676#define SXP_PINS_LVD_MODE 0x1000 677#define SXP_PINS_HVD_MODE 0x0800 678#define SXP_PINS_SE_MODE 0x0400 679#define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE) 680 681/* The above have to be put together with the DIFFM pin to make sense */ 682#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 683#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 684#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 685#define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE) 686 687/* 688 * RISC and Host Command and Control Block Register Offsets 689 */ 690 691#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 692#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 693#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 694#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 695#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 696#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 697#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 698#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 699#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 700#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 701#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 702#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 703#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 704#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 705#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 706#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 707#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 708#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 709#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 710#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 711#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 712#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 713#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 714#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 715#define RISC_MTR2100 RISC_BLOCK+0x30 716 717#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 718#define DUAL_BANK 8 719#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 720#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 721#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 722#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 723#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 724#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 725#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 726 727 728/* PROCESSOR STATUS REGISTER */ 729#define RISC_PSR_FORCE_TRUE 0x8000 730#define RISC_PSR_LOOP_COUNT_DONE 0x4000 731#define RISC_PSR_RISC_INT 0x2000 732#define RISC_PSR_TIMER_ROLLOVER 0x1000 733#define RISC_PSR_ALU_OVERFLOW 0x0800 734#define RISC_PSR_ALU_MSB 0x0400 735#define RISC_PSR_ALU_CARRY 0x0200 736#define RISC_PSR_ALU_ZERO 0x0100 737 738#define RISC_PSR_PCI_ULTRA 0x0080 739#define RISC_PSR_SBUS_ULTRA 0x0020 740 741#define RISC_PSR_DMA_INT 0x0010 742#define RISC_PSR_SXP_INT 0x0008 743#define RISC_PSR_HOST_INT 0x0004 744#define RISC_PSR_INT_PENDING 0x0002 745#define RISC_PSR_FORCE_FALSE 0x0001 746 747 748/* Host Command and Control */ 749#define HCCR_CMD_NOP 0x0000 /* NOP */ 750#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 751#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 752#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 753#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 754#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 755 * Disable RISC pause on FPM 756 * parity error. 757 */ 758#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 759#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 760#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 761#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 762#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 763#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 764#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 765#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 766 767 768#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 769#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 770#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 771#define ISP2100_HCCR_PARITY 0x0001 772 773#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 774#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 775#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 776 777#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 778#define HCCR_RESET 0x0040 /* R : reset in progress */ 779#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 780 781#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 782 783/* 784 * Defines for Interrupts 785 */ 786#define ISP_INTS_ENABLED(isp) \ 787 ((IS_SCSI(isp))? \ 788 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ 789 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ 790 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) 791 792#define ISP_ENABLE_INTS(isp) \ 793 (IS_SCSI(isp) ? \ 794 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ 795 (IS_24XX(isp) ? \ 796 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ 797 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) 798 799#define ISP_DISABLE_INTS(isp) \ 800 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) 801 802/* 803 * NVRAM Definitions (PCI cards only) 804 */ 805 806#define ISPBSMX(c, byte, shift, mask) \ 807 (((c)[(byte)] >> (shift)) & (mask)) 808/* 809 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 810 * 811 * Some portion of the front of this is for general host adapter properties 812 * This is followed by an array of per-target parameters, and is tailed off 813 * with a checksum xor byte at offset 127. For non-byte entities data is 814 * stored in Little Endian order. 815 */ 816 817#define ISP_NVRAM_SIZE 128 818 819#define ISP_NVRAM_VERSION(c) (c)[4] 820#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 821#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 822#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 823#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 824#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 825#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 826#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 827#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 828#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 829#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 830#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 831#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 832#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 833#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 834#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 835#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 836#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 837#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 838#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 839#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 840#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 841#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 842#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 843#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 844#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 845#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 846#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 847#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 848#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 849 850#define ISP_NVRAM_TARGOFF 28 851#define ISP_NVRAM_TARGSIZE 6 852#define _IxT(tgt, tidx) \ 853 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) 854#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 855#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 856#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 857#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 858#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 859#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 860#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 861#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 862#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 863#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 864#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 865#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 866#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 867 868/* 869 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 870 * 871 * Some portion of the front of this is for general host adapter properties 872 * This is followed by an array of per-target parameters, and is tailed off 873 * with a checksum xor byte at offset 256. For non-byte entities data is 874 * stored in Little Endian order. 875 */ 876 877#define ISP1080_NVRAM_SIZE 256 878 879#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 880 881/* Offset 5 */ 882/* 883 uint8_t bios_configuration_mode :2; 884 uint8_t bios_disable :1; 885 uint8_t selectable_scsi_boot_enable :1; 886 uint8_t cd_rom_boot_enable :1; 887 uint8_t disable_loading_risc_code :1; 888 uint8_t enable_64bit_addressing :1; 889 uint8_t unused_7 :1; 890 */ 891 892/* Offsets 6, 7 */ 893/* 894 uint8_t boot_lun_number :5; 895 uint8_t scsi_bus_number :1; 896 uint8_t unused_6 :1; 897 uint8_t unused_7 :1; 898 uint8_t boot_target_number :4; 899 uint8_t unused_12 :1; 900 uint8_t unused_13 :1; 901 uint8_t unused_14 :1; 902 uint8_t unused_15 :1; 903 */ 904 905#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 906 907#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 908#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 909 910#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 911#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 912#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 913 914#define ISP1080_ISP_PARAMETER(c) \ 915 (((c)[18]) | ((c)[19] << 8)) 916 917#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 918#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 919 920#define ISP1080_BUS1_OFF 112 921 922#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 923 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 924#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 925 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 926#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 927 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 928#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 929 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 930 931#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 932 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 933#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 934 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 935#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 936 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 937#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 938 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 939 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 940#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 941 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 942 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 943 944#define ISP1080_NVRAM_TARGOFF(b) \ 945 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 946#define ISP1080_NVRAM_TARGSIZE 6 947#define _IxT8(tgt, tidx, b) \ 948 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 949 950#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 951 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 952#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 953 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 954#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 955 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 956#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 957 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 958#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 959 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 960#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 961 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 962#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 963 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 964#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 965 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 966#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 967 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 968#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 969 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 970#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 971 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 972#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 973 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 974#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 975 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 976 977#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 978#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 979#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 980#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 981#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 982#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 983#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 984#define ISP12160_FAST_POST ISP1080_FAST_POST 985#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 986 987#define ISP12160_NVRAM_INITIATOR_ID \ 988 ISP1080_NVRAM_INITIATOR_ID 989#define ISP12160_NVRAM_BUS_RESET_DELAY \ 990 ISP1080_NVRAM_BUS_RESET_DELAY 991#define ISP12160_NVRAM_BUS_RETRY_COUNT \ 992 ISP1080_NVRAM_BUS_RETRY_COUNT 993#define ISP12160_NVRAM_BUS_RETRY_DELAY \ 994 ISP1080_NVRAM_BUS_RETRY_DELAY 995#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 996 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 997#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 998 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 999#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 1000 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 1001#define ISP12160_NVRAM_SELECTION_TIMEOUT \ 1002 ISP1080_NVRAM_SELECTION_TIMEOUT 1003#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 1004 ISP1080_NVRAM_MAX_QUEUE_DEPTH 1005 1006 1007#define ISP12160_BUS0_OFF 24 1008#define ISP12160_BUS1_OFF 136 1009 1010#define ISP12160_NVRAM_TARGOFF(b) \ 1011 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 1012 1013#define ISP12160_NVRAM_TARGSIZE 6 1014#define _IxT16(tgt, tidx, b) \ 1015 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 1016 1017#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 1018 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 1019#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 1020 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 1021#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 1022 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 1023#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 1024 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 1025#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 1026 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 1027#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 1028 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 1029#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 1030 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 1031#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 1032 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 1033 1034#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 1035 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 1036#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 1037 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 1038 1039#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 1040 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 1041#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 1042 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 1043 1044#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 1045 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 1046#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 1047 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 1048#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 1049 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 1050 1051/* 1052 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. 1053 * 1054 * Some portion of the front of this is for general RISC engine parameters, 1055 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 1056 * 1057 * This is followed by some general host adapter parameters, and ends with 1058 * a checksum xor byte at offset 255. For non-byte entities data is stored 1059 * in Little Endian order. 1060 */ 1061#define ISP2100_NVRAM_SIZE 256 1062/* ISP_NVRAM_VERSION is in same overall place */ 1063#define ISP2100_NVRAM_RISCVER(c) (c)[6] 1064#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) 1065#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 1066#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 1067#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1068#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 1069#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 1070 1071#define ISP2100_NVRAM_PORT_NAME(c) (\ 1072 (((uint64_t)(c)[18]) << 56) | \ 1073 (((uint64_t)(c)[19]) << 48) | \ 1074 (((uint64_t)(c)[20]) << 40) | \ 1075 (((uint64_t)(c)[21]) << 32) | \ 1076 (((uint64_t)(c)[22]) << 24) | \ 1077 (((uint64_t)(c)[23]) << 16) | \ 1078 (((uint64_t)(c)[24]) << 8) | \ 1079 (((uint64_t)(c)[25]) << 0)) 1080 1081#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 1082#define ISP2100_NVRAM_TOV(c) ((c)[29]) 1083 1084#define ISP2100_NVRAM_NODE_NAME(c) (\ 1085 (((uint64_t)(c)[30]) << 56) | \ 1086 (((uint64_t)(c)[31]) << 48) | \ 1087 (((uint64_t)(c)[32]) << 40) | \ 1088 (((uint64_t)(c)[33]) << 32) | \ 1089 (((uint64_t)(c)[34]) << 24) | \ 1090 (((uint64_t)(c)[35]) << 16) | \ 1091 (((uint64_t)(c)[36]) << 8) | \ 1092 (((uint64_t)(c)[37]) << 0)) 1093 1094#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 1095 1096#define ISP2100_RACC_TIMER(c) (c)[40] 1097#define ISP2100_IDELAY_TIMER(c) (c)[41] 1098 1099#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 1100 1101#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 1102 1103#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) 1104#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 1105#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 1106#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 1107#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 1108#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 1109#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 1110 1111#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1112 (((uint64_t)(c)[72]) << 56) | \ 1113 (((uint64_t)(c)[73]) << 48) | \ 1114 (((uint64_t)(c)[74]) << 40) | \ 1115 (((uint64_t)(c)[75]) << 32) | \ 1116 (((uint64_t)(c)[76]) << 24) | \ 1117 (((uint64_t)(c)[77]) << 16) | \ 1118 (((uint64_t)(c)[78]) << 8) | \ 1119 (((uint64_t)(c)[79]) << 0)) 1120 1121#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1122#define ISP2100_RESET_DELAY(c) (c)[81] 1123 1124#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) 1125 1126/* 1127 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 1128 */ 1129#define ISP2400_NVRAM_PORT0_ADDR 0x80 1130#define ISP2400_NVRAM_PORT1_ADDR 0x180 1131#define ISP2400_NVRAM_SIZE 512 1132 1133#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 1134#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 1135#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1136#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) 1137#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 1138 1139#define ISP2400_NVRAM_PORT_NAME(c) (\ 1140 (((uint64_t)(c)[20]) << 56) | \ 1141 (((uint64_t)(c)[21]) << 48) | \ 1142 (((uint64_t)(c)[22]) << 40) | \ 1143 (((uint64_t)(c)[23]) << 32) | \ 1144 (((uint64_t)(c)[24]) << 24) | \ 1145 (((uint64_t)(c)[25]) << 16) | \ 1146 (((uint64_t)(c)[26]) << 8) | \ 1147 (((uint64_t)(c)[27]) << 0)) 1148 1149#define ISP2400_NVRAM_NODE_NAME(c) (\ 1150 (((uint64_t)(c)[28]) << 56) | \ 1151 (((uint64_t)(c)[29]) << 48) | \ 1152 (((uint64_t)(c)[30]) << 40) | \ 1153 (((uint64_t)(c)[31]) << 32) | \ 1154 (((uint64_t)(c)[32]) << 24) | \ 1155 (((uint64_t)(c)[33]) << 16) | \ 1156 (((uint64_t)(c)[34]) << 8) | \ 1157 (((uint64_t)(c)[35]) << 0)) 1158 1159#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 1160#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 1161#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 1162#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 1163 1164#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 1165 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 1166#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 1167 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 1168#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 1169 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 1170 1171/* 1172 * Firmware Crash Dump 1173 * 1174 * QLogic needs specific information format when they look at firmware crashes. 1175 * 1176 * This is incredibly kernel memory consumptive (to say the least), so this 1177 * code is only compiled in when needed. 1178 */ 1179 1180#define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1181 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1182 (352 * sizeof (uint16_t)) + /* RISC registers */ \ 1183 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1184#define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1185 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1186 (464 * sizeof (uint16_t)) + /* RISC registers */ \ 1187 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1188 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1189 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1190/* the larger of the two */ 1191#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1192#endif /* _ISPREG_H */
| 399/* BIU2400_HCCR definitions */ 400 401#define HCCR_2400_CMD_NOP 0x00000000 402#define HCCR_2400_CMD_RESET 0x10000000 403#define HCCR_2400_CMD_CLEAR_RESET 0x20000000 404#define HCCR_2400_CMD_PAUSE 0x30000000 405#define HCCR_2400_CMD_RELEASE 0x40000000 406#define HCCR_2400_CMD_SET_HOST_INT 0x50000000 407#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000 408#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000 409 410#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */ 411#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */ 412#define HCCR_2400_RISC_RESET (1 << 5) /* RO */ 413 414 415/* 416 * Mailbox Block Register Offsets 417 */ 418 419#define INMAILBOX0 (MBOX_BLOCK+0x0) 420#define INMAILBOX1 (MBOX_BLOCK+0x2) 421#define INMAILBOX2 (MBOX_BLOCK+0x4) 422#define INMAILBOX3 (MBOX_BLOCK+0x6) 423#define INMAILBOX4 (MBOX_BLOCK+0x8) 424#define INMAILBOX5 (MBOX_BLOCK+0xA) 425#define INMAILBOX6 (MBOX_BLOCK+0xC) 426#define INMAILBOX7 (MBOX_BLOCK+0xE) 427 428#define OUTMAILBOX0 (MBOX_BLOCK+0x0) 429#define OUTMAILBOX1 (MBOX_BLOCK+0x2) 430#define OUTMAILBOX2 (MBOX_BLOCK+0x4) 431#define OUTMAILBOX3 (MBOX_BLOCK+0x6) 432#define OUTMAILBOX4 (MBOX_BLOCK+0x8) 433#define OUTMAILBOX5 (MBOX_BLOCK+0xA) 434#define OUTMAILBOX6 (MBOX_BLOCK+0xC) 435#define OUTMAILBOX7 (MBOX_BLOCK+0xE) 436 437/* 438 * Strictly speaking, it's 439 * SCSI && 2100 : 8 MBOX registers 440 * 2200: 24 MBOX registers 441 * 2300/2400: 32 MBOX registers 442 */ 443#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1)) 444#define ISP_NMBOX(isp) ((IS_24XX(isp) || IS_23XX(isp))? 32 : (IS_2200(isp) ? 24 : 8)) 445#define ISP_NMBOX_BMASK(isp) \ 446 ((IS_24XX(isp) || IS_23XX(isp))? 0xffffffff : (IS_2200(isp)? 0x00ffffff : 0xff)) 447#define MAX_MAILBOX 32 448/* if timeout == 0, then default timeout is picked */ 449#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */ 450typedef struct { 451 uint16_t param[MAX_MAILBOX]; 452 uint32_t ibits; /* bits to add for register copyin */ 453 uint32_t obits; /* bits to add for register copyout */ 454 uint32_t ibitm; /* bits to mask for register copyin */ 455 uint32_t obitm; /* bits to mask for register copyout */ 456 uint32_t 457 lineno : 16, 458 : 12, 459 logval : 4; 460 uint32_t timeout; 461 const char *func; 462} mbreg_t; 463#define MBSINIT(mbxp, code, loglev, timo) \ 464 ISP_MEMZERO((mbxp), sizeof (mbreg_t)); \ 465 (mbxp)->ibitm = ~0; \ 466 (mbxp)->obitm = ~0; \ 467 (mbxp)->param[0] = code; \ 468 (mbxp)->lineno = __LINE__; \ 469 (mbxp)->func = __func__; \ 470 (mbxp)->logval = loglev; \ 471 (mbxp)->timeout = timo 472 473 474/* 475 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00). 476 * NB: The RISC processor must be paused and the appropriate register 477 * bank selected via BIU2100_CSR bits. 478 */ 479 480#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96) 481#define FPM_SOFT_RESET 0x0100 482 483#define FBM_CMD (BIU_BLOCK + 0xB8) 484#define FBMCMD_FIFO_RESET_ALL 0xA000 485 486 487/* 488 * SXP Block Register Offsets 489 */ 490#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */ 491#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */ 492#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */ 493#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */ 494#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */ 495#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */ 496#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */ 497#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */ 498#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */ 499#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */ 500#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */ 501#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */ 502#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */ 503#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */ 504#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */ 505#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */ 506#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */ 507#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */ 508#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */ 509#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */ 510#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */ 511#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */ 512#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */ 513#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */ 514#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */ 515#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */ 516#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */ 517#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */ 518#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */ 519#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */ 520#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */ 521#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */ 522#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */ 523#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */ 524#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */ 525#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */ 526#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */ 527#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */ 528#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */ 529 530/* for 1080/1280/1240 only */ 531#define SXP_BANK1_SELECT 0x100 532 533 534/* SXP CONF1 REGISTER */ 535#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */ 536#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */ 537#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */ 538#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */ 539#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */ 540 541/* SXP CONF2 REGISTER */ 542#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */ 543#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */ 544#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */ 545#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */ 546#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */ 547#define SXP_CONF2_SELECT 0x0001 /* Enable selection */ 548 549/* SXP INTERRUPT REGISTER */ 550#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */ 551#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */ 552#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */ 553#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */ 554#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */ 555#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */ 556#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */ 557#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */ 558#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */ 559#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */ 560 561 562/* SXP GROSS ERROR REGISTER */ 563#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */ 564#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */ 565#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */ 566#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */ 567#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */ 568#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */ 569#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */ 570 571/* SXP EXCEPTION REGISTER */ 572#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */ 573#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */ 574#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */ 575#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */ 576#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */ 577#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */ 578#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */ 579#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */ 580#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */ 581#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */ 582 583 /* SXP OVERRIDE REGISTER */ 584#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */ 585#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */ 586#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */ 587#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */ 588#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */ 589#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */ 590#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */ 591#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */ 592#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */ 593#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */ 594#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */ 595#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */ 596#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */ 597 598/* SXP COMMANDS */ 599#define SXP_RESET_BUS_CMD 0x300b 600 601/* SXP SCSI ID REGISTER */ 602#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */ 603#define SXP_SELECT_ID 0x000F /* Select id */ 604 605/* SXP DEV CONFIG1 REGISTER */ 606#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */ 607#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */ 608#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */ 609 610 611/* SXP DEV CONFIG2 REGISTER */ 612#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */ 613#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */ 614#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */ 615#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */ 616#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */ 617 618 619/* SXP PHASE POINTER REGISTER */ 620#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */ 621#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */ 622#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */ 623#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */ 624 625 626/* SXP FIFO STATUS REGISTER */ 627#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */ 628#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */ 629#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */ 630#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */ 631 632 633/* SXP CONTROL PINS REGISTER */ 634#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */ 635#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */ 636#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */ 637#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */ 638#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */ 639#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */ 640#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */ 641#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */ 642#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */ 643#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */ 644#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */ 645#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */ 646 647/* 648 * Set the hold time for the SCSI Bus Reset to be 250 ms 649 */ 650#define SXP_SCSI_BUS_RESET_HOLD_TIME 250 651 652/* SXP DIFF PINS REGISTER */ 653#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */ 654#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */ 655#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */ 656#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */ 657#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */ 658#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */ 659 660/* Ultra2 only */ 661#define SXP_PINS_LVD_MODE 0x1000 662#define SXP_PINS_HVD_MODE 0x0800 663#define SXP_PINS_SE_MODE 0x0400 664#define SXP_PINS_MODE_MASK (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE) 665 666/* The above have to be put together with the DIFFM pin to make sense */ 667#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE) 668#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE) 669#define ISP1080_SE_MODE (SXP_PINS_SE_MODE) 670#define ISP1080_MODE_MASK (SXP_PINS_MODE_MASK|SXP_PINS_DIFF_MODE) 671 672/* 673 * RISC and Host Command and Control Block Register Offsets 674 */ 675 676#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */ 677#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */ 678#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */ 679#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */ 680#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */ 681#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */ 682#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */ 683#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */ 684#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */ 685#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */ 686#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */ 687#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */ 688#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */ 689#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */ 690#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */ 691#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */ 692#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */ 693#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */ 694#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */ 695#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */ 696#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */ 697#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */ 698#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */ 699#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */ 700#define RISC_MTR2100 RISC_BLOCK+0x30 701 702#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */ 703#define DUAL_BANK 8 704#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */ 705#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */ 706#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */ 707#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */ 708#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */ 709#define TCR RISC_BLOCK+0x46 /* W : Test Control */ 710#define TMR RISC_BLOCK+0x48 /* W : Test Mode */ 711 712 713/* PROCESSOR STATUS REGISTER */ 714#define RISC_PSR_FORCE_TRUE 0x8000 715#define RISC_PSR_LOOP_COUNT_DONE 0x4000 716#define RISC_PSR_RISC_INT 0x2000 717#define RISC_PSR_TIMER_ROLLOVER 0x1000 718#define RISC_PSR_ALU_OVERFLOW 0x0800 719#define RISC_PSR_ALU_MSB 0x0400 720#define RISC_PSR_ALU_CARRY 0x0200 721#define RISC_PSR_ALU_ZERO 0x0100 722 723#define RISC_PSR_PCI_ULTRA 0x0080 724#define RISC_PSR_SBUS_ULTRA 0x0020 725 726#define RISC_PSR_DMA_INT 0x0010 727#define RISC_PSR_SXP_INT 0x0008 728#define RISC_PSR_HOST_INT 0x0004 729#define RISC_PSR_INT_PENDING 0x0002 730#define RISC_PSR_FORCE_FALSE 0x0001 731 732 733/* Host Command and Control */ 734#define HCCR_CMD_NOP 0x0000 /* NOP */ 735#define HCCR_CMD_RESET 0x1000 /* Reset RISC */ 736#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */ 737#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */ 738#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */ 739#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /* 740 * Disable RISC pause on FPM 741 * parity error. 742 */ 743#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */ 744#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */ 745#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */ 746#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */ 747#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */ 748#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */ 749#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */ 750#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */ 751 752 753#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400 754#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200 755#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100 756#define ISP2100_HCCR_PARITY 0x0001 757 758#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */ 759#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */ 760#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */ 761 762#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */ 763#define HCCR_RESET 0x0040 /* R : reset in progress */ 764#define HCCR_PAUSE 0x0020 /* R : RISC paused */ 765 766#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */ 767 768/* 769 * Defines for Interrupts 770 */ 771#define ISP_INTS_ENABLED(isp) \ 772 ((IS_SCSI(isp))? \ 773 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \ 774 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \ 775 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK))) 776 777#define ISP_ENABLE_INTS(isp) \ 778 (IS_SCSI(isp) ? \ 779 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \ 780 (IS_24XX(isp) ? \ 781 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \ 782 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK)))) 783 784#define ISP_DISABLE_INTS(isp) \ 785 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0) 786 787/* 788 * NVRAM Definitions (PCI cards only) 789 */ 790 791#define ISPBSMX(c, byte, shift, mask) \ 792 (((c)[(byte)] >> (shift)) & (mask)) 793/* 794 * Qlogic 1020/1040 NVRAM is an array of 128 bytes. 795 * 796 * Some portion of the front of this is for general host adapter properties 797 * This is followed by an array of per-target parameters, and is tailed off 798 * with a checksum xor byte at offset 127. For non-byte entities data is 799 * stored in Little Endian order. 800 */ 801 802#define ISP_NVRAM_SIZE 128 803 804#define ISP_NVRAM_VERSION(c) (c)[4] 805#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03) 806#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01) 807#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01) 808#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f) 809#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6] 810#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7] 811#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8] 812#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f) 813#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01) 814#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01) 815#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01) 816#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01) 817#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10] 818#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01) 819#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01) 820#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01) 821#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01) 822#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01) 823#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01) 824#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01) 825#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01) 826#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8)) 827#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8)) 828#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01) 829#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01) 830#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01) 831#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01) 832#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01) 833#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01) 834 835#define ISP_NVRAM_TARGOFF 28 836#define ISP_NVRAM_TARGSIZE 6 837#define _IxT(tgt, tidx) \ 838 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx)) 839#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01) 840#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01) 841#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01) 842#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01) 843#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01) 844#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01) 845#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01) 846#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01) 847#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff) 848#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff) 849#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f) 850#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01) 851#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01) 852 853/* 854 * Qlogic 1080/1240 NVRAM is an array of 256 bytes. 855 * 856 * Some portion of the front of this is for general host adapter properties 857 * This is followed by an array of per-target parameters, and is tailed off 858 * with a checksum xor byte at offset 256. For non-byte entities data is 859 * stored in Little Endian order. 860 */ 861 862#define ISP1080_NVRAM_SIZE 256 863 864#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c) 865 866/* Offset 5 */ 867/* 868 uint8_t bios_configuration_mode :2; 869 uint8_t bios_disable :1; 870 uint8_t selectable_scsi_boot_enable :1; 871 uint8_t cd_rom_boot_enable :1; 872 uint8_t disable_loading_risc_code :1; 873 uint8_t enable_64bit_addressing :1; 874 uint8_t unused_7 :1; 875 */ 876 877/* Offsets 6, 7 */ 878/* 879 uint8_t boot_lun_number :5; 880 uint8_t scsi_bus_number :1; 881 uint8_t unused_6 :1; 882 uint8_t unused_7 :1; 883 uint8_t boot_target_number :4; 884 uint8_t unused_12 :1; 885 uint8_t unused_13 :1; 886 uint8_t unused_14 :1; 887 uint8_t unused_15 :1; 888 */ 889 890#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01) 891 892#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01) 893#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f) 894 895#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01) 896#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03) 897#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03) 898 899#define ISP1080_ISP_PARAMETER(c) \ 900 (((c)[18]) | ((c)[19] << 8)) 901 902#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01) 903#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01) 904 905#define ISP1080_BUS1_OFF 112 906 907#define ISP1080_NVRAM_INITIATOR_ID(c, b) \ 908 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f) 909#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \ 910 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25] 911#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \ 912 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26] 913#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \ 914 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27] 915 916#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \ 917 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f) 918#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \ 919 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01) 920#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \ 921 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01) 922#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \ 923 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \ 924 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8)) 925#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \ 926 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \ 927 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8)) 928 929#define ISP1080_NVRAM_TARGOFF(b) \ 930 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF)) 931#define ISP1080_NVRAM_TARGSIZE 6 932#define _IxT8(tgt, tidx, b) \ 933 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx)) 934 935#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \ 936 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01) 937#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \ 938 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01) 939#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \ 940 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01) 941#define ISP1080_NVRAM_TGT_TQING(c, t, b) \ 942 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01) 943#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \ 944 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01) 945#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \ 946 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01) 947#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \ 948 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01) 949#define ISP1080_NVRAM_TGT_DISC(c, t, b) \ 950 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01) 951#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 952 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff) 953#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 954 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff) 955#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 956 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f) 957#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 958 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01) 959#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \ 960 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01) 961 962#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE 963#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE 964#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD 965#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT 966#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE 967#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE 968#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER 969#define ISP12160_FAST_POST ISP1080_FAST_POST 970#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION 971 972#define ISP12160_NVRAM_INITIATOR_ID \ 973 ISP1080_NVRAM_INITIATOR_ID 974#define ISP12160_NVRAM_BUS_RESET_DELAY \ 975 ISP1080_NVRAM_BUS_RESET_DELAY 976#define ISP12160_NVRAM_BUS_RETRY_COUNT \ 977 ISP1080_NVRAM_BUS_RETRY_COUNT 978#define ISP12160_NVRAM_BUS_RETRY_DELAY \ 979 ISP1080_NVRAM_BUS_RETRY_DELAY 980#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \ 981 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME 982#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \ 983 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION 984#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \ 985 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION 986#define ISP12160_NVRAM_SELECTION_TIMEOUT \ 987 ISP1080_NVRAM_SELECTION_TIMEOUT 988#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \ 989 ISP1080_NVRAM_MAX_QUEUE_DEPTH 990 991 992#define ISP12160_BUS0_OFF 24 993#define ISP12160_BUS1_OFF 136 994 995#define ISP12160_NVRAM_TARGOFF(b) \ 996 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16) 997 998#define ISP12160_NVRAM_TARGSIZE 6 999#define _IxT16(tgt, tidx, b) \ 1000 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx)) 1001 1002#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \ 1003 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01) 1004#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \ 1005 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01) 1006#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \ 1007 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01) 1008#define ISP12160_NVRAM_TGT_TQING(c, t, b) \ 1009 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01) 1010#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \ 1011 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01) 1012#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \ 1013 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01) 1014#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \ 1015 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01) 1016#define ISP12160_NVRAM_TGT_DISC(c, t, b) \ 1017 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01) 1018 1019#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \ 1020 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff) 1021#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \ 1022 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff) 1023 1024#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \ 1025 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f) 1026#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \ 1027 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01) 1028 1029#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \ 1030 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f) 1031#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \ 1032 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03) 1033#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \ 1034 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01) 1035 1036/* 1037 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes. 1038 * 1039 * Some portion of the front of this is for general RISC engine parameters, 1040 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command. 1041 * 1042 * This is followed by some general host adapter parameters, and ends with 1043 * a checksum xor byte at offset 255. For non-byte entities data is stored 1044 * in Little Endian order. 1045 */ 1046#define ISP2100_NVRAM_SIZE 256 1047/* ISP_NVRAM_VERSION is in same overall place */ 1048#define ISP2100_NVRAM_RISCVER(c) (c)[6] 1049#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8)) 1050#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8)) 1051#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8)) 1052#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1053#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16] 1054#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17] 1055 1056#define ISP2100_NVRAM_PORT_NAME(c) (\ 1057 (((uint64_t)(c)[18]) << 56) | \ 1058 (((uint64_t)(c)[19]) << 48) | \ 1059 (((uint64_t)(c)[20]) << 40) | \ 1060 (((uint64_t)(c)[21]) << 32) | \ 1061 (((uint64_t)(c)[22]) << 24) | \ 1062 (((uint64_t)(c)[23]) << 16) | \ 1063 (((uint64_t)(c)[24]) << 8) | \ 1064 (((uint64_t)(c)[25]) << 0)) 1065 1066#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8)) 1067#define ISP2100_NVRAM_TOV(c) ((c)[29]) 1068 1069#define ISP2100_NVRAM_NODE_NAME(c) (\ 1070 (((uint64_t)(c)[30]) << 56) | \ 1071 (((uint64_t)(c)[31]) << 48) | \ 1072 (((uint64_t)(c)[32]) << 40) | \ 1073 (((uint64_t)(c)[33]) << 32) | \ 1074 (((uint64_t)(c)[34]) << 24) | \ 1075 (((uint64_t)(c)[35]) << 16) | \ 1076 (((uint64_t)(c)[36]) << 8) | \ 1077 (((uint64_t)(c)[37]) << 0)) 1078 1079#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8)) 1080 1081#define ISP2100_RACC_TIMER(c) (c)[40] 1082#define ISP2100_IDELAY_TIMER(c) (c)[41] 1083 1084#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8)) 1085 1086#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8)) 1087 1088#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8)) 1089#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01) 1090#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01) 1091#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01) 1092#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01) 1093#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01) 1094#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01) 1095 1096#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\ 1097 (((uint64_t)(c)[72]) << 56) | \ 1098 (((uint64_t)(c)[73]) << 48) | \ 1099 (((uint64_t)(c)[74]) << 40) | \ 1100 (((uint64_t)(c)[75]) << 32) | \ 1101 (((uint64_t)(c)[76]) << 24) | \ 1102 (((uint64_t)(c)[77]) << 16) | \ 1103 (((uint64_t)(c)[78]) << 8) | \ 1104 (((uint64_t)(c)[79]) << 0)) 1105 1106#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80] 1107#define ISP2100_RESET_DELAY(c) (c)[81] 1108 1109#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8)) 1110 1111/* 1112 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum. 1113 */ 1114#define ISP2400_NVRAM_PORT0_ADDR 0x80 1115#define ISP2400_NVRAM_PORT1_ADDR 0x180 1116#define ISP2400_NVRAM_SIZE 512 1117 1118#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8)) 1119#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8)) 1120#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8)) 1121#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8)) 1122#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8)) 1123 1124#define ISP2400_NVRAM_PORT_NAME(c) (\ 1125 (((uint64_t)(c)[20]) << 56) | \ 1126 (((uint64_t)(c)[21]) << 48) | \ 1127 (((uint64_t)(c)[22]) << 40) | \ 1128 (((uint64_t)(c)[23]) << 32) | \ 1129 (((uint64_t)(c)[24]) << 24) | \ 1130 (((uint64_t)(c)[25]) << 16) | \ 1131 (((uint64_t)(c)[26]) << 8) | \ 1132 (((uint64_t)(c)[27]) << 0)) 1133 1134#define ISP2400_NVRAM_NODE_NAME(c) (\ 1135 (((uint64_t)(c)[28]) << 56) | \ 1136 (((uint64_t)(c)[29]) << 48) | \ 1137 (((uint64_t)(c)[30]) << 40) | \ 1138 (((uint64_t)(c)[31]) << 32) | \ 1139 (((uint64_t)(c)[32]) << 24) | \ 1140 (((uint64_t)(c)[33]) << 16) | \ 1141 (((uint64_t)(c)[34]) << 8) | \ 1142 (((uint64_t)(c)[35]) << 0)) 1143 1144#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8)) 1145#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8)) 1146#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8)) 1147#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8)) 1148 1149#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \ 1150 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24)) 1151#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \ 1152 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24)) 1153#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \ 1154 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24)) 1155 1156/* 1157 * Firmware Crash Dump 1158 * 1159 * QLogic needs specific information format when they look at firmware crashes. 1160 * 1161 * This is incredibly kernel memory consumptive (to say the least), so this 1162 * code is only compiled in when needed. 1163 */ 1164 1165#define QLA2200_RISC_IMAGE_DUMP_SIZE \ 1166 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1167 (352 * sizeof (uint16_t)) + /* RISC registers */ \ 1168 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */ 1169#define QLA2300_RISC_IMAGE_DUMP_SIZE \ 1170 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \ 1171 (464 * sizeof (uint16_t)) + /* RISC registers */ \ 1172 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \ 1173 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \ 1174 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */ 1175/* the larger of the two */ 1176#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE 1177#endif /* _ISPREG_H */
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