Deleted Added
full compact
ispreg.h (163899) ispreg.h (166929)
1/* $FreeBSD: head/sys/dev/isp/ispreg.h 163899 2006-11-02 03:21:32Z mjacob $ */
1/* $FreeBSD: head/sys/dev/isp/ispreg.h 166929 2007-02-23 21:59:21Z mjacob $ */
2/*-
3 * Machine Independent (well, as best as possible) register
4 * definitions for Qlogic ISP SCSI adapters.
5 *
6 * Copyright (c) 1997-2006 by Matthew Jacob
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice immediately at the beginning of the file, without modification,
14 * this list of conditions, and the following disclaimer.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30#ifndef _ISPREG_H
31#define _ISPREG_H
32
33/*
34 * Hardware definitions for the Qlogic ISP registers.
35 */
36
37/*
38 * This defines types of access to various registers.
39 *
40 * R: Read Only
41 * W: Write Only
42 * RW: Read/Write
43 *
44 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only
45 * if RISC processor in ISP is paused.
46 */
47
48/*
49 * Offsets for various register blocks.
50 *
51 * Sad but true, different architectures have different offsets.
52 *
53 * Don't be alarmed if none of this makes sense. The original register
54 * layout set some defines in a certain pattern. Everything else has been
55 * grafted on since. For example, the ISP1080 manual will state that DMA
56 * registers start at 0x80 from the base of the register address space.
57 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
58 * to start at offset 0x60 because the DMA registers are all defined to
59 * be DMA_BLOCK+0x20 and so on. Clear?
60 */
61
62#define BIU_REGS_OFF 0x00
63
64#define PCI_MBOX_REGS_OFF 0x70
65#define PCI_MBOX_REGS2100_OFF 0x10
66#define PCI_MBOX_REGS2300_OFF 0x40
67#define PCI_MBOX_REGS2400_OFF 0x80
68#define SBUS_MBOX_REGS_OFF 0x80
69
70#define PCI_SXP_REGS_OFF 0x80
71#define SBUS_SXP_REGS_OFF 0x200
72
73#define PCI_RISC_REGS_OFF 0x80
74#define SBUS_RISC_REGS_OFF 0x400
75
76/* Bless me! Chip designers have putzed it again! */
77#define ISP1080_DMA_REGS_OFF 0x60
78#define DMA_REGS_OFF 0x00 /* same as BIU block */
79
80#define SBUS_REGSIZE 0x450
81#define PCI_REGSIZE 0x100
82
83/*
84 * NB: The *_BLOCK definitions have no specific hardware meaning.
85 * They serve simply to note to the MD layer which block of
86 * registers offsets are being accessed.
87 */
88#define _NREG_BLKS 5
89#define _BLK_REG_SHFT 13
90#define _BLK_REG_MASK (7 << _BLK_REG_SHFT)
91#define BIU_BLOCK (0 << _BLK_REG_SHFT)
92#define MBOX_BLOCK (1 << _BLK_REG_SHFT)
93#define SXP_BLOCK (2 << _BLK_REG_SHFT)
94#define RISC_BLOCK (3 << _BLK_REG_SHFT)
95#define DMA_BLOCK (4 << _BLK_REG_SHFT)
96
97/*
98 * Bus Interface Block Register Offsets
99 */
100
101#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
102#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
103#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
104#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
105#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
106#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
107#define BIU2100_CSR (BIU_BLOCK+0x6)
108#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
109#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
110#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
111#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
112/*
113 * These are specific to the 2300.
114 */
115#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */
116#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */
117#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */
118#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */
119
120#define BIU_R2HSTSLO (BIU_BLOCK+0x18)
121#define BIU_R2HSTSHI (BIU_BLOCK+0x1A)
122
123#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
124#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
125#define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */
126#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
127#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
128#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
129#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
130#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
131#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
132#define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */
133#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
134#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
135#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
136
137/* fifo command stuff- mostly for SPI */
138#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
139#define RDMA2100_CONTROL DFIFO_COMMAND
140#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
141
142/*
143 * Putzed DMA register layouts.
144 */
145#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
146#define CDMA2100_CONTROL CDMA_CONF
147#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
148#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
149#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
150#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
151#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
152#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
153#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
154#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
155
156#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
157#define TDMA2100_CONTROL DDMA_CONF
158#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
159#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
160#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
161#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
162#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
163#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
164#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
165/* these are for the 1040A cards */
166#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
167#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
168
169
170/*
171 * Bus Interface Block Register Definitions
172 */
173/* BUS CONFIGURATION REGISTER #0 */
174#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */
175/* BUS CONFIGURATION REGISTER #1 */
176
177#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */
178#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */
179
180#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */
181#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */
182#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */
183#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */
184#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */
185#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */
186#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */
187#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */
188#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */
189#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
190#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
191
192#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
193#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
194#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
195
196/* ISP2100 Bus Control/Status Register */
197
198#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */
199#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */
200#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */
201#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */
202#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */
203#define BIU2100_NVRAM_OFFSET (1 << 14)
204#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */
205#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */
206#define BIU2100_SOFT_RESET 0x01
207/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */
208
209
210/* BUS CONTROL REGISTER */
211#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */
212#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */
213#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */
214#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */
215#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */
216#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */
217
218#define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)
219
220#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000
221#define BIU2100_ICR_ENA_FPM_INT 0x0020
222#define BIU2100_ICR_ENA_FB_INT 0x0010
223#define BIU2100_ICR_ENA_RISC_INT 0x0008
224#define BIU2100_ICR_ENA_CDMA_INT 0x0004
225#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002
226#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
227#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
228
229#define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)
230
231/* BUS STATUS REGISTER */
232#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */
233#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */
234#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */
235#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */
236#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */
237
238#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
239#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
240#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
241#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
242#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
243#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
244#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
245
246#define INT_PENDING(isp, isr) \
247 IS_FC(isp)? \
248 (IS_24XX(isp)? (isr & BIU2400_ISR_RISC_INT) : (isr & BIU2100_ISR_RISC_INT)) :\
249 (isr & BIU_ISR_RISC_INT)
250
251#define INT_PENDING_MASK(isp) \
252 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \
253 (BIU_ISR_RISC_INT))
254
255/* BUS SEMAPHORE REGISTER */
256#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
257#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
258
259/* NVRAM SEMAPHORE REGISTER */
260#define BIU_NVRAM_CLOCK 0x0001
261#define BIU_NVRAM_SELECT 0x0002
262#define BIU_NVRAM_DATAOUT 0x0004
263#define BIU_NVRAM_DATAIN 0x0008
264#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */
265#define ISP_NVRAM_READ 6
266
267/* COMNMAND && DATA DMA CONFIGURATION REGISTER */
268#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */
269#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */
270#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */
271#define DMA_DMA_DIRECTION 0x0001 /*
272 * Set DMA direction:
273 * 0 - DMA FIFO to host
274 * 1 - Host to DMA FIFO
275 */
276
277/* COMMAND && DATA DMA CONTROL REGISTER */
278#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */
279#define DMA_CNTRL_CLEAR_CHAN 0x0008 /*
280 * Clear FIFO and DMA Channel,
281 * reset DMA registers
282 */
283#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */
284#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */
285#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */
286
287/*
288 * Variants of same for 2100
289 */
290#define DMA_CNTRL2100_CLEAR_CHAN 0x0004
291#define DMA_CNTRL2100_RESET_INT 0x0002
292
293
294
295/* DMA STATUS REGISTER */
296#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */
297#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */
298#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */
299#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */
300#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */
301#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */
302
303#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */
304#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */
305#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */
306#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */
307#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */
308#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */
309#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */
310#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */
311#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */
312#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */
313#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */
314
315/* DMA Status Register, pipeline status bits */
316#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */
317#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */
318#define DMA_SBUS_PIPE_STAGE1 0x0040 /*
319 * Pipeline stage 1 Loaded,
320 * stage 2 empty
321 */
322#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */
323#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */
324#define DMA_PCI_PIPE_STAGE1 0x0001 /*
325 * Pipeline stage 1 Loaded,
326 * stage 2 empty
327 */
328#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */
329
330/* DMA Status Register, channel status bits */
331#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */
332#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */
333#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */
334#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */
335#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */
336#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */
337#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */
338
339
340/* DMA FIFO STATUS REGISTER */
341#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */
342#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */
343#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */
344#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */
345
346/*
347 * 2400 Interface Offsets and Register Definitions
348 *
349 * The 2400 looks quite different in terms of registers from other QLogic cards.
350 * It is getting to be a genuine pain and challenge to keep the same model
351 * for all.
352 */
353#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00)
354#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04)
355#define BIU2400_CSR (BIU_BLOCK+0x08)
356#define BIU2400_ICR (BIU_BLOCK+0x0C)
357#define BIU2400_ISR (BIU_BLOCK+0x10)
358
359#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
360#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
361#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
362#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
363#define BIU2400_PRI_RQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
364#define BIU2400_PRI_RSPINP (BIU_BLOCK+0x30) /* Priority Request Q Out */
365
366#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
367#define BIU2400_ATIO_REQINP (BIU_BLOCK+0x40) /* ATIO Queue Out */
368
369#define BIU2400_R2HSTSLO (BIU_BLOCK+0x44)
370#define BIU2400_R2HSTSHI (BIU_BLOCK+0x46)
371
372#define BIU2400_HCCR (BIU_BLOCK+0x48)
373#define BIU2400_GPIOD (BIU_BLOCK+0x4C)
374#define BIU2400_GPIOE (BIU_BLOCK+0x50)
375#define BIU2400_HSEMA (BIU_BLOCK+0x58)
376
377/* BIU2400_FLASH_ADDR definitions */
378#define BIU2400_FLASH_DFLAG (1 << 30)
379
380/* BIU2400_CSR definitions */
381#define BIU2400_NVERR (1 << 18)
382#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */
383#define BIU2400_DMA_STOP (1 << 16)
384#define BIU2400_FUNCTION (1 << 15) /* RO */
385#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
386#define BIU2400_CSR_64BIT (1 << 2) /* RO */
387#define BIU2400_FLASH_ENABLE (1 << 1)
388#define BIU2400_SOFT_RESET (1 << 0)
389
390/* BIU2400_ICR definitions */
391#define BIU2400_ICR_ENA_RISC_INT 0x8
392#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
393
394/* BIU2400_ISR definitions */
395#define BIU2400_ISR_RISC_INT 0x8
396
397#define BIU2400_R2HST_INTR BIU_R2HST_INTR
398#define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED
399#define BIU2400_R2HST_ISTAT_MASK 0x1f
400/* interrupt status meanings */
401#define ISP2400R2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
402#define ISP2400R2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
403#define ISP2400R2HST_MBX_OK 0x10 /* mailbox cmd done ok */
404#define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
405#define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */
406#define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
407#define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */
408#define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */
409
410/* BIU2400_HCCR definitions */
411
2/*-
3 * Machine Independent (well, as best as possible) register
4 * definitions for Qlogic ISP SCSI adapters.
5 *
6 * Copyright (c) 1997-2006 by Matthew Jacob
7 * All rights reserved.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice immediately at the beginning of the file, without modification,
14 * this list of conditions, and the following disclaimer.
15 * 2. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30#ifndef _ISPREG_H
31#define _ISPREG_H
32
33/*
34 * Hardware definitions for the Qlogic ISP registers.
35 */
36
37/*
38 * This defines types of access to various registers.
39 *
40 * R: Read Only
41 * W: Write Only
42 * RW: Read/Write
43 *
44 * R*, W*, RW*: Read Only, Write Only, Read/Write, but only
45 * if RISC processor in ISP is paused.
46 */
47
48/*
49 * Offsets for various register blocks.
50 *
51 * Sad but true, different architectures have different offsets.
52 *
53 * Don't be alarmed if none of this makes sense. The original register
54 * layout set some defines in a certain pattern. Everything else has been
55 * grafted on since. For example, the ISP1080 manual will state that DMA
56 * registers start at 0x80 from the base of the register address space.
57 * That's true, but for our purposes, we define DMA_REGS_OFF for the 1080
58 * to start at offset 0x60 because the DMA registers are all defined to
59 * be DMA_BLOCK+0x20 and so on. Clear?
60 */
61
62#define BIU_REGS_OFF 0x00
63
64#define PCI_MBOX_REGS_OFF 0x70
65#define PCI_MBOX_REGS2100_OFF 0x10
66#define PCI_MBOX_REGS2300_OFF 0x40
67#define PCI_MBOX_REGS2400_OFF 0x80
68#define SBUS_MBOX_REGS_OFF 0x80
69
70#define PCI_SXP_REGS_OFF 0x80
71#define SBUS_SXP_REGS_OFF 0x200
72
73#define PCI_RISC_REGS_OFF 0x80
74#define SBUS_RISC_REGS_OFF 0x400
75
76/* Bless me! Chip designers have putzed it again! */
77#define ISP1080_DMA_REGS_OFF 0x60
78#define DMA_REGS_OFF 0x00 /* same as BIU block */
79
80#define SBUS_REGSIZE 0x450
81#define PCI_REGSIZE 0x100
82
83/*
84 * NB: The *_BLOCK definitions have no specific hardware meaning.
85 * They serve simply to note to the MD layer which block of
86 * registers offsets are being accessed.
87 */
88#define _NREG_BLKS 5
89#define _BLK_REG_SHFT 13
90#define _BLK_REG_MASK (7 << _BLK_REG_SHFT)
91#define BIU_BLOCK (0 << _BLK_REG_SHFT)
92#define MBOX_BLOCK (1 << _BLK_REG_SHFT)
93#define SXP_BLOCK (2 << _BLK_REG_SHFT)
94#define RISC_BLOCK (3 << _BLK_REG_SHFT)
95#define DMA_BLOCK (4 << _BLK_REG_SHFT)
96
97/*
98 * Bus Interface Block Register Offsets
99 */
100
101#define BIU_ID_LO (BIU_BLOCK+0x0) /* R : Bus ID, Low */
102#define BIU2100_FLASH_ADDR (BIU_BLOCK+0x0)
103#define BIU_ID_HI (BIU_BLOCK+0x2) /* R : Bus ID, High */
104#define BIU2100_FLASH_DATA (BIU_BLOCK+0x2)
105#define BIU_CONF0 (BIU_BLOCK+0x4) /* R : Bus Configuration #0 */
106#define BIU_CONF1 (BIU_BLOCK+0x6) /* R : Bus Configuration #1 */
107#define BIU2100_CSR (BIU_BLOCK+0x6)
108#define BIU_ICR (BIU_BLOCK+0x8) /* RW : Bus Interface Ctrl */
109#define BIU_ISR (BIU_BLOCK+0xA) /* R : Bus Interface Status */
110#define BIU_SEMA (BIU_BLOCK+0xC) /* RW : Bus Semaphore */
111#define BIU_NVRAM (BIU_BLOCK+0xE) /* RW : Bus NVRAM */
112/*
113 * These are specific to the 2300.
114 */
115#define BIU_REQINP (BIU_BLOCK+0x10) /* Request Queue In */
116#define BIU_REQOUTP (BIU_BLOCK+0x12) /* Request Queue Out */
117#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */
118#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */
119
120#define BIU_R2HSTSLO (BIU_BLOCK+0x18)
121#define BIU_R2HSTSHI (BIU_BLOCK+0x1A)
122
123#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
124#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
125#define BIU_R2HST_ISTAT_MASK 0x3f /* intr information && status */
126#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
127#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
128#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
129#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
130#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
131#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
132#define ISPR2HST_RQST_UPDATE 0x14 /* Resquest Queue Update */
133#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
134#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
135#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
136
137/* fifo command stuff- mostly for SPI */
138#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
139#define RDMA2100_CONTROL DFIFO_COMMAND
140#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
141
142/*
143 * Putzed DMA register layouts.
144 */
145#define CDMA_CONF (DMA_BLOCK+0x20) /* RW*: DMA Configuration */
146#define CDMA2100_CONTROL CDMA_CONF
147#define CDMA_CONTROL (DMA_BLOCK+0x22) /* RW*: DMA Control */
148#define CDMA_STATUS (DMA_BLOCK+0x24) /* R : DMA Status */
149#define CDMA_FIFO_STS (DMA_BLOCK+0x26) /* R : DMA FIFO Status */
150#define CDMA_COUNT (DMA_BLOCK+0x28) /* RW*: DMA Transfer Count */
151#define CDMA_ADDR0 (DMA_BLOCK+0x2C) /* RW*: DMA Address, Word 0 */
152#define CDMA_ADDR1 (DMA_BLOCK+0x2E) /* RW*: DMA Address, Word 1 */
153#define CDMA_ADDR2 (DMA_BLOCK+0x30) /* RW*: DMA Address, Word 2 */
154#define CDMA_ADDR3 (DMA_BLOCK+0x32) /* RW*: DMA Address, Word 3 */
155
156#define DDMA_CONF (DMA_BLOCK+0x40) /* RW*: DMA Configuration */
157#define TDMA2100_CONTROL DDMA_CONF
158#define DDMA_CONTROL (DMA_BLOCK+0x42) /* RW*: DMA Control */
159#define DDMA_STATUS (DMA_BLOCK+0x44) /* R : DMA Status */
160#define DDMA_FIFO_STS (DMA_BLOCK+0x46) /* R : DMA FIFO Status */
161#define DDMA_COUNT_LO (DMA_BLOCK+0x48) /* RW*: DMA Xfer Count, Low */
162#define DDMA_COUNT_HI (DMA_BLOCK+0x4A) /* RW*: DMA Xfer Count, High */
163#define DDMA_ADDR0 (DMA_BLOCK+0x4C) /* RW*: DMA Address, Word 0 */
164#define DDMA_ADDR1 (DMA_BLOCK+0x4E) /* RW*: DMA Address, Word 1 */
165/* these are for the 1040A cards */
166#define DDMA_ADDR2 (DMA_BLOCK+0x50) /* RW*: DMA Address, Word 2 */
167#define DDMA_ADDR3 (DMA_BLOCK+0x52) /* RW*: DMA Address, Word 3 */
168
169
170/*
171 * Bus Interface Block Register Definitions
172 */
173/* BUS CONFIGURATION REGISTER #0 */
174#define BIU_CONF0_HW_MASK 0x000F /* Hardware revision mask */
175/* BUS CONFIGURATION REGISTER #1 */
176
177#define BIU_SBUS_CONF1_PARITY 0x0100 /* Enable parity checking */
178#define BIU_SBUS_CONF1_FCODE_MASK 0x00F0 /* Fcode cycle mask */
179
180#define BIU_PCI_CONF1_FIFO_128 0x0040 /* 128 bytes FIFO threshold */
181#define BIU_PCI_CONF1_FIFO_64 0x0030 /* 64 bytes FIFO threshold */
182#define BIU_PCI_CONF1_FIFO_32 0x0020 /* 32 bytes FIFO threshold */
183#define BIU_PCI_CONF1_FIFO_16 0x0010 /* 16 bytes FIFO threshold */
184#define BIU_BURST_ENABLE 0x0004 /* Global enable Bus bursts */
185#define BIU_SBUS_CONF1_FIFO_64 0x0003 /* 64 bytes FIFO threshold */
186#define BIU_SBUS_CONF1_FIFO_32 0x0002 /* 32 bytes FIFO threshold */
187#define BIU_SBUS_CONF1_FIFO_16 0x0001 /* 16 bytes FIFO threshold */
188#define BIU_SBUS_CONF1_FIFO_8 0x0000 /* 8 bytes FIFO threshold */
189#define BIU_SBUS_CONF1_BURST8 0x0008 /* Enable 8-byte bursts */
190#define BIU_PCI_CONF1_SXP 0x0008 /* SXP register select */
191
192#define BIU_PCI1080_CONF1_SXP0 0x0100 /* SXP bank #1 select */
193#define BIU_PCI1080_CONF1_SXP1 0x0200 /* SXP bank #2 select */
194#define BIU_PCI1080_CONF1_DMA 0x0300 /* DMA bank select */
195
196/* ISP2100 Bus Control/Status Register */
197
198#define BIU2100_ICSR_REGBSEL 0x30 /* RW: register bank select */
199#define BIU2100_RISC_REGS (0 << 4) /* RISC Regs */
200#define BIU2100_FB_REGS (1 << 4) /* FrameBuffer Regs */
201#define BIU2100_FPM0_REGS (2 << 4) /* FPM 0 Regs */
202#define BIU2100_FPM1_REGS (3 << 4) /* FPM 1 Regs */
203#define BIU2100_NVRAM_OFFSET (1 << 14)
204#define BIU2100_FLASH_UPPER_64K 0x04 /* RW: Upper 64K Bank Select */
205#define BIU2100_FLASH_ENABLE 0x02 /* RW: Enable Flash RAM */
206#define BIU2100_SOFT_RESET 0x01
207/* SOFT RESET FOR ISP2100 is same bit, but in this register, not ICR */
208
209
210/* BUS CONTROL REGISTER */
211#define BIU_ICR_ENABLE_DMA_INT 0x0020 /* Enable DMA interrupts */
212#define BIU_ICR_ENABLE_CDMA_INT 0x0010 /* Enable CDMA interrupts */
213#define BIU_ICR_ENABLE_SXP_INT 0x0008 /* Enable SXP interrupts */
214#define BIU_ICR_ENABLE_RISC_INT 0x0004 /* Enable Risc interrupts */
215#define BIU_ICR_ENABLE_ALL_INTS 0x0002 /* Global enable all inter */
216#define BIU_ICR_SOFT_RESET 0x0001 /* Soft Reset of ISP */
217
218#define BIU_IMASK (BIU_ICR_ENABLE_RISC_INT|BIU_ICR_ENABLE_ALL_INTS)
219
220#define BIU2100_ICR_ENABLE_ALL_INTS 0x8000
221#define BIU2100_ICR_ENA_FPM_INT 0x0020
222#define BIU2100_ICR_ENA_FB_INT 0x0010
223#define BIU2100_ICR_ENA_RISC_INT 0x0008
224#define BIU2100_ICR_ENA_CDMA_INT 0x0004
225#define BIU2100_ICR_ENABLE_RXDMA_INT 0x0002
226#define BIU2100_ICR_ENABLE_TXDMA_INT 0x0001
227#define BIU2100_ICR_DISABLE_ALL_INTS 0x0000
228
229#define BIU2100_IMASK (BIU2100_ICR_ENA_RISC_INT|BIU2100_ICR_ENABLE_ALL_INTS)
230
231/* BUS STATUS REGISTER */
232#define BIU_ISR_DMA_INT 0x0020 /* DMA interrupt pending */
233#define BIU_ISR_CDMA_INT 0x0010 /* CDMA interrupt pending */
234#define BIU_ISR_SXP_INT 0x0008 /* SXP interrupt pending */
235#define BIU_ISR_RISC_INT 0x0004 /* Risc interrupt pending */
236#define BIU_ISR_IPEND 0x0002 /* Global interrupt pending */
237
238#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
239#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
240#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
241#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
242#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
243#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
244#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
245
246#define INT_PENDING(isp, isr) \
247 IS_FC(isp)? \
248 (IS_24XX(isp)? (isr & BIU2400_ISR_RISC_INT) : (isr & BIU2100_ISR_RISC_INT)) :\
249 (isr & BIU_ISR_RISC_INT)
250
251#define INT_PENDING_MASK(isp) \
252 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \
253 (BIU_ISR_RISC_INT))
254
255/* BUS SEMAPHORE REGISTER */
256#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
257#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
258
259/* NVRAM SEMAPHORE REGISTER */
260#define BIU_NVRAM_CLOCK 0x0001
261#define BIU_NVRAM_SELECT 0x0002
262#define BIU_NVRAM_DATAOUT 0x0004
263#define BIU_NVRAM_DATAIN 0x0008
264#define BIU_NVRAM_BUSY 0x0080 /* 2322/24xx only */
265#define ISP_NVRAM_READ 6
266
267/* COMNMAND && DATA DMA CONFIGURATION REGISTER */
268#define DMA_ENABLE_SXP_DMA 0x0008 /* Enable SXP to DMA Data */
269#define DMA_ENABLE_INTS 0x0004 /* Enable interrupts to RISC */
270#define DMA_ENABLE_BURST 0x0002 /* Enable Bus burst trans */
271#define DMA_DMA_DIRECTION 0x0001 /*
272 * Set DMA direction:
273 * 0 - DMA FIFO to host
274 * 1 - Host to DMA FIFO
275 */
276
277/* COMMAND && DATA DMA CONTROL REGISTER */
278#define DMA_CNTRL_SUSPEND_CHAN 0x0010 /* Suspend DMA transfer */
279#define DMA_CNTRL_CLEAR_CHAN 0x0008 /*
280 * Clear FIFO and DMA Channel,
281 * reset DMA registers
282 */
283#define DMA_CNTRL_CLEAR_FIFO 0x0004 /* Clear DMA FIFO */
284#define DMA_CNTRL_RESET_INT 0x0002 /* Clear DMA interrupt */
285#define DMA_CNTRL_STROBE 0x0001 /* Start DMA transfer */
286
287/*
288 * Variants of same for 2100
289 */
290#define DMA_CNTRL2100_CLEAR_CHAN 0x0004
291#define DMA_CNTRL2100_RESET_INT 0x0002
292
293
294
295/* DMA STATUS REGISTER */
296#define DMA_SBUS_STATUS_PIPE_MASK 0x00C0 /* DMA Pipeline status mask */
297#define DMA_SBUS_STATUS_CHAN_MASK 0x0030 /* Channel status mask */
298#define DMA_SBUS_STATUS_BUS_PARITY 0x0008 /* Parity Error on bus */
299#define DMA_SBUS_STATUS_BUS_ERR 0x0004 /* Error Detected on bus */
300#define DMA_SBUS_STATUS_TERM_COUNT 0x0002 /* DMA Transfer Completed */
301#define DMA_SBUS_STATUS_INTERRUPT 0x0001 /* Enable DMA channel inter */
302
303#define DMA_PCI_STATUS_INTERRUPT 0x8000 /* Enable DMA channel inter */
304#define DMA_PCI_STATUS_RETRY_STAT 0x4000 /* Retry status */
305#define DMA_PCI_STATUS_CHAN_MASK 0x3000 /* Channel status mask */
306#define DMA_PCI_STATUS_FIFO_OVR 0x0100 /* DMA FIFO overrun cond */
307#define DMA_PCI_STATUS_FIFO_UDR 0x0080 /* DMA FIFO underrun cond */
308#define DMA_PCI_STATUS_BUS_ERR 0x0040 /* Error Detected on bus */
309#define DMA_PCI_STATUS_BUS_PARITY 0x0020 /* Parity Error on bus */
310#define DMA_PCI_STATUS_CLR_PEND 0x0010 /* DMA clear pending */
311#define DMA_PCI_STATUS_TERM_COUNT 0x0008 /* DMA Transfer Completed */
312#define DMA_PCI_STATUS_DMA_SUSP 0x0004 /* DMA suspended */
313#define DMA_PCI_STATUS_PIPE_MASK 0x0003 /* DMA Pipeline status mask */
314
315/* DMA Status Register, pipeline status bits */
316#define DMA_SBUS_PIPE_FULL 0x00C0 /* Both pipeline stages full */
317#define DMA_SBUS_PIPE_OVERRUN 0x0080 /* Pipeline overrun */
318#define DMA_SBUS_PIPE_STAGE1 0x0040 /*
319 * Pipeline stage 1 Loaded,
320 * stage 2 empty
321 */
322#define DMA_PCI_PIPE_FULL 0x0003 /* Both pipeline stages full */
323#define DMA_PCI_PIPE_OVERRUN 0x0002 /* Pipeline overrun */
324#define DMA_PCI_PIPE_STAGE1 0x0001 /*
325 * Pipeline stage 1 Loaded,
326 * stage 2 empty
327 */
328#define DMA_PIPE_EMPTY 0x0000 /* All pipeline stages empty */
329
330/* DMA Status Register, channel status bits */
331#define DMA_SBUS_CHAN_SUSPEND 0x0030 /* Channel error or suspended */
332#define DMA_SBUS_CHAN_TRANSFER 0x0020 /* Chan transfer in progress */
333#define DMA_SBUS_CHAN_ACTIVE 0x0010 /* Chan trans to host active */
334#define DMA_PCI_CHAN_TRANSFER 0x3000 /* Chan transfer in progress */
335#define DMA_PCI_CHAN_SUSPEND 0x2000 /* Channel error or suspended */
336#define DMA_PCI_CHAN_ACTIVE 0x1000 /* Chan trans to host active */
337#define ISP_DMA_CHAN_IDLE 0x0000 /* Chan idle (normal comp) */
338
339
340/* DMA FIFO STATUS REGISTER */
341#define DMA_FIFO_STATUS_OVERRUN 0x0200 /* FIFO Overrun Condition */
342#define DMA_FIFO_STATUS_UNDERRUN 0x0100 /* FIFO Underrun Condition */
343#define DMA_FIFO_SBUS_COUNT_MASK 0x007F /* FIFO Byte count mask */
344#define DMA_FIFO_PCI_COUNT_MASK 0x00FF /* FIFO Byte count mask */
345
346/*
347 * 2400 Interface Offsets and Register Definitions
348 *
349 * The 2400 looks quite different in terms of registers from other QLogic cards.
350 * It is getting to be a genuine pain and challenge to keep the same model
351 * for all.
352 */
353#define BIU2400_FLASH_ADDR (BIU_BLOCK+0x00)
354#define BIU2400_FLASH_DATA (BIU_BLOCK+0x04)
355#define BIU2400_CSR (BIU_BLOCK+0x08)
356#define BIU2400_ICR (BIU_BLOCK+0x0C)
357#define BIU2400_ISR (BIU_BLOCK+0x10)
358
359#define BIU2400_REQINP (BIU_BLOCK+0x1C) /* Request Queue In */
360#define BIU2400_REQOUTP (BIU_BLOCK+0x20) /* Request Queue Out */
361#define BIU2400_RSPINP (BIU_BLOCK+0x24) /* Response Queue In */
362#define BIU2400_RSPOUTP (BIU_BLOCK+0x28) /* Response Queue Out */
363#define BIU2400_PRI_RQINP (BIU_BLOCK+0x2C) /* Priority Request Q In */
364#define BIU2400_PRI_RSPINP (BIU_BLOCK+0x30) /* Priority Request Q Out */
365
366#define BIU2400_ATIO_RSPINP (BIU_BLOCK+0x3C) /* ATIO Queue In */
367#define BIU2400_ATIO_REQINP (BIU_BLOCK+0x40) /* ATIO Queue Out */
368
369#define BIU2400_R2HSTSLO (BIU_BLOCK+0x44)
370#define BIU2400_R2HSTSHI (BIU_BLOCK+0x46)
371
372#define BIU2400_HCCR (BIU_BLOCK+0x48)
373#define BIU2400_GPIOD (BIU_BLOCK+0x4C)
374#define BIU2400_GPIOE (BIU_BLOCK+0x50)
375#define BIU2400_HSEMA (BIU_BLOCK+0x58)
376
377/* BIU2400_FLASH_ADDR definitions */
378#define BIU2400_FLASH_DFLAG (1 << 30)
379
380/* BIU2400_CSR definitions */
381#define BIU2400_NVERR (1 << 18)
382#define BIU2400_DMA_ACTIVE (1 << 17) /* RO */
383#define BIU2400_DMA_STOP (1 << 16)
384#define BIU2400_FUNCTION (1 << 15) /* RO */
385#define BIU2400_PCIX_MODE(x) (((x) >> 8) & 0xf) /* RO */
386#define BIU2400_CSR_64BIT (1 << 2) /* RO */
387#define BIU2400_FLASH_ENABLE (1 << 1)
388#define BIU2400_SOFT_RESET (1 << 0)
389
390/* BIU2400_ICR definitions */
391#define BIU2400_ICR_ENA_RISC_INT 0x8
392#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
393
394/* BIU2400_ISR definitions */
395#define BIU2400_ISR_RISC_INT 0x8
396
397#define BIU2400_R2HST_INTR BIU_R2HST_INTR
398#define BIU2400_R2HST_PAUSED BIU_R2HST_PAUSED
399#define BIU2400_R2HST_ISTAT_MASK 0x1f
400/* interrupt status meanings */
401#define ISP2400R2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
402#define ISP2400R2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
403#define ISP2400R2HST_MBX_OK 0x10 /* mailbox cmd done ok */
404#define ISP2400R2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
405#define ISP2400R2HST_ASYNC_EVENT 0x12 /* Async Event */
406#define ISP2400R2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
407#define ISP2400R2HST_ATIO_RSPQ_UPDATE 0x1C /* ATIO Response Queue Update */
408#define ISP2400R2HST_ATIO_RQST_UPDATE 0x1D /* ATIO Request Queue Update */
409
410/* BIU2400_HCCR definitions */
411
412#define HCCR_2400_CMD_NOP (0x0 << 28)
413#define HCCR_2400_CMD_RESET (0x1 << 28)
414#define HCCR_2400_CMD_CLEAR_RESET (0x2 << 28)
415#define HCCR_2400_CMD_PAUSE (0x3 << 28)
416#define HCCR_2400_CMD_RELEASE (0x4 << 28)
417#define HCCR_2400_CMD_SET_HOST_INT (0x5 << 28)
418#define HCCR_2400_CMD_CLEAR_HOST_INT (0x6 << 28)
419#define HCCR_2400_CMD_CLEAR_RISC_INT (0xA << 28)
412#define HCCR_2400_CMD_NOP 0x00000000
413#define HCCR_2400_CMD_RESET 0x10000000
414#define HCCR_2400_CMD_CLEAR_RESET 0x20000000
415#define HCCR_2400_CMD_PAUSE 0x30000000
416#define HCCR_2400_CMD_RELEASE 0x40000000
417#define HCCR_2400_CMD_SET_HOST_INT 0x50000000
418#define HCCR_2400_CMD_CLEAR_HOST_INT 0x60000000
419#define HCCR_2400_CMD_CLEAR_RISC_INT 0xA0000000
420
421#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
422#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */
423#define HCCR_2400_RISC_RESET (1 << 5) /* RO */
424
425
426/*
427 * Mailbox Block Register Offsets
428 */
429
430#define INMAILBOX0 (MBOX_BLOCK+0x0)
431#define INMAILBOX1 (MBOX_BLOCK+0x2)
432#define INMAILBOX2 (MBOX_BLOCK+0x4)
433#define INMAILBOX3 (MBOX_BLOCK+0x6)
434#define INMAILBOX4 (MBOX_BLOCK+0x8)
435#define INMAILBOX5 (MBOX_BLOCK+0xA)
436#define INMAILBOX6 (MBOX_BLOCK+0xC)
437#define INMAILBOX7 (MBOX_BLOCK+0xE)
438
439#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
440#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
441#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
442#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
443#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
444#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
445#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
446#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
447
448/*
449 * Strictly speaking, it's
450 * SCSI && 2100 : 8 MBOX registers
451 * 2200: 24 MBOX registers
452 * 2300/2400: 32 MBOX registers
453 */
454#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1))
455#define NMBOX(isp) \
456 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \
457 ((isp)->isp_type & ISP_HA_FC))? 12 : 6)
458#define NMBOX_BMASK(isp) \
459 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \
460 ((isp)->isp_type & ISP_HA_FC))? 0xfff : 0x3f)
461
462#define MAX_MAILBOX(isp) ((IS_FC(isp))? 12 : 8)
463#define MAILBOX_STORAGE 12
464/* if timeout == 0, then default timeout is picked */
465#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */
466typedef struct {
467 uint16_t param[MAILBOX_STORAGE];
468 uint16_t ibits;
469 uint16_t obits;
470 uint32_t : 28,
471 logval : 4;
472 uint32_t timeout;
473} mbreg_t;
474
475/*
476 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
477 * NB: The RISC processor must be paused and the appropriate register
478 * bank selected via BIU2100_CSR bits.
479 */
480
481#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
482#define FPM_SOFT_RESET 0x0100
483
484#define FBM_CMD (BIU_BLOCK + 0xB8)
485#define FBMCMD_FIFO_RESET_ALL 0xA000
486
487
488/*
489 * SXP Block Register Offsets
490 */
491#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
492#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
493#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
494#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
495#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
496#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
497#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
498#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
499#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
500#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
501#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
502#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
503#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
504#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
505#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
506#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
507#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
508#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
509#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
510#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
511#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
512#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
513#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
514#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
515#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
516#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
517#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
518#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
519#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
520#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
521#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
522#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
523#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
524#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
525#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
526#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
527#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
528#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
529#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
530
531/* for 1080/1280/1240 only */
532#define SXP_BANK1_SELECT 0x100
533
534
535/* SXP CONF1 REGISTER */
536#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */
537#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */
538#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */
539#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */
540#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */
541
542/* SXP CONF2 REGISTER */
543#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */
544#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */
545#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */
546#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */
547#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */
548#define SXP_CONF2_SELECT 0x0001 /* Enable selection */
549
550/* SXP INTERRUPT REGISTER */
551#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */
552#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */
553#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */
554#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */
555#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */
556#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */
557#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */
558#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */
559#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */
560#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */
561
562
563/* SXP GROSS ERROR REGISTER */
564#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */
565#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */
566#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */
567#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */
568#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */
569#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */
570#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */
571
572/* SXP EXCEPTION REGISTER */
573#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */
574#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */
575#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */
576#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */
577#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */
578#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */
579#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */
580#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */
581#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */
582#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */
583
584 /* SXP OVERRIDE REGISTER */
585#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */
586#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */
587#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */
588#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */
589#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */
590#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */
591#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */
592#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */
593#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */
594#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */
595#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */
596#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */
597#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */
598
599/* SXP COMMANDS */
600#define SXP_RESET_BUS_CMD 0x300b
601
602/* SXP SCSI ID REGISTER */
603#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */
604#define SXP_SELECT_ID 0x000F /* Select id */
605
606/* SXP DEV CONFIG1 REGISTER */
607#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */
608#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */
609#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */
610
611
612/* SXP DEV CONFIG2 REGISTER */
613#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */
614#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */
615#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */
616#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */
617#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */
618
619
620/* SXP PHASE POINTER REGISTER */
621#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */
622#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */
623#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */
624#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */
625
626
627/* SXP FIFO STATUS REGISTER */
628#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */
629#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */
630#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */
631#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */
632
633
634/* SXP CONTROL PINS REGISTER */
635#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */
636#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */
637#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */
638#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */
639#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */
640#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */
641#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */
642#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */
643#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */
644#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */
645#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */
646#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */
647
648/*
649 * Set the hold time for the SCSI Bus Reset to be 250 ms
650 */
651#define SXP_SCSI_BUS_RESET_HOLD_TIME 250
652
653/* SXP DIFF PINS REGISTER */
654#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */
655#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */
656#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */
657#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */
658#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
659#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
660
661/* Ultra2 only */
662#define SXP_PINS_LVD_MODE 0x1000
663#define SXP_PINS_HVD_MODE 0x0800
664#define SXP_PINS_SE_MODE 0x0400
665
666/* The above have to be put together with the DIFFM pin to make sense */
667#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE)
668#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE)
669#define ISP1080_SE_MODE (SXP_PINS_SE_MODE)
670#define ISP1080_MODE_MASK \
671 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE)
672
673/*
674 * RISC and Host Command and Control Block Register Offsets
675 */
676
677#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
678#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
679#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
680#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
681#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
682#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
683#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
684#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
685#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
686#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
687#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
688#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
689#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
690#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
691#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
692#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
693#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
694#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
695#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
696#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
697#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
698#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
699#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
700#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
701#define RISC_MTR2100 RISC_BLOCK+0x30
702
703#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
704#define DUAL_BANK 8
705#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
706#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
707#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
708#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
709#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
710#define TCR RISC_BLOCK+0x46 /* W : Test Control */
711#define TMR RISC_BLOCK+0x48 /* W : Test Mode */
712
713
714/* PROCESSOR STATUS REGISTER */
715#define RISC_PSR_FORCE_TRUE 0x8000
716#define RISC_PSR_LOOP_COUNT_DONE 0x4000
717#define RISC_PSR_RISC_INT 0x2000
718#define RISC_PSR_TIMER_ROLLOVER 0x1000
719#define RISC_PSR_ALU_OVERFLOW 0x0800
720#define RISC_PSR_ALU_MSB 0x0400
721#define RISC_PSR_ALU_CARRY 0x0200
722#define RISC_PSR_ALU_ZERO 0x0100
723
724#define RISC_PSR_PCI_ULTRA 0x0080
725#define RISC_PSR_SBUS_ULTRA 0x0020
726
727#define RISC_PSR_DMA_INT 0x0010
728#define RISC_PSR_SXP_INT 0x0008
729#define RISC_PSR_HOST_INT 0x0004
730#define RISC_PSR_INT_PENDING 0x0002
731#define RISC_PSR_FORCE_FALSE 0x0001
732
733
734/* Host Command and Control */
735#define HCCR_CMD_NOP 0x0000 /* NOP */
736#define HCCR_CMD_RESET 0x1000 /* Reset RISC */
737#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
738#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
739#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
740#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /*
741 * Disable RISC pause on FPM
742 * parity error.
743 */
744#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
745#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
746#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
747#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */
748#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */
749#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */
750#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */
751#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */
752
753
754#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400
755#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200
756#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100
757#define ISP2100_HCCR_PARITY 0x0001
758
759#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */
760#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */
761#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */
762
763#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */
764#define HCCR_RESET 0x0040 /* R : reset in progress */
765#define HCCR_PAUSE 0x0020 /* R : RISC paused */
766
767#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
768
769/*
770 * Defines for Interrupts
771 */
772#define ISP_INTS_ENABLED(isp) \
773 ((IS_SCSI(isp))? \
774 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \
775 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \
776 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK)))
777
778#define ISP_ENABLE_INTS(isp) \
779 (IS_SCSI(isp) ? \
780 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \
781 (IS_24XX(isp) ? \
782 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \
783 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK))))
784
785#define ISP_DISABLE_INTS(isp) \
786 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0)
787
788/*
789 * NVRAM Definitions (PCI cards only)
790 */
791
792#define ISPBSMX(c, byte, shift, mask) \
793 (((c)[(byte)] >> (shift)) & (mask))
794/*
795 * Qlogic 1020/1040 NVRAM is an array of 128 bytes.
796 *
797 * Some portion of the front of this is for general host adapter properties
798 * This is followed by an array of per-target parameters, and is tailed off
799 * with a checksum xor byte at offset 127. For non-byte entities data is
800 * stored in Little Endian order.
801 */
802
803#define ISP_NVRAM_SIZE 128
804
805#define ISP_NVRAM_VERSION(c) (c)[4]
806#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
807#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
808#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01)
809#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f)
810#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6]
811#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7]
812#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8]
813#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f)
814#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01)
815#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01)
816#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01)
817#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01)
818#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10]
819#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01)
820#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01)
821#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01)
822#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01)
823#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01)
824#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01)
825#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01)
826#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01)
827#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8))
828#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8))
829#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01)
830#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01)
831#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01)
832#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01)
833#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01)
834#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01)
835
836#define ISP_NVRAM_TARGOFF 28
837#define ISP_NVRAM_TARGSIZE 6
838#define _IxT(tgt, tidx) \
839 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx))
840#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01)
841#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01)
842#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01)
843#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01)
844#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01)
845#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01)
846#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01)
847#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01)
848#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff)
849#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff)
850#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
851#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
852#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
853
854/*
855 * Qlogic 1080/1240 NVRAM is an array of 256 bytes.
856 *
857 * Some portion of the front of this is for general host adapter properties
858 * This is followed by an array of per-target parameters, and is tailed off
859 * with a checksum xor byte at offset 256. For non-byte entities data is
860 * stored in Little Endian order.
861 */
862
863#define ISP1080_NVRAM_SIZE 256
864
865#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c)
866
867/* Offset 5 */
868/*
869 uint8_t bios_configuration_mode :2;
870 uint8_t bios_disable :1;
871 uint8_t selectable_scsi_boot_enable :1;
872 uint8_t cd_rom_boot_enable :1;
873 uint8_t disable_loading_risc_code :1;
874 uint8_t enable_64bit_addressing :1;
875 uint8_t unused_7 :1;
876 */
877
878/* Offsets 6, 7 */
879/*
880 uint8_t boot_lun_number :5;
881 uint8_t scsi_bus_number :1;
882 uint8_t unused_6 :1;
883 uint8_t unused_7 :1;
884 uint8_t boot_target_number :4;
885 uint8_t unused_12 :1;
886 uint8_t unused_13 :1;
887 uint8_t unused_14 :1;
888 uint8_t unused_15 :1;
889 */
890
891#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01)
892
893#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01)
894#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f)
895
896#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01)
897#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03)
898#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03)
899
900#define ISP1080_ISP_PARAMETER(c) \
901 (((c)[18]) | ((c)[19] << 8))
902
903#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01)
904#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01)
905
906#define ISP1080_BUS1_OFF 112
907
908#define ISP1080_NVRAM_INITIATOR_ID(c, b) \
909 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
910#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \
911 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
912#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \
913 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
914#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \
915 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]
916
917#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \
918 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
919#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \
920 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
921#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \
922 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
923#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \
924 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
925 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
926#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \
927 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
928 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))
929
930#define ISP1080_NVRAM_TARGOFF(b) \
931 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
932#define ISP1080_NVRAM_TARGSIZE 6
933#define _IxT8(tgt, tidx, b) \
934 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
935
936#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \
937 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
938#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \
939 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
940#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \
941 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
942#define ISP1080_NVRAM_TGT_TQING(c, t, b) \
943 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
944#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \
945 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
946#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \
947 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
948#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \
949 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
950#define ISP1080_NVRAM_TGT_DISC(c, t, b) \
951 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
952#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
953 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
954#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
955 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
956#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
957 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
958#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
959 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
960#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
961 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
962
963#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE
964#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE
965#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD
966#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT
967#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE
968#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE
969#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER
970#define ISP12160_FAST_POST ISP1080_FAST_POST
971#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION
972
973#define ISP12160_NVRAM_INITIATOR_ID \
974 ISP1080_NVRAM_INITIATOR_ID
975#define ISP12160_NVRAM_BUS_RESET_DELAY \
976 ISP1080_NVRAM_BUS_RESET_DELAY
977#define ISP12160_NVRAM_BUS_RETRY_COUNT \
978 ISP1080_NVRAM_BUS_RETRY_COUNT
979#define ISP12160_NVRAM_BUS_RETRY_DELAY \
980 ISP1080_NVRAM_BUS_RETRY_DELAY
981#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \
982 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME
983#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \
984 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION
985#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \
986 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION
987#define ISP12160_NVRAM_SELECTION_TIMEOUT \
988 ISP1080_NVRAM_SELECTION_TIMEOUT
989#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \
990 ISP1080_NVRAM_MAX_QUEUE_DEPTH
991
992
993#define ISP12160_BUS0_OFF 24
994#define ISP12160_BUS1_OFF 136
995
996#define ISP12160_NVRAM_TARGOFF(b) \
997 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16)
998
999#define ISP12160_NVRAM_TARGSIZE 6
1000#define _IxT16(tgt, tidx, b) \
1001 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
1002
1003#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \
1004 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01)
1005#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \
1006 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01)
1007#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \
1008 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01)
1009#define ISP12160_NVRAM_TGT_TQING(c, t, b) \
1010 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01)
1011#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \
1012 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01)
1013#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \
1014 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01)
1015#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \
1016 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01)
1017#define ISP12160_NVRAM_TGT_DISC(c, t, b) \
1018 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01)
1019
1020#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
1021 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff)
1022#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
1023 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff)
1024
1025#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
1026 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f)
1027#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
1028 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01)
1029
1030#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \
1031 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f)
1032#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \
1033 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03)
1034#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \
1035 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01)
1036
1037/*
1038 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes.
1039 *
1040 * Some portion of the front of this is for general RISC engine parameters,
1041 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
1042 *
1043 * This is followed by some general host adapter parameters, and ends with
1044 * a checksum xor byte at offset 255. For non-byte entities data is stored
1045 * in Little Endian order.
1046 */
1047#define ISP2100_NVRAM_SIZE 256
1048/* ISP_NVRAM_VERSION is in same overall place */
1049#define ISP2100_NVRAM_RISCVER(c) (c)[6]
1050#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8))
1051#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8))
1052#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8))
1053#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1054#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16]
1055#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17]
1056
1057#define ISP2100_NVRAM_PORT_NAME(c) (\
1058 (((uint64_t)(c)[18]) << 56) | \
1059 (((uint64_t)(c)[19]) << 48) | \
1060 (((uint64_t)(c)[20]) << 40) | \
1061 (((uint64_t)(c)[21]) << 32) | \
1062 (((uint64_t)(c)[22]) << 24) | \
1063 (((uint64_t)(c)[23]) << 16) | \
1064 (((uint64_t)(c)[24]) << 8) | \
1065 (((uint64_t)(c)[25]) << 0))
1066
1067#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8))
1068#define ISP2100_NVRAM_TOV(c) ((c)[29])
1069
1070#define ISP2100_NVRAM_NODE_NAME(c) (\
1071 (((uint64_t)(c)[30]) << 56) | \
1072 (((uint64_t)(c)[31]) << 48) | \
1073 (((uint64_t)(c)[32]) << 40) | \
1074 (((uint64_t)(c)[33]) << 32) | \
1075 (((uint64_t)(c)[34]) << 24) | \
1076 (((uint64_t)(c)[35]) << 16) | \
1077 (((uint64_t)(c)[36]) << 8) | \
1078 (((uint64_t)(c)[37]) << 0))
1079
1080#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8))
1081
1082#define ISP2100_RACC_TIMER(c) (c)[40]
1083#define ISP2100_IDELAY_TIMER(c) (c)[41]
1084
1085#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8))
1086
1087#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8))
1088
1089#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8))
1090#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01)
1091#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01)
1092#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01)
1093#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01)
1094#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01)
1095#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01)
1096
1097#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\
1098 (((uint64_t)(c)[72]) << 56) | \
1099 (((uint64_t)(c)[73]) << 48) | \
1100 (((uint64_t)(c)[74]) << 40) | \
1101 (((uint64_t)(c)[75]) << 32) | \
1102 (((uint64_t)(c)[76]) << 24) | \
1103 (((uint64_t)(c)[77]) << 16) | \
1104 (((uint64_t)(c)[78]) << 8) | \
1105 (((uint64_t)(c)[79]) << 0))
1106
1107#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80]
1108#define ISP2100_RESET_DELAY(c) (c)[81]
1109
1110#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8))
1111
1112/*
1113 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum.
1114 */
1115#define ISP2400_NVRAM_PORT0_ADDR 0x80
1116#define ISP2400_NVRAM_PORT1_ADDR 0x180
1117#define ISP2400_NVRAM_SIZE 512
1118
1119#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8))
1120#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8))
1121#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1122#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8))
1123#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8))
1124
1125#define ISP2400_NVRAM_PORT_NAME(c) (\
1126 (((uint64_t)(c)[20]) << 56) | \
1127 (((uint64_t)(c)[21]) << 48) | \
1128 (((uint64_t)(c)[22]) << 40) | \
1129 (((uint64_t)(c)[23]) << 32) | \
1130 (((uint64_t)(c)[24]) << 24) | \
1131 (((uint64_t)(c)[25]) << 16) | \
1132 (((uint64_t)(c)[26]) << 8) | \
1133 (((uint64_t)(c)[27]) << 0))
1134
1135#define ISP2400_NVRAM_NODE_NAME(c) (\
1136 (((uint64_t)(c)[28]) << 56) | \
1137 (((uint64_t)(c)[29]) << 48) | \
1138 (((uint64_t)(c)[30]) << 40) | \
1139 (((uint64_t)(c)[31]) << 32) | \
1140 (((uint64_t)(c)[32]) << 24) | \
1141 (((uint64_t)(c)[33]) << 16) | \
1142 (((uint64_t)(c)[34]) << 8) | \
1143 (((uint64_t)(c)[35]) << 0))
1144
1145#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8))
1146#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8))
1147#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8))
1148#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8))
1149
1150#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \
1151 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24))
1152#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \
1153 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24))
1154#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
1155 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))
1156
1157/*
1158 * Firmware Crash Dump
1159 *
1160 * QLogic needs specific information format when they look at firmware crashes.
1161 *
1162 * This is incredibly kernel memory consumptive (to say the least), so this
1163 * code is only compiled in when needed.
1164 */
1165
1166#define QLA2200_RISC_IMAGE_DUMP_SIZE \
1167 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1168 (352 * sizeof (uint16_t)) + /* RISC registers */ \
1169 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */
1170#define QLA2300_RISC_IMAGE_DUMP_SIZE \
1171 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1172 (464 * sizeof (uint16_t)) + /* RISC registers */ \
1173 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \
1174 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \
1175 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */
1176/* the larger of the two */
1177#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE
1178#endif /* _ISPREG_H */
420
421#define HCCR_2400_RISC_ERR(x) (((x) >> 12) & 0x7) /* RO */
422#define HCCR_2400_RISC2HOST_INT (1 << 6) /* RO */
423#define HCCR_2400_RISC_RESET (1 << 5) /* RO */
424
425
426/*
427 * Mailbox Block Register Offsets
428 */
429
430#define INMAILBOX0 (MBOX_BLOCK+0x0)
431#define INMAILBOX1 (MBOX_BLOCK+0x2)
432#define INMAILBOX2 (MBOX_BLOCK+0x4)
433#define INMAILBOX3 (MBOX_BLOCK+0x6)
434#define INMAILBOX4 (MBOX_BLOCK+0x8)
435#define INMAILBOX5 (MBOX_BLOCK+0xA)
436#define INMAILBOX6 (MBOX_BLOCK+0xC)
437#define INMAILBOX7 (MBOX_BLOCK+0xE)
438
439#define OUTMAILBOX0 (MBOX_BLOCK+0x0)
440#define OUTMAILBOX1 (MBOX_BLOCK+0x2)
441#define OUTMAILBOX2 (MBOX_BLOCK+0x4)
442#define OUTMAILBOX3 (MBOX_BLOCK+0x6)
443#define OUTMAILBOX4 (MBOX_BLOCK+0x8)
444#define OUTMAILBOX5 (MBOX_BLOCK+0xA)
445#define OUTMAILBOX6 (MBOX_BLOCK+0xC)
446#define OUTMAILBOX7 (MBOX_BLOCK+0xE)
447
448/*
449 * Strictly speaking, it's
450 * SCSI && 2100 : 8 MBOX registers
451 * 2200: 24 MBOX registers
452 * 2300/2400: 32 MBOX registers
453 */
454#define MBOX_OFF(n) (MBOX_BLOCK + ((n) << 1))
455#define NMBOX(isp) \
456 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \
457 ((isp)->isp_type & ISP_HA_FC))? 12 : 6)
458#define NMBOX_BMASK(isp) \
459 (((((isp)->isp_type & ISP_HA_SCSI) >= ISP_HA_SCSI_1040A) || \
460 ((isp)->isp_type & ISP_HA_FC))? 0xfff : 0x3f)
461
462#define MAX_MAILBOX(isp) ((IS_FC(isp))? 12 : 8)
463#define MAILBOX_STORAGE 12
464/* if timeout == 0, then default timeout is picked */
465#define MBCMD_DEFAULT_TIMEOUT 100000 /* 100 ms */
466typedef struct {
467 uint16_t param[MAILBOX_STORAGE];
468 uint16_t ibits;
469 uint16_t obits;
470 uint32_t : 28,
471 logval : 4;
472 uint32_t timeout;
473} mbreg_t;
474
475/*
476 * Fibre Protocol Module and Frame Buffer Register Offsets/Definitions (2X00).
477 * NB: The RISC processor must be paused and the appropriate register
478 * bank selected via BIU2100_CSR bits.
479 */
480
481#define FPM_DIAG_CONFIG (BIU_BLOCK + 0x96)
482#define FPM_SOFT_RESET 0x0100
483
484#define FBM_CMD (BIU_BLOCK + 0xB8)
485#define FBMCMD_FIFO_RESET_ALL 0xA000
486
487
488/*
489 * SXP Block Register Offsets
490 */
491#define SXP_PART_ID (SXP_BLOCK+0x0) /* R : Part ID Code */
492#define SXP_CONFIG1 (SXP_BLOCK+0x2) /* RW*: Configuration Reg #1 */
493#define SXP_CONFIG2 (SXP_BLOCK+0x4) /* RW*: Configuration Reg #2 */
494#define SXP_CONFIG3 (SXP_BLOCK+0x6) /* RW*: Configuration Reg #2 */
495#define SXP_INSTRUCTION (SXP_BLOCK+0xC) /* RW*: Instruction Pointer */
496#define SXP_RETURN_ADDR (SXP_BLOCK+0x10) /* RW*: Return Address */
497#define SXP_COMMAND (SXP_BLOCK+0x14) /* RW*: Command */
498#define SXP_INTERRUPT (SXP_BLOCK+0x18) /* R : Interrupt */
499#define SXP_SEQUENCE (SXP_BLOCK+0x1C) /* RW*: Sequence */
500#define SXP_GROSS_ERR (SXP_BLOCK+0x1E) /* R : Gross Error */
501#define SXP_EXCEPTION (SXP_BLOCK+0x20) /* RW*: Exception Enable */
502#define SXP_OVERRIDE (SXP_BLOCK+0x24) /* RW*: Override */
503#define SXP_LIT_BASE (SXP_BLOCK+0x28) /* RW*: Literal Base */
504#define SXP_USER_FLAGS (SXP_BLOCK+0x2C) /* RW*: User Flags */
505#define SXP_USER_EXCEPT (SXP_BLOCK+0x30) /* RW*: User Exception */
506#define SXP_BREAKPOINT (SXP_BLOCK+0x34) /* RW*: Breakpoint */
507#define SXP_SCSI_ID (SXP_BLOCK+0x40) /* RW*: SCSI ID */
508#define SXP_DEV_CONFIG1 (SXP_BLOCK+0x42) /* RW*: Device Config Reg #1 */
509#define SXP_DEV_CONFIG2 (SXP_BLOCK+0x44) /* RW*: Device Config Reg #2 */
510#define SXP_PHASE_PTR (SXP_BLOCK+0x48) /* RW*: SCSI Phase Pointer */
511#define SXP_BUF_PTR (SXP_BLOCK+0x4C) /* RW*: SCSI Buffer Pointer */
512#define SXP_BUF_CTR (SXP_BLOCK+0x50) /* RW*: SCSI Buffer Counter */
513#define SXP_BUFFER (SXP_BLOCK+0x52) /* RW*: SCSI Buffer */
514#define SXP_BUF_BYTE (SXP_BLOCK+0x54) /* RW*: SCSI Buffer Byte */
515#define SXP_BUF_WD (SXP_BLOCK+0x56) /* RW*: SCSI Buffer Word */
516#define SXP_BUF_WD_TRAN (SXP_BLOCK+0x58) /* RW*: SCSI Buffer Wd xlate */
517#define SXP_FIFO (SXP_BLOCK+0x5A) /* RW*: SCSI FIFO */
518#define SXP_FIFO_STATUS (SXP_BLOCK+0x5C) /* RW*: SCSI FIFO Status */
519#define SXP_FIFO_TOP (SXP_BLOCK+0x5E) /* RW*: SCSI FIFO Top Resid */
520#define SXP_FIFO_BOTTOM (SXP_BLOCK+0x60) /* RW*: SCSI FIFO Bot Resid */
521#define SXP_TRAN_REG (SXP_BLOCK+0x64) /* RW*: SCSI Transferr Reg */
522#define SXP_TRAN_CNT_LO (SXP_BLOCK+0x68) /* RW*: SCSI Trans Count */
523#define SXP_TRAN_CNT_HI (SXP_BLOCK+0x6A) /* RW*: SCSI Trans Count */
524#define SXP_TRAN_CTR_LO (SXP_BLOCK+0x6C) /* RW*: SCSI Trans Counter */
525#define SXP_TRAN_CTR_HI (SXP_BLOCK+0x6E) /* RW*: SCSI Trans Counter */
526#define SXP_ARB_DATA (SXP_BLOCK+0x70) /* R : SCSI Arb Data */
527#define SXP_PINS_CTRL (SXP_BLOCK+0x72) /* RW*: SCSI Control Pins */
528#define SXP_PINS_DATA (SXP_BLOCK+0x74) /* RW*: SCSI Data Pins */
529#define SXP_PINS_DIFF (SXP_BLOCK+0x76) /* RW*: SCSI Diff Pins */
530
531/* for 1080/1280/1240 only */
532#define SXP_BANK1_SELECT 0x100
533
534
535/* SXP CONF1 REGISTER */
536#define SXP_CONF1_ASYNCH_SETUP 0xF000 /* Asynchronous setup time */
537#define SXP_CONF1_SELECTION_UNIT 0x0000 /* Selection time unit */
538#define SXP_CONF1_SELECTION_TIMEOUT 0x0600 /* Selection timeout */
539#define SXP_CONF1_CLOCK_FACTOR 0x00E0 /* Clock factor */
540#define SXP_CONF1_SCSI_ID 0x000F /* SCSI id */
541
542/* SXP CONF2 REGISTER */
543#define SXP_CONF2_DISABLE_FILTER 0x0040 /* Disable SCSI rec filters */
544#define SXP_CONF2_REQ_ACK_PULLUPS 0x0020 /* Enable req/ack pullups */
545#define SXP_CONF2_DATA_PULLUPS 0x0010 /* Enable data pullups */
546#define SXP_CONF2_CONFIG_AUTOLOAD 0x0008 /* Enable dev conf auto-load */
547#define SXP_CONF2_RESELECT 0x0002 /* Enable reselection */
548#define SXP_CONF2_SELECT 0x0001 /* Enable selection */
549
550/* SXP INTERRUPT REGISTER */
551#define SXP_INT_PARITY_ERR 0x8000 /* Parity error detected */
552#define SXP_INT_GROSS_ERR 0x4000 /* Gross error detected */
553#define SXP_INT_FUNCTION_ABORT 0x2000 /* Last cmd aborted */
554#define SXP_INT_CONDITION_FAILED 0x1000 /* Last cond failed test */
555#define SXP_INT_FIFO_EMPTY 0x0800 /* SCSI FIFO is empty */
556#define SXP_INT_BUF_COUNTER_ZERO 0x0400 /* SCSI buf count == zero */
557#define SXP_INT_XFER_ZERO 0x0200 /* SCSI trans count == zero */
558#define SXP_INT_INT_PENDING 0x0080 /* SXP interrupt pending */
559#define SXP_INT_CMD_RUNNING 0x0040 /* SXP is running a command */
560#define SXP_INT_INT_RETURN_CODE 0x000F /* Interrupt return code */
561
562
563/* SXP GROSS ERROR REGISTER */
564#define SXP_GROSS_OFFSET_RESID 0x0040 /* Req/Ack offset not zero */
565#define SXP_GROSS_OFFSET_UNDERFLOW 0x0020 /* Req/Ack offset underflow */
566#define SXP_GROSS_OFFSET_OVERFLOW 0x0010 /* Req/Ack offset overflow */
567#define SXP_GROSS_FIFO_UNDERFLOW 0x0008 /* SCSI FIFO underflow */
568#define SXP_GROSS_FIFO_OVERFLOW 0x0004 /* SCSI FIFO overflow */
569#define SXP_GROSS_WRITE_ERR 0x0002 /* SXP and RISC wrote to reg */
570#define SXP_GROSS_ILLEGAL_INST 0x0001 /* Bad inst loaded into SXP */
571
572/* SXP EXCEPTION REGISTER */
573#define SXP_EXCEPT_USER_0 0x8000 /* Enable user exception #0 */
574#define SXP_EXCEPT_USER_1 0x4000 /* Enable user exception #1 */
575#define PCI_SXP_EXCEPT_SCAM 0x0400 /* SCAM Selection enable */
576#define SXP_EXCEPT_BUS_FREE 0x0200 /* Enable Bus Free det */
577#define SXP_EXCEPT_TARGET_ATN 0x0100 /* Enable TGT mode atten det */
578#define SXP_EXCEPT_RESELECTED 0x0080 /* Enable ReSEL exc handling */
579#define SXP_EXCEPT_SELECTED 0x0040 /* Enable SEL exc handling */
580#define SXP_EXCEPT_ARBITRATION 0x0020 /* Enable ARB exc handling */
581#define SXP_EXCEPT_GROSS_ERR 0x0010 /* Enable gross error except */
582#define SXP_EXCEPT_BUS_RESET 0x0008 /* Enable Bus Reset except */
583
584 /* SXP OVERRIDE REGISTER */
585#define SXP_ORIDE_EXT_TRIGGER 0x8000 /* Enable external trigger */
586#define SXP_ORIDE_STEP 0x4000 /* Enable single step mode */
587#define SXP_ORIDE_BREAKPOINT 0x2000 /* Enable breakpoint reg */
588#define SXP_ORIDE_PIN_WRITE 0x1000 /* Enable write to SCSI pins */
589#define SXP_ORIDE_FORCE_OUTPUTS 0x0800 /* Force SCSI outputs on */
590#define SXP_ORIDE_LOOPBACK 0x0400 /* Enable SCSI loopback mode */
591#define SXP_ORIDE_PARITY_TEST 0x0200 /* Enable parity test mode */
592#define SXP_ORIDE_TRISTATE_ENA_PINS 0x0100 /* Tristate SCSI enable pins */
593#define SXP_ORIDE_TRISTATE_PINS 0x0080 /* Tristate SCSI pins */
594#define SXP_ORIDE_FIFO_RESET 0x0008 /* Reset SCSI FIFO */
595#define SXP_ORIDE_CMD_TERMINATE 0x0004 /* Terminate cur SXP com */
596#define SXP_ORIDE_RESET_REG 0x0002 /* Reset SXP registers */
597#define SXP_ORIDE_RESET_MODULE 0x0001 /* Reset SXP module */
598
599/* SXP COMMANDS */
600#define SXP_RESET_BUS_CMD 0x300b
601
602/* SXP SCSI ID REGISTER */
603#define SXP_SELECTING_ID 0x0F00 /* (Re)Selecting id */
604#define SXP_SELECT_ID 0x000F /* Select id */
605
606/* SXP DEV CONFIG1 REGISTER */
607#define SXP_DCONF1_SYNC_HOLD 0x7000 /* Synchronous data hold */
608#define SXP_DCONF1_SYNC_SETUP 0x0F00 /* Synchronous data setup */
609#define SXP_DCONF1_SYNC_OFFSET 0x000F /* Synchronous data offset */
610
611
612/* SXP DEV CONFIG2 REGISTER */
613#define SXP_DCONF2_FLAGS_MASK 0xF000 /* Device flags */
614#define SXP_DCONF2_WIDE 0x0400 /* Enable wide SCSI */
615#define SXP_DCONF2_PARITY 0x0200 /* Enable parity checking */
616#define SXP_DCONF2_BLOCK_MODE 0x0100 /* Enable blk mode xfr count */
617#define SXP_DCONF2_ASSERTION_MASK 0x0007 /* Assersion period mask */
618
619
620/* SXP PHASE POINTER REGISTER */
621#define SXP_PHASE_STATUS_PTR 0x1000 /* Status buffer offset */
622#define SXP_PHASE_MSG_IN_PTR 0x0700 /* Msg in buffer offset */
623#define SXP_PHASE_COM_PTR 0x00F0 /* Command buffer offset */
624#define SXP_PHASE_MSG_OUT_PTR 0x0007 /* Msg out buffer offset */
625
626
627/* SXP FIFO STATUS REGISTER */
628#define SXP_FIFO_TOP_RESID 0x8000 /* Top residue reg full */
629#define SXP_FIFO_ACK_RESID 0x4000 /* Wide transfers odd resid */
630#define SXP_FIFO_COUNT_MASK 0x001C /* Words in SXP FIFO */
631#define SXP_FIFO_BOTTOM_RESID 0x0001 /* Bottom residue reg full */
632
633
634/* SXP CONTROL PINS REGISTER */
635#define SXP_PINS_CON_PHASE 0x8000 /* Scsi phase valid */
636#define SXP_PINS_CON_PARITY_HI 0x0400 /* Parity pin */
637#define SXP_PINS_CON_PARITY_LO 0x0200 /* Parity pin */
638#define SXP_PINS_CON_REQ 0x0100 /* SCSI bus REQUEST */
639#define SXP_PINS_CON_ACK 0x0080 /* SCSI bus ACKNOWLEDGE */
640#define SXP_PINS_CON_RST 0x0040 /* SCSI bus RESET */
641#define SXP_PINS_CON_BSY 0x0020 /* SCSI bus BUSY */
642#define SXP_PINS_CON_SEL 0x0010 /* SCSI bus SELECT */
643#define SXP_PINS_CON_ATN 0x0008 /* SCSI bus ATTENTION */
644#define SXP_PINS_CON_MSG 0x0004 /* SCSI bus MESSAGE */
645#define SXP_PINS_CON_CD 0x0002 /* SCSI bus COMMAND */
646#define SXP_PINS_CON_IO 0x0001 /* SCSI bus INPUT */
647
648/*
649 * Set the hold time for the SCSI Bus Reset to be 250 ms
650 */
651#define SXP_SCSI_BUS_RESET_HOLD_TIME 250
652
653/* SXP DIFF PINS REGISTER */
654#define SXP_PINS_DIFF_SENSE 0x0200 /* DIFFSENS sig on SCSI bus */
655#define SXP_PINS_DIFF_MODE 0x0100 /* DIFFM signal */
656#define SXP_PINS_DIFF_ENABLE_OUTPUT 0x0080 /* Enable SXP SCSI data drv */
657#define SXP_PINS_DIFF_PINS_MASK 0x007C /* Differential control pins */
658#define SXP_PINS_DIFF_TARGET 0x0002 /* Enable SXP target mode */
659#define SXP_PINS_DIFF_INITIATOR 0x0001 /* Enable SXP initiator mode */
660
661/* Ultra2 only */
662#define SXP_PINS_LVD_MODE 0x1000
663#define SXP_PINS_HVD_MODE 0x0800
664#define SXP_PINS_SE_MODE 0x0400
665
666/* The above have to be put together with the DIFFM pin to make sense */
667#define ISP1080_LVD_MODE (SXP_PINS_LVD_MODE)
668#define ISP1080_HVD_MODE (SXP_PINS_HVD_MODE|SXP_PINS_DIFF_MODE)
669#define ISP1080_SE_MODE (SXP_PINS_SE_MODE)
670#define ISP1080_MODE_MASK \
671 (SXP_PINS_LVD_MODE|SXP_PINS_HVD_MODE|SXP_PINS_SE_MODE|SXP_PINS_DIFF_MODE)
672
673/*
674 * RISC and Host Command and Control Block Register Offsets
675 */
676
677#define RISC_ACC RISC_BLOCK+0x0 /* RW*: Accumulator */
678#define RISC_R1 RISC_BLOCK+0x2 /* RW*: GP Reg R1 */
679#define RISC_R2 RISC_BLOCK+0x4 /* RW*: GP Reg R2 */
680#define RISC_R3 RISC_BLOCK+0x6 /* RW*: GP Reg R3 */
681#define RISC_R4 RISC_BLOCK+0x8 /* RW*: GP Reg R4 */
682#define RISC_R5 RISC_BLOCK+0xA /* RW*: GP Reg R5 */
683#define RISC_R6 RISC_BLOCK+0xC /* RW*: GP Reg R6 */
684#define RISC_R7 RISC_BLOCK+0xE /* RW*: GP Reg R7 */
685#define RISC_R8 RISC_BLOCK+0x10 /* RW*: GP Reg R8 */
686#define RISC_R9 RISC_BLOCK+0x12 /* RW*: GP Reg R9 */
687#define RISC_R10 RISC_BLOCK+0x14 /* RW*: GP Reg R10 */
688#define RISC_R11 RISC_BLOCK+0x16 /* RW*: GP Reg R11 */
689#define RISC_R12 RISC_BLOCK+0x18 /* RW*: GP Reg R12 */
690#define RISC_R13 RISC_BLOCK+0x1a /* RW*: GP Reg R13 */
691#define RISC_R14 RISC_BLOCK+0x1c /* RW*: GP Reg R14 */
692#define RISC_R15 RISC_BLOCK+0x1e /* RW*: GP Reg R15 */
693#define RISC_PSR RISC_BLOCK+0x20 /* RW*: Processor Status */
694#define RISC_IVR RISC_BLOCK+0x22 /* RW*: Interrupt Vector */
695#define RISC_PCR RISC_BLOCK+0x24 /* RW*: Processor Ctrl */
696#define RISC_RAR0 RISC_BLOCK+0x26 /* RW*: Ram Address #0 */
697#define RISC_RAR1 RISC_BLOCK+0x28 /* RW*: Ram Address #1 */
698#define RISC_LCR RISC_BLOCK+0x2a /* RW*: Loop Counter */
699#define RISC_PC RISC_BLOCK+0x2c /* R : Program Counter */
700#define RISC_MTR RISC_BLOCK+0x2e /* RW*: Memory Timing */
701#define RISC_MTR2100 RISC_BLOCK+0x30
702
703#define RISC_EMB RISC_BLOCK+0x30 /* RW*: Ext Mem Boundary */
704#define DUAL_BANK 8
705#define RISC_SP RISC_BLOCK+0x32 /* RW*: Stack Pointer */
706#define RISC_HRL RISC_BLOCK+0x3e /* R *: Hardware Rev Level */
707#define HCCR RISC_BLOCK+0x40 /* RW : Host Command & Ctrl */
708#define BP0 RISC_BLOCK+0x42 /* RW : Processor Brkpt #0 */
709#define BP1 RISC_BLOCK+0x44 /* RW : Processor Brkpt #1 */
710#define TCR RISC_BLOCK+0x46 /* W : Test Control */
711#define TMR RISC_BLOCK+0x48 /* W : Test Mode */
712
713
714/* PROCESSOR STATUS REGISTER */
715#define RISC_PSR_FORCE_TRUE 0x8000
716#define RISC_PSR_LOOP_COUNT_DONE 0x4000
717#define RISC_PSR_RISC_INT 0x2000
718#define RISC_PSR_TIMER_ROLLOVER 0x1000
719#define RISC_PSR_ALU_OVERFLOW 0x0800
720#define RISC_PSR_ALU_MSB 0x0400
721#define RISC_PSR_ALU_CARRY 0x0200
722#define RISC_PSR_ALU_ZERO 0x0100
723
724#define RISC_PSR_PCI_ULTRA 0x0080
725#define RISC_PSR_SBUS_ULTRA 0x0020
726
727#define RISC_PSR_DMA_INT 0x0010
728#define RISC_PSR_SXP_INT 0x0008
729#define RISC_PSR_HOST_INT 0x0004
730#define RISC_PSR_INT_PENDING 0x0002
731#define RISC_PSR_FORCE_FALSE 0x0001
732
733
734/* Host Command and Control */
735#define HCCR_CMD_NOP 0x0000 /* NOP */
736#define HCCR_CMD_RESET 0x1000 /* Reset RISC */
737#define HCCR_CMD_PAUSE 0x2000 /* Pause RISC */
738#define HCCR_CMD_RELEASE 0x3000 /* Release Paused RISC */
739#define HCCR_CMD_STEP 0x4000 /* Single Step RISC */
740#define HCCR_2X00_DISABLE_PARITY_PAUSE 0x4001 /*
741 * Disable RISC pause on FPM
742 * parity error.
743 */
744#define HCCR_CMD_SET_HOST_INT 0x5000 /* Set Host Interrupt */
745#define HCCR_CMD_CLEAR_HOST_INT 0x6000 /* Clear Host Interrupt */
746#define HCCR_CMD_CLEAR_RISC_INT 0x7000 /* Clear RISC interrupt */
747#define HCCR_CMD_BREAKPOINT 0x8000 /* Change breakpoint enables */
748#define PCI_HCCR_CMD_BIOS 0x9000 /* Write BIOS (disable) */
749#define PCI_HCCR_CMD_PARITY 0xA000 /* Write parity enable */
750#define PCI_HCCR_CMD_PARITY_ERR 0xE000 /* Generate parity error */
751#define HCCR_CMD_TEST_MODE 0xF000 /* Set Test Mode */
752
753
754#define ISP2100_HCCR_PARITY_ENABLE_2 0x0400
755#define ISP2100_HCCR_PARITY_ENABLE_1 0x0200
756#define ISP2100_HCCR_PARITY_ENABLE_0 0x0100
757#define ISP2100_HCCR_PARITY 0x0001
758
759#define PCI_HCCR_PARITY 0x0400 /* Parity error flag */
760#define PCI_HCCR_PARITY_ENABLE_1 0x0200 /* Parity enable bank 1 */
761#define PCI_HCCR_PARITY_ENABLE_0 0x0100 /* Parity enable bank 0 */
762
763#define HCCR_HOST_INT 0x0080 /* R : Host interrupt set */
764#define HCCR_RESET 0x0040 /* R : reset in progress */
765#define HCCR_PAUSE 0x0020 /* R : RISC paused */
766
767#define PCI_HCCR_BIOS 0x0001 /* W : BIOS enable */
768
769/*
770 * Defines for Interrupts
771 */
772#define ISP_INTS_ENABLED(isp) \
773 ((IS_SCSI(isp))? \
774 (ISP_READ(isp, BIU_ICR) & BIU_IMASK) : \
775 (IS_24XX(isp)? (ISP_READ(isp, BIU2400_ICR) & BIU2400_IMASK) : \
776 (ISP_READ(isp, BIU_ICR) & BIU2100_IMASK)))
777
778#define ISP_ENABLE_INTS(isp) \
779 (IS_SCSI(isp) ? \
780 ISP_WRITE(isp, BIU_ICR, BIU_IMASK) : \
781 (IS_24XX(isp) ? \
782 (ISP_WRITE(isp, BIU2400_ICR, BIU2400_IMASK)) : \
783 (ISP_WRITE(isp, BIU_ICR, BIU2100_IMASK))))
784
785#define ISP_DISABLE_INTS(isp) \
786 IS_24XX(isp)? ISP_WRITE(isp, BIU2400_ICR, 0) : ISP_WRITE(isp, BIU_ICR, 0)
787
788/*
789 * NVRAM Definitions (PCI cards only)
790 */
791
792#define ISPBSMX(c, byte, shift, mask) \
793 (((c)[(byte)] >> (shift)) & (mask))
794/*
795 * Qlogic 1020/1040 NVRAM is an array of 128 bytes.
796 *
797 * Some portion of the front of this is for general host adapter properties
798 * This is followed by an array of per-target parameters, and is tailed off
799 * with a checksum xor byte at offset 127. For non-byte entities data is
800 * stored in Little Endian order.
801 */
802
803#define ISP_NVRAM_SIZE 128
804
805#define ISP_NVRAM_VERSION(c) (c)[4]
806#define ISP_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 5, 0, 0x03)
807#define ISP_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 5, 2, 0x01)
808#define ISP_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 5, 3, 0x01)
809#define ISP_NVRAM_INITIATOR_ID(c) ISPBSMX(c, 5, 4, 0x0f)
810#define ISP_NVRAM_BUS_RESET_DELAY(c) (c)[6]
811#define ISP_NVRAM_BUS_RETRY_COUNT(c) (c)[7]
812#define ISP_NVRAM_BUS_RETRY_DELAY(c) (c)[8]
813#define ISP_NVRAM_ASYNC_DATA_SETUP_TIME(c) ISPBSMX(c, 9, 0, 0x0f)
814#define ISP_NVRAM_REQ_ACK_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 4, 0x01)
815#define ISP_NVRAM_DATA_LINE_ACTIVE_NEGATION(c) ISPBSMX(c, 9, 5, 0x01)
816#define ISP_NVRAM_DATA_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 6, 0x01)
817#define ISP_NVRAM_CMD_DMA_BURST_ENABLE(c) ISPBSMX(c, 9, 7, 0x01)
818#define ISP_NVRAM_TAG_AGE_LIMIT(c) (c)[10]
819#define ISP_NVRAM_LOWTRM_ENABLE(c) ISPBSMX(c, 11, 0, 0x01)
820#define ISP_NVRAM_HITRM_ENABLE(c) ISPBSMX(c, 11, 1, 0x01)
821#define ISP_NVRAM_PCMC_BURST_ENABLE(c) ISPBSMX(c, 11, 2, 0x01)
822#define ISP_NVRAM_ENABLE_60_MHZ(c) ISPBSMX(c, 11, 3, 0x01)
823#define ISP_NVRAM_SCSI_RESET_DISABLE(c) ISPBSMX(c, 11, 4, 0x01)
824#define ISP_NVRAM_ENABLE_AUTO_TERM(c) ISPBSMX(c, 11, 5, 0x01)
825#define ISP_NVRAM_FIFO_THRESHOLD_128(c) ISPBSMX(c, 11, 6, 0x01)
826#define ISP_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 11, 7, 0x01)
827#define ISP_NVRAM_SELECTION_TIMEOUT(c) (((c)[12]) | ((c)[13] << 8))
828#define ISP_NVRAM_MAX_QUEUE_DEPTH(c) (((c)[14]) | ((c)[15] << 8))
829#define ISP_NVRAM_SCSI_BUS_SIZE(c) ISPBSMX(c, 16, 0, 0x01)
830#define ISP_NVRAM_SCSI_BUS_TYPE(c) ISPBSMX(c, 16, 1, 0x01)
831#define ISP_NVRAM_ADAPTER_CLK_SPEED(c) ISPBSMX(c, 16, 2, 0x01)
832#define ISP_NVRAM_SOFT_TERM_SUPPORT(c) ISPBSMX(c, 16, 3, 0x01)
833#define ISP_NVRAM_FLASH_ONBOARD(c) ISPBSMX(c, 16, 4, 0x01)
834#define ISP_NVRAM_FAST_MTTR_ENABLE(c) ISPBSMX(c, 22, 0, 0x01)
835
836#define ISP_NVRAM_TARGOFF 28
837#define ISP_NVRAM_TARGSIZE 6
838#define _IxT(tgt, tidx) \
839 (ISP_NVRAM_TARGOFF + (ISP_NVRAM_TARGSIZE * (tgt)) + (tidx))
840#define ISP_NVRAM_TGT_RENEG(c, t) ISPBSMX(c, _IxT(t, 0), 0, 0x01)
841#define ISP_NVRAM_TGT_QFRZ(c, t) ISPBSMX(c, _IxT(t, 0), 1, 0x01)
842#define ISP_NVRAM_TGT_ARQ(c, t) ISPBSMX(c, _IxT(t, 0), 2, 0x01)
843#define ISP_NVRAM_TGT_TQING(c, t) ISPBSMX(c, _IxT(t, 0), 3, 0x01)
844#define ISP_NVRAM_TGT_SYNC(c, t) ISPBSMX(c, _IxT(t, 0), 4, 0x01)
845#define ISP_NVRAM_TGT_WIDE(c, t) ISPBSMX(c, _IxT(t, 0), 5, 0x01)
846#define ISP_NVRAM_TGT_PARITY(c, t) ISPBSMX(c, _IxT(t, 0), 6, 0x01)
847#define ISP_NVRAM_TGT_DISC(c, t) ISPBSMX(c, _IxT(t, 0), 7, 0x01)
848#define ISP_NVRAM_TGT_EXEC_THROTTLE(c, t) ISPBSMX(c, _IxT(t, 1), 0, 0xff)
849#define ISP_NVRAM_TGT_SYNC_PERIOD(c, t) ISPBSMX(c, _IxT(t, 2), 0, 0xff)
850#define ISP_NVRAM_TGT_SYNC_OFFSET(c, t) ISPBSMX(c, _IxT(t, 3), 0, 0x0f)
851#define ISP_NVRAM_TGT_DEVICE_ENABLE(c, t) ISPBSMX(c, _IxT(t, 3), 4, 0x01)
852#define ISP_NVRAM_TGT_LUN_DISABLE(c, t) ISPBSMX(c, _IxT(t, 3), 5, 0x01)
853
854/*
855 * Qlogic 1080/1240 NVRAM is an array of 256 bytes.
856 *
857 * Some portion of the front of this is for general host adapter properties
858 * This is followed by an array of per-target parameters, and is tailed off
859 * with a checksum xor byte at offset 256. For non-byte entities data is
860 * stored in Little Endian order.
861 */
862
863#define ISP1080_NVRAM_SIZE 256
864
865#define ISP1080_NVRAM_VERSION(c) ISP_NVRAM_VERSION(c)
866
867/* Offset 5 */
868/*
869 uint8_t bios_configuration_mode :2;
870 uint8_t bios_disable :1;
871 uint8_t selectable_scsi_boot_enable :1;
872 uint8_t cd_rom_boot_enable :1;
873 uint8_t disable_loading_risc_code :1;
874 uint8_t enable_64bit_addressing :1;
875 uint8_t unused_7 :1;
876 */
877
878/* Offsets 6, 7 */
879/*
880 uint8_t boot_lun_number :5;
881 uint8_t scsi_bus_number :1;
882 uint8_t unused_6 :1;
883 uint8_t unused_7 :1;
884 uint8_t boot_target_number :4;
885 uint8_t unused_12 :1;
886 uint8_t unused_13 :1;
887 uint8_t unused_14 :1;
888 uint8_t unused_15 :1;
889 */
890
891#define ISP1080_NVRAM_HBA_ENABLE(c) ISPBSMX(c, 16, 3, 0x01)
892
893#define ISP1080_NVRAM_BURST_ENABLE(c) ISPBSMX(c, 16, 1, 0x01)
894#define ISP1080_NVRAM_FIFO_THRESHOLD(c) ISPBSMX(c, 16, 4, 0x0f)
895
896#define ISP1080_NVRAM_AUTO_TERM_SUPPORT(c) ISPBSMX(c, 17, 7, 0x01)
897#define ISP1080_NVRAM_BUS0_TERM_MODE(c) ISPBSMX(c, 17, 0, 0x03)
898#define ISP1080_NVRAM_BUS1_TERM_MODE(c) ISPBSMX(c, 17, 2, 0x03)
899
900#define ISP1080_ISP_PARAMETER(c) \
901 (((c)[18]) | ((c)[19] << 8))
902
903#define ISP1080_FAST_POST(c) ISPBSMX(c, 20, 0, 0x01)
904#define ISP1080_REPORT_LVD_TRANSITION(c) ISPBSMX(c, 20, 1, 0x01)
905
906#define ISP1080_BUS1_OFF 112
907
908#define ISP1080_NVRAM_INITIATOR_ID(c, b) \
909 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 24, 0, 0x0f)
910#define ISP1080_NVRAM_BUS_RESET_DELAY(c, b) \
911 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 25]
912#define ISP1080_NVRAM_BUS_RETRY_COUNT(c, b) \
913 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 26]
914#define ISP1080_NVRAM_BUS_RETRY_DELAY(c, b) \
915 (c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 27]
916
917#define ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME(c, b) \
918 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 0, 0x0f)
919#define ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION(c, b) \
920 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 4, 0x01)
921#define ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION(c, b) \
922 ISPBSMX(c, ((b == 0)? 0 : ISP1080_BUS1_OFF) + 28, 5, 0x01)
923#define ISP1080_NVRAM_SELECTION_TIMEOUT(c, b) \
924 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 30]) | \
925 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 31] << 8))
926#define ISP1080_NVRAM_MAX_QUEUE_DEPTH(c, b) \
927 (((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 32]) | \
928 ((c)[((b == 0)? 0 : ISP1080_BUS1_OFF) + 33] << 8))
929
930#define ISP1080_NVRAM_TARGOFF(b) \
931 ((b == 0)? 40: (40 + ISP1080_BUS1_OFF))
932#define ISP1080_NVRAM_TARGSIZE 6
933#define _IxT8(tgt, tidx, b) \
934 (ISP1080_NVRAM_TARGOFF((b)) + (ISP1080_NVRAM_TARGSIZE * (tgt)) + (tidx))
935
936#define ISP1080_NVRAM_TGT_RENEG(c, t, b) \
937 ISPBSMX(c, _IxT8(t, 0, (b)), 0, 0x01)
938#define ISP1080_NVRAM_TGT_QFRZ(c, t, b) \
939 ISPBSMX(c, _IxT8(t, 0, (b)), 1, 0x01)
940#define ISP1080_NVRAM_TGT_ARQ(c, t, b) \
941 ISPBSMX(c, _IxT8(t, 0, (b)), 2, 0x01)
942#define ISP1080_NVRAM_TGT_TQING(c, t, b) \
943 ISPBSMX(c, _IxT8(t, 0, (b)), 3, 0x01)
944#define ISP1080_NVRAM_TGT_SYNC(c, t, b) \
945 ISPBSMX(c, _IxT8(t, 0, (b)), 4, 0x01)
946#define ISP1080_NVRAM_TGT_WIDE(c, t, b) \
947 ISPBSMX(c, _IxT8(t, 0, (b)), 5, 0x01)
948#define ISP1080_NVRAM_TGT_PARITY(c, t, b) \
949 ISPBSMX(c, _IxT8(t, 0, (b)), 6, 0x01)
950#define ISP1080_NVRAM_TGT_DISC(c, t, b) \
951 ISPBSMX(c, _IxT8(t, 0, (b)), 7, 0x01)
952#define ISP1080_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
953 ISPBSMX(c, _IxT8(t, 1, (b)), 0, 0xff)
954#define ISP1080_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
955 ISPBSMX(c, _IxT8(t, 2, (b)), 0, 0xff)
956#define ISP1080_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
957 ISPBSMX(c, _IxT8(t, 3, (b)), 0, 0x0f)
958#define ISP1080_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
959 ISPBSMX(c, _IxT8(t, 3, (b)), 4, 0x01)
960#define ISP1080_NVRAM_TGT_LUN_DISABLE(c, t, b) \
961 ISPBSMX(c, _IxT8(t, 3, (b)), 5, 0x01)
962
963#define ISP12160_NVRAM_HBA_ENABLE ISP1080_NVRAM_HBA_ENABLE
964#define ISP12160_NVRAM_BURST_ENABLE ISP1080_NVRAM_BURST_ENABLE
965#define ISP12160_NVRAM_FIFO_THRESHOLD ISP1080_NVRAM_FIFO_THRESHOLD
966#define ISP12160_NVRAM_AUTO_TERM_SUPPORT ISP1080_NVRAM_AUTO_TERM_SUPPORT
967#define ISP12160_NVRAM_BUS0_TERM_MODE ISP1080_NVRAM_BUS0_TERM_MODE
968#define ISP12160_NVRAM_BUS1_TERM_MODE ISP1080_NVRAM_BUS1_TERM_MODE
969#define ISP12160_ISP_PARAMETER ISP12160_ISP_PARAMETER
970#define ISP12160_FAST_POST ISP1080_FAST_POST
971#define ISP12160_REPORT_LVD_TRANSITION ISP1080_REPORT_LVD_TRANSTION
972
973#define ISP12160_NVRAM_INITIATOR_ID \
974 ISP1080_NVRAM_INITIATOR_ID
975#define ISP12160_NVRAM_BUS_RESET_DELAY \
976 ISP1080_NVRAM_BUS_RESET_DELAY
977#define ISP12160_NVRAM_BUS_RETRY_COUNT \
978 ISP1080_NVRAM_BUS_RETRY_COUNT
979#define ISP12160_NVRAM_BUS_RETRY_DELAY \
980 ISP1080_NVRAM_BUS_RETRY_DELAY
981#define ISP12160_NVRAM_ASYNC_DATA_SETUP_TIME \
982 ISP1080_NVRAM_ASYNC_DATA_SETUP_TIME
983#define ISP12160_NVRAM_REQ_ACK_ACTIVE_NEGATION \
984 ISP1080_NVRAM_REQ_ACK_ACTIVE_NEGATION
985#define ISP12160_NVRAM_DATA_LINE_ACTIVE_NEGATION \
986 ISP1080_NVRAM_DATA_LINE_ACTIVE_NEGATION
987#define ISP12160_NVRAM_SELECTION_TIMEOUT \
988 ISP1080_NVRAM_SELECTION_TIMEOUT
989#define ISP12160_NVRAM_MAX_QUEUE_DEPTH \
990 ISP1080_NVRAM_MAX_QUEUE_DEPTH
991
992
993#define ISP12160_BUS0_OFF 24
994#define ISP12160_BUS1_OFF 136
995
996#define ISP12160_NVRAM_TARGOFF(b) \
997 (((b == 0)? ISP12160_BUS0_OFF : ISP12160_BUS1_OFF) + 16)
998
999#define ISP12160_NVRAM_TARGSIZE 6
1000#define _IxT16(tgt, tidx, b) \
1001 (ISP12160_NVRAM_TARGOFF((b))+(ISP12160_NVRAM_TARGSIZE * (tgt))+(tidx))
1002
1003#define ISP12160_NVRAM_TGT_RENEG(c, t, b) \
1004 ISPBSMX(c, _IxT16(t, 0, (b)), 0, 0x01)
1005#define ISP12160_NVRAM_TGT_QFRZ(c, t, b) \
1006 ISPBSMX(c, _IxT16(t, 0, (b)), 1, 0x01)
1007#define ISP12160_NVRAM_TGT_ARQ(c, t, b) \
1008 ISPBSMX(c, _IxT16(t, 0, (b)), 2, 0x01)
1009#define ISP12160_NVRAM_TGT_TQING(c, t, b) \
1010 ISPBSMX(c, _IxT16(t, 0, (b)), 3, 0x01)
1011#define ISP12160_NVRAM_TGT_SYNC(c, t, b) \
1012 ISPBSMX(c, _IxT16(t, 0, (b)), 4, 0x01)
1013#define ISP12160_NVRAM_TGT_WIDE(c, t, b) \
1014 ISPBSMX(c, _IxT16(t, 0, (b)), 5, 0x01)
1015#define ISP12160_NVRAM_TGT_PARITY(c, t, b) \
1016 ISPBSMX(c, _IxT16(t, 0, (b)), 6, 0x01)
1017#define ISP12160_NVRAM_TGT_DISC(c, t, b) \
1018 ISPBSMX(c, _IxT16(t, 0, (b)), 7, 0x01)
1019
1020#define ISP12160_NVRAM_TGT_EXEC_THROTTLE(c, t, b) \
1021 ISPBSMX(c, _IxT16(t, 1, (b)), 0, 0xff)
1022#define ISP12160_NVRAM_TGT_SYNC_PERIOD(c, t, b) \
1023 ISPBSMX(c, _IxT16(t, 2, (b)), 0, 0xff)
1024
1025#define ISP12160_NVRAM_TGT_SYNC_OFFSET(c, t, b) \
1026 ISPBSMX(c, _IxT16(t, 3, (b)), 0, 0x1f)
1027#define ISP12160_NVRAM_TGT_DEVICE_ENABLE(c, t, b) \
1028 ISPBSMX(c, _IxT16(t, 3, (b)), 5, 0x01)
1029
1030#define ISP12160_NVRAM_PPR_OPTIONS(c, t, b) \
1031 ISPBSMX(c, _IxT16(t, 4, (b)), 0, 0x0f)
1032#define ISP12160_NVRAM_PPR_WIDTH(c, t, b) \
1033 ISPBSMX(c, _IxT16(t, 4, (b)), 4, 0x03)
1034#define ISP12160_NVRAM_PPR_ENABLE(c, t, b) \
1035 ISPBSMX(c, _IxT16(t, 4, (b)), 7, 0x01)
1036
1037/*
1038 * Qlogic 2100 thru 2300 NVRAM is an array of 256 bytes.
1039 *
1040 * Some portion of the front of this is for general RISC engine parameters,
1041 * mostly reflecting the state of the last INITIALIZE FIRMWARE mailbox command.
1042 *
1043 * This is followed by some general host adapter parameters, and ends with
1044 * a checksum xor byte at offset 255. For non-byte entities data is stored
1045 * in Little Endian order.
1046 */
1047#define ISP2100_NVRAM_SIZE 256
1048/* ISP_NVRAM_VERSION is in same overall place */
1049#define ISP2100_NVRAM_RISCVER(c) (c)[6]
1050#define ISP2100_NVRAM_OPTIONS(c) ((c)[8] | ((c)[9] << 8))
1051#define ISP2100_NVRAM_MAXFRAMELENGTH(c) (((c)[10]) | ((c)[11] << 8))
1052#define ISP2100_NVRAM_MAXIOCBALLOCATION(c) (((c)[12]) | ((c)[13] << 8))
1053#define ISP2100_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1054#define ISP2100_NVRAM_RETRY_COUNT(c) (c)[16]
1055#define ISP2100_NVRAM_RETRY_DELAY(c) (c)[17]
1056
1057#define ISP2100_NVRAM_PORT_NAME(c) (\
1058 (((uint64_t)(c)[18]) << 56) | \
1059 (((uint64_t)(c)[19]) << 48) | \
1060 (((uint64_t)(c)[20]) << 40) | \
1061 (((uint64_t)(c)[21]) << 32) | \
1062 (((uint64_t)(c)[22]) << 24) | \
1063 (((uint64_t)(c)[23]) << 16) | \
1064 (((uint64_t)(c)[24]) << 8) | \
1065 (((uint64_t)(c)[25]) << 0))
1066
1067#define ISP2100_NVRAM_HARDLOOPID(c) ((c)[26] | ((c)[27] << 8))
1068#define ISP2100_NVRAM_TOV(c) ((c)[29])
1069
1070#define ISP2100_NVRAM_NODE_NAME(c) (\
1071 (((uint64_t)(c)[30]) << 56) | \
1072 (((uint64_t)(c)[31]) << 48) | \
1073 (((uint64_t)(c)[32]) << 40) | \
1074 (((uint64_t)(c)[33]) << 32) | \
1075 (((uint64_t)(c)[34]) << 24) | \
1076 (((uint64_t)(c)[35]) << 16) | \
1077 (((uint64_t)(c)[36]) << 8) | \
1078 (((uint64_t)(c)[37]) << 0))
1079
1080#define ISP2100_XFW_OPTIONS(c) ((c)[38] | ((c)[39] << 8))
1081
1082#define ISP2100_RACC_TIMER(c) (c)[40]
1083#define ISP2100_IDELAY_TIMER(c) (c)[41]
1084
1085#define ISP2100_ZFW_OPTIONS(c) ((c)[42] | ((c)[43] << 8))
1086
1087#define ISP2100_SERIAL_LINK(c) ((c)[68] | ((c)[69] << 8))
1088
1089#define ISP2100_NVRAM_HBA_OPTIONS(c) ((c)[70] | ((c)[71] << 8))
1090#define ISP2100_NVRAM_HBA_DISABLE(c) ISPBSMX(c, 70, 0, 0x01)
1091#define ISP2100_NVRAM_BIOS_DISABLE(c) ISPBSMX(c, 70, 1, 0x01)
1092#define ISP2100_NVRAM_LUN_DISABLE(c) ISPBSMX(c, 70, 2, 0x01)
1093#define ISP2100_NVRAM_ENABLE_SELECT_BOOT(c) ISPBSMX(c, 70, 3, 0x01)
1094#define ISP2100_NVRAM_DISABLE_CODELOAD(c) ISPBSMX(c, 70, 4, 0x01)
1095#define ISP2100_NVRAM_SET_CACHELINESZ(c) ISPBSMX(c, 70, 5, 0x01)
1096
1097#define ISP2100_NVRAM_BOOT_NODE_NAME(c) (\
1098 (((uint64_t)(c)[72]) << 56) | \
1099 (((uint64_t)(c)[73]) << 48) | \
1100 (((uint64_t)(c)[74]) << 40) | \
1101 (((uint64_t)(c)[75]) << 32) | \
1102 (((uint64_t)(c)[76]) << 24) | \
1103 (((uint64_t)(c)[77]) << 16) | \
1104 (((uint64_t)(c)[78]) << 8) | \
1105 (((uint64_t)(c)[79]) << 0))
1106
1107#define ISP2100_NVRAM_BOOT_LUN(c) (c)[80]
1108#define ISP2100_RESET_DELAY(c) (c)[81]
1109
1110#define ISP2100_HBA_FEATURES(c) ((c)[232] | ((c)[233] << 8))
1111
1112/*
1113 * Qlogic 2400 NVRAM is an array of 512 bytes with a 32 bit checksum.
1114 */
1115#define ISP2400_NVRAM_PORT0_ADDR 0x80
1116#define ISP2400_NVRAM_PORT1_ADDR 0x180
1117#define ISP2400_NVRAM_SIZE 512
1118
1119#define ISP2400_NVRAM_VERSION(c) ((c)[4] | ((c)[5] << 8))
1120#define ISP2400_NVRAM_MAXFRAMELENGTH(c) (((c)[12]) | ((c)[13] << 8))
1121#define ISP2400_NVRAM_EXECUTION_THROTTLE(c) (((c)[14]) | ((c)[15] << 8))
1122#define ISP2400_NVRAM_EXCHANGE_COUNT(c) (((c)[16]) | ((c)[17] << 8))
1123#define ISP2400_NVRAM_HARDLOOPID(c) ((c)[18] | ((c)[19] << 8))
1124
1125#define ISP2400_NVRAM_PORT_NAME(c) (\
1126 (((uint64_t)(c)[20]) << 56) | \
1127 (((uint64_t)(c)[21]) << 48) | \
1128 (((uint64_t)(c)[22]) << 40) | \
1129 (((uint64_t)(c)[23]) << 32) | \
1130 (((uint64_t)(c)[24]) << 24) | \
1131 (((uint64_t)(c)[25]) << 16) | \
1132 (((uint64_t)(c)[26]) << 8) | \
1133 (((uint64_t)(c)[27]) << 0))
1134
1135#define ISP2400_NVRAM_NODE_NAME(c) (\
1136 (((uint64_t)(c)[28]) << 56) | \
1137 (((uint64_t)(c)[29]) << 48) | \
1138 (((uint64_t)(c)[30]) << 40) | \
1139 (((uint64_t)(c)[31]) << 32) | \
1140 (((uint64_t)(c)[32]) << 24) | \
1141 (((uint64_t)(c)[33]) << 16) | \
1142 (((uint64_t)(c)[34]) << 8) | \
1143 (((uint64_t)(c)[35]) << 0))
1144
1145#define ISP2400_NVRAM_LOGIN_RETRY_CNT(c) ((c)[36] | ((c)[37] << 8))
1146#define ISP2400_NVRAM_LINK_DOWN_ON_NOS(c) ((c)[38] | ((c)[39] << 8))
1147#define ISP2400_NVRAM_INTERRUPT_DELAY(c) ((c)[40] | ((c)[41] << 8))
1148#define ISP2400_NVRAM_LOGIN_TIMEOUT(c) ((c)[42] | ((c)[43] << 8))
1149
1150#define ISP2400_NVRAM_FIRMWARE_OPTIONS1(c) \
1151 ((c)[44] | ((c)[45] << 8) | ((c)[46] << 16) | ((c)[47] << 24))
1152#define ISP2400_NVRAM_FIRMWARE_OPTIONS2(c) \
1153 ((c)[48] | ((c)[49] << 8) | ((c)[50] << 16) | ((c)[51] << 24))
1154#define ISP2400_NVRAM_FIRMWARE_OPTIONS3(c) \
1155 ((c)[52] | ((c)[53] << 8) | ((c)[54] << 16) | ((c)[55] << 24))
1156
1157/*
1158 * Firmware Crash Dump
1159 *
1160 * QLogic needs specific information format when they look at firmware crashes.
1161 *
1162 * This is incredibly kernel memory consumptive (to say the least), so this
1163 * code is only compiled in when needed.
1164 */
1165
1166#define QLA2200_RISC_IMAGE_DUMP_SIZE \
1167 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1168 (352 * sizeof (uint16_t)) + /* RISC registers */ \
1169 (61440 * sizeof (uint16_t)) /* RISC SRAM (offset 0x1000..0xffff) */
1170#define QLA2300_RISC_IMAGE_DUMP_SIZE \
1171 (1 * sizeof (uint16_t)) + /* 'used' flag (also HBA type) */ \
1172 (464 * sizeof (uint16_t)) + /* RISC registers */ \
1173 (63488 * sizeof (uint16_t)) + /* RISC SRAM (0x0800..0xffff) */ \
1174 (4096 * sizeof (uint16_t)) + /* RISC SRAM (0x10000..0x10FFF) */ \
1175 (61440 * sizeof (uint16_t)) /* RISC SRAM (0x11000..0x1FFFF) */
1176/* the larger of the two */
1177#define ISP_CRASH_IMAGE_SIZE QLA2300_RISC_IMAGE_DUMP_SIZE
1178#endif /* _ISPREG_H */