1/* $FreeBSD: stable/10/sys/dev/isp/ispreg.h 290785 2015-11-13 19:42:55Z mav $ */
2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
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120#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */
121#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */
122
123#define BIU_R2HSTSLO (BIU_BLOCK+0x18)
124#define BIU_R2HSTSHI (BIU_BLOCK+0x1A)
125
126#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
127#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
128#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
129#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
130#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
131#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
132#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
133#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
134#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
135#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
136#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
137#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
138#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
139#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
140#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
141#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
142
143/* fifo command stuff- mostly for SPI */
144#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
145#define RDMA2100_CONTROL DFIFO_COMMAND
146#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
147
148/*
149 * Putzed DMA register layouts.
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244#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
245#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
246#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
247#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
248#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
249#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
250#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
251
252#define INT_PENDING_MASK(isp) \
253 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \
254 (BIU_ISR_RISC_INT))
255
256/* BUS SEMAPHORE REGISTER */
257#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
258#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
259
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391
392/* BIU2400_ICR definitions */
393#define BIU2400_ICR_ENA_RISC_INT 0x8
394#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
395
396/* BIU2400_ISR definitions */
397#define BIU2400_ISR_RISC_INT 0x8
398
399/* BIU2400_HCCR definitions */
400
401#define HCCR_2400_CMD_NOP 0x00000000
402#define HCCR_2400_CMD_RESET 0x10000000
403#define HCCR_2400_CMD_CLEAR_RESET 0x20000000
404#define HCCR_2400_CMD_PAUSE 0x30000000
405#define HCCR_2400_CMD_RELEASE 0x40000000
406#define HCCR_2400_CMD_SET_HOST_INT 0x50000000
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2/*-
3 * Copyright (c) 1997-2009 by Matthew Jacob
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
--- 110 unchanged lines hidden (view full) ---
120#define BIU_RSPINP (BIU_BLOCK+0x14) /* Response Queue In */
121#define BIU_RSPOUTP (BIU_BLOCK+0x16) /* Response Queue Out */
122
123#define BIU_R2HSTSLO (BIU_BLOCK+0x18)
124#define BIU_R2HSTSHI (BIU_BLOCK+0x1A)
125
126#define BIU_R2HST_INTR (1 << 15) /* RISC to Host Interrupt */
127#define BIU_R2HST_PAUSED (1 << 8) /* RISC paused */
128#define BIU_R2HST_ISTAT_MASK 0xff /* intr information && status */
129#define ISPR2HST_ROM_MBX_OK 0x1 /* ROM mailbox cmd done ok */
130#define ISPR2HST_ROM_MBX_FAIL 0x2 /* ROM mailbox cmd done fail */
131#define ISPR2HST_MBX_OK 0x10 /* mailbox cmd done ok */
132#define ISPR2HST_MBX_FAIL 0x11 /* mailbox cmd done fail */
133#define ISPR2HST_ASYNC_EVENT 0x12 /* Async Event */
134#define ISPR2HST_RSPQ_UPDATE 0x13 /* Response Queue Update */
135#define ISPR2HST_RSPQ_UPDATE2 0x14 /* Response Queue Update */
136#define ISPR2HST_RIO_16 0x15 /* RIO 1-16 */
137#define ISPR2HST_FPOST 0x16 /* Low 16 bits fast post */
138#define ISPR2HST_FPOST_CTIO 0x17 /* Low 16 bits fast post ctio */
139#define ISPR2HST_ATIO_UPDATE 0x1C /* ATIO Queue Update */
140#define ISPR2HST_ATIO_RSPQ_UPDATE 0x1D /* ATIO & Request Update */
141#define ISPR2HST_ATIO_UPDATE2 0x1E /* ATIO Queue Update */
142
143/* fifo command stuff- mostly for SPI */
144#define DFIFO_COMMAND (BIU_BLOCK+0x60) /* RW : Command FIFO Port */
145#define RDMA2100_CONTROL DFIFO_COMMAND
146#define DFIFO_DATA (BIU_BLOCK+0x62) /* RW : Data FIFO Port */
147
148/*
149 * Putzed DMA register layouts.
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244#define BIU2100_ISR_INT_PENDING 0x8000 /* Global interrupt pending */
245#define BIU2100_ISR_FPM_INT 0x0020 /* FPM interrupt pending */
246#define BIU2100_ISR_FB_INT 0x0010 /* FB interrupt pending */
247#define BIU2100_ISR_RISC_INT 0x0008 /* Risc interrupt pending */
248#define BIU2100_ISR_CDMA_INT 0x0004 /* CDMA interrupt pending */
249#define BIU2100_ISR_RXDMA_INT_PENDING 0x0002 /* Global interrupt pending */
250#define BIU2100_ISR_TXDMA_INT_PENDING 0x0001 /* Global interrupt pending */
251
252#define INT_PENDING_MASK(isp) \
253 (IS_FC(isp)? (IS_24XX(isp)? BIU2400_ISR_RISC_INT : BIU2100_ISR_RISC_INT) : \
254 (BIU_ISR_RISC_INT))
255
256/* BUS SEMAPHORE REGISTER */
257#define BIU_SEMA_STATUS 0x0002 /* Semaphore Status Bit */
258#define BIU_SEMA_LOCK 0x0001 /* Semaphore Lock Bit */
259
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391
392/* BIU2400_ICR definitions */
393#define BIU2400_ICR_ENA_RISC_INT 0x8
394#define BIU2400_IMASK (BIU2400_ICR_ENA_RISC_INT)
395
396/* BIU2400_ISR definitions */
397#define BIU2400_ISR_RISC_INT 0x8
398
399/* BIU2400_HCCR definitions */
400
401#define HCCR_2400_CMD_NOP 0x00000000
402#define HCCR_2400_CMD_RESET 0x10000000
403#define HCCR_2400_CMD_CLEAR_RESET 0x20000000
404#define HCCR_2400_CMD_PAUSE 0x30000000
405#define HCCR_2400_CMD_RELEASE 0x40000000
406#define HCCR_2400_CMD_SET_HOST_INT 0x50000000
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