1/* $FreeBSD: head/sys/dev/isp/ispmbox.h 151834 2005-10-29 02:46:59Z mjacob $ */
| 1/* $FreeBSD: head/sys/dev/isp/ispmbox.h 154704 2006-01-23 06:23:37Z mjacob $ */
|
2/*-
3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
4 *
| 2/*-
3 * Mailbox and Queue Entry Definitions for for Qlogic ISP SCSI adapters.
4 *
|
5 * Copyright (c) 1997, 1998, 1999, 2000 by Matthew Jacob
| 5 * Copyright (c) 1997-2006 by Matthew Jacob
|
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice immediately at the beginning of the file, without modification,
13 * this list of conditions, and the following disclaimer.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30#ifndef _ISPMBOX_H
31#define _ISPMBOX_H
32
33/*
34 * Mailbox Command Opcodes
35 */
36#define MBOX_NO_OP 0x0000
37#define MBOX_LOAD_RAM 0x0001
38#define MBOX_EXEC_FIRMWARE 0x0002
39#define MBOX_DUMP_RAM 0x0003
40#define MBOX_WRITE_RAM_WORD 0x0004
41#define MBOX_READ_RAM_WORD 0x0005
42#define MBOX_MAILBOX_REG_TEST 0x0006
43#define MBOX_VERIFY_CHECKSUM 0x0007
44#define MBOX_ABOUT_FIRMWARE 0x0008
45 /* 9 */
46 /* a */
47 /* b */
48 /* c */
49 /* d */
50#define MBOX_CHECK_FIRMWARE 0x000e
51#define MBOX_READ_RAM_WORD_EXTENDED 0x000f
52#define MBOX_INIT_REQ_QUEUE 0x0010
53#define MBOX_INIT_RES_QUEUE 0x0011
54#define MBOX_EXECUTE_IOCB 0x0012
55#define MBOX_WAKE_UP 0x0013
56#define MBOX_STOP_FIRMWARE 0x0014
57#define MBOX_ABORT 0x0015
58#define MBOX_ABORT_DEVICE 0x0016
59#define MBOX_ABORT_TARGET 0x0017
60#define MBOX_BUS_RESET 0x0018
61#define MBOX_STOP_QUEUE 0x0019
62#define MBOX_START_QUEUE 0x001a
63#define MBOX_SINGLE_STEP_QUEUE 0x001b
64#define MBOX_ABORT_QUEUE 0x001c
65#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
66 /* 1e */
67#define MBOX_GET_FIRMWARE_STATUS 0x001f
68#define MBOX_GET_INIT_SCSI_ID 0x0020
69#define MBOX_GET_SELECT_TIMEOUT 0x0021
70#define MBOX_GET_RETRY_COUNT 0x0022
71#define MBOX_GET_TAG_AGE_LIMIT 0x0023
72#define MBOX_GET_CLOCK_RATE 0x0024
73#define MBOX_GET_ACT_NEG_STATE 0x0025
74#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
75#define MBOX_GET_SBUS_PARAMS 0x0027
76#define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS
77#define MBOX_GET_TARGET_PARAMS 0x0028
78#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
79#define MBOX_GET_RESET_DELAY_PARAMS 0x002a
80 /* 2b */
81 /* 2c */
82 /* 2d */
83 /* 2e */
84 /* 2f */
85#define MBOX_SET_INIT_SCSI_ID 0x0030
86#define MBOX_SET_SELECT_TIMEOUT 0x0031
87#define MBOX_SET_RETRY_COUNT 0x0032
88#define MBOX_SET_TAG_AGE_LIMIT 0x0033
89#define MBOX_SET_CLOCK_RATE 0x0034
90#define MBOX_SET_ACT_NEG_STATE 0x0035
91#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
92#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
93#define MBOX_SET_PCI_PARAMETERS 0x0037
94#define MBOX_SET_TARGET_PARAMS 0x0038
95#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
96#define MBOX_SET_RESET_DELAY_PARAMS 0x003a
97 /* 3b */
98 /* 3c */
99 /* 3d */
100 /* 3e */
101 /* 3f */
102#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
103#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
104#define MBOX_EXEC_BIOS_IOCB 0x0042
105#define MBOX_SET_FW_FEATURES 0x004a
106#define MBOX_GET_FW_FEATURES 0x004b
107#define FW_FEATURE_FAST_POST 0x1
108#define FW_FEATURE_LVD_NOTIFY 0x2
109#define FW_FEATURE_RIO_32BIT 0x4
110#define FW_FEATURE_RIO_16BIT 0x8
111
112#define MBOX_INIT_REQ_QUEUE_A64 0x0052
113#define MBOX_INIT_RES_QUEUE_A64 0x0053
114
115#define MBOX_ENABLE_TARGET_MODE 0x0055
116#define ENABLE_TARGET_FLAG 0x8000
117#define ENABLE_TQING_FLAG 0x0004
118#define ENABLE_MANDATORY_DISC 0x0002
119#define MBOX_GET_TARGET_STATUS 0x0056
120
121/* These are for the ISP2X00 FC cards */
122#define MBOX_GET_LOOP_ID 0x0020
123#define MBOX_GET_FIRMWARE_OPTIONS 0x0028
124#define MBOX_SET_FIRMWARE_OPTIONS 0x0038
125#define MBOX_GET_RESOURCE_COUNT 0x0042
126#define MBOX_ENHANCED_GET_PDB 0x0047
127#define MBOX_EXEC_COMMAND_IOCB_A64 0x0054
128#define MBOX_INIT_FIRMWARE 0x0060
129#define MBOX_GET_INIT_CONTROL_BLOCK 0x0061
130#define MBOX_INIT_LIP 0x0062
131#define MBOX_GET_FC_AL_POSITION_MAP 0x0063
132#define MBOX_GET_PORT_DB 0x0064
133#define MBOX_CLEAR_ACA 0x0065
134#define MBOX_TARGET_RESET 0x0066
135#define MBOX_CLEAR_TASK_SET 0x0067
136#define MBOX_ABORT_TASK_SET 0x0068
137#define MBOX_GET_FW_STATE 0x0069
138#define MBOX_GET_PORT_NAME 0x006A
139#define MBOX_GET_LINK_STATUS 0x006B
140#define MBOX_INIT_LIP_RESET 0x006C
141#define MBOX_SEND_SNS 0x006E
142#define MBOX_FABRIC_LOGIN 0x006F
143#define MBOX_SEND_CHANGE_REQUEST 0x0070
144#define MBOX_FABRIC_LOGOUT 0x0071
145#define MBOX_INIT_LIP_LOGIN 0x0072
146#define MBOX_LUN_RESET 0x007E
147
148#define MBOX_DRIVER_HEARTBEAT 0x005B
149#define MBOX_FW_HEARTBEAT 0x005C
150
151#define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */
152#define MBGSD_GET_RATE 0
153#define MBGSD_SET_RATE 1
154#define MBGSD_ONEGB 0
155#define MBGSD_TWOGB 1
156#define MBGSD_AUTO 2
157
158
159#define ISP2100_SET_PCI_PARAM 0x00ff
160
161#define MBOX_BUSY 0x04
162
| 6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice immediately at the beginning of the file, without modification,
13 * this list of conditions, and the following disclaimer.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30#ifndef _ISPMBOX_H
31#define _ISPMBOX_H
32
33/*
34 * Mailbox Command Opcodes
35 */
36#define MBOX_NO_OP 0x0000
37#define MBOX_LOAD_RAM 0x0001
38#define MBOX_EXEC_FIRMWARE 0x0002
39#define MBOX_DUMP_RAM 0x0003
40#define MBOX_WRITE_RAM_WORD 0x0004
41#define MBOX_READ_RAM_WORD 0x0005
42#define MBOX_MAILBOX_REG_TEST 0x0006
43#define MBOX_VERIFY_CHECKSUM 0x0007
44#define MBOX_ABOUT_FIRMWARE 0x0008
45 /* 9 */
46 /* a */
47 /* b */
48 /* c */
49 /* d */
50#define MBOX_CHECK_FIRMWARE 0x000e
51#define MBOX_READ_RAM_WORD_EXTENDED 0x000f
52#define MBOX_INIT_REQ_QUEUE 0x0010
53#define MBOX_INIT_RES_QUEUE 0x0011
54#define MBOX_EXECUTE_IOCB 0x0012
55#define MBOX_WAKE_UP 0x0013
56#define MBOX_STOP_FIRMWARE 0x0014
57#define MBOX_ABORT 0x0015
58#define MBOX_ABORT_DEVICE 0x0016
59#define MBOX_ABORT_TARGET 0x0017
60#define MBOX_BUS_RESET 0x0018
61#define MBOX_STOP_QUEUE 0x0019
62#define MBOX_START_QUEUE 0x001a
63#define MBOX_SINGLE_STEP_QUEUE 0x001b
64#define MBOX_ABORT_QUEUE 0x001c
65#define MBOX_GET_DEV_QUEUE_STATUS 0x001d
66 /* 1e */
67#define MBOX_GET_FIRMWARE_STATUS 0x001f
68#define MBOX_GET_INIT_SCSI_ID 0x0020
69#define MBOX_GET_SELECT_TIMEOUT 0x0021
70#define MBOX_GET_RETRY_COUNT 0x0022
71#define MBOX_GET_TAG_AGE_LIMIT 0x0023
72#define MBOX_GET_CLOCK_RATE 0x0024
73#define MBOX_GET_ACT_NEG_STATE 0x0025
74#define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
75#define MBOX_GET_SBUS_PARAMS 0x0027
76#define MBOX_GET_PCI_PARAMS MBOX_GET_SBUS_PARAMS
77#define MBOX_GET_TARGET_PARAMS 0x0028
78#define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
79#define MBOX_GET_RESET_DELAY_PARAMS 0x002a
80 /* 2b */
81 /* 2c */
82 /* 2d */
83 /* 2e */
84 /* 2f */
85#define MBOX_SET_INIT_SCSI_ID 0x0030
86#define MBOX_SET_SELECT_TIMEOUT 0x0031
87#define MBOX_SET_RETRY_COUNT 0x0032
88#define MBOX_SET_TAG_AGE_LIMIT 0x0033
89#define MBOX_SET_CLOCK_RATE 0x0034
90#define MBOX_SET_ACT_NEG_STATE 0x0035
91#define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
92#define MBOX_SET_SBUS_CONTROL_PARAMS 0x0037
93#define MBOX_SET_PCI_PARAMETERS 0x0037
94#define MBOX_SET_TARGET_PARAMS 0x0038
95#define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
96#define MBOX_SET_RESET_DELAY_PARAMS 0x003a
97 /* 3b */
98 /* 3c */
99 /* 3d */
100 /* 3e */
101 /* 3f */
102#define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
103#define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
104#define MBOX_EXEC_BIOS_IOCB 0x0042
105#define MBOX_SET_FW_FEATURES 0x004a
106#define MBOX_GET_FW_FEATURES 0x004b
107#define FW_FEATURE_FAST_POST 0x1
108#define FW_FEATURE_LVD_NOTIFY 0x2
109#define FW_FEATURE_RIO_32BIT 0x4
110#define FW_FEATURE_RIO_16BIT 0x8
111
112#define MBOX_INIT_REQ_QUEUE_A64 0x0052
113#define MBOX_INIT_RES_QUEUE_A64 0x0053
114
115#define MBOX_ENABLE_TARGET_MODE 0x0055
116#define ENABLE_TARGET_FLAG 0x8000
117#define ENABLE_TQING_FLAG 0x0004
118#define ENABLE_MANDATORY_DISC 0x0002
119#define MBOX_GET_TARGET_STATUS 0x0056
120
121/* These are for the ISP2X00 FC cards */
122#define MBOX_GET_LOOP_ID 0x0020
123#define MBOX_GET_FIRMWARE_OPTIONS 0x0028
124#define MBOX_SET_FIRMWARE_OPTIONS 0x0038
125#define MBOX_GET_RESOURCE_COUNT 0x0042
126#define MBOX_ENHANCED_GET_PDB 0x0047
127#define MBOX_EXEC_COMMAND_IOCB_A64 0x0054
128#define MBOX_INIT_FIRMWARE 0x0060
129#define MBOX_GET_INIT_CONTROL_BLOCK 0x0061
130#define MBOX_INIT_LIP 0x0062
131#define MBOX_GET_FC_AL_POSITION_MAP 0x0063
132#define MBOX_GET_PORT_DB 0x0064
133#define MBOX_CLEAR_ACA 0x0065
134#define MBOX_TARGET_RESET 0x0066
135#define MBOX_CLEAR_TASK_SET 0x0067
136#define MBOX_ABORT_TASK_SET 0x0068
137#define MBOX_GET_FW_STATE 0x0069
138#define MBOX_GET_PORT_NAME 0x006A
139#define MBOX_GET_LINK_STATUS 0x006B
140#define MBOX_INIT_LIP_RESET 0x006C
141#define MBOX_SEND_SNS 0x006E
142#define MBOX_FABRIC_LOGIN 0x006F
143#define MBOX_SEND_CHANGE_REQUEST 0x0070
144#define MBOX_FABRIC_LOGOUT 0x0071
145#define MBOX_INIT_LIP_LOGIN 0x0072
146#define MBOX_LUN_RESET 0x007E
147
148#define MBOX_DRIVER_HEARTBEAT 0x005B
149#define MBOX_FW_HEARTBEAT 0x005C
150
151#define MBOX_GET_SET_DATA_RATE 0x005D /* 23XX only */
152#define MBGSD_GET_RATE 0
153#define MBGSD_SET_RATE 1
154#define MBGSD_ONEGB 0
155#define MBGSD_TWOGB 1
156#define MBGSD_AUTO 2
157
158
159#define ISP2100_SET_PCI_PARAM 0x00ff
160
161#define MBOX_BUSY 0x04
162
|
163typedef struct {
164 u_int16_t param[8];
165} mbreg_t;
166
| |
167/*
168 * Mailbox Command Complete Status Codes
169 */
170#define MBOX_COMMAND_COMPLETE 0x4000
171#define MBOX_INVALID_COMMAND 0x4001
172#define MBOX_HOST_INTERFACE_ERROR 0x4002
173#define MBOX_TEST_FAILED 0x4003
174#define MBOX_COMMAND_ERROR 0x4005
175#define MBOX_COMMAND_PARAM_ERROR 0x4006
176#define MBOX_PORT_ID_USED 0x4007
177#define MBOX_LOOP_ID_USED 0x4008
178#define MBOX_ALL_IDS_USED 0x4009
179#define MBOX_NOT_LOGGED_IN 0x400A
180#define MBLOGALL 0x000f
181#define MBLOGNONE 0x0000
182#define MBLOGMASK(x) ((x) & 0xf)
183
184/*
185 * Asynchronous event status codes
186 */
187#define ASYNC_BUS_RESET 0x8001
188#define ASYNC_SYSTEM_ERROR 0x8002
189#define ASYNC_RQS_XFER_ERR 0x8003
190#define ASYNC_RSP_XFER_ERR 0x8004
191#define ASYNC_QWAKEUP 0x8005
192#define ASYNC_TIMEOUT_RESET 0x8006
193#define ASYNC_DEVICE_RESET 0x8007
194#define ASYNC_EXTMSG_UNDERRUN 0x800A
195#define ASYNC_SCAM_INT 0x800B
196#define ASYNC_HUNG_SCSI 0x800C
197#define ASYNC_KILLED_BUS 0x800D
198#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
199#define ASYNC_LIP_OCCURRED 0x8010
200#define ASYNC_LOOP_UP 0x8011
201#define ASYNC_LOOP_DOWN 0x8012
202#define ASYNC_LOOP_RESET 0x8013
203#define ASYNC_PDB_CHANGED 0x8014
204#define ASYNC_CHANGE_NOTIFY 0x8015
205#define ASYNC_LIP_F8 0x8016
206#define ASYNC_CMD_CMPLT 0x8020
207#define ASYNC_CTIO_DONE 0x8021
208#define ASYNC_IP_XMIT_DONE 0x8022
209#define ASYNC_IP_RECV_DONE 0x8023
210#define ASYNC_IP_BROADCAST 0x8024
211#define ASYNC_IP_RCVQ_LOW 0x8025
212#define ASYNC_IP_RCVQ_EMPTY 0x8026
213#define ASYNC_IP_RECV_DONE_ALIGNED 0x8027
214#define ASYNC_PTPMODE 0x8030
215#define ASYNC_RIO1 0x8031
216#define ASYNC_RIO2 0x8032
217#define ASYNC_RIO3 0x8033
218#define ASYNC_RIO4 0x8034
219#define ASYNC_RIO5 0x8035
220#define ASYNC_CONNMODE 0x8036
221#define ISP_CONN_LOOP 1
222#define ISP_CONN_PTP 2
223#define ISP_CONN_BADLIP 3
224#define ISP_CONN_FATAL 4
225#define ISP_CONN_LOOPBACK 5
226#define ASYNC_RIO_RESP 0x8040
227#define ASYNC_RIO_COMP 0x8042
228/*
229 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options
230 * mailbox command to enable this.
231 */
232#define ASYNC_QFULL_SENT 0x8049
233
234/*
235 * Mailbox Usages
236 */
237
238#define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \
239 ISP_WRITE(isp, isp->isp_rqstinrp, value)
240
241#define READ_REQUEST_QUEUE_OUT_POINTER(isp) \
242 ISP_READ(isp, isp->isp_rqstoutrp)
243
244#define READ_RESPONSE_QUEUE_IN_POINTER(isp) \
245 ISP_READ(isp, isp->isp_respinrp)
246
247#define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \
248 ISP_WRITE(isp, isp->isp_respoutrp, value)
249
250/*
251 * Command Structure Definitions
252 */
253
254typedef struct {
255 u_int32_t ds_base;
256 u_int32_t ds_count;
257} ispds_t;
258
259typedef struct {
260 u_int32_t ds_base;
261 u_int32_t ds_basehi;
262 u_int32_t ds_count;
263} ispds64_t;
264
265#define DSTYPE_32BIT 0
266#define DSTYPE_64BIT 1
267typedef struct {
268 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */
269 u_int32_t ds_segment; /* unused */
270 u_int32_t ds_base; /* 32 bit address of DSD list */
271} ispdslist_t;
272
273
274/*
275 * These elements get swizzled around for SBus instances.
276 */
277#define ISP_SWAP8(a, b) { \
278 u_int8_t tmp; \
279 tmp = a; \
280 a = b; \
281 b = tmp; \
282}
283typedef struct {
284 u_int8_t rqs_entry_type;
285 u_int8_t rqs_entry_count;
286 u_int8_t rqs_seqno;
287 u_int8_t rqs_flags;
288} isphdr_t;
289
290/* RQS Flag definitions */
291#define RQSFLAG_CONTINUATION 0x01
292#define RQSFLAG_FULL 0x02
293#define RQSFLAG_BADHEADER 0x04
294#define RQSFLAG_BADPACKET 0x08
295
296/* RQS entry_type definitions */
297#define RQSTYPE_REQUEST 0x01
298#define RQSTYPE_DATASEG 0x02
299#define RQSTYPE_RESPONSE 0x03
300#define RQSTYPE_MARKER 0x04
301#define RQSTYPE_CMDONLY 0x05
302#define RQSTYPE_ATIO 0x06 /* Target Mode */
303#define RQSTYPE_CTIO 0x07 /* Target Mode */
304#define RQSTYPE_SCAM 0x08
305#define RQSTYPE_A64 0x09
306#define RQSTYPE_A64_CONT 0x0a
307#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
308#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
309#define RQSTYPE_NOTIFY 0x0d /* Target Mode */
310#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
311#define RQSTYPE_CTIO1 0x0f /* Target Mode */
312#define RQSTYPE_STATUS_CONT 0x10
313#define RQSTYPE_T2RQS 0x11
314#define RQSTYPE_IP_XMIT 0x13
315#define RQSTYPE_T4RQS 0x15
316#define RQSTYPE_ATIO2 0x16 /* Target Mode */
317#define RQSTYPE_CTIO2 0x17 /* Target Mode */
318#define RQSTYPE_CSET0 0x18
319#define RQSTYPE_T3RQS 0x19
320#define RQSTYPE_IP_XMIT_64 0x1b
321#define RQSTYPE_CTIO4 0x1e /* Target Mode */
322#define RQSTYPE_CTIO3 0x1f /* Target Mode */
323#define RQSTYPE_RIO1 0x21
324#define RQSTYPE_RIO2 0x22
325#define RQSTYPE_IP_RECV 0x23
326#define RQSTYPE_IP_RECV_CONT 0x24
327
328
329#define ISP_RQDSEG 4
330typedef struct {
331 isphdr_t req_header;
332 u_int32_t req_handle;
333 u_int8_t req_lun_trn;
334 u_int8_t req_target;
335 u_int16_t req_cdblen;
336#define req_modifier req_cdblen /* marker packet */
337 u_int16_t req_flags;
338 u_int16_t req_reserved;
339 u_int16_t req_time;
340 u_int16_t req_seg_count;
341 u_int8_t req_cdb[12];
342 ispds_t req_dataseg[ISP_RQDSEG];
343} ispreq_t;
344
345#define ispreq64_t ispreqt3_t /* same as.... */
346#define ISP_RQDSEG_A64 2
347
348/*
349 * A request packet can also be a marker packet.
350 */
351#define SYNC_DEVICE 0
352#define SYNC_TARGET 1
353#define SYNC_ALL 2
| 163/*
164 * Mailbox Command Complete Status Codes
165 */
166#define MBOX_COMMAND_COMPLETE 0x4000
167#define MBOX_INVALID_COMMAND 0x4001
168#define MBOX_HOST_INTERFACE_ERROR 0x4002
169#define MBOX_TEST_FAILED 0x4003
170#define MBOX_COMMAND_ERROR 0x4005
171#define MBOX_COMMAND_PARAM_ERROR 0x4006
172#define MBOX_PORT_ID_USED 0x4007
173#define MBOX_LOOP_ID_USED 0x4008
174#define MBOX_ALL_IDS_USED 0x4009
175#define MBOX_NOT_LOGGED_IN 0x400A
176#define MBLOGALL 0x000f
177#define MBLOGNONE 0x0000
178#define MBLOGMASK(x) ((x) & 0xf)
179
180/*
181 * Asynchronous event status codes
182 */
183#define ASYNC_BUS_RESET 0x8001
184#define ASYNC_SYSTEM_ERROR 0x8002
185#define ASYNC_RQS_XFER_ERR 0x8003
186#define ASYNC_RSP_XFER_ERR 0x8004
187#define ASYNC_QWAKEUP 0x8005
188#define ASYNC_TIMEOUT_RESET 0x8006
189#define ASYNC_DEVICE_RESET 0x8007
190#define ASYNC_EXTMSG_UNDERRUN 0x800A
191#define ASYNC_SCAM_INT 0x800B
192#define ASYNC_HUNG_SCSI 0x800C
193#define ASYNC_KILLED_BUS 0x800D
194#define ASYNC_BUS_TRANSIT 0x800E /* LVD -> HVD, eg. */
195#define ASYNC_LIP_OCCURRED 0x8010
196#define ASYNC_LOOP_UP 0x8011
197#define ASYNC_LOOP_DOWN 0x8012
198#define ASYNC_LOOP_RESET 0x8013
199#define ASYNC_PDB_CHANGED 0x8014
200#define ASYNC_CHANGE_NOTIFY 0x8015
201#define ASYNC_LIP_F8 0x8016
202#define ASYNC_CMD_CMPLT 0x8020
203#define ASYNC_CTIO_DONE 0x8021
204#define ASYNC_IP_XMIT_DONE 0x8022
205#define ASYNC_IP_RECV_DONE 0x8023
206#define ASYNC_IP_BROADCAST 0x8024
207#define ASYNC_IP_RCVQ_LOW 0x8025
208#define ASYNC_IP_RCVQ_EMPTY 0x8026
209#define ASYNC_IP_RECV_DONE_ALIGNED 0x8027
210#define ASYNC_PTPMODE 0x8030
211#define ASYNC_RIO1 0x8031
212#define ASYNC_RIO2 0x8032
213#define ASYNC_RIO3 0x8033
214#define ASYNC_RIO4 0x8034
215#define ASYNC_RIO5 0x8035
216#define ASYNC_CONNMODE 0x8036
217#define ISP_CONN_LOOP 1
218#define ISP_CONN_PTP 2
219#define ISP_CONN_BADLIP 3
220#define ISP_CONN_FATAL 4
221#define ISP_CONN_LOOPBACK 5
222#define ASYNC_RIO_RESP 0x8040
223#define ASYNC_RIO_COMP 0x8042
224/*
225 * 2.01.31 2200 Only. Need Bit 13 in Mailbox 1 for Set Firmware Options
226 * mailbox command to enable this.
227 */
228#define ASYNC_QFULL_SENT 0x8049
229
230/*
231 * Mailbox Usages
232 */
233
234#define WRITE_REQUEST_QUEUE_IN_POINTER(isp, value) \
235 ISP_WRITE(isp, isp->isp_rqstinrp, value)
236
237#define READ_REQUEST_QUEUE_OUT_POINTER(isp) \
238 ISP_READ(isp, isp->isp_rqstoutrp)
239
240#define READ_RESPONSE_QUEUE_IN_POINTER(isp) \
241 ISP_READ(isp, isp->isp_respinrp)
242
243#define WRITE_RESPONSE_QUEUE_OUT_POINTER(isp, value) \
244 ISP_WRITE(isp, isp->isp_respoutrp, value)
245
246/*
247 * Command Structure Definitions
248 */
249
250typedef struct {
251 u_int32_t ds_base;
252 u_int32_t ds_count;
253} ispds_t;
254
255typedef struct {
256 u_int32_t ds_base;
257 u_int32_t ds_basehi;
258 u_int32_t ds_count;
259} ispds64_t;
260
261#define DSTYPE_32BIT 0
262#define DSTYPE_64BIT 1
263typedef struct {
264 u_int16_t ds_type; /* 0-> ispds_t, 1-> ispds64_t */
265 u_int32_t ds_segment; /* unused */
266 u_int32_t ds_base; /* 32 bit address of DSD list */
267} ispdslist_t;
268
269
270/*
271 * These elements get swizzled around for SBus instances.
272 */
273#define ISP_SWAP8(a, b) { \
274 u_int8_t tmp; \
275 tmp = a; \
276 a = b; \
277 b = tmp; \
278}
279typedef struct {
280 u_int8_t rqs_entry_type;
281 u_int8_t rqs_entry_count;
282 u_int8_t rqs_seqno;
283 u_int8_t rqs_flags;
284} isphdr_t;
285
286/* RQS Flag definitions */
287#define RQSFLAG_CONTINUATION 0x01
288#define RQSFLAG_FULL 0x02
289#define RQSFLAG_BADHEADER 0x04
290#define RQSFLAG_BADPACKET 0x08
291
292/* RQS entry_type definitions */
293#define RQSTYPE_REQUEST 0x01
294#define RQSTYPE_DATASEG 0x02
295#define RQSTYPE_RESPONSE 0x03
296#define RQSTYPE_MARKER 0x04
297#define RQSTYPE_CMDONLY 0x05
298#define RQSTYPE_ATIO 0x06 /* Target Mode */
299#define RQSTYPE_CTIO 0x07 /* Target Mode */
300#define RQSTYPE_SCAM 0x08
301#define RQSTYPE_A64 0x09
302#define RQSTYPE_A64_CONT 0x0a
303#define RQSTYPE_ENABLE_LUN 0x0b /* Target Mode */
304#define RQSTYPE_MODIFY_LUN 0x0c /* Target Mode */
305#define RQSTYPE_NOTIFY 0x0d /* Target Mode */
306#define RQSTYPE_NOTIFY_ACK 0x0e /* Target Mode */
307#define RQSTYPE_CTIO1 0x0f /* Target Mode */
308#define RQSTYPE_STATUS_CONT 0x10
309#define RQSTYPE_T2RQS 0x11
310#define RQSTYPE_IP_XMIT 0x13
311#define RQSTYPE_T4RQS 0x15
312#define RQSTYPE_ATIO2 0x16 /* Target Mode */
313#define RQSTYPE_CTIO2 0x17 /* Target Mode */
314#define RQSTYPE_CSET0 0x18
315#define RQSTYPE_T3RQS 0x19
316#define RQSTYPE_IP_XMIT_64 0x1b
317#define RQSTYPE_CTIO4 0x1e /* Target Mode */
318#define RQSTYPE_CTIO3 0x1f /* Target Mode */
319#define RQSTYPE_RIO1 0x21
320#define RQSTYPE_RIO2 0x22
321#define RQSTYPE_IP_RECV 0x23
322#define RQSTYPE_IP_RECV_CONT 0x24
323
324
325#define ISP_RQDSEG 4
326typedef struct {
327 isphdr_t req_header;
328 u_int32_t req_handle;
329 u_int8_t req_lun_trn;
330 u_int8_t req_target;
331 u_int16_t req_cdblen;
332#define req_modifier req_cdblen /* marker packet */
333 u_int16_t req_flags;
334 u_int16_t req_reserved;
335 u_int16_t req_time;
336 u_int16_t req_seg_count;
337 u_int8_t req_cdb[12];
338 ispds_t req_dataseg[ISP_RQDSEG];
339} ispreq_t;
340
341#define ispreq64_t ispreqt3_t /* same as.... */
342#define ISP_RQDSEG_A64 2
343
344/*
345 * A request packet can also be a marker packet.
346 */
347#define SYNC_DEVICE 0
348#define SYNC_TARGET 1
349#define SYNC_ALL 2
|
| 350#define SYNC_LIP 3
|
354
355#define ISP_RQDSEG_T2 3
356typedef struct {
357 isphdr_t req_header;
358 u_int32_t req_handle;
359 u_int8_t req_lun_trn;
360 u_int8_t req_target;
361 u_int16_t req_scclun;
362 u_int16_t req_flags;
363 u_int16_t _res2;
364 u_int16_t req_time;
365 u_int16_t req_seg_count;
366 u_int8_t req_cdb[16];
367 u_int32_t req_totalcnt;
368 ispds_t req_dataseg[ISP_RQDSEG_T2];
369} ispreqt2_t;
370
| 351
352#define ISP_RQDSEG_T2 3
353typedef struct {
354 isphdr_t req_header;
355 u_int32_t req_handle;
356 u_int8_t req_lun_trn;
357 u_int8_t req_target;
358 u_int16_t req_scclun;
359 u_int16_t req_flags;
360 u_int16_t _res2;
361 u_int16_t req_time;
362 u_int16_t req_seg_count;
363 u_int8_t req_cdb[16];
364 u_int32_t req_totalcnt;
365 ispds_t req_dataseg[ISP_RQDSEG_T2];
366} ispreqt2_t;
367
|
| 368typedef struct {
369 isphdr_t req_header;
370 u_int32_t req_handle;
371 u_int16_t req_target;
372 u_int16_t req_scclun;
373 u_int16_t req_flags;
374 u_int16_t _res2;
375 u_int16_t req_time;
376 u_int16_t req_seg_count;
377 u_int8_t req_cdb[16];
378 u_int32_t req_totalcnt;
379 ispds_t req_dataseg[ISP_RQDSEG_T2];
380} ispreqt2e_t;
381
|
371#define ISP_RQDSEG_T3 2
372typedef struct {
373 isphdr_t req_header;
374 u_int32_t req_handle;
375 u_int8_t req_lun_trn;
376 u_int8_t req_target;
377 u_int16_t req_scclun;
378 u_int16_t req_flags;
379 u_int16_t _res2;
380 u_int16_t req_time;
381 u_int16_t req_seg_count;
382 u_int8_t req_cdb[16];
383 u_int32_t req_totalcnt;
384 ispds64_t req_dataseg[ISP_RQDSEG_T3];
385} ispreqt3_t;
386
| 382#define ISP_RQDSEG_T3 2
383typedef struct {
384 isphdr_t req_header;
385 u_int32_t req_handle;
386 u_int8_t req_lun_trn;
387 u_int8_t req_target;
388 u_int16_t req_scclun;
389 u_int16_t req_flags;
390 u_int16_t _res2;
391 u_int16_t req_time;
392 u_int16_t req_seg_count;
393 u_int8_t req_cdb[16];
394 u_int32_t req_totalcnt;
395 ispds64_t req_dataseg[ISP_RQDSEG_T3];
396} ispreqt3_t;
397
|
| 398typedef struct {
399 isphdr_t req_header;
400 u_int32_t req_handle;
401 u_int16_t req_target;
402 u_int16_t req_scclun;
403 u_int16_t req_flags;
404 u_int16_t _res2;
405 u_int16_t req_time;
406 u_int16_t req_seg_count;
407 u_int8_t req_cdb[16];
408 u_int32_t req_totalcnt;
409 ispds64_t req_dataseg[ISP_RQDSEG_T3];
410} ispreqt3e_t;
411
|
387/* req_flag values */
388#define REQFLAG_NODISCON 0x0001
389#define REQFLAG_HTAG 0x0002
390#define REQFLAG_OTAG 0x0004
391#define REQFLAG_STAG 0x0008
392#define REQFLAG_TARGET_RTN 0x0010
393
394#define REQFLAG_NODATA 0x0000
395#define REQFLAG_DATA_IN 0x0020
396#define REQFLAG_DATA_OUT 0x0040
397#define REQFLAG_DATA_UNKNOWN 0x0060
398
399#define REQFLAG_DISARQ 0x0100
400#define REQFLAG_FRC_ASYNC 0x0200
401#define REQFLAG_FRC_SYNC 0x0400
402#define REQFLAG_FRC_WIDE 0x0800
403#define REQFLAG_NOPARITY 0x1000
404#define REQFLAG_STOPQ 0x2000
405#define REQFLAG_XTRASNS 0x4000
406#define REQFLAG_PRIORITY 0x8000
407
408typedef struct {
409 isphdr_t req_header;
410 u_int32_t req_handle;
411 u_int8_t req_lun_trn;
412 u_int8_t req_target;
413 u_int16_t req_cdblen;
414 u_int16_t req_flags;
415 u_int16_t _res1;
416 u_int16_t req_time;
417 u_int16_t req_seg_count;
418 u_int8_t req_cdb[44];
419} ispextreq_t;
420
421#define ISP_CDSEG 7
422typedef struct {
423 isphdr_t req_header;
424 u_int32_t _res1;
425 ispds_t req_dataseg[ISP_CDSEG];
426} ispcontreq_t;
427
428#define ISP_CDSEG64 5
429typedef struct {
430 isphdr_t req_header;
431 ispds64_t req_dataseg[ISP_CDSEG64];
432} ispcontreq64_t;
433
434typedef struct {
435 isphdr_t req_header;
436 u_int32_t req_handle;
437 u_int16_t req_scsi_status;
438 u_int16_t req_completion_status;
439 u_int16_t req_state_flags;
440 u_int16_t req_status_flags;
441 u_int16_t req_time;
442#define req_response_len req_time /* FC only */
443 u_int16_t req_sense_len;
444 u_int32_t req_resid;
445 u_int8_t req_response[8]; /* FC only */
446 u_int8_t req_sense_data[32];
447} ispstatusreq_t;
448
449typedef struct {
450 isphdr_t req_header;
451 u_int8_t req_sense_data[60];
452} ispstatus_cont_t;
453
454/*
455 * For Qlogic 2X00, the high order byte of SCSI status has
456 * additional meaning.
457 */
458#define RQCS_RU 0x800 /* Residual Under */
459#define RQCS_RO 0x400 /* Residual Over */
460#define RQCS_RESID (RQCS_RU|RQCS_RO)
461#define RQCS_SV 0x200 /* Sense Length Valid */
462#define RQCS_RV 0x100 /* FCP Response Length Valid */
463
464/*
465 * Completion Status Codes.
466 */
467#define RQCS_COMPLETE 0x0000
468#define RQCS_DMA_ERROR 0x0002
469#define RQCS_RESET_OCCURRED 0x0004
470#define RQCS_ABORTED 0x0005
471#define RQCS_TIMEOUT 0x0006
472#define RQCS_DATA_OVERRUN 0x0007
473#define RQCS_DATA_UNDERRUN 0x0015
474#define RQCS_QUEUE_FULL 0x001C
475
476/* 1X00 Only Completion Codes */
477#define RQCS_INCOMPLETE 0x0001
478#define RQCS_TRANSPORT_ERROR 0x0003
479#define RQCS_COMMAND_OVERRUN 0x0008
480#define RQCS_STATUS_OVERRUN 0x0009
481#define RQCS_BAD_MESSAGE 0x000a
482#define RQCS_NO_MESSAGE_OUT 0x000b
483#define RQCS_EXT_ID_FAILED 0x000c
484#define RQCS_IDE_MSG_FAILED 0x000d
485#define RQCS_ABORT_MSG_FAILED 0x000e
486#define RQCS_REJECT_MSG_FAILED 0x000f
487#define RQCS_NOP_MSG_FAILED 0x0010
488#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
489#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
490#define RQCS_ID_MSG_FAILED 0x0013
491#define RQCS_UNEXP_BUS_FREE 0x0014
492#define RQCS_XACT_ERR1 0x0018
493#define RQCS_XACT_ERR2 0x0019
494#define RQCS_XACT_ERR3 0x001A
495#define RQCS_BAD_ENTRY 0x001B
496#define RQCS_PHASE_SKIPPED 0x001D
497#define RQCS_ARQS_FAILED 0x001E
498#define RQCS_WIDE_FAILED 0x001F
499#define RQCS_SYNCXFER_FAILED 0x0020
500#define RQCS_LVD_BUSERR 0x0021
501
502/* 2X00 Only Completion Codes */
503#define RQCS_PORT_UNAVAILABLE 0x0028
504#define RQCS_PORT_LOGGED_OUT 0x0029
505#define RQCS_PORT_CHANGED 0x002A
506#define RQCS_PORT_BUSY 0x002B
507
508/*
509 * 1X00 specific State Flags
510 */
511#define RQSF_GOT_BUS 0x0100
512#define RQSF_GOT_TARGET 0x0200
513#define RQSF_SENT_CDB 0x0400
514#define RQSF_XFRD_DATA 0x0800
515#define RQSF_GOT_STATUS 0x1000
516#define RQSF_GOT_SENSE 0x2000
517#define RQSF_XFER_COMPLETE 0x4000
518
519/*
520 * 2X00 specific State Flags
521 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available)
522 */
523#define RQSF_DATA_IN 0x0020
524#define RQSF_DATA_OUT 0x0040
525#define RQSF_STAG 0x0008
526#define RQSF_OTAG 0x0004
527#define RQSF_HTAG 0x0002
528/*
529 * 1X00 Status Flags
530 */
531#define RQSTF_DISCONNECT 0x0001
532#define RQSTF_SYNCHRONOUS 0x0002
533#define RQSTF_PARITY_ERROR 0x0004
534#define RQSTF_BUS_RESET 0x0008
535#define RQSTF_DEVICE_RESET 0x0010
536#define RQSTF_ABORTED 0x0020
537#define RQSTF_TIMEOUT 0x0040
538#define RQSTF_NEGOTIATION 0x0080
539
540/*
541 * 2X00 specific state flags
542 */
543/* RQSF_SENT_CDB */
544/* RQSF_XFRD_DATA */
545/* RQSF_GOT_STATUS */
546/* RQSF_XFER_COMPLETE */
547
548/*
549 * 2X00 specific status flags
550 */
551/* RQSTF_ABORTED */
552/* RQSTF_TIMEOUT */
553#define RQSTF_DMA_ERROR 0x0080
554#define RQSTF_LOGOUT 0x2000
555
556/*
557 * Miscellaneous
558 */
559#ifndef ISP_EXEC_THROTTLE
560#define ISP_EXEC_THROTTLE 16
561#endif
562
563/*
564 * About Firmware returns an 'attribute' word in mailbox 6.
565 */
566#define ISP_FW_ATTR_TMODE 0x01
567#define ISP_FW_ATTR_SCCLUN 0x02
568#define ISP_FW_ATTR_FABRIC 0x04
569#define ISP_FW_ATTR_CLASS2 0x08
570#define ISP_FW_ATTR_FCTAPE 0x10
571#define ISP_FW_ATTR_IP 0x20
| 412/* req_flag values */
413#define REQFLAG_NODISCON 0x0001
414#define REQFLAG_HTAG 0x0002
415#define REQFLAG_OTAG 0x0004
416#define REQFLAG_STAG 0x0008
417#define REQFLAG_TARGET_RTN 0x0010
418
419#define REQFLAG_NODATA 0x0000
420#define REQFLAG_DATA_IN 0x0020
421#define REQFLAG_DATA_OUT 0x0040
422#define REQFLAG_DATA_UNKNOWN 0x0060
423
424#define REQFLAG_DISARQ 0x0100
425#define REQFLAG_FRC_ASYNC 0x0200
426#define REQFLAG_FRC_SYNC 0x0400
427#define REQFLAG_FRC_WIDE 0x0800
428#define REQFLAG_NOPARITY 0x1000
429#define REQFLAG_STOPQ 0x2000
430#define REQFLAG_XTRASNS 0x4000
431#define REQFLAG_PRIORITY 0x8000
432
433typedef struct {
434 isphdr_t req_header;
435 u_int32_t req_handle;
436 u_int8_t req_lun_trn;
437 u_int8_t req_target;
438 u_int16_t req_cdblen;
439 u_int16_t req_flags;
440 u_int16_t _res1;
441 u_int16_t req_time;
442 u_int16_t req_seg_count;
443 u_int8_t req_cdb[44];
444} ispextreq_t;
445
446#define ISP_CDSEG 7
447typedef struct {
448 isphdr_t req_header;
449 u_int32_t _res1;
450 ispds_t req_dataseg[ISP_CDSEG];
451} ispcontreq_t;
452
453#define ISP_CDSEG64 5
454typedef struct {
455 isphdr_t req_header;
456 ispds64_t req_dataseg[ISP_CDSEG64];
457} ispcontreq64_t;
458
459typedef struct {
460 isphdr_t req_header;
461 u_int32_t req_handle;
462 u_int16_t req_scsi_status;
463 u_int16_t req_completion_status;
464 u_int16_t req_state_flags;
465 u_int16_t req_status_flags;
466 u_int16_t req_time;
467#define req_response_len req_time /* FC only */
468 u_int16_t req_sense_len;
469 u_int32_t req_resid;
470 u_int8_t req_response[8]; /* FC only */
471 u_int8_t req_sense_data[32];
472} ispstatusreq_t;
473
474typedef struct {
475 isphdr_t req_header;
476 u_int8_t req_sense_data[60];
477} ispstatus_cont_t;
478
479/*
480 * For Qlogic 2X00, the high order byte of SCSI status has
481 * additional meaning.
482 */
483#define RQCS_RU 0x800 /* Residual Under */
484#define RQCS_RO 0x400 /* Residual Over */
485#define RQCS_RESID (RQCS_RU|RQCS_RO)
486#define RQCS_SV 0x200 /* Sense Length Valid */
487#define RQCS_RV 0x100 /* FCP Response Length Valid */
488
489/*
490 * Completion Status Codes.
491 */
492#define RQCS_COMPLETE 0x0000
493#define RQCS_DMA_ERROR 0x0002
494#define RQCS_RESET_OCCURRED 0x0004
495#define RQCS_ABORTED 0x0005
496#define RQCS_TIMEOUT 0x0006
497#define RQCS_DATA_OVERRUN 0x0007
498#define RQCS_DATA_UNDERRUN 0x0015
499#define RQCS_QUEUE_FULL 0x001C
500
501/* 1X00 Only Completion Codes */
502#define RQCS_INCOMPLETE 0x0001
503#define RQCS_TRANSPORT_ERROR 0x0003
504#define RQCS_COMMAND_OVERRUN 0x0008
505#define RQCS_STATUS_OVERRUN 0x0009
506#define RQCS_BAD_MESSAGE 0x000a
507#define RQCS_NO_MESSAGE_OUT 0x000b
508#define RQCS_EXT_ID_FAILED 0x000c
509#define RQCS_IDE_MSG_FAILED 0x000d
510#define RQCS_ABORT_MSG_FAILED 0x000e
511#define RQCS_REJECT_MSG_FAILED 0x000f
512#define RQCS_NOP_MSG_FAILED 0x0010
513#define RQCS_PARITY_ERROR_MSG_FAILED 0x0011
514#define RQCS_DEVICE_RESET_MSG_FAILED 0x0012
515#define RQCS_ID_MSG_FAILED 0x0013
516#define RQCS_UNEXP_BUS_FREE 0x0014
517#define RQCS_XACT_ERR1 0x0018
518#define RQCS_XACT_ERR2 0x0019
519#define RQCS_XACT_ERR3 0x001A
520#define RQCS_BAD_ENTRY 0x001B
521#define RQCS_PHASE_SKIPPED 0x001D
522#define RQCS_ARQS_FAILED 0x001E
523#define RQCS_WIDE_FAILED 0x001F
524#define RQCS_SYNCXFER_FAILED 0x0020
525#define RQCS_LVD_BUSERR 0x0021
526
527/* 2X00 Only Completion Codes */
528#define RQCS_PORT_UNAVAILABLE 0x0028
529#define RQCS_PORT_LOGGED_OUT 0x0029
530#define RQCS_PORT_CHANGED 0x002A
531#define RQCS_PORT_BUSY 0x002B
532
533/*
534 * 1X00 specific State Flags
535 */
536#define RQSF_GOT_BUS 0x0100
537#define RQSF_GOT_TARGET 0x0200
538#define RQSF_SENT_CDB 0x0400
539#define RQSF_XFRD_DATA 0x0800
540#define RQSF_GOT_STATUS 0x1000
541#define RQSF_GOT_SENSE 0x2000
542#define RQSF_XFER_COMPLETE 0x4000
543
544/*
545 * 2X00 specific State Flags
546 * (same as 1X00 except RQSF_GOT_BUS/RQSF_GOT_TARGET are not available)
547 */
548#define RQSF_DATA_IN 0x0020
549#define RQSF_DATA_OUT 0x0040
550#define RQSF_STAG 0x0008
551#define RQSF_OTAG 0x0004
552#define RQSF_HTAG 0x0002
553/*
554 * 1X00 Status Flags
555 */
556#define RQSTF_DISCONNECT 0x0001
557#define RQSTF_SYNCHRONOUS 0x0002
558#define RQSTF_PARITY_ERROR 0x0004
559#define RQSTF_BUS_RESET 0x0008
560#define RQSTF_DEVICE_RESET 0x0010
561#define RQSTF_ABORTED 0x0020
562#define RQSTF_TIMEOUT 0x0040
563#define RQSTF_NEGOTIATION 0x0080
564
565/*
566 * 2X00 specific state flags
567 */
568/* RQSF_SENT_CDB */
569/* RQSF_XFRD_DATA */
570/* RQSF_GOT_STATUS */
571/* RQSF_XFER_COMPLETE */
572
573/*
574 * 2X00 specific status flags
575 */
576/* RQSTF_ABORTED */
577/* RQSTF_TIMEOUT */
578#define RQSTF_DMA_ERROR 0x0080
579#define RQSTF_LOGOUT 0x2000
580
581/*
582 * Miscellaneous
583 */
584#ifndef ISP_EXEC_THROTTLE
585#define ISP_EXEC_THROTTLE 16
586#endif
587
588/*
589 * About Firmware returns an 'attribute' word in mailbox 6.
590 */
591#define ISP_FW_ATTR_TMODE 0x01
592#define ISP_FW_ATTR_SCCLUN 0x02
593#define ISP_FW_ATTR_FABRIC 0x04
594#define ISP_FW_ATTR_CLASS2 0x08
595#define ISP_FW_ATTR_FCTAPE 0x10
596#define ISP_FW_ATTR_IP 0x20
|
| 597#define ISP_FW_ATTR_VI 0x40
598#define ISP_FW_ATTR_VI_SOLARIS 0x80
599#define ISP_FW_ATTR_2KLOGINS 0x100 /* XXX: just a guess */
|
572
| 600
|
| 601#define IS_2KLOGIN(isp) \
602 (IS_FC(isp) && (FCPARAM(isp)->isp_fwattr & ISP_FW_ATTR_2KLOGINS))
603
|
573/*
574 * Reduced Interrupt Operation Response Queue Entreis
575 */
576
577typedef struct {
578 isphdr_t req_header;
579 u_int32_t req_handles[15];
580} isp_rio1_t;
581
582typedef struct {
583 isphdr_t req_header;
584 u_int16_t req_handles[30];
585} isp_rio2_t;
586
587/*
588 * FC (ISP2100) specific data structures
589 */
590
591/*
592 * Initialization Control Block
593 *
594 * Version One (prime) format.
595 */
596typedef struct isp_icb {
597 u_int8_t icb_version;
598 u_int8_t _reserved0;
599 u_int16_t icb_fwoptions;
600 u_int16_t icb_maxfrmlen;
601 u_int16_t icb_maxalloc;
602 u_int16_t icb_execthrottle;
603 u_int8_t icb_retry_count;
604 u_int8_t icb_retry_delay;
605 u_int8_t icb_portname[8];
606 u_int16_t icb_hardaddr;
607 u_int8_t icb_iqdevtype;
608 u_int8_t icb_logintime;
609 u_int8_t icb_nodename[8];
610 u_int16_t icb_rqstout;
611 u_int16_t icb_rspnsin;
612 u_int16_t icb_rqstqlen;
613 u_int16_t icb_rsltqlen;
614 u_int16_t icb_rqstaddr[4];
615 u_int16_t icb_respaddr[4];
616 u_int16_t icb_lunenables;
617 u_int8_t icb_ccnt;
618 u_int8_t icb_icnt;
619 u_int16_t icb_lunetimeout;
620 u_int16_t _reserved1;
621 u_int16_t icb_xfwoptions;
622 u_int8_t icb_racctimer;
623 u_int8_t icb_idelaytimer;
624 u_int16_t icb_zfwoptions;
625 u_int16_t _reserved2[13];
626} isp_icb_t;
627#define ICB_VERSION1 1
628
629#define ICBOPT_HARD_ADDRESS 0x0001
630#define ICBOPT_FAIRNESS 0x0002
631#define ICBOPT_FULL_DUPLEX 0x0004
632#define ICBOPT_FAST_POST 0x0008
633#define ICBOPT_TGT_ENABLE 0x0010
634#define ICBOPT_INI_DISABLE 0x0020
635#define ICBOPT_INI_ADISC 0x0040
636#define ICBOPT_INI_TGTTYPE 0x0080
637#define ICBOPT_PDBCHANGE_AE 0x0100
638#define ICBOPT_NOLIP 0x0200
639#define ICBOPT_SRCHDOWN 0x0400
640#define ICBOPT_PREVLOOP 0x0800
641#define ICBOPT_STOP_ON_QFULL 0x1000
642#define ICBOPT_FULL_LOGIN 0x2000
643#define ICBOPT_BOTH_WWNS 0x4000
644#define ICBOPT_EXTENDED 0x8000
645
646#define ICBXOPT_CLASS2_ACK0 0x0200
647#define ICBXOPT_CLASS2 0x0100
648#define ICBXOPT_LOOP_ONLY (0 << 4)
649#define ICBXOPT_PTP_ONLY (1 << 4)
650#define ICBXOPT_LOOP_2_PTP (2 << 4)
651#define ICBXOPT_PTP_2_LOOP (3 << 4)
652
653/*
654 * The lower 4 bits of the xfwoptions field are the OPERATION MODE bits.
655 * RIO is not defined for the 23XX cards
656 */
657#define ICBXOPT_RIO_OFF 0
658#define ICBXOPT_RIO_16BIT 1
659#define ICBXOPT_RIO_32BIT 2
660#define ICBXOPT_RIO_16BIT_IOCB 3
661#define ICBXOPT_RIO_32BIT_IOCB 4
662#define ICBXOPT_ZIO 5
663
664#define ICBZOPT_ENA_RDXFR_RDY 0x01
665#define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */
666/* These 3 only apply to the 2300 */
667#define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14)
668#define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14)
669#define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14)
670
671
672#define ICB_MIN_FRMLEN 256
673#define ICB_MAX_FRMLEN 2112
674#define ICB_DFLT_FRMLEN 1024
675#define ICB_DFLT_ALLOC 256
676#define ICB_DFLT_THROTTLE 16
677#define ICB_DFLT_RDELAY 5
678#define ICB_DFLT_RCOUNT 3
679
680
681#define RQRSP_ADDR0015 0
682#define RQRSP_ADDR1631 1
683#define RQRSP_ADDR3247 2
684#define RQRSP_ADDR4863 3
685
686
687#define ICB_NNM0 7
688#define ICB_NNM1 6
689#define ICB_NNM2 5
690#define ICB_NNM3 4
691#define ICB_NNM4 3
692#define ICB_NNM5 2
693#define ICB_NNM6 1
694#define ICB_NNM7 0
695
696#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
697 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \
698 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \
699 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
700 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
701 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
702 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
703 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
704 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
705
706#define MAKE_WWN_FROM_NODE_NAME(wwn, array) \
707 wwn = ((u_int64_t) array[ICB_NNM0]) | \
708 ((u_int64_t) array[ICB_NNM1] << 8) | \
709 ((u_int64_t) array[ICB_NNM2] << 16) | \
710 ((u_int64_t) array[ICB_NNM3] << 24) | \
711 ((u_int64_t) array[ICB_NNM4] << 32) | \
712 ((u_int64_t) array[ICB_NNM5] << 40) | \
713 ((u_int64_t) array[ICB_NNM6] << 48) | \
714 ((u_int64_t) array[ICB_NNM7] << 56)
715
716/*
717 * FC-AL Position Map
718 *
719 * This is an at most 128 byte map that returns either
720 * the LILP or Firmware generated list of ports.
721 *
722 * We deviate a bit from the returned qlogic format to
723 * use an extra bit to say whether this was a LILP or
724 * f/w generated map.
725 */
726typedef struct {
727 u_int8_t fwmap : 1,
728 count : 7;
729 u_int8_t map[127];
730} fcpos_map_t;
731
732/*
733 * Port Data Base Element
734 */
735
736typedef struct {
737 u_int16_t pdb_options;
738 u_int8_t pdb_mstate;
739 u_int8_t pdb_sstate;
740#define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2])
741 u_int8_t pdb_hardaddr_bits[4];
742 u_int8_t pdb_portid_bits[4];
743 u_int8_t pdb_nodename[8];
744 u_int8_t pdb_portname[8];
745 u_int16_t pdb_execthrottle;
746 u_int16_t pdb_exec_count;
747 u_int8_t pdb_retry_count;
748 u_int8_t pdb_retry_delay;
749 u_int16_t pdb_resalloc;
750 u_int16_t pdb_curalloc;
751 u_int16_t pdb_qhead;
752 u_int16_t pdb_qtail;
753 u_int16_t pdb_tl_next;
754 u_int16_t pdb_tl_last;
755 u_int16_t pdb_features; /* PLOGI, Common Service */
756 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */
757 u_int16_t pdb_roi; /* PLOGI, Common Service */
758 u_int8_t pdb_target;
759 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */
760 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */
761 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */
762 u_int16_t pdb_noseq; /* PLOGI, Class 3 */
763 u_int16_t pdb_labrtflg;
764 u_int16_t pdb_lstopflg;
765 u_int16_t pdb_sqhead;
766 u_int16_t pdb_sqtail;
767 u_int16_t pdb_ptimer;
768 u_int16_t pdb_nxt_seqid;
769 u_int16_t pdb_fcount;
770 u_int16_t pdb_prli_len;
771 u_int16_t pdb_prli_svc0;
772 u_int16_t pdb_prli_svc3;
773 u_int16_t pdb_loopid;
774 u_int16_t pdb_il_ptr;
775 u_int16_t pdb_sl_ptr;
776} isp_pdb_t;
777
778#define PDB_OPTIONS_XMITTING (1<<11)
779#define PDB_OPTIONS_LNKXMIT (1<<10)
780#define PDB_OPTIONS_ABORTED (1<<9)
781#define PDB_OPTIONS_ADISC (1<<1)
782
783#define PDB_STATE_DISCOVERY 0
784#define PDB_STATE_WDISC_ACK 1
785#define PDB_STATE_PLOGI 2
786#define PDB_STATE_PLOGI_ACK 3
787#define PDB_STATE_PRLI 4
788#define PDB_STATE_PRLI_ACK 5
789#define PDB_STATE_LOGGED_IN 6
790#define PDB_STATE_PORT_UNAVAIL 7
791#define PDB_STATE_PRLO 8
792#define PDB_STATE_PRLO_ACK 9
793#define PDB_STATE_PLOGO 10
794#define PDB_STATE_PLOG_ACK 11
795
796#define SVC3_TGT_ROLE 0x10
797#define SVC3_INI_ROLE 0x20
798#define SVC3_ROLE_MASK 0x30
799#define SVC3_ROLE_SHIFT 4
800
801/*
802 * CT definition
803 *
804 * This is as the QLogic f/w documentations defines it- which is just opposite,
805 * bit wise, from what the specification defines it as. Additionally, the
806 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped.
807 */
808
809typedef struct {
810 u_int8_t ct_revision;
811 u_int8_t ct_portid[3];
812 u_int8_t ct_fcs_type;
813 u_int8_t ct_fcs_subtype;
814 u_int8_t ct_options;
815 u_int8_t ct_res0;
816 u_int16_t ct_response;
817 u_int16_t ct_resid;
818 u_int8_t ct_res1;
819 u_int8_t ct_reason;
820 u_int8_t ct_explanation;
821 u_int8_t ct_vunique;
822} ct_hdr_t;
823#define FS_ACC 0x8002
824#define FS_RJT 0x8001
825
826#define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */
827#define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */
828#define FC4_FC_SVC 0x20 /* Fibre Channel Services */
829
830#define SNS_GA_NXT 0x100
831#define SNS_GPN_ID 0x112
832#define SNS_GNN_ID 0x113
833#define SNS_GFF_ID 0x11F
834#define SNS_GID_FT 0x171
835#define SNS_RFT_ID 0x217
836typedef struct {
837 u_int16_t snscb_rblen; /* response buffer length (words) */
838 u_int16_t snscb_res0;
839 u_int16_t snscb_addr[4]; /* response buffer address */
840 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
841 u_int16_t snscb_res1;
842 u_int16_t snscb_data[1]; /* variable data */
843} sns_screq_t; /* Subcommand Request Structure */
844
845typedef struct {
846 u_int16_t snscb_rblen; /* response buffer length (words) */
847 u_int16_t snscb_res0;
848 u_int16_t snscb_addr[4]; /* response buffer address */
849 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
850 u_int16_t snscb_res1;
851 u_int16_t snscb_cmd;
852 u_int16_t snscb_res2;
853 u_int32_t snscb_res3;
854 u_int32_t snscb_port;
855} sns_ga_nxt_req_t;
856#define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t))
857
858typedef struct {
859 u_int16_t snscb_rblen; /* response buffer length (words) */
860 u_int16_t snscb_res0;
861 u_int16_t snscb_addr[4]; /* response buffer address */
862 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
863 u_int16_t snscb_res1;
864 u_int16_t snscb_cmd;
865 u_int16_t snscb_res2;
866 u_int32_t snscb_res3;
867 u_int32_t snscb_portid;
868} sns_gxn_id_req_t;
869#define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t))
870
871typedef struct {
872 u_int16_t snscb_rblen; /* response buffer length (words) */
873 u_int16_t snscb_res0;
874 u_int16_t snscb_addr[4]; /* response buffer address */
875 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
876 u_int16_t snscb_res1;
877 u_int16_t snscb_cmd;
878 u_int16_t snscb_mword_div_2;
879 u_int32_t snscb_res3;
880 u_int32_t snscb_fc4_type;
881} sns_gid_ft_req_t;
882#define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t))
883
884typedef struct {
885 u_int16_t snscb_rblen; /* response buffer length (words) */
886 u_int16_t snscb_res0;
887 u_int16_t snscb_addr[4]; /* response buffer address */
888 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
889 u_int16_t snscb_res1;
890 u_int16_t snscb_cmd;
891 u_int16_t snscb_res2;
892 u_int32_t snscb_res3;
893 u_int32_t snscb_port;
894 u_int32_t snscb_fc4_types[8];
895} sns_rft_id_req_t;
896#define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t))
897
898typedef struct {
899 ct_hdr_t snscb_cthdr;
900 u_int8_t snscb_port_type;
901 u_int8_t snscb_port_id[3];
902 u_int8_t snscb_portname[8];
903 u_int16_t snscb_data[1]; /* variable data */
904} sns_scrsp_t; /* Subcommand Response Structure */
905
906typedef struct {
907 ct_hdr_t snscb_cthdr;
908 u_int8_t snscb_port_type;
909 u_int8_t snscb_port_id[3];
910 u_int8_t snscb_portname[8];
911 u_int8_t snscb_pnlen; /* symbolic port name length */
912 u_int8_t snscb_pname[255]; /* symbolic port name */
913 u_int8_t snscb_nodename[8];
914 u_int8_t snscb_nnlen; /* symbolic node name length */
915 u_int8_t snscb_nname[255]; /* symbolic node name */
916 u_int8_t snscb_ipassoc[8];
917 u_int8_t snscb_ipaddr[16];
918 u_int8_t snscb_svc_class[4];
919 u_int8_t snscb_fc4_types[32];
920 u_int8_t snscb_fpname[8];
921 u_int8_t snscb_reserved;
922 u_int8_t snscb_hardaddr[3];
923} sns_ga_nxt_rsp_t; /* Subcommand Response Structure */
924#define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t))
925
926typedef struct {
927 ct_hdr_t snscb_cthdr;
928 u_int8_t snscb_wwn[8];
929} sns_gxn_id_rsp_t;
930#define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t))
931
932typedef struct {
933 ct_hdr_t snscb_cthdr;
934 u_int32_t snscb_fc4_features[32];
935} sns_gff_id_rsp_t;
936#define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t))
937
938typedef struct {
939 ct_hdr_t snscb_cthdr;
940 struct {
941 u_int8_t control;
942 u_int8_t portid[3];
943 } snscb_ports[1];
944} sns_gid_ft_rsp_t;
945#define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2))
946
947#define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t))
948
949#endif /* _ISPMBOX_H */
| 604/*
605 * Reduced Interrupt Operation Response Queue Entreis
606 */
607
608typedef struct {
609 isphdr_t req_header;
610 u_int32_t req_handles[15];
611} isp_rio1_t;
612
613typedef struct {
614 isphdr_t req_header;
615 u_int16_t req_handles[30];
616} isp_rio2_t;
617
618/*
619 * FC (ISP2100) specific data structures
620 */
621
622/*
623 * Initialization Control Block
624 *
625 * Version One (prime) format.
626 */
627typedef struct isp_icb {
628 u_int8_t icb_version;
629 u_int8_t _reserved0;
630 u_int16_t icb_fwoptions;
631 u_int16_t icb_maxfrmlen;
632 u_int16_t icb_maxalloc;
633 u_int16_t icb_execthrottle;
634 u_int8_t icb_retry_count;
635 u_int8_t icb_retry_delay;
636 u_int8_t icb_portname[8];
637 u_int16_t icb_hardaddr;
638 u_int8_t icb_iqdevtype;
639 u_int8_t icb_logintime;
640 u_int8_t icb_nodename[8];
641 u_int16_t icb_rqstout;
642 u_int16_t icb_rspnsin;
643 u_int16_t icb_rqstqlen;
644 u_int16_t icb_rsltqlen;
645 u_int16_t icb_rqstaddr[4];
646 u_int16_t icb_respaddr[4];
647 u_int16_t icb_lunenables;
648 u_int8_t icb_ccnt;
649 u_int8_t icb_icnt;
650 u_int16_t icb_lunetimeout;
651 u_int16_t _reserved1;
652 u_int16_t icb_xfwoptions;
653 u_int8_t icb_racctimer;
654 u_int8_t icb_idelaytimer;
655 u_int16_t icb_zfwoptions;
656 u_int16_t _reserved2[13];
657} isp_icb_t;
658#define ICB_VERSION1 1
659
660#define ICBOPT_HARD_ADDRESS 0x0001
661#define ICBOPT_FAIRNESS 0x0002
662#define ICBOPT_FULL_DUPLEX 0x0004
663#define ICBOPT_FAST_POST 0x0008
664#define ICBOPT_TGT_ENABLE 0x0010
665#define ICBOPT_INI_DISABLE 0x0020
666#define ICBOPT_INI_ADISC 0x0040
667#define ICBOPT_INI_TGTTYPE 0x0080
668#define ICBOPT_PDBCHANGE_AE 0x0100
669#define ICBOPT_NOLIP 0x0200
670#define ICBOPT_SRCHDOWN 0x0400
671#define ICBOPT_PREVLOOP 0x0800
672#define ICBOPT_STOP_ON_QFULL 0x1000
673#define ICBOPT_FULL_LOGIN 0x2000
674#define ICBOPT_BOTH_WWNS 0x4000
675#define ICBOPT_EXTENDED 0x8000
676
677#define ICBXOPT_CLASS2_ACK0 0x0200
678#define ICBXOPT_CLASS2 0x0100
679#define ICBXOPT_LOOP_ONLY (0 << 4)
680#define ICBXOPT_PTP_ONLY (1 << 4)
681#define ICBXOPT_LOOP_2_PTP (2 << 4)
682#define ICBXOPT_PTP_2_LOOP (3 << 4)
683
684/*
685 * The lower 4 bits of the xfwoptions field are the OPERATION MODE bits.
686 * RIO is not defined for the 23XX cards
687 */
688#define ICBXOPT_RIO_OFF 0
689#define ICBXOPT_RIO_16BIT 1
690#define ICBXOPT_RIO_32BIT 2
691#define ICBXOPT_RIO_16BIT_IOCB 3
692#define ICBXOPT_RIO_32BIT_IOCB 4
693#define ICBXOPT_ZIO 5
694
695#define ICBZOPT_ENA_RDXFR_RDY 0x01
696#define ICBZOPT_ENA_OOF (1 << 6) /* out of order frame handling */
697/* These 3 only apply to the 2300 */
698#define ICBZOPT_RATE_ONEGB (MBGSD_ONEGB << 14)
699#define ICBZOPT_RATE_TWOGB (MBGSD_TWOGB << 14)
700#define ICBZOPT_RATE_AUTO (MBGSD_AUTO << 14)
701
702
703#define ICB_MIN_FRMLEN 256
704#define ICB_MAX_FRMLEN 2112
705#define ICB_DFLT_FRMLEN 1024
706#define ICB_DFLT_ALLOC 256
707#define ICB_DFLT_THROTTLE 16
708#define ICB_DFLT_RDELAY 5
709#define ICB_DFLT_RCOUNT 3
710
711
712#define RQRSP_ADDR0015 0
713#define RQRSP_ADDR1631 1
714#define RQRSP_ADDR3247 2
715#define RQRSP_ADDR4863 3
716
717
718#define ICB_NNM0 7
719#define ICB_NNM1 6
720#define ICB_NNM2 5
721#define ICB_NNM3 4
722#define ICB_NNM4 3
723#define ICB_NNM5 2
724#define ICB_NNM6 1
725#define ICB_NNM7 0
726
727#define MAKE_NODE_NAME_FROM_WWN(array, wwn) \
728 array[ICB_NNM0] = (u_int8_t) ((wwn >> 0) & 0xff), \
729 array[ICB_NNM1] = (u_int8_t) ((wwn >> 8) & 0xff), \
730 array[ICB_NNM2] = (u_int8_t) ((wwn >> 16) & 0xff), \
731 array[ICB_NNM3] = (u_int8_t) ((wwn >> 24) & 0xff), \
732 array[ICB_NNM4] = (u_int8_t) ((wwn >> 32) & 0xff), \
733 array[ICB_NNM5] = (u_int8_t) ((wwn >> 40) & 0xff), \
734 array[ICB_NNM6] = (u_int8_t) ((wwn >> 48) & 0xff), \
735 array[ICB_NNM7] = (u_int8_t) ((wwn >> 56) & 0xff)
736
737#define MAKE_WWN_FROM_NODE_NAME(wwn, array) \
738 wwn = ((u_int64_t) array[ICB_NNM0]) | \
739 ((u_int64_t) array[ICB_NNM1] << 8) | \
740 ((u_int64_t) array[ICB_NNM2] << 16) | \
741 ((u_int64_t) array[ICB_NNM3] << 24) | \
742 ((u_int64_t) array[ICB_NNM4] << 32) | \
743 ((u_int64_t) array[ICB_NNM5] << 40) | \
744 ((u_int64_t) array[ICB_NNM6] << 48) | \
745 ((u_int64_t) array[ICB_NNM7] << 56)
746
747/*
748 * FC-AL Position Map
749 *
750 * This is an at most 128 byte map that returns either
751 * the LILP or Firmware generated list of ports.
752 *
753 * We deviate a bit from the returned qlogic format to
754 * use an extra bit to say whether this was a LILP or
755 * f/w generated map.
756 */
757typedef struct {
758 u_int8_t fwmap : 1,
759 count : 7;
760 u_int8_t map[127];
761} fcpos_map_t;
762
763/*
764 * Port Data Base Element
765 */
766
767typedef struct {
768 u_int16_t pdb_options;
769 u_int8_t pdb_mstate;
770 u_int8_t pdb_sstate;
771#define BITS2WORD(x) ((x)[0] << 16 | (x)[3] << 8 | (x)[2])
772 u_int8_t pdb_hardaddr_bits[4];
773 u_int8_t pdb_portid_bits[4];
774 u_int8_t pdb_nodename[8];
775 u_int8_t pdb_portname[8];
776 u_int16_t pdb_execthrottle;
777 u_int16_t pdb_exec_count;
778 u_int8_t pdb_retry_count;
779 u_int8_t pdb_retry_delay;
780 u_int16_t pdb_resalloc;
781 u_int16_t pdb_curalloc;
782 u_int16_t pdb_qhead;
783 u_int16_t pdb_qtail;
784 u_int16_t pdb_tl_next;
785 u_int16_t pdb_tl_last;
786 u_int16_t pdb_features; /* PLOGI, Common Service */
787 u_int16_t pdb_pconcurrnt; /* PLOGI, Common Service */
788 u_int16_t pdb_roi; /* PLOGI, Common Service */
789 u_int8_t pdb_target;
790 u_int8_t pdb_initiator; /* PLOGI, Class 3 Control Flags */
791 u_int16_t pdb_rdsiz; /* PLOGI, Class 3 */
792 u_int16_t pdb_ncseq; /* PLOGI, Class 3 */
793 u_int16_t pdb_noseq; /* PLOGI, Class 3 */
794 u_int16_t pdb_labrtflg;
795 u_int16_t pdb_lstopflg;
796 u_int16_t pdb_sqhead;
797 u_int16_t pdb_sqtail;
798 u_int16_t pdb_ptimer;
799 u_int16_t pdb_nxt_seqid;
800 u_int16_t pdb_fcount;
801 u_int16_t pdb_prli_len;
802 u_int16_t pdb_prli_svc0;
803 u_int16_t pdb_prli_svc3;
804 u_int16_t pdb_loopid;
805 u_int16_t pdb_il_ptr;
806 u_int16_t pdb_sl_ptr;
807} isp_pdb_t;
808
809#define PDB_OPTIONS_XMITTING (1<<11)
810#define PDB_OPTIONS_LNKXMIT (1<<10)
811#define PDB_OPTIONS_ABORTED (1<<9)
812#define PDB_OPTIONS_ADISC (1<<1)
813
814#define PDB_STATE_DISCOVERY 0
815#define PDB_STATE_WDISC_ACK 1
816#define PDB_STATE_PLOGI 2
817#define PDB_STATE_PLOGI_ACK 3
818#define PDB_STATE_PRLI 4
819#define PDB_STATE_PRLI_ACK 5
820#define PDB_STATE_LOGGED_IN 6
821#define PDB_STATE_PORT_UNAVAIL 7
822#define PDB_STATE_PRLO 8
823#define PDB_STATE_PRLO_ACK 9
824#define PDB_STATE_PLOGO 10
825#define PDB_STATE_PLOG_ACK 11
826
827#define SVC3_TGT_ROLE 0x10
828#define SVC3_INI_ROLE 0x20
829#define SVC3_ROLE_MASK 0x30
830#define SVC3_ROLE_SHIFT 4
831
832/*
833 * CT definition
834 *
835 * This is as the QLogic f/w documentations defines it- which is just opposite,
836 * bit wise, from what the specification defines it as. Additionally, the
837 * ct_response and ct_resid (really from FC-GS-2) need to be byte swapped.
838 */
839
840typedef struct {
841 u_int8_t ct_revision;
842 u_int8_t ct_portid[3];
843 u_int8_t ct_fcs_type;
844 u_int8_t ct_fcs_subtype;
845 u_int8_t ct_options;
846 u_int8_t ct_res0;
847 u_int16_t ct_response;
848 u_int16_t ct_resid;
849 u_int8_t ct_res1;
850 u_int8_t ct_reason;
851 u_int8_t ct_explanation;
852 u_int8_t ct_vunique;
853} ct_hdr_t;
854#define FS_ACC 0x8002
855#define FS_RJT 0x8001
856
857#define FC4_IP 5 /* ISO/EEC 8802-2 LLC/SNAP "Out of Order Delivery" */
858#define FC4_SCSI 8 /* SCSI-3 via Fivre Channel Protocol (FCP) */
859#define FC4_FC_SVC 0x20 /* Fibre Channel Services */
860
861#define SNS_GA_NXT 0x100
862#define SNS_GPN_ID 0x112
863#define SNS_GNN_ID 0x113
864#define SNS_GFF_ID 0x11F
865#define SNS_GID_FT 0x171
866#define SNS_RFT_ID 0x217
867typedef struct {
868 u_int16_t snscb_rblen; /* response buffer length (words) */
869 u_int16_t snscb_res0;
870 u_int16_t snscb_addr[4]; /* response buffer address */
871 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
872 u_int16_t snscb_res1;
873 u_int16_t snscb_data[1]; /* variable data */
874} sns_screq_t; /* Subcommand Request Structure */
875
876typedef struct {
877 u_int16_t snscb_rblen; /* response buffer length (words) */
878 u_int16_t snscb_res0;
879 u_int16_t snscb_addr[4]; /* response buffer address */
880 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
881 u_int16_t snscb_res1;
882 u_int16_t snscb_cmd;
883 u_int16_t snscb_res2;
884 u_int32_t snscb_res3;
885 u_int32_t snscb_port;
886} sns_ga_nxt_req_t;
887#define SNS_GA_NXT_REQ_SIZE (sizeof (sns_ga_nxt_req_t))
888
889typedef struct {
890 u_int16_t snscb_rblen; /* response buffer length (words) */
891 u_int16_t snscb_res0;
892 u_int16_t snscb_addr[4]; /* response buffer address */
893 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
894 u_int16_t snscb_res1;
895 u_int16_t snscb_cmd;
896 u_int16_t snscb_res2;
897 u_int32_t snscb_res3;
898 u_int32_t snscb_portid;
899} sns_gxn_id_req_t;
900#define SNS_GXN_ID_REQ_SIZE (sizeof (sns_gxn_id_req_t))
901
902typedef struct {
903 u_int16_t snscb_rblen; /* response buffer length (words) */
904 u_int16_t snscb_res0;
905 u_int16_t snscb_addr[4]; /* response buffer address */
906 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
907 u_int16_t snscb_res1;
908 u_int16_t snscb_cmd;
909 u_int16_t snscb_mword_div_2;
910 u_int32_t snscb_res3;
911 u_int32_t snscb_fc4_type;
912} sns_gid_ft_req_t;
913#define SNS_GID_FT_REQ_SIZE (sizeof (sns_gid_ft_req_t))
914
915typedef struct {
916 u_int16_t snscb_rblen; /* response buffer length (words) */
917 u_int16_t snscb_res0;
918 u_int16_t snscb_addr[4]; /* response buffer address */
919 u_int16_t snscb_sblen; /* subcommand buffer length (words) */
920 u_int16_t snscb_res1;
921 u_int16_t snscb_cmd;
922 u_int16_t snscb_res2;
923 u_int32_t snscb_res3;
924 u_int32_t snscb_port;
925 u_int32_t snscb_fc4_types[8];
926} sns_rft_id_req_t;
927#define SNS_RFT_ID_REQ_SIZE (sizeof (sns_rft_id_req_t))
928
929typedef struct {
930 ct_hdr_t snscb_cthdr;
931 u_int8_t snscb_port_type;
932 u_int8_t snscb_port_id[3];
933 u_int8_t snscb_portname[8];
934 u_int16_t snscb_data[1]; /* variable data */
935} sns_scrsp_t; /* Subcommand Response Structure */
936
937typedef struct {
938 ct_hdr_t snscb_cthdr;
939 u_int8_t snscb_port_type;
940 u_int8_t snscb_port_id[3];
941 u_int8_t snscb_portname[8];
942 u_int8_t snscb_pnlen; /* symbolic port name length */
943 u_int8_t snscb_pname[255]; /* symbolic port name */
944 u_int8_t snscb_nodename[8];
945 u_int8_t snscb_nnlen; /* symbolic node name length */
946 u_int8_t snscb_nname[255]; /* symbolic node name */
947 u_int8_t snscb_ipassoc[8];
948 u_int8_t snscb_ipaddr[16];
949 u_int8_t snscb_svc_class[4];
950 u_int8_t snscb_fc4_types[32];
951 u_int8_t snscb_fpname[8];
952 u_int8_t snscb_reserved;
953 u_int8_t snscb_hardaddr[3];
954} sns_ga_nxt_rsp_t; /* Subcommand Response Structure */
955#define SNS_GA_NXT_RESP_SIZE (sizeof (sns_ga_nxt_rsp_t))
956
957typedef struct {
958 ct_hdr_t snscb_cthdr;
959 u_int8_t snscb_wwn[8];
960} sns_gxn_id_rsp_t;
961#define SNS_GXN_ID_RESP_SIZE (sizeof (sns_gxn_id_rsp_t))
962
963typedef struct {
964 ct_hdr_t snscb_cthdr;
965 u_int32_t snscb_fc4_features[32];
966} sns_gff_id_rsp_t;
967#define SNS_GFF_ID_RESP_SIZE (sizeof (sns_gff_id_rsp_t))
968
969typedef struct {
970 ct_hdr_t snscb_cthdr;
971 struct {
972 u_int8_t control;
973 u_int8_t portid[3];
974 } snscb_ports[1];
975} sns_gid_ft_rsp_t;
976#define SNS_GID_FT_RESP_SIZE(x) ((sizeof (sns_gid_ft_rsp_t)) + ((x - 1) << 2))
977
978#define SNS_RFT_ID_RESP_SIZE (sizeof (ct_hdr_t))
979
980#endif /* _ISPMBOX_H */
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