1/*-
2 * Copyright (c) 1999 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Paul Kranenburg.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 * from: NetBSD: hmereg.h,v 1.7 2001/04/30 03:47:34 lukem Exp
37 *
| 1/*-
2 * Copyright (c) 1999 The NetBSD Foundation, Inc.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Paul Kranenburg.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the NetBSD
19 * Foundation, Inc. and its contributors.
20 * 4. Neither the name of The NetBSD Foundation nor the names of its
21 * contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
26 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 * from: NetBSD: hmereg.h,v 1.7 2001/04/30 03:47:34 lukem Exp
37 *
|
39 */
40
41/*
42 * HME Shared Ethernet Block register offsets
43 */
44#define HME_SEBI_RESET (0*4)
45#define HME_SEBI_CFG (1*4)
46#define HME_SEBI_STAT (64*4)
47#define HME_SEBI_IMASK (65*4)
48
49/* HME SEB bits. */
50#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */
51#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */
52
53#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */
54#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */
55#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */
56#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */
57#define HME_SEB_CFG_64BIT 0x00000004 /* ? */
58#define HME_SEB_CFG_PARITY 0x00000008 /* ? */
59
60#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */
61#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */
62#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */
63#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */
64#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */
65#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
66#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */
67#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */
68#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */
69#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
70#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
71#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */
72#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */
73#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */
74#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */
75#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */
76#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */
77#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */
78#define HME_SEB_STAT_RXERR 0x00040000 /* rx dma error */
79#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx dma */
80#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx dma */
81#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx dma */
82#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */
83#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */
84#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */
85#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */
86#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx dma */
87#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx dma */
88#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx dma */
89#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error durig tx dma */
90#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */
91#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */
92#define HME_SEB_STAT_BITS "\177\020" \
93 "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \
94 "b\3CCNTEXP\0b\4LCNTEXP\0b\5RFIFOVF\0" \
95 "b\6CVCNTEXP\0b\7STSTERR\0b\10SENTFRAME\0" \
96 "b\11TFIFO_UND\0b\12MAXPKTERR\0b\13NCNTEXP\0" \
97 "b\14ECNTEXP\0b\15LCCNTEXP\0b\16FCNTEXP\0" \
98 "b\17DTIMEXP\0b\20RXTOHOST\0b\21NORXD\0" \
99 "b\22RXERR\0b\23RXLATERR\0b\24RXPERR\0" \
100 "b\25RXTERR\0b\26EOPERR\0b\27MIFIRQ\0" \
101 "b\30HOSTTOTX\0b\31TXALL\0b\32XTEACK\0" \
102 "b\33TXLERR\0b\34TXPERR\0b\35TXTERR\0" \
103 "b\36SLVERR\0b\37SLVPERR\0\0"
104
105#define HME_SEB_STAT_ALL_ERRORS \
106 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
107 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
108 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
109 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
110 HME_SEB_STAT_MAXPKTERR| HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR |\
111 HME_SEB_STAT_RFIFOVF)
112
113#define HME_SEB_STAT_VLAN_ERRORS \
114 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
115 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
116 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
117 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
118 HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_RFIFOVF)
119
120/*
121 * HME Transmitter register offsets
122 */
123#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */
124#define HME_ETXI_CFG (1*4)
125#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */
126#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */
127#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */
128#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */
129#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */
130#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */
131#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */
132#define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */
133#define HME_ETXI_STATEMACHINE (10*4) /* State machine */
134#define HME_ETXI_RSIZE (11*4) /* Ring size */
135#define HME_ETXI_BPTR (12*4) /* Buffer pointer */
136
137
138/* TXI_PENDING bits */
139#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */
140
141/* TXI_CFG bits */
142#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX dma */
143#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */
144#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */
145#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */
146
147
148/*
149 * HME Receiver register offsets
150 */
151#define HME_ERXI_CFG (0*4)
152#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */
153#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */
154#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */
155#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */
156#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */
157#define HME_ERXI_FIFO_SRPTR (6*4) /* FIFO shadow read pointer */
158#define HME_ERXI_STATEMACHINE (7*4) /* State machine */
159
160/* RXI_CFG bits */
161#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX dma */
162#define HME_ERX_CFG_FBO_MASK 0x00000038 /* RX first byte offset */
163#define HME_ERX_CFG_FBO_SHIFT 0x00000003
164#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */
165#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */
166#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */
167#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */
168#define HME_ERX_CFG_RINGSIZEMSK 0x00000600 /* Descriptor ring size: 256 */
169#define HME_ERX_CFG_CSUMSTART 0x007f0000 /* cksum offset */
170
171/*
172 * HME MAC-core register offsets
173 */
174#define HME_MACI_XIF (0*4)
175#define HME_MACI_TXSWRST (130*4) /* TX reset */
176#define HME_MACI_TXCFG (131*4) /* TX config */
177#define HME_MACI_JSIZE (139*4) /* TX jam size */
178#define HME_MACI_TXSIZE (140*4) /* TX max size */
179#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */
180#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */
181#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */
182#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */
183#define HME_MACI_RANDSEED (148*4) /* */
184#define HME_MACI_RXSWRST (194*4) /* RX reset */
185#define HME_MACI_RXCFG (195*4) /* RX config */
186#define HME_MACI_RXSIZE (196*4) /* RX max size */
187#define HME_MACI_MACADDR2 (198*4) /* MAC address */
188#define HME_MACI_MACADDR1 (199*4)
189#define HME_MACI_MACADDR0 (200*4)
190#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */
191#define HME_MACI_HASHTAB2 (209*4)
192#define HME_MACI_HASHTAB1 (210*4)
193#define HME_MACI_HASHTAB0 (211*4)
194#define HME_MACI_AFILTER2 (212*4) /* Address filter */
195#define HME_MACI_AFILTER1 (213*4)
196#define HME_MACI_AFILTER0 (214*4)
197#define HME_MACI_AFILTER_MASK (215*4)
198
199/* XIF config register. */
200#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */
201#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */
202#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */
203#define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */
204#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */
205#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */
206#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */
207#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */
208
209/* Transmit config register. */
210#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
211#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
212#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
213#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
214#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
215#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
216#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
217
218/* Receive config register. */
219#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
220#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
221#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
222#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */
223#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
224#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
225#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
226#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
227#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
228
229/*
230 * HME MIF register offsets
231 */
232#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */
233#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */
234#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */
235#define HME_MIFI_FO (3*4) /* frame output */
236#define HME_MIFI_CFG (4*4) /* */
237#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */
238#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */
239#define HME_MIFI_SM (7*4) /* State machine (ro) */
240
241/* MIF Configuration register */
242#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */
243#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */
244#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */
245#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register adddress */
246#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */
247#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */
248#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy adddress */
249
250/* MIF Frame/Output register */
251#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */
252#define HME_MIF_FO_ST_SHIFT 30 /* */
253#define HME_MIF_FO_OPC 0x30000000 /* Opcode */
254#define HME_MIF_FO_OPC_SHIFT 28 /* */
255#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */
256#define HME_MIF_FO_PHYAD_SHIFT 23 /* */
257#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */
258#define HME_MIF_FO_REGAD_SHIFT 18 /* */
259#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */
260#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */
261#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */
262
263/* Wired HME PHY addresses */
264#define HME_PHYAD_INTERNAL 1
265#define HME_PHYAD_EXTERNAL 0
266
267/*
268 * Buffer Descriptors.
269 */
270#define HME_XD_SIZE 8
271#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0)
272#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4)
273#define HME_XD_GETFLAGS(p, b, i) \
274 ((p) ? le32toh(*((u_int32_t *)HME_XD_FLAGS(b,i))) : \
275 (*((u_int32_t *)HME_XD_FLAGS(b,i))))
276#define HME_XD_SETFLAGS(p, b, i, f) do { \
277 *((u_int32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32(f) : (f)); \
278} while(0)
279#define HME_XD_SETADDR(p, b, i, a) do { \
280 *((u_int32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32(a) : (a)); \
281} while(0)
282
283/* Descriptor flag values */
284#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
285#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */
286#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */
287#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */
288#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */
289#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */
290#define HME_XD_RXLENSHIFT 16
291#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */
292#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */
293
294/* Macros to encode/decode the receive buffer size from the flags field */
295#define HME_XD_ENCODE_RSIZE(sz) \
296 (((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK)
297#define HME_XD_DECODE_RSIZE(flags) \
298 (((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT)
299
300/* Provide encode/decode macros for the transmit buffers for symmetry */
301#define HME_XD_ENCODE_TSIZE(sz) \
302 (((sz) << 0) & HME_XD_TXLENMSK)
303#define HME_XD_DECODE_TSIZE(flags) \
304 (((flags) & HME_XD_TXLENMSK) >> 0)
305
306#define PCI_HME_BASEADDR 0x10
| 39 */
40
41/*
42 * HME Shared Ethernet Block register offsets
43 */
44#define HME_SEBI_RESET (0*4)
45#define HME_SEBI_CFG (1*4)
46#define HME_SEBI_STAT (64*4)
47#define HME_SEBI_IMASK (65*4)
48
49/* HME SEB bits. */
50#define HME_SEB_RESET_ETX 0x00000001 /* reset external transmitter */
51#define HME_SEB_RESET_ERX 0x00000002 /* reset external receiver */
52
53#define HME_SEB_CFG_BURSTMASK 0x00000003 /* covers all burst bits */
54#define HME_SEB_CFG_BURST16 0x00000000 /* 16 byte bursts */
55#define HME_SEB_CFG_BURST32 0x00000001 /* 32 byte bursts */
56#define HME_SEB_CFG_BURST64 0x00000002 /* 64 byte bursts */
57#define HME_SEB_CFG_64BIT 0x00000004 /* ? */
58#define HME_SEB_CFG_PARITY 0x00000008 /* ? */
59
60#define HME_SEB_STAT_GOTFRAME 0x00000001 /* frame received */
61#define HME_SEB_STAT_RCNTEXP 0x00000002 /* rx frame count expired */
62#define HME_SEB_STAT_ACNTEXP 0x00000004 /* align error count expired */
63#define HME_SEB_STAT_CCNTEXP 0x00000008 /* crc error count expired */
64#define HME_SEB_STAT_LCNTEXP 0x00000010 /* length error count expired */
65#define HME_SEB_STAT_RFIFOVF 0x00000020 /* rx fifo overflow */
66#define HME_SEB_STAT_CVCNTEXP 0x00000040 /* code violation counter exp */
67#define HME_SEB_STAT_STSTERR 0x00000080 /* xif sqe test failed */
68#define HME_SEB_STAT_SENTFRAME 0x00000100 /* frame sent */
69#define HME_SEB_STAT_TFIFO_UND 0x00000200 /* tx fifo underrun */
70#define HME_SEB_STAT_MAXPKTERR 0x00000400 /* max-packet size error */
71#define HME_SEB_STAT_NCNTEXP 0x00000800 /* normal collision count exp */
72#define HME_SEB_STAT_ECNTEXP 0x00001000 /* excess collision count exp */
73#define HME_SEB_STAT_LCCNTEXP 0x00002000 /* late collision count exp */
74#define HME_SEB_STAT_FCNTEXP 0x00004000 /* first collision count exp */
75#define HME_SEB_STAT_DTIMEXP 0x00008000 /* defer timer expired */
76#define HME_SEB_STAT_RXTOHOST 0x00010000 /* pkt moved from rx fifo->memory */
77#define HME_SEB_STAT_NORXD 0x00020000 /* out of receive descriptors */
78#define HME_SEB_STAT_RXERR 0x00040000 /* rx dma error */
79#define HME_SEB_STAT_RXLATERR 0x00080000 /* late error during rx dma */
80#define HME_SEB_STAT_RXPERR 0x00100000 /* parity error during rx dma */
81#define HME_SEB_STAT_RXTERR 0x00200000 /* tag error during rx dma */
82#define HME_SEB_STAT_EOPERR 0x00400000 /* tx descriptor did not set EOP */
83#define HME_SEB_STAT_MIFIRQ 0x00800000 /* mif needs attention */
84#define HME_SEB_STAT_HOSTTOTX 0x01000000 /* pkt moved from memory->tx fifo */
85#define HME_SEB_STAT_TXALL 0x02000000 /* all pkts in fifo transmitted */
86#define HME_SEB_STAT_TXEACK 0x04000000 /* error during tx dma */
87#define HME_SEB_STAT_TXLERR 0x08000000 /* late error during tx dma */
88#define HME_SEB_STAT_TXPERR 0x10000000 /* parity error during tx dma */
89#define HME_SEB_STAT_TXTERR 0x20000000 /* tag error durig tx dma */
90#define HME_SEB_STAT_SLVERR 0x40000000 /* pio access error */
91#define HME_SEB_STAT_SLVPERR 0x80000000 /* pio access parity error */
92#define HME_SEB_STAT_BITS "\177\020" \
93 "b\0GOTFRAME\0b\1RCNTEXP\0b\2ACNTEXP\0" \
94 "b\3CCNTEXP\0b\4LCNTEXP\0b\5RFIFOVF\0" \
95 "b\6CVCNTEXP\0b\7STSTERR\0b\10SENTFRAME\0" \
96 "b\11TFIFO_UND\0b\12MAXPKTERR\0b\13NCNTEXP\0" \
97 "b\14ECNTEXP\0b\15LCCNTEXP\0b\16FCNTEXP\0" \
98 "b\17DTIMEXP\0b\20RXTOHOST\0b\21NORXD\0" \
99 "b\22RXERR\0b\23RXLATERR\0b\24RXPERR\0" \
100 "b\25RXTERR\0b\26EOPERR\0b\27MIFIRQ\0" \
101 "b\30HOSTTOTX\0b\31TXALL\0b\32XTEACK\0" \
102 "b\33TXLERR\0b\34TXPERR\0b\35TXTERR\0" \
103 "b\36SLVERR\0b\37SLVPERR\0\0"
104
105#define HME_SEB_STAT_ALL_ERRORS \
106 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
107 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
108 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
109 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
110 HME_SEB_STAT_MAXPKTERR| HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR |\
111 HME_SEB_STAT_RFIFOVF)
112
113#define HME_SEB_STAT_VLAN_ERRORS \
114 (HME_SEB_STAT_SLVPERR | HME_SEB_STAT_SLVERR | HME_SEB_STAT_TXTERR |\
115 HME_SEB_STAT_TXPERR | HME_SEB_STAT_TXLERR | HME_SEB_STAT_TXEACK |\
116 HME_SEB_STAT_EOPERR | HME_SEB_STAT_RXTERR | HME_SEB_STAT_RXPERR |\
117 HME_SEB_STAT_RXLATERR | HME_SEB_STAT_RXERR | HME_SEB_STAT_NORXD |\
118 HME_SEB_STAT_TFIFO_UND| HME_SEB_STAT_STSTERR | HME_SEB_STAT_RFIFOVF)
119
120/*
121 * HME Transmitter register offsets
122 */
123#define HME_ETXI_PENDING (0*4) /* Pending/wakeup */
124#define HME_ETXI_CFG (1*4)
125#define HME_ETXI_RING (2*4) /* Descriptor Ring pointer */
126#define HME_ETXI_BBASE (3*4) /* Buffer base address (ro) */
127#define HME_ETXI_BDISP (4*4) /* Buffer displacement (ro) */
128#define HME_ETXI_FIFO_WPTR (5*4) /* FIFO write pointer */
129#define HME_ETXI_FIFO_SWPTR (6*4) /* FIFO shadow write pointer */
130#define HME_ETXI_FIFO_RPTR (7*4) /* FIFO read pointer */
131#define HME_ETXI_FIFO_SRPTR (8*4) /* FIFO shadow read pointer */
132#define HME_ETXI_FIFO_PKTCNT (9*4) /* FIFO packet counter */
133#define HME_ETXI_STATEMACHINE (10*4) /* State machine */
134#define HME_ETXI_RSIZE (11*4) /* Ring size */
135#define HME_ETXI_BPTR (12*4) /* Buffer pointer */
136
137
138/* TXI_PENDING bits */
139#define HME_ETX_TP_DMAWAKEUP 0x00000001 /* Start tx (rw, auto-clear) */
140
141/* TXI_CFG bits */
142#define HME_ETX_CFG_DMAENABLE 0x00000001 /* Enable TX dma */
143#define HME_ETX_CFG_FIFOTHRESH 0x000003fe /* TX fifo threshold */
144#define HME_ETX_CFG_IRQDAFTER 0x00000400 /* Intr after tx-fifo empty */
145#define HME_ETX_CFG_IRQDBEFORE 0x00000000 /* Intr before tx-fifo empty */
146
147
148/*
149 * HME Receiver register offsets
150 */
151#define HME_ERXI_CFG (0*4)
152#define HME_ERXI_RING (1*4) /* Descriptor Ring pointer */
153#define HME_ERXI_BPTR (2*4) /* Data Buffer pointer (ro) */
154#define HME_ERXI_FIFO_WPTR (3*4) /* FIFO write pointer */
155#define HME_ERXI_FIFO_SWPTR (4*4) /* FIFO shadow write pointer */
156#define HME_ERXI_FIFO_RPTR (5*4) /* FIFO read pointer */
157#define HME_ERXI_FIFO_SRPTR (6*4) /* FIFO shadow read pointer */
158#define HME_ERXI_STATEMACHINE (7*4) /* State machine */
159
160/* RXI_CFG bits */
161#define HME_ERX_CFG_DMAENABLE 0x00000001 /* Enable RX dma */
162#define HME_ERX_CFG_FBO_MASK 0x00000038 /* RX first byte offset */
163#define HME_ERX_CFG_FBO_SHIFT 0x00000003
164#define HME_ERX_CFG_RINGSIZE32 0x00000000 /* Descriptor ring size: 32 */
165#define HME_ERX_CFG_RINGSIZE64 0x00000200 /* Descriptor ring size: 64 */
166#define HME_ERX_CFG_RINGSIZE128 0x00000400 /* Descriptor ring size: 128 */
167#define HME_ERX_CFG_RINGSIZE256 0x00000600 /* Descriptor ring size: 256 */
168#define HME_ERX_CFG_RINGSIZEMSK 0x00000600 /* Descriptor ring size: 256 */
169#define HME_ERX_CFG_CSUMSTART 0x007f0000 /* cksum offset */
170
171/*
172 * HME MAC-core register offsets
173 */
174#define HME_MACI_XIF (0*4)
175#define HME_MACI_TXSWRST (130*4) /* TX reset */
176#define HME_MACI_TXCFG (131*4) /* TX config */
177#define HME_MACI_JSIZE (139*4) /* TX jam size */
178#define HME_MACI_TXSIZE (140*4) /* TX max size */
179#define HME_MACI_NCCNT (144*4) /* TX normal collision cnt */
180#define HME_MACI_FCCNT (145*4) /* TX first collision cnt */
181#define HME_MACI_EXCNT (146*4) /* TX excess collision cnt */
182#define HME_MACI_LTCNT (147*4) /* TX late collision cnt */
183#define HME_MACI_RANDSEED (148*4) /* */
184#define HME_MACI_RXSWRST (194*4) /* RX reset */
185#define HME_MACI_RXCFG (195*4) /* RX config */
186#define HME_MACI_RXSIZE (196*4) /* RX max size */
187#define HME_MACI_MACADDR2 (198*4) /* MAC address */
188#define HME_MACI_MACADDR1 (199*4)
189#define HME_MACI_MACADDR0 (200*4)
190#define HME_MACI_HASHTAB3 (208*4) /* Address hash table */
191#define HME_MACI_HASHTAB2 (209*4)
192#define HME_MACI_HASHTAB1 (210*4)
193#define HME_MACI_HASHTAB0 (211*4)
194#define HME_MACI_AFILTER2 (212*4) /* Address filter */
195#define HME_MACI_AFILTER1 (213*4)
196#define HME_MACI_AFILTER0 (214*4)
197#define HME_MACI_AFILTER_MASK (215*4)
198
199/* XIF config register. */
200#define HME_MAC_XIF_OE 0x00000001 /* Output driver enable */
201#define HME_MAC_XIF_XLBACK 0x00000002 /* Loopback-mode XIF enable */
202#define HME_MAC_XIF_MLBACK 0x00000004 /* Loopback-mode MII enable */
203#define HME_MAC_XIF_MIIENABLE 0x00000008 /* MII receive buffer enable */
204#define HME_MAC_XIF_SQENABLE 0x00000010 /* SQE test enable */
205#define HME_MAC_XIF_SQETWIN 0x000003e0 /* SQE time window */
206#define HME_MAC_XIF_LANCE 0x00000010 /* Lance mode enable */
207#define HME_MAC_XIF_LIPG0 0x000003e0 /* Lance mode IPG0 */
208
209/* Transmit config register. */
210#define HME_MAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
211#define HME_MAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
212#define HME_MAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
213#define HME_MAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
214#define HME_MAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
215#define HME_MAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
216#define HME_MAC_TXCFG_DGIVEUP 0x00000400 /* Don't give up on transmits */
217
218/* Receive config register. */
219#define HME_MAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
220#define HME_MAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
221#define HME_MAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
222#define HME_MAC_RXCFG_DERR 0x00000080 /* Disable error checking */
223#define HME_MAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
224#define HME_MAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
225#define HME_MAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
226#define HME_MAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
227#define HME_MAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
228
229/*
230 * HME MIF register offsets
231 */
232#define HME_MIFI_BB_CLK (0*4) /* bit-bang clock */
233#define HME_MIFI_BB_DATA (1*4) /* bit-bang data */
234#define HME_MIFI_BB_OE (2*4) /* bit-bang output enable */
235#define HME_MIFI_FO (3*4) /* frame output */
236#define HME_MIFI_CFG (4*4) /* */
237#define HME_MIFI_IMASK (5*4) /* Interrupt mask for status change */
238#define HME_MIFI_STAT (6*4) /* Status (ro, auto-clear) */
239#define HME_MIFI_SM (7*4) /* State machine (ro) */
240
241/* MIF Configuration register */
242#define HME_MIF_CFG_PHY 0x00000001 /* PHY select */
243#define HME_MIF_CFG_PE 0x00000002 /* Poll enable */
244#define HME_MIF_CFG_BBMODE 0x00000004 /* Bit-bang mode */
245#define HME_MIF_CFG_PRADDR 0x000000f8 /* Poll register adddress */
246#define HME_MIF_CFG_MDI0 0x00000100 /* MDI_0 (ro) */
247#define HME_MIF_CFG_MDI1 0x00000200 /* MDI_1 (ro) */
248#define HME_MIF_CFG_PPADDR 0x00007c00 /* Poll phy adddress */
249
250/* MIF Frame/Output register */
251#define HME_MIF_FO_ST 0xc0000000 /* Start of frame */
252#define HME_MIF_FO_ST_SHIFT 30 /* */
253#define HME_MIF_FO_OPC 0x30000000 /* Opcode */
254#define HME_MIF_FO_OPC_SHIFT 28 /* */
255#define HME_MIF_FO_PHYAD 0x0f800000 /* PHY Address */
256#define HME_MIF_FO_PHYAD_SHIFT 23 /* */
257#define HME_MIF_FO_REGAD 0x007c0000 /* Register Address */
258#define HME_MIF_FO_REGAD_SHIFT 18 /* */
259#define HME_MIF_FO_TAMSB 0x00020000 /* Turn-around MSB */
260#define HME_MIF_FO_TALSB 0x00010000 /* Turn-around LSB */
261#define HME_MIF_FO_DATA 0x0000ffff /* data to read or write */
262
263/* Wired HME PHY addresses */
264#define HME_PHYAD_INTERNAL 1
265#define HME_PHYAD_EXTERNAL 0
266
267/*
268 * Buffer Descriptors.
269 */
270#define HME_XD_SIZE 8
271#define HME_XD_FLAGS(base, index) ((base) + ((index) * HME_XD_SIZE) + 0)
272#define HME_XD_ADDR(base, index) ((base) + ((index) * HME_XD_SIZE) + 4)
273#define HME_XD_GETFLAGS(p, b, i) \
274 ((p) ? le32toh(*((u_int32_t *)HME_XD_FLAGS(b,i))) : \
275 (*((u_int32_t *)HME_XD_FLAGS(b,i))))
276#define HME_XD_SETFLAGS(p, b, i, f) do { \
277 *((u_int32_t *)HME_XD_FLAGS(b,i)) = ((p) ? htole32(f) : (f)); \
278} while(0)
279#define HME_XD_SETADDR(p, b, i, a) do { \
280 *((u_int32_t *)HME_XD_ADDR(b,i)) = ((p) ? htole32(a) : (a)); \
281} while(0)
282
283/* Descriptor flag values */
284#define HME_XD_OWN 0x80000000 /* ownership: 1=hw, 0=sw */
285#define HME_XD_SOP 0x40000000 /* start of packet marker (tx) */
286#define HME_XD_OFL 0x40000000 /* buffer overflow (rx) */
287#define HME_XD_EOP 0x20000000 /* end of packet marker (tx) */
288#define HME_XD_TXCKSUM 0x10000000 /* checksum enable (tx) */
289#define HME_XD_RXLENMSK 0x3fff0000 /* packet length mask (rx) */
290#define HME_XD_RXLENSHIFT 16
291#define HME_XD_TXLENMSK 0x00003fff /* packet length mask (tx) */
292#define HME_XD_RXCKSUM 0x0000ffff /* packet checksum (rx) */
293
294/* Macros to encode/decode the receive buffer size from the flags field */
295#define HME_XD_ENCODE_RSIZE(sz) \
296 (((sz) << HME_XD_RXLENSHIFT) & HME_XD_RXLENMSK)
297#define HME_XD_DECODE_RSIZE(flags) \
298 (((flags) & HME_XD_RXLENMSK) >> HME_XD_RXLENSHIFT)
299
300/* Provide encode/decode macros for the transmit buffers for symmetry */
301#define HME_XD_ENCODE_TSIZE(sz) \
302 (((sz) << 0) & HME_XD_TXLENMSK)
303#define HME_XD_DECODE_TSIZE(flags) \
304 (((flags) & HME_XD_TXLENMSK) >> 0)
305
306#define PCI_HME_BASEADDR 0x10
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