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if_gem.c (164931) if_gem.c (169269)
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
28 */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 14 unchanged lines hidden (view full) ---

23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 164931 2006-12-06 02:04:25Z marius $");
31__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 169269 2007-05-04 19:15:28Z phk $");
32
33/*
34 * Driver for Sun GEM ethernet controllers.
35 */
36
37#if 0
38#define GEM_DEBUG
39#endif

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50#include <sys/mbuf.h>
51#include <sys/malloc.h>
52#include <sys/kernel.h>
53#include <sys/lock.h>
54#include <sys/module.h>
55#include <sys/mutex.h>
56#include <sys/socket.h>
57#include <sys/sockio.h>
32
33/*
34 * Driver for Sun GEM ethernet controllers.
35 */
36
37#if 0
38#define GEM_DEBUG
39#endif

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50#include <sys/mbuf.h>
51#include <sys/malloc.h>
52#include <sys/kernel.h>
53#include <sys/lock.h>
54#include <sys/module.h>
55#include <sys/mutex.h>
56#include <sys/socket.h>
57#include <sys/sockio.h>
58#include <sys/rman.h>
58
59#include <net/bpf.h>
60#include <net/ethernet.h>
61#include <net/if.h>
62#include <net/if_arp.h>
63#include <net/if_dl.h>
64#include <net/if_media.h>
65#include <net/if_types.h>

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252 /*
253 * From this point forward, the attachment cannot fail. A failure
254 * before this point releases all resources that may have been
255 * allocated.
256 */
257
258 /* Get RX FIFO size */
259 sc->sc_rxfifosize = 64 *
59
60#include <net/bpf.h>
61#include <net/ethernet.h>
62#include <net/if.h>
63#include <net/if_arp.h>
64#include <net/if_dl.h>
65#include <net/if_media.h>
66#include <net/if_types.h>

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253 /*
254 * From this point forward, the attachment cannot fail. A failure
255 * before this point releases all resources that may have been
256 * allocated.
257 */
258
259 /* Get RX FIFO size */
260 sc->sc_rxfifosize = 64 *
260 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
261 bus_read_4(sc->sc_res[0], GEM_RX_FIFO_SIZE);
261
262 /* Get TX FIFO size */
262
263 /* Get TX FIFO size */
263 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
264 v = bus_read_4(sc->sc_res[0], GEM_TX_FIFO_SIZE);
264 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
265 sc->sc_rxfifosize / 1024, v / 16);
266
267 /* Initialize ifnet structure. */
268 ifp->if_softc = sc;
269 if_initname(ifp, device_get_name(sc->sc_dev),
270 device_get_unit(sc->sc_dev));
271 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;

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310#endif
311 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
312 } else {
313#ifdef GEM_DEBUG
314 printf("using internal phy\n");
315#endif
316 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
317 }
265 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
266 sc->sc_rxfifosize / 1024, v / 16);
267
268 /* Initialize ifnet structure. */
269 ifp->if_softc = sc;
270 if_initname(ifp, device_get_name(sc->sc_dev),
271 device_get_unit(sc->sc_dev));
272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;

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311#endif
312 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
313 } else {
314#ifdef GEM_DEBUG
315 printf("using internal phy\n");
316#endif
317 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
318 }
318 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
319 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG,
319 sc->sc_mif_config);
320 /* Attach the interface. */
321 ether_ifattach(ifp, sc->sc_enaddr);
322
323#ifdef notyet
324 /*
325 * Add a suspend hook to make sure we come back up after a
326 * resume.

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554 bus_addr_t r;
555 u_int32_t clr;
556 u_int32_t set;
557{
558 int i;
559 u_int32_t reg;
560
561 for (i = TRIES; i--; DELAY(100)) {
320 sc->sc_mif_config);
321 /* Attach the interface. */
322 ether_ifattach(ifp, sc->sc_enaddr);
323
324#ifdef notyet
325 /*
326 * Add a suspend hook to make sure we come back up after a
327 * resume.

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555 bus_addr_t r;
556 u_int32_t clr;
557 u_int32_t set;
558{
559 int i;
560 u_int32_t reg;
561
562 for (i = TRIES; i--; DELAY(100)) {
562 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r);
563 reg = bus_read_4(sc->sc_res[0], r);
563 if ((r & clr) == 0 && (r & set) == set)
564 return (1);
565 }
566 return (0);
567}
568
569void
570gem_reset(sc)
571 struct gem_softc *sc;
572{
564 if ((r & clr) == 0 && (r & set) == set)
565 return (1);
566 }
567 return (0);
568}
569
570void
571gem_reset(sc)
572 struct gem_softc *sc;
573{
573 bus_space_tag_t t = sc->sc_bustag;
574 bus_space_handle_t h = sc->sc_h;
575
576#ifdef GEM_DEBUG
577 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
578#endif
579 gem_reset_rx(sc);
580 gem_reset_tx(sc);
581
582 /* Do a full reset */
574
575#ifdef GEM_DEBUG
576 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
577#endif
578 gem_reset_rx(sc);
579 gem_reset_tx(sc);
580
581 /* Do a full reset */
583 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
582 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
584 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
585 device_printf(sc->sc_dev, "cannot reset device\n");
586}
587
588
589/*
590 * gem_rxdrain:
591 *

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663
664/*
665 * Reset the receiver
666 */
667int
668gem_reset_rx(sc)
669 struct gem_softc *sc;
670{
583 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
584 device_printf(sc->sc_dev, "cannot reset device\n");
585}
586
587
588/*
589 * gem_rxdrain:
590 *

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662
663/*
664 * Reset the receiver
665 */
666int
667gem_reset_rx(sc)
668 struct gem_softc *sc;
669{
671 bus_space_tag_t t = sc->sc_bustag;
672 bus_space_handle_t h = sc->sc_h;
673
674 /*
675 * Resetting while DMA is in progress can cause a bus hang, so we
676 * disable DMA first.
677 */
678 gem_disable_rx(sc);
670
671 /*
672 * Resetting while DMA is in progress can cause a bus hang, so we
673 * disable DMA first.
674 */
675 gem_disable_rx(sc);
679 bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
676 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0);
680 /* Wait till it finishes */
681 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
682 device_printf(sc->sc_dev, "cannot disable read dma\n");
683
684 /* Wait 5ms extra. */
685 DELAY(5000);
686
687 /* Finally, reset the ERX */
677 /* Wait till it finishes */
678 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
679 device_printf(sc->sc_dev, "cannot disable read dma\n");
680
681 /* Wait 5ms extra. */
682 DELAY(5000);
683
684 /* Finally, reset the ERX */
688 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
685 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX);
689 /* Wait till it finishes */
690 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
691 device_printf(sc->sc_dev, "cannot reset receiver\n");
692 return (1);
693 }
694 return (0);
695}
696
697
698/*
699 * Reset the transmitter
700 */
701static int
702gem_reset_tx(sc)
703 struct gem_softc *sc;
704{
686 /* Wait till it finishes */
687 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
688 device_printf(sc->sc_dev, "cannot reset receiver\n");
689 return (1);
690 }
691 return (0);
692}
693
694
695/*
696 * Reset the transmitter
697 */
698static int
699gem_reset_tx(sc)
700 struct gem_softc *sc;
701{
705 bus_space_tag_t t = sc->sc_bustag;
706 bus_space_handle_t h = sc->sc_h;
707 int i;
708
709 /*
710 * Resetting while DMA is in progress can cause a bus hang, so we
711 * disable DMA first.
712 */
713 gem_disable_tx(sc);
702 int i;
703
704 /*
705 * Resetting while DMA is in progress can cause a bus hang, so we
706 * disable DMA first.
707 */
708 gem_disable_tx(sc);
714 bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
709 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0);
715 /* Wait till it finishes */
716 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
717 device_printf(sc->sc_dev, "cannot disable read dma\n");
718
719 /* Wait 5ms extra. */
720 DELAY(5000);
721
722 /* Finally, reset the ETX */
710 /* Wait till it finishes */
711 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
712 device_printf(sc->sc_dev, "cannot disable read dma\n");
713
714 /* Wait 5ms extra. */
715 DELAY(5000);
716
717 /* Finally, reset the ETX */
723 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
718 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX);
724 /* Wait till it finishes */
725 for (i = TRIES; i--; DELAY(100))
719 /* Wait till it finishes */
720 for (i = TRIES; i--; DELAY(100))
726 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
721 if ((bus_read_4(sc->sc_res[0], GEM_RESET) & GEM_RESET_TX) == 0)
727 break;
728 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
729 device_printf(sc->sc_dev, "cannot reset receiver\n");
730 return (1);
731 }
732 return (0);
733}
734
735/*
736 * disable receiver.
737 */
738static int
739gem_disable_rx(sc)
740 struct gem_softc *sc;
741{
722 break;
723 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
724 device_printf(sc->sc_dev, "cannot reset receiver\n");
725 return (1);
726 }
727 return (0);
728}
729
730/*
731 * disable receiver.
732 */
733static int
734gem_disable_rx(sc)
735 struct gem_softc *sc;
736{
742 bus_space_tag_t t = sc->sc_bustag;
743 bus_space_handle_t h = sc->sc_h;
744 u_int32_t cfg;
745
746 /* Flip the enable bit */
737 u_int32_t cfg;
738
739 /* Flip the enable bit */
747 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
740 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
748 cfg &= ~GEM_MAC_RX_ENABLE;
741 cfg &= ~GEM_MAC_RX_ENABLE;
749 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
742 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg);
750
751 /* Wait for it to finish */
752 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
753}
754
755/*
756 * disable transmitter.
757 */
758static int
759gem_disable_tx(sc)
760 struct gem_softc *sc;
761{
743
744 /* Wait for it to finish */
745 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
746}
747
748/*
749 * disable transmitter.
750 */
751static int
752gem_disable_tx(sc)
753 struct gem_softc *sc;
754{
762 bus_space_tag_t t = sc->sc_bustag;
763 bus_space_handle_t h = sc->sc_h;
764 u_int32_t cfg;
765
766 /* Flip the enable bit */
755 u_int32_t cfg;
756
757 /* Flip the enable bit */
767 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
758 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG);
768 cfg &= ~GEM_MAC_TX_ENABLE;
759 cfg &= ~GEM_MAC_TX_ENABLE;
769 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
760 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg);
770
771 /* Wait for it to finish */
772 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
773}
774
775/*
776 * Initialize interface.
777 */

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877 * Initialization of interface; set up initialization block
878 * and transmit/receive descriptor rings.
879 */
880static void
881gem_init_locked(sc)
882 struct gem_softc *sc;
883{
884 struct ifnet *ifp = sc->sc_ifp;
761
762 /* Wait for it to finish */
763 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
764}
765
766/*
767 * Initialize interface.
768 */

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868 * Initialization of interface; set up initialization block
869 * and transmit/receive descriptor rings.
870 */
871static void
872gem_init_locked(sc)
873 struct gem_softc *sc;
874{
875 struct ifnet *ifp = sc->sc_ifp;
885 bus_space_tag_t t = sc->sc_bustag;
886 bus_space_handle_t h = sc->sc_h;
887 u_int32_t v;
888
889 GEM_LOCK_ASSERT(sc, MA_OWNED);
890
891#ifdef GEM_DEBUG
892 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev));
893#endif
894 /*

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914 /* step 4. TX MAC registers & counters */
915 gem_init_regs(sc);
916
917 /* step 5. RX MAC registers & counters */
918 gem_setladrf(sc);
919
920 /* step 6 & 7. Program Descriptor Ring Base Addresses */
921 /* NOTE: we use only 32-bit DMA addresses here. */
876 u_int32_t v;
877
878 GEM_LOCK_ASSERT(sc, MA_OWNED);
879
880#ifdef GEM_DEBUG
881 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev));
882#endif
883 /*

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903 /* step 4. TX MAC registers & counters */
904 gem_init_regs(sc);
905
906 /* step 5. RX MAC registers & counters */
907 gem_setladrf(sc);
908
909 /* step 6 & 7. Program Descriptor Ring Base Addresses */
910 /* NOTE: we use only 32-bit DMA addresses here. */
922 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
923 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
911 bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_HI, 0);
912 bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
924
913
925 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
926 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
914 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0);
915 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
927#ifdef GEM_DEBUG
928 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
929 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
930#endif
931
932 /* step 8. Global Configuration & Interrupt Mask */
916#ifdef GEM_DEBUG
917 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
918 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
919#endif
920
921 /* step 8. Global Configuration & Interrupt Mask */
933 bus_space_write_4(t, h, GEM_INTMASK,
922 bus_write_4(sc->sc_res[0], GEM_INTMASK,
934 ~(GEM_INTR_TX_INTME|
935 GEM_INTR_TX_EMPTY|
936 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
937 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
938 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
939 GEM_INTR_BERR));
923 ~(GEM_INTR_TX_INTME|
924 GEM_INTR_TX_EMPTY|
925 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
926 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
927 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
928 GEM_INTR_BERR));
940 bus_space_write_4(t, h, GEM_MAC_RX_MASK,
929 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK,
941 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
930 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
942 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
943 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
931 bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK, 0xffff); /* XXXX */
932 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK, 0); /* XXXX */
944
945 /* step 9. ETX Configuration: use mostly default values */
946
947 /* Enable DMA */
948 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
933
934 /* step 9. ETX Configuration: use mostly default values */
935
936 /* Enable DMA */
937 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
949 bus_space_write_4(t, h, GEM_TX_CONFIG,
938 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG,
950 v|GEM_TX_CONFIG_TXDMA_EN|
951 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
952
953 /* step 10. ERX Configuration */
954
955 /* Encode Receive Descriptor ring size: four possible values */
956 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
957
958 /* Enable DMA */
939 v|GEM_TX_CONFIG_TXDMA_EN|
940 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
941
942 /* step 10. ERX Configuration */
943
944 /* Encode Receive Descriptor ring size: four possible values */
945 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
946
947 /* Enable DMA */
959 bus_space_write_4(t, h, GEM_RX_CONFIG,
948 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG,
960 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
961 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
962 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
963 /*
964 * The following value is for an OFF Threshold of about 3/4 full
965 * and an ON Threshold of 1/4 full.
966 */
949 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
950 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
951 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
952 /*
953 * The following value is for an OFF Threshold of about 3/4 full
954 * and an ON Threshold of 1/4 full.
955 */
967 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
956 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH,
968 (3 * sc->sc_rxfifosize / 256) |
969 ( (sc->sc_rxfifosize / 256) << 12));
957 (3 * sc->sc_rxfifosize / 256) |
958 ( (sc->sc_rxfifosize / 256) << 12));
970 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
959 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING, (6<<12)|6);
971
972 /* step 11. Configure Media */
973 mii_mediachg(sc->sc_mii);
974
975 /* step 12. RX_MAC Configuration Register */
960
961 /* step 11. Configure Media */
962 mii_mediachg(sc->sc_mii);
963
964 /* step 12. RX_MAC Configuration Register */
976 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
965 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
977 v |= GEM_MAC_RX_ENABLE;
966 v |= GEM_MAC_RX_ENABLE;
978 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
967 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
979
980 /* step 14. Issue Transmit Pending command */
981
982 /* step 15. Give the reciever a swift kick */
968
969 /* step 14. Issue Transmit Pending command */
970
971 /* step 15. Give the reciever a swift kick */
983 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
972 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC-4);
984
985 /* Start the one second timer. */
986 sc->sc_wdog_timer = 0;
987 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
988
989 ifp->if_drv_flags |= IFF_DRV_RUNNING;
990 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
991 sc->sc_ifflags = ifp->if_flags;

--- 49 unchanged lines hidden (view full) ---

1041 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1042 return (error);
1043}
1044
1045static void
1046gem_init_regs(sc)
1047 struct gem_softc *sc;
1048{
973
974 /* Start the one second timer. */
975 sc->sc_wdog_timer = 0;
976 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
977
978 ifp->if_drv_flags |= IFF_DRV_RUNNING;
979 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
980 sc->sc_ifflags = ifp->if_flags;

--- 49 unchanged lines hidden (view full) ---

1030 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1031 return (error);
1032}
1033
1034static void
1035gem_init_regs(sc)
1036 struct gem_softc *sc;
1037{
1049 bus_space_tag_t t = sc->sc_bustag;
1050 bus_space_handle_t h = sc->sc_h;
1051 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1052 u_int32_t v;
1053
1054 /* These regs are not cleared on reset */
1055 if (!sc->sc_inited) {
1056
1057 /* Wooo. Magic values. */
1038 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1039 u_int32_t v;
1040
1041 /* These regs are not cleared on reset */
1042 if (!sc->sc_inited) {
1043
1044 /* Wooo. Magic values. */
1058 bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
1059 bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
1060 bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
1045 bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0);
1046 bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8);
1047 bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4);
1061
1048
1062 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1049 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1063 /* Max frame and max burst size */
1050 /* Max frame and max burst size */
1064 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
1051 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME,
1065 (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) |
1066 (0x2000 << 16));
1067
1052 (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) |
1053 (0x2000 << 16));
1054
1068 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
1069 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
1070 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1055 bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7);
1056 bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4);
1057 bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10);
1071 /* Dunno.... */
1058 /* Dunno.... */
1072 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
1073 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
1059 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088);
1060 bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED,
1074 ((laddr[5]<<8)|laddr[4])&0x3ff);
1075
1076 /* Secondary MAC addr set to 0:0:0:0:0:0 */
1061 ((laddr[5]<<8)|laddr[4])&0x3ff);
1062
1063 /* Secondary MAC addr set to 0:0:0:0:0:0 */
1077 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
1078 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
1079 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
1064 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR3, 0);
1065 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR4, 0);
1066 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR5, 0);
1080
1081 /* MAC control addr set to 01:80:c2:00:00:01 */
1067
1068 /* MAC control addr set to 01:80:c2:00:00:01 */
1082 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
1083 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
1084 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
1069 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR6, 0x0001);
1070 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR7, 0xc200);
1071 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR8, 0x0180);
1085
1086 /* MAC filter addr set to 0:0:0:0:0:0 */
1072
1073 /* MAC filter addr set to 0:0:0:0:0:0 */
1087 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
1088 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
1089 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
1074 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0);
1075 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0);
1076 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0);
1090
1077
1091 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
1092 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
1078 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0);
1079 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0);
1093
1094 sc->sc_inited = 1;
1095 }
1096
1097 /* Counters need to be zeroed */
1080
1081 sc->sc_inited = 1;
1082 }
1083
1084 /* Counters need to be zeroed */
1098 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
1099 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
1100 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
1101 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
1102 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
1103 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
1104 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
1105 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
1106 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
1107 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
1108 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
1085 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
1086 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
1087 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
1088 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
1089 bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0);
1090 bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0);
1091 bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0);
1092 bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0);
1093 bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0);
1094 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0);
1095 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0);
1109
1110 /* Un-pause stuff */
1111#if 0
1096
1097 /* Un-pause stuff */
1098#if 0
1112 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1099 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1113#else
1100#else
1114 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
1101 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0);
1115#endif
1116
1117 /*
1118 * Set the station address.
1119 */
1102#endif
1103
1104 /*
1105 * Set the station address.
1106 */
1120 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1121 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1122 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1107 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1108 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1109 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1123
1124 /*
1125 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1126 */
1110
1111 /*
1112 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1113 */
1127 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
1114 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1128 v = GEM_MAC_XIF_TX_MII_ENA;
1129 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
1130 v |= GEM_MAC_XIF_FDPLX_LED;
1131 if (sc->sc_flags & GEM_GIGABIT)
1132 v |= GEM_MAC_XIF_GMII_MODE;
1133 }
1115 v = GEM_MAC_XIF_TX_MII_ENA;
1116 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
1117 v |= GEM_MAC_XIF_FDPLX_LED;
1118 if (sc->sc_flags & GEM_GIGABIT)
1119 v |= GEM_MAC_XIF_GMII_MODE;
1120 }
1134 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
1121 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
1135}
1136
1137static void
1138gem_start(ifp)
1139 struct ifnet *ifp;
1140{
1141 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1142

--- 56 unchanged lines hidden (view full) ---

1199 }
1200
1201 ntx++;
1202 /* Kick the transmitter. */
1203#ifdef GEM_DEBUG
1204 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
1205 device_get_name(sc->sc_dev), sc->sc_txnext);
1206#endif
1122}
1123
1124static void
1125gem_start(ifp)
1126 struct ifnet *ifp;
1127{
1128 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1129

--- 56 unchanged lines hidden (view full) ---

1186 }
1187
1188 ntx++;
1189 /* Kick the transmitter. */
1190#ifdef GEM_DEBUG
1191 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
1192 device_get_name(sc->sc_dev), sc->sc_txnext);
1193#endif
1207 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK,
1194 bus_write_4(sc->sc_res[0], GEM_TX_KICK,
1208 sc->sc_txnext);
1209
1210 BPF_MTAP(ifp, m0);
1211 } while (1);
1212
1213 if (txmfail == -1 || sc->sc_txfree == 0) {
1214 /* No more slots left; notify upper layer. */
1215 ifp->if_drv_flags |= IFF_DRV_OACTIVE;

--- 19 unchanged lines hidden (view full) ---

1235/*
1236 * Transmit interrupt.
1237 */
1238static void
1239gem_tint(sc)
1240 struct gem_softc *sc;
1241{
1242 struct ifnet *ifp = sc->sc_ifp;
1195 sc->sc_txnext);
1196
1197 BPF_MTAP(ifp, m0);
1198 } while (1);
1199
1200 if (txmfail == -1 || sc->sc_txfree == 0) {
1201 /* No more slots left; notify upper layer. */
1202 ifp->if_drv_flags |= IFF_DRV_OACTIVE;

--- 19 unchanged lines hidden (view full) ---

1222/*
1223 * Transmit interrupt.
1224 */
1225static void
1226gem_tint(sc)
1227 struct gem_softc *sc;
1228{
1229 struct ifnet *ifp = sc->sc_ifp;
1243 bus_space_tag_t t = sc->sc_bustag;
1244 bus_space_handle_t mac = sc->sc_h;
1245 struct gem_txsoft *txs;
1246 int txlast;
1247 int progress = 0;
1248
1249
1250#ifdef GEM_DEBUG
1251 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev));
1252#endif
1253
1254 /*
1255 * Unload collision counters
1256 */
1257 ifp->if_collisions +=
1230 struct gem_txsoft *txs;
1231 int txlast;
1232 int progress = 0;
1233
1234
1235#ifdef GEM_DEBUG
1236 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev));
1237#endif
1238
1239 /*
1240 * Unload collision counters
1241 */
1242 ifp->if_collisions +=
1258 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
1259 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
1260 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
1261 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
1243 bus_read_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT) +
1244 bus_read_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT) +
1245 bus_read_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT) +
1246 bus_read_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT);
1262
1263 /*
1264 * then clear the hardware counters.
1265 */
1247
1248 /*
1249 * then clear the hardware counters.
1250 */
1266 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
1267 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
1268 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
1269 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
1251 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0);
1252 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0);
1253 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0);
1254 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0);
1270
1271 /*
1272 * Go through our Tx list and free mbufs for those
1273 * frames that have been transmitted.
1274 */
1275 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1276 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1277

--- 15 unchanged lines hidden (view full) ---

1293
1294 /*
1295 * In theory, we could harveast some descriptors before
1296 * the ring is empty, but that's a bit complicated.
1297 *
1298 * GEM_TX_COMPLETION points to the last descriptor
1299 * processed +1.
1300 */
1255
1256 /*
1257 * Go through our Tx list and free mbufs for those
1258 * frames that have been transmitted.
1259 */
1260 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1261 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1262

--- 15 unchanged lines hidden (view full) ---

1278
1279 /*
1280 * In theory, we could harveast some descriptors before
1281 * the ring is empty, but that's a bit complicated.
1282 *
1283 * GEM_TX_COMPLETION points to the last descriptor
1284 * processed +1.
1285 */
1301 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
1286 txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION);
1302#ifdef GEM_DEBUG
1303 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
1304 "txs->txs_lastdesc = %d, txlast = %d",
1305 txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1306#endif
1307 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1308 if ((txlast >= txs->txs_firstdesc) &&
1309 (txlast <= txs->txs_lastdesc))

--- 25 unchanged lines hidden (view full) ---

1335 ifp->if_opackets++;
1336 progress = 1;
1337 }
1338
1339#ifdef GEM_DEBUG
1340 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
1341 "GEM_TX_DATA_PTR %llx "
1342 "GEM_TX_COMPLETION %x",
1287#ifdef GEM_DEBUG
1288 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
1289 "txs->txs_lastdesc = %d, txlast = %d",
1290 txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1291#endif
1292 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1293 if ((txlast >= txs->txs_firstdesc) &&
1294 (txlast <= txs->txs_lastdesc))

--- 25 unchanged lines hidden (view full) ---

1320 ifp->if_opackets++;
1321 progress = 1;
1322 }
1323
1324#ifdef GEM_DEBUG
1325 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
1326 "GEM_TX_DATA_PTR %llx "
1327 "GEM_TX_COMPLETION %x",
1343 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE),
1344 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h,
1328 bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE),
1329 ((long long) bus_read_4(sc->sc_res[0],
1345 GEM_TX_DATA_PTR_HI) << 32) |
1330 GEM_TX_DATA_PTR_HI) << 32) |
1346 bus_space_read_4(sc->sc_bustag, sc->sc_h,
1331 bus_read_4(sc->sc_res[0],
1347 GEM_TX_DATA_PTR_LO),
1332 GEM_TX_DATA_PTR_LO),
1348 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
1333 bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION));
1349#endif
1350
1351 if (progress) {
1352 if (sc->sc_txfree == GEM_NTXDESC - 1)
1353 sc->sc_txwin = 0;
1354
1355 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */
1356 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;

--- 23 unchanged lines hidden (view full) ---

1380/*
1381 * Receive interrupt.
1382 */
1383static void
1384gem_rint(sc)
1385 struct gem_softc *sc;
1386{
1387 struct ifnet *ifp = sc->sc_ifp;
1334#endif
1335
1336 if (progress) {
1337 if (sc->sc_txfree == GEM_NTXDESC - 1)
1338 sc->sc_txwin = 0;
1339
1340 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */
1341 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;

--- 23 unchanged lines hidden (view full) ---

1365/*
1366 * Receive interrupt.
1367 */
1368static void
1369gem_rint(sc)
1370 struct gem_softc *sc;
1371{
1372 struct ifnet *ifp = sc->sc_ifp;
1388 bus_space_tag_t t = sc->sc_bustag;
1389 bus_space_handle_t h = sc->sc_h;
1390 struct gem_rxsoft *rxs;
1391 struct mbuf *m;
1392 u_int64_t rxstat;
1393 u_int32_t rxcomp;
1394 int i, len, progress = 0;
1395
1396#ifdef GEM_RINT_TIMEOUT
1397 callout_stop(&sc->sc_rx_ch);
1398#endif
1399#ifdef GEM_DEBUG
1400 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
1401#endif
1402
1403 /*
1404 * Read the completion register once. This limits
1405 * how long the following loop can execute.
1406 */
1373 struct gem_rxsoft *rxs;
1374 struct mbuf *m;
1375 u_int64_t rxstat;
1376 u_int32_t rxcomp;
1377 int i, len, progress = 0;
1378
1379#ifdef GEM_RINT_TIMEOUT
1380 callout_stop(&sc->sc_rx_ch);
1381#endif
1382#ifdef GEM_DEBUG
1383 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
1384#endif
1385
1386 /*
1387 * Read the completion register once. This limits
1388 * how long the following loop can execute.
1389 */
1407 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
1390 rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION);
1408
1409#ifdef GEM_DEBUG
1410 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1411 sc->sc_rxptr, rxcomp);
1412#endif
1413 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1414 for (i = sc->sc_rxptr; i != rxcomp;
1415 i = GEM_NEXTRX(i)) {

--- 67 unchanged lines hidden (view full) ---

1483
1484 if (progress) {
1485 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1486 /* Update the receive pointer. */
1487 if (i == sc->sc_rxptr) {
1488 device_printf(sc->sc_dev, "rint: ring wrap\n");
1489 }
1490 sc->sc_rxptr = i;
1391
1392#ifdef GEM_DEBUG
1393 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1394 sc->sc_rxptr, rxcomp);
1395#endif
1396 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1397 for (i = sc->sc_rxptr; i != rxcomp;
1398 i = GEM_NEXTRX(i)) {

--- 67 unchanged lines hidden (view full) ---

1466
1467 if (progress) {
1468 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1469 /* Update the receive pointer. */
1470 if (i == sc->sc_rxptr) {
1471 device_printf(sc->sc_dev, "rint: ring wrap\n");
1472 }
1473 sc->sc_rxptr = i;
1491 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
1474 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_PREVRX(i));
1492 }
1493
1494#ifdef GEM_DEBUG
1495 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
1475 }
1476
1477#ifdef GEM_DEBUG
1478 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
1496 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
1479 sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION));
1497#endif
1498}
1499
1500
1501/*
1502 * gem_add_rxbuf:
1503 *
1504 * Add a receive buffer to the indicated descriptor.

--- 61 unchanged lines hidden (view full) ---

1566}
1567
1568
1569void
1570gem_intr(v)
1571 void *v;
1572{
1573 struct gem_softc *sc = (struct gem_softc *)v;
1480#endif
1481}
1482
1483
1484/*
1485 * gem_add_rxbuf:
1486 *
1487 * Add a receive buffer to the indicated descriptor.

--- 61 unchanged lines hidden (view full) ---

1549}
1550
1551
1552void
1553gem_intr(v)
1554 void *v;
1555{
1556 struct gem_softc *sc = (struct gem_softc *)v;
1574 bus_space_tag_t t = sc->sc_bustag;
1575 bus_space_handle_t seb = sc->sc_h;
1576 u_int32_t status;
1577
1578 GEM_LOCK(sc);
1557 u_int32_t status;
1558
1559 GEM_LOCK(sc);
1579 status = bus_space_read_4(t, seb, GEM_STATUS);
1560 status = bus_read_4(sc->sc_res[0], GEM_STATUS);
1580#ifdef GEM_DEBUG
1581 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
1582 device_get_name(sc->sc_dev), (status>>19),
1583 (u_int)status);
1584#endif
1585
1586 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1587 gem_eint(sc, status);
1588
1589 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1590 gem_tint(sc);
1591
1592 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1593 gem_rint(sc);
1594
1595 /* We should eventually do more than just print out error stats. */
1596 if (status & GEM_INTR_TX_MAC) {
1561#ifdef GEM_DEBUG
1562 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
1563 device_get_name(sc->sc_dev), (status>>19),
1564 (u_int)status);
1565#endif
1566
1567 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1568 gem_eint(sc, status);
1569
1570 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1571 gem_tint(sc);
1572
1573 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1574 gem_rint(sc);
1575
1576 /* We should eventually do more than just print out error stats. */
1577 if (status & GEM_INTR_TX_MAC) {
1597 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
1578 int txstat = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS);
1598 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1599 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1600 txstat);
1601 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1602 gem_init_locked(sc);
1603 }
1604 if (status & GEM_INTR_RX_MAC) {
1579 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1580 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1581 txstat);
1582 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1583 gem_init_locked(sc);
1584 }
1585 if (status & GEM_INTR_RX_MAC) {
1605 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
1586 int rxstat = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS);
1606 /*
1607 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often
1608 * due to a silicon bug so handle them silently.
1609 */
1610 if (rxstat & GEM_MAC_RX_OVERFLOW)
1611 gem_init_locked(sc);
1612 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1613 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",

--- 7 unchanged lines hidden (view full) ---

1621 struct gem_softc *sc;
1622{
1623
1624 GEM_LOCK_ASSERT(sc, MA_OWNED);
1625
1626#ifdef GEM_DEBUG
1627 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
1628 "GEM_MAC_RX_CONFIG %x",
1587 /*
1588 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often
1589 * due to a silicon bug so handle them silently.
1590 */
1591 if (rxstat & GEM_MAC_RX_OVERFLOW)
1592 gem_init_locked(sc);
1593 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1594 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",

--- 7 unchanged lines hidden (view full) ---

1602 struct gem_softc *sc;
1603{
1604
1605 GEM_LOCK_ASSERT(sc, MA_OWNED);
1606
1607#ifdef GEM_DEBUG
1608 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
1609 "GEM_MAC_RX_CONFIG %x",
1629 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
1630 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
1631 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG));
1610 bus_read_4(sc->sc_res[0], GEM_RX_CONFIG),
1611 bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS),
1612 bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG));
1632 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
1633 "GEM_MAC_TX_CONFIG %x",
1613 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
1614 "GEM_MAC_TX_CONFIG %x",
1634 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
1635 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS),
1636 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG));
1615 bus_read_4(sc->sc_res[0], GEM_TX_CONFIG),
1616 bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS),
1617 bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG));
1637#endif
1638
1639 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1640 return (0);
1641
1642 device_printf(sc->sc_dev, "device timeout\n");
1643 ++sc->sc_ifp->if_oerrors;
1644

--- 4 unchanged lines hidden (view full) ---

1649
1650/*
1651 * Initialize the MII Management Interface
1652 */
1653static void
1654gem_mifinit(sc)
1655 struct gem_softc *sc;
1656{
1618#endif
1619
1620 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
1621 return (0);
1622
1623 device_printf(sc->sc_dev, "device timeout\n");
1624 ++sc->sc_ifp->if_oerrors;
1625

--- 4 unchanged lines hidden (view full) ---

1630
1631/*
1632 * Initialize the MII Management Interface
1633 */
1634static void
1635gem_mifinit(sc)
1636 struct gem_softc *sc;
1637{
1657 bus_space_tag_t t = sc->sc_bustag;
1658 bus_space_handle_t mif = sc->sc_h;
1659
1660 /* Configure the MIF in frame mode */
1638
1639 /* Configure the MIF in frame mode */
1661 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1640 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1662 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1641 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1663 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
1642 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, sc->sc_mif_config);
1664}
1665
1666/*
1667 * MII interface
1668 *
1669 * The GEM MII interface supports at least three different operating modes:
1670 *
1671 * Bitbang mode is implemented using data, clock and output enable registers.

--- 6 unchanged lines hidden (view full) ---

1678 *
1679 */
1680int
1681gem_mii_readreg(dev, phy, reg)
1682 device_t dev;
1683 int phy, reg;
1684{
1685 struct gem_softc *sc = device_get_softc(dev);
1643}
1644
1645/*
1646 * MII interface
1647 *
1648 * The GEM MII interface supports at least three different operating modes:
1649 *
1650 * Bitbang mode is implemented using data, clock and output enable registers.

--- 6 unchanged lines hidden (view full) ---

1657 *
1658 */
1659int
1660gem_mii_readreg(dev, phy, reg)
1661 device_t dev;
1662 int phy, reg;
1663{
1664 struct gem_softc *sc = device_get_softc(dev);
1686 bus_space_tag_t t = sc->sc_bustag;
1687 bus_space_handle_t mif = sc->sc_h;
1688 int n;
1689 u_int32_t v;
1690
1691#ifdef GEM_DEBUG_PHY
1692 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1693#endif
1694
1695#if 0
1696 /* Select the desired PHY in the MIF configuration register */
1665 int n;
1666 u_int32_t v;
1667
1668#ifdef GEM_DEBUG_PHY
1669 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1670#endif
1671
1672#if 0
1673 /* Select the desired PHY in the MIF configuration register */
1697 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1674 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1698 /* Clear PHY select bit */
1699 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1700 if (phy == GEM_PHYAD_EXTERNAL)
1701 /* Set PHY select bit to get at external device */
1702 v |= GEM_MIF_CONFIG_PHY_SEL;
1675 /* Clear PHY select bit */
1676 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1677 if (phy == GEM_PHYAD_EXTERNAL)
1678 /* Set PHY select bit to get at external device */
1679 v |= GEM_MIF_CONFIG_PHY_SEL;
1703 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1680 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
1704#endif
1705
1706 /* Construct the frame command */
1707 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1708 GEM_MIF_FRAME_READ;
1709
1681#endif
1682
1683 /* Construct the frame command */
1684 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1685 GEM_MIF_FRAME_READ;
1686
1710 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1687 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1711 for (n = 0; n < 100; n++) {
1712 DELAY(1);
1688 for (n = 0; n < 100; n++) {
1689 DELAY(1);
1713 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1690 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1714 if (v & GEM_MIF_FRAME_TA0)
1715 return (v & GEM_MIF_FRAME_DATA);
1716 }
1717
1718 device_printf(sc->sc_dev, "mii_read timeout\n");
1719 return (0);
1720}
1721
1722int
1723gem_mii_writereg(dev, phy, reg, val)
1724 device_t dev;
1725 int phy, reg, val;
1726{
1727 struct gem_softc *sc = device_get_softc(dev);
1691 if (v & GEM_MIF_FRAME_TA0)
1692 return (v & GEM_MIF_FRAME_DATA);
1693 }
1694
1695 device_printf(sc->sc_dev, "mii_read timeout\n");
1696 return (0);
1697}
1698
1699int
1700gem_mii_writereg(dev, phy, reg, val)
1701 device_t dev;
1702 int phy, reg, val;
1703{
1704 struct gem_softc *sc = device_get_softc(dev);
1728 bus_space_tag_t t = sc->sc_bustag;
1729 bus_space_handle_t mif = sc->sc_h;
1730 int n;
1731 u_int32_t v;
1732
1733#ifdef GEM_DEBUG_PHY
1734 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
1735#endif
1736
1737#if 0
1738 /* Select the desired PHY in the MIF configuration register */
1705 int n;
1706 u_int32_t v;
1707
1708#ifdef GEM_DEBUG_PHY
1709 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
1710#endif
1711
1712#if 0
1713 /* Select the desired PHY in the MIF configuration register */
1739 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1714 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1740 /* Clear PHY select bit */
1741 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1742 if (phy == GEM_PHYAD_EXTERNAL)
1743 /* Set PHY select bit to get at external device */
1744 v |= GEM_MIF_CONFIG_PHY_SEL;
1715 /* Clear PHY select bit */
1716 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1717 if (phy == GEM_PHYAD_EXTERNAL)
1718 /* Set PHY select bit to get at external device */
1719 v |= GEM_MIF_CONFIG_PHY_SEL;
1745 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1720 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v);
1746#endif
1747 /* Construct the frame command */
1748 v = GEM_MIF_FRAME_WRITE |
1749 (phy << GEM_MIF_PHY_SHIFT) |
1750 (reg << GEM_MIF_REG_SHIFT) |
1751 (val & GEM_MIF_FRAME_DATA);
1752
1721#endif
1722 /* Construct the frame command */
1723 v = GEM_MIF_FRAME_WRITE |
1724 (phy << GEM_MIF_PHY_SHIFT) |
1725 (reg << GEM_MIF_REG_SHIFT) |
1726 (val & GEM_MIF_FRAME_DATA);
1727
1753 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1728 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v);
1754 for (n = 0; n < 100; n++) {
1755 DELAY(1);
1729 for (n = 0; n < 100; n++) {
1730 DELAY(1);
1756 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1731 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME);
1757 if (v & GEM_MIF_FRAME_TA0)
1758 return (1);
1759 }
1760
1761 device_printf(sc->sc_dev, "mii_write timeout\n");
1762 return (0);
1763}
1764
1765void
1766gem_mii_statchg(dev)
1767 device_t dev;
1768{
1769 struct gem_softc *sc = device_get_softc(dev);
1770#ifdef GEM_DEBUG
1771 int instance;
1772#endif
1732 if (v & GEM_MIF_FRAME_TA0)
1733 return (1);
1734 }
1735
1736 device_printf(sc->sc_dev, "mii_write timeout\n");
1737 return (0);
1738}
1739
1740void
1741gem_mii_statchg(dev)
1742 device_t dev;
1743{
1744 struct gem_softc *sc = device_get_softc(dev);
1745#ifdef GEM_DEBUG
1746 int instance;
1747#endif
1773 bus_space_tag_t t = sc->sc_bustag;
1774 bus_space_handle_t mac = sc->sc_h;
1775 u_int32_t v;
1776
1777#ifdef GEM_DEBUG
1778 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
1779 if (sc->sc_debug)
1780 printf("gem_mii_statchg: status change: phy = %d\n",
1781 sc->sc_phys[instance]);
1782#endif
1783
1784 /* Set tx full duplex options */
1748 u_int32_t v;
1749
1750#ifdef GEM_DEBUG
1751 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
1752 if (sc->sc_debug)
1753 printf("gem_mii_statchg: status change: phy = %d\n",
1754 sc->sc_phys[instance]);
1755#endif
1756
1757 /* Set tx full duplex options */
1785 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
1758 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0);
1786 DELAY(10000); /* reg must be cleared and delay before changing. */
1787 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1788 GEM_MAC_TX_ENABLE;
1789 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
1790 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
1791 }
1759 DELAY(10000); /* reg must be cleared and delay before changing. */
1760 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1761 GEM_MAC_TX_ENABLE;
1762 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
1763 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
1764 }
1792 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
1765 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, v);
1793
1794 /* XIF Configuration */
1795 v = GEM_MAC_XIF_LINK_LED;
1796 v |= GEM_MAC_XIF_TX_MII_ENA;
1797
1798 /* If an external transceiver is connected, enable its MII drivers */
1766
1767 /* XIF Configuration */
1768 v = GEM_MAC_XIF_LINK_LED;
1769 v |= GEM_MAC_XIF_TX_MII_ENA;
1770
1771 /* If an external transceiver is connected, enable its MII drivers */
1799 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
1772 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG);
1800 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1801 /* External MII needs echo disable if half duplex. */
1802 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1803 /* turn on full duplex LED */
1804 v |= GEM_MAC_XIF_FDPLX_LED;
1805 else
1806 /* half duplex -- disable echo */
1807 v |= GEM_MAC_XIF_ECHO_DISABL;
1808
1809 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
1810 v |= GEM_MAC_XIF_GMII_MODE;
1811 else
1812 v &= ~GEM_MAC_XIF_GMII_MODE;
1813 } else {
1814 /* Internal MII needs buf enable */
1815 v |= GEM_MAC_XIF_MII_BUF_ENA;
1816 }
1773 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1774 /* External MII needs echo disable if half duplex. */
1775 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1776 /* turn on full duplex LED */
1777 v |= GEM_MAC_XIF_FDPLX_LED;
1778 else
1779 /* half duplex -- disable echo */
1780 v |= GEM_MAC_XIF_ECHO_DISABL;
1781
1782 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
1783 v |= GEM_MAC_XIF_GMII_MODE;
1784 else
1785 v &= ~GEM_MAC_XIF_GMII_MODE;
1786 } else {
1787 /* Internal MII needs buf enable */
1788 v |= GEM_MAC_XIF_MII_BUF_ENA;
1789 }
1817 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
1790 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v);
1818}
1819
1820int
1821gem_mediachange(ifp)
1822 struct ifnet *ifp;
1823{
1824 struct gem_softc *sc = ifp->if_softc;
1825 int error;

--- 80 unchanged lines hidden (view full) ---

1906 * Set up the logical address filter.
1907 */
1908static void
1909gem_setladrf(sc)
1910 struct gem_softc *sc;
1911{
1912 struct ifnet *ifp = sc->sc_ifp;
1913 struct ifmultiaddr *inm;
1791}
1792
1793int
1794gem_mediachange(ifp)
1795 struct ifnet *ifp;
1796{
1797 struct gem_softc *sc = ifp->if_softc;
1798 int error;

--- 80 unchanged lines hidden (view full) ---

1879 * Set up the logical address filter.
1880 */
1881static void
1882gem_setladrf(sc)
1883 struct gem_softc *sc;
1884{
1885 struct ifnet *ifp = sc->sc_ifp;
1886 struct ifmultiaddr *inm;
1914 bus_space_tag_t t = sc->sc_bustag;
1915 bus_space_handle_t h = sc->sc_h;
1916 u_int32_t crc;
1917 u_int32_t hash[16];
1918 u_int32_t v;
1919 int i;
1920
1921 GEM_LOCK_ASSERT(sc, MA_OWNED);
1922
1923 /* Get current RX configuration */
1887 u_int32_t crc;
1888 u_int32_t hash[16];
1889 u_int32_t v;
1890 int i;
1891
1892 GEM_LOCK_ASSERT(sc, MA_OWNED);
1893
1894 /* Get current RX configuration */
1924 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
1895 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG);
1925
1926 /*
1927 * Turn off promiscuous mode, promiscuous group mode (all multicast),
1928 * and hash filter. Depending on the case, the right bit will be
1929 * enabled.
1930 */
1931 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
1932 GEM_MAC_RX_PROMISC_GRP);

--- 36 unchanged lines hidden (view full) ---

1969 }
1970 IF_ADDR_UNLOCK(ifp);
1971
1972 v |= GEM_MAC_RX_HASH_FILTER;
1973 ifp->if_flags &= ~IFF_ALLMULTI;
1974
1975 /* Now load the hash table into the chip (if we are using it) */
1976 for (i = 0; i < 16; i++) {
1896
1897 /*
1898 * Turn off promiscuous mode, promiscuous group mode (all multicast),
1899 * and hash filter. Depending on the case, the right bit will be
1900 * enabled.
1901 */
1902 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
1903 GEM_MAC_RX_PROMISC_GRP);

--- 36 unchanged lines hidden (view full) ---

1940 }
1941 IF_ADDR_UNLOCK(ifp);
1942
1943 v |= GEM_MAC_RX_HASH_FILTER;
1944 ifp->if_flags &= ~IFF_ALLMULTI;
1945
1946 /* Now load the hash table into the chip (if we are using it) */
1947 for (i = 0; i < 16; i++) {
1977 bus_space_write_4(t, h,
1948 bus_write_4(sc->sc_res[0],
1978 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
1979 hash[i]);
1980 }
1981
1982chipit:
1949 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
1950 hash[i]);
1951 }
1952
1953chipit:
1983 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
1954 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v);
1984}
1955}