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if_gem.c (109623) if_gem.c (109648)
1/*
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
28 *
1/*
2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 12 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
28 *
29 * $FreeBSD: head/sys/dev/gem/if_gem.c 109623 2003-01-21 08:56:16Z alfred $
29 * $FreeBSD: head/sys/dev/gem/if_gem.c 109648 2003-01-21 17:17:01Z tmm $
30 */
31
32/*
33 * Driver for Sun GEM ethernet controllers.
34 */
35
36#define GEM_DEBUG
37

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366 bus_dmamap_destroy(sc->sc_rdmatag,
367 sc->sc_rxsoft[i].rxs_dmamap);
368 }
369 for (i = 0; i < GEM_TXQUEUELEN; i++) {
370 if (sc->sc_txsoft[i].txs_dmamap != NULL)
371 bus_dmamap_destroy(sc->sc_tdmatag,
372 sc->sc_txsoft[i].txs_dmamap);
373 }
30 */
31
32/*
33 * Driver for Sun GEM ethernet controllers.
34 */
35
36#define GEM_DEBUG
37

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366 bus_dmamap_destroy(sc->sc_rdmatag,
367 sc->sc_rxsoft[i].rxs_dmamap);
368 }
369 for (i = 0; i < GEM_TXQUEUELEN; i++) {
370 if (sc->sc_txsoft[i].txs_dmamap != NULL)
371 bus_dmamap_destroy(sc->sc_tdmatag,
372 sc->sc_txsoft[i].txs_dmamap);
373 }
374 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
375 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE);
374 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
375 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
376 sc->sc_cddmamap);
377 bus_dma_tag_destroy(sc->sc_cdmatag);
378 bus_dma_tag_destroy(sc->sc_tdmatag);
379 bus_dma_tag_destroy(sc->sc_rdmatag);
380 bus_dma_tag_destroy(sc->sc_pdmatag);
381}

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565 struct gem_softc *sc;
566{
567 struct gem_rxsoft *rxs;
568 int i;
569
570 for (i = 0; i < GEM_NRXDESC; i++) {
571 rxs = &sc->sc_rxsoft[i];
572 if (rxs->rxs_mbuf != NULL) {
376 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
377 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
378 sc->sc_cddmamap);
379 bus_dma_tag_destroy(sc->sc_cdmatag);
380 bus_dma_tag_destroy(sc->sc_tdmatag);
381 bus_dma_tag_destroy(sc->sc_rdmatag);
382 bus_dma_tag_destroy(sc->sc_pdmatag);
383}

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567 struct gem_softc *sc;
568{
569 struct gem_rxsoft *rxs;
570 int i;
571
572 for (i = 0; i < GEM_NRXDESC; i++) {
573 rxs = &sc->sc_rxsoft[i];
574 if (rxs->rxs_mbuf != NULL) {
575 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
576 BUS_DMASYNC_POSTREAD);
573 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
574 m_freem(rxs->rxs_mbuf);
575 rxs->rxs_mbuf = NULL;
576 }
577 }
578}
579
580/*

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597 gem_disable_rx(sc);
598
599 /*
600 * Release any queued transmit buffers.
601 */
602 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
603 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
604 if (txs->txs_ndescs != 0) {
577 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
578 m_freem(rxs->rxs_mbuf);
579 rxs->rxs_mbuf = NULL;
580 }
581 }
582}
583
584/*

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601 gem_disable_rx(sc);
602
603 /*
604 * Release any queued transmit buffers.
605 */
606 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
607 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
608 if (txs->txs_ndescs != 0) {
609 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
610 BUS_DMASYNC_POSTWRITE);
605 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
606 if (txs->txs_mbuf != NULL) {
607 m_freem(txs->txs_mbuf);
608 txs->txs_mbuf = NULL;
609 }
610 }
611 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
612 }

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745 /*
746 * Initialize the transmit descriptor ring.
747 */
748 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
749 for (i = 0; i < GEM_NTXDESC; i++) {
750 sc->sc_txdescs[i].gd_flags = 0;
751 sc->sc_txdescs[i].gd_addr = 0;
752 }
611 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
612 if (txs->txs_mbuf != NULL) {
613 m_freem(txs->txs_mbuf);
614 txs->txs_mbuf = NULL;
615 }
616 }
617 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
618 }

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751 /*
752 * Initialize the transmit descriptor ring.
753 */
754 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
755 for (i = 0; i < GEM_NTXDESC; i++) {
756 sc->sc_txdescs[i].gd_flags = 0;
757 sc->sc_txdescs[i].gd_addr = 0;
758 }
753 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
754 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
755 sc->sc_txfree = GEM_MAXTXFREE;
756 sc->sc_txnext = 0;
757 sc->sc_txwin = 0;
758
759 /*
760 * Initialize the receive descriptor and receive job
761 * descriptor rings.
762 */

--- 10 unchanged lines hidden (view full) ---

773 */
774 gem_rxdrain(sc);
775 return (1);
776 }
777 } else
778 GEM_INIT_RXDESC(sc, i);
779 }
780 sc->sc_rxptr = 0;
759 sc->sc_txfree = GEM_MAXTXFREE;
760 sc->sc_txnext = 0;
761 sc->sc_txwin = 0;
762
763 /*
764 * Initialize the receive descriptor and receive job
765 * descriptor rings.
766 */

--- 10 unchanged lines hidden (view full) ---

777 */
778 gem_rxdrain(sc);
779 return (1);
780 }
781 } else
782 GEM_INIT_RXDESC(sc, i);
783 }
784 sc->sc_rxptr = 0;
785 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
786 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
781
782 return (0);
783}
784
785static int
786gem_ringsize(sz)
787 int sz;
788{

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973 BUS_DMASYNC_PREWRITE);
974
975 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, "
976 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc,
977 txs->txs_ndescs);
978 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
979 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
980
787
788 return (0);
789}
790
791static int
792gem_ringsize(sz)
793 int sz;
794{

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979 BUS_DMASYNC_PREWRITE);
980
981 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, "
982 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc,
983 txs->txs_ndescs);
984 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
985 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
986
981 /* Sync the descriptors we're using. */
982 GEM_CDTXSYNC(sc, sc->sc_txnext, txs->txs_ndescs,
983 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
984
985 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
986 sc->sc_txfree -= txs->txs_ndescs;
987 return (0);
988
989fail:
990 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error);
991 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
992 return (error);

--- 151 unchanged lines hidden (view full) ---

1144 }
1145
1146 if (txmfail == -1 || sc->sc_txfree == 0) {
1147 /* No more slots left; notify upper layer. */
1148 ifp->if_flags |= IFF_OACTIVE;
1149 }
1150
1151 if (ntx > 0) {
987 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
988 sc->sc_txfree -= txs->txs_ndescs;
989 return (0);
990
991fail:
992 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error);
993 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
994 return (error);

--- 151 unchanged lines hidden (view full) ---

1146 }
1147
1148 if (txmfail == -1 || sc->sc_txfree == 0) {
1149 /* No more slots left; notify upper layer. */
1150 ifp->if_flags |= IFF_OACTIVE;
1151 }
1152
1153 if (ntx > 0) {
1154 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1155
1152 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1153 device_get_name(sc->sc_dev), firsttx);
1154
1155 /* Set a watchdog timer in case the chip flakes out. */
1156 ifp->if_timer = 5;
1157 CTR2(KTR_GEM, "%s: gem_start: watchdog %d",
1158 device_get_name(sc->sc_dev), ifp->if_timer);
1159 }

--- 32 unchanged lines hidden (view full) ---

1192 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
1193 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
1194 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
1195
1196 /*
1197 * Go through our Tx list and free mbufs for those
1198 * frames that have been transmitted.
1199 */
1156 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1157 device_get_name(sc->sc_dev), firsttx);
1158
1159 /* Set a watchdog timer in case the chip flakes out. */
1160 ifp->if_timer = 5;
1161 CTR2(KTR_GEM, "%s: gem_start: watchdog %d",
1162 device_get_name(sc->sc_dev), ifp->if_timer);
1163 }

--- 32 unchanged lines hidden (view full) ---

1196 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
1197 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
1198 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
1199
1200 /*
1201 * Go through our Tx list and free mbufs for those
1202 * frames that have been transmitted.
1203 */
1204 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1200 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1205 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1201 GEM_CDTXSYNC(sc, txs->txs_lastdesc,
1202 txs->txs_ndescs,
1203 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1204
1205#ifdef GEM_DEBUG
1206 if (ifp->if_flags & IFF_DEBUG) {
1207 int i;
1208 printf(" txsoft %p transmit chain:\n", txs);
1209 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1210 printf("descriptor %d: ", i);
1211 printf("gd_flags: 0x%016llx\t", (long long)

--- 105 unchanged lines hidden (view full) ---

1317 /*
1318 * Read the completion register once. This limits
1319 * how long the following loop can execute.
1320 */
1321 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
1322
1323 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1324 sc->sc_rxptr, rxcomp);
1206
1207#ifdef GEM_DEBUG
1208 if (ifp->if_flags & IFF_DEBUG) {
1209 int i;
1210 printf(" txsoft %p transmit chain:\n", txs);
1211 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1212 printf("descriptor %d: ", i);
1213 printf("gd_flags: 0x%016llx\t", (long long)

--- 105 unchanged lines hidden (view full) ---

1319 /*
1320 * Read the completion register once. This limits
1321 * how long the following loop can execute.
1322 */
1323 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
1324
1325 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1326 sc->sc_rxptr, rxcomp);
1327 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1325 for (i = sc->sc_rxptr; i != rxcomp;
1326 i = GEM_NEXTRX(i)) {
1327 rxs = &sc->sc_rxsoft[i];
1328
1328 for (i = sc->sc_rxptr; i != rxcomp;
1329 i = GEM_NEXTRX(i)) {
1330 rxs = &sc->sc_rxsoft[i];
1331
1329 GEM_CDRXSYNC(sc, i,
1330 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1331
1332 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
1333
1334 if (rxstat & GEM_RD_OWN) {
1335#if 0 /* XXX: In case of emergency, re-enable this. */
1336 /*
1337 * The descriptor is still marked as owned, although
1338 * it is supposed to have completed. This has been
1339 * observed on some machines. Just exiting here

--- 12 unchanged lines hidden (view full) ---

1352
1353 if (rxstat & GEM_RD_BAD_CRC) {
1354 ifp->if_ierrors++;
1355 device_printf(sc->sc_dev, "receive error: CRC error\n");
1356 GEM_INIT_RXDESC(sc, i);
1357 continue;
1358 }
1359
1332 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
1333
1334 if (rxstat & GEM_RD_OWN) {
1335#if 0 /* XXX: In case of emergency, re-enable this. */
1336 /*
1337 * The descriptor is still marked as owned, although
1338 * it is supposed to have completed. This has been
1339 * observed on some machines. Just exiting here

--- 12 unchanged lines hidden (view full) ---

1352
1353 if (rxstat & GEM_RD_BAD_CRC) {
1354 ifp->if_ierrors++;
1355 device_printf(sc->sc_dev, "receive error: CRC error\n");
1356 GEM_INIT_RXDESC(sc, i);
1357 continue;
1358 }
1359
1360 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1361 BUS_DMASYNC_POSTREAD);
1362#ifdef GEM_DEBUG
1363 if (ifp->if_flags & IFF_DEBUG) {
1364 printf(" rxsoft %p descriptor %d: ", rxs, i);
1365 printf("gd_flags: 0x%016llx\t", (long long)
1366 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
1367 printf("gd_addr: 0x%016llx\n", (long long)
1368 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
1369 }

--- 9 unchanged lines hidden (view full) ---

1379 * Allocate a new mbuf cluster. If that fails, we are
1380 * out of memory, and must drop the packet and recycle
1381 * the buffer that's already attached to this descriptor.
1382 */
1383 m = rxs->rxs_mbuf;
1384 if (gem_add_rxbuf(sc, i) != 0) {
1385 ifp->if_ierrors++;
1386 GEM_INIT_RXDESC(sc, i);
1360#ifdef GEM_DEBUG
1361 if (ifp->if_flags & IFF_DEBUG) {
1362 printf(" rxsoft %p descriptor %d: ", rxs, i);
1363 printf("gd_flags: 0x%016llx\t", (long long)
1364 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
1365 printf("gd_addr: 0x%016llx\n", (long long)
1366 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
1367 }

--- 9 unchanged lines hidden (view full) ---

1377 * Allocate a new mbuf cluster. If that fails, we are
1378 * out of memory, and must drop the packet and recycle
1379 * the buffer that's already attached to this descriptor.
1380 */
1381 m = rxs->rxs_mbuf;
1382 if (gem_add_rxbuf(sc, i) != 0) {
1383 ifp->if_ierrors++;
1384 GEM_INIT_RXDESC(sc, i);
1387 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1388 BUS_DMASYNC_PREREAD);
1389 continue;
1390 }
1391 m->m_data += 2; /* We're already off by two */
1392
1393 m->m_pkthdr.rcvif = ifp;
1394 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
1395
1396 /* Pass it on. */
1397 (*ifp->if_input)(ifp, m);
1398 }
1399
1400 if (progress) {
1385 continue;
1386 }
1387 m->m_data += 2; /* We're already off by two */
1388
1389 m->m_pkthdr.rcvif = ifp;
1390 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
1391
1392 /* Pass it on. */
1393 (*ifp->if_input)(ifp, m);
1394 }
1395
1396 if (progress) {
1397 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1401 /* Update the receive pointer. */
1402 if (i == sc->sc_rxptr) {
1403 device_printf(sc->sc_dev, "rint: ring wrap\n");
1404 }
1405 sc->sc_rxptr = i;
1406 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
1407 }
1408

--- 21 unchanged lines hidden (view full) ---

1430 return (ENOBUFS);
1431 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1432
1433#ifdef GEM_DEBUG
1434 /* bzero the packet to check dma */
1435 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1436#endif
1437
1398 /* Update the receive pointer. */
1399 if (i == sc->sc_rxptr) {
1400 device_printf(sc->sc_dev, "rint: ring wrap\n");
1401 }
1402 sc->sc_rxptr = i;
1403 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
1404 }
1405

--- 21 unchanged lines hidden (view full) ---

1427 return (ENOBUFS);
1428 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1429
1430#ifdef GEM_DEBUG
1431 /* bzero the packet to check dma */
1432 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1433#endif
1434
1438 if (rxs->rxs_mbuf != NULL)
1435 if (rxs->rxs_mbuf != NULL) {
1436 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1437 BUS_DMASYNC_POSTREAD);
1439 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1438 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1439 }
1440
1441 rxs->rxs_mbuf = m;
1442
1443 error = bus_dmamap_load_mbuf(sc->sc_rdmatag, rxs->rxs_dmamap,
1444 m, gem_rxdma_callback, rxs, BUS_DMA_NOWAIT);
1445 if (error != 0 || rxs->rxs_paddr == 0) {
1446 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1447 "%d\n", idx, error);

--- 437 unchanged lines hidden --- 		1440
1441 rxs->rxs_mbuf = m;
1442
1443 error = bus_dmamap_load_mbuf(sc->sc_rdmatag, rxs->rxs_dmamap,
1444 m, gem_rxdma_callback, rxs, BUS_DMA_NOWAIT);
1445 if (error != 0 || rxs->rxs_paddr == 0) {
1446 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1447 "%d\n", idx, error);

--- 437 unchanged lines hidden ---