1/*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 14 unchanged lines hidden (view full) --- 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 28 */ 29 30#include <sys/cdefs.h> |
31__FBSDID("$FreeBSD: head/sys/dev/gem/if_gem.c 169269 2007-05-04 19:15:28Z phk $"); |
32 33/* 34 * Driver for Sun GEM ethernet controllers. 35 */ 36 37#if 0 38#define GEM_DEBUG 39#endif --- 10 unchanged lines hidden (view full) --- 50#include <sys/mbuf.h> 51#include <sys/malloc.h> 52#include <sys/kernel.h> 53#include <sys/lock.h> 54#include <sys/module.h> 55#include <sys/mutex.h> 56#include <sys/socket.h> 57#include <sys/sockio.h> |
58#include <sys/rman.h> |
59 60#include <net/bpf.h> 61#include <net/ethernet.h> 62#include <net/if.h> 63#include <net/if_arp.h> 64#include <net/if_dl.h> 65#include <net/if_media.h> 66#include <net/if_types.h> --- 186 unchanged lines hidden (view full) --- 253 /* 254 * From this point forward, the attachment cannot fail. A failure 255 * before this point releases all resources that may have been 256 * allocated. 257 */ 258 259 /* Get RX FIFO size */ 260 sc->sc_rxfifosize = 64 * |
261 bus_read_4(sc->sc_res[0], GEM_RX_FIFO_SIZE); |
262 263 /* Get TX FIFO size */ |
264 v = bus_read_4(sc->sc_res[0], GEM_TX_FIFO_SIZE); |
265 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 266 sc->sc_rxfifosize / 1024, v / 16); 267 268 /* Initialize ifnet structure. */ 269 ifp->if_softc = sc; 270 if_initname(ifp, device_get_name(sc->sc_dev), 271 device_get_unit(sc->sc_dev)); 272 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; --- 38 unchanged lines hidden (view full) --- 311#endif 312 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL; 313 } else { 314#ifdef GEM_DEBUG 315 printf("using internal phy\n"); 316#endif 317 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL; 318 } |
319 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, |
320 sc->sc_mif_config); 321 /* Attach the interface. */ 322 ether_ifattach(ifp, sc->sc_enaddr); 323 324#ifdef notyet 325 /* 326 * Add a suspend hook to make sure we come back up after a 327 * resume. --- 227 unchanged lines hidden (view full) --- 555 bus_addr_t r; 556 u_int32_t clr; 557 u_int32_t set; 558{ 559 int i; 560 u_int32_t reg; 561 562 for (i = TRIES; i--; DELAY(100)) { |
563 reg = bus_read_4(sc->sc_res[0], r); |
564 if ((r & clr) == 0 && (r & set) == set) 565 return (1); 566 } 567 return (0); 568} 569 570void 571gem_reset(sc) 572 struct gem_softc *sc; 573{ |
574 575#ifdef GEM_DEBUG 576 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev)); 577#endif 578 gem_reset_rx(sc); 579 gem_reset_tx(sc); 580 581 /* Do a full reset */ |
582 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX | GEM_RESET_TX); |
583 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0)) 584 device_printf(sc->sc_dev, "cannot reset device\n"); 585} 586 587 588/* 589 * gem_rxdrain: 590 * --- 71 unchanged lines hidden (view full) --- 662 663/* 664 * Reset the receiver 665 */ 666int 667gem_reset_rx(sc) 668 struct gem_softc *sc; 669{ |
670 671 /* 672 * Resetting while DMA is in progress can cause a bus hang, so we 673 * disable DMA first. 674 */ 675 gem_disable_rx(sc); |
676 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, 0); |
677 /* Wait till it finishes */ 678 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0)) 679 device_printf(sc->sc_dev, "cannot disable read dma\n"); 680 681 /* Wait 5ms extra. */ 682 DELAY(5000); 683 684 /* Finally, reset the ERX */ |
685 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_RX); |
686 /* Wait till it finishes */ 687 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 688 device_printf(sc->sc_dev, "cannot reset receiver\n"); 689 return (1); 690 } 691 return (0); 692} 693 694 695/* 696 * Reset the transmitter 697 */ 698static int 699gem_reset_tx(sc) 700 struct gem_softc *sc; 701{ |
702 int i; 703 704 /* 705 * Resetting while DMA is in progress can cause a bus hang, so we 706 * disable DMA first. 707 */ 708 gem_disable_tx(sc); |
709 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, 0); |
710 /* Wait till it finishes */ 711 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0)) 712 device_printf(sc->sc_dev, "cannot disable read dma\n"); 713 714 /* Wait 5ms extra. */ 715 DELAY(5000); 716 717 /* Finally, reset the ETX */ |
718 bus_write_4(sc->sc_res[0], GEM_RESET, GEM_RESET_TX); |
719 /* Wait till it finishes */ 720 for (i = TRIES; i--; DELAY(100)) |
721 if ((bus_read_4(sc->sc_res[0], GEM_RESET) & GEM_RESET_TX) == 0) |
722 break; 723 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) { 724 device_printf(sc->sc_dev, "cannot reset receiver\n"); 725 return (1); 726 } 727 return (0); 728} 729 730/* 731 * disable receiver. 732 */ 733static int 734gem_disable_rx(sc) 735 struct gem_softc *sc; 736{ |
737 u_int32_t cfg; 738 739 /* Flip the enable bit */ |
740 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG); |
741 cfg &= ~GEM_MAC_RX_ENABLE; |
742 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, cfg); |
743 744 /* Wait for it to finish */ 745 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0)); 746} 747 748/* 749 * disable transmitter. 750 */ 751static int 752gem_disable_tx(sc) 753 struct gem_softc *sc; 754{ |
755 u_int32_t cfg; 756 757 /* Flip the enable bit */ |
758 cfg = bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG); |
759 cfg &= ~GEM_MAC_TX_ENABLE; |
760 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, cfg); |
761 762 /* Wait for it to finish */ 763 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0)); 764} 765 766/* 767 * Initialize interface. 768 */ --- 99 unchanged lines hidden (view full) --- 868 * Initialization of interface; set up initialization block 869 * and transmit/receive descriptor rings. 870 */ 871static void 872gem_init_locked(sc) 873 struct gem_softc *sc; 874{ 875 struct ifnet *ifp = sc->sc_ifp; |
876 u_int32_t v; 877 878 GEM_LOCK_ASSERT(sc, MA_OWNED); 879 880#ifdef GEM_DEBUG 881 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev)); 882#endif 883 /* --- 19 unchanged lines hidden (view full) --- 903 /* step 4. TX MAC registers & counters */ 904 gem_init_regs(sc); 905 906 /* step 5. RX MAC registers & counters */ 907 gem_setladrf(sc); 908 909 /* step 6 & 7. Program Descriptor Ring Base Addresses */ 910 /* NOTE: we use only 32-bit DMA addresses here. */ |
911 bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_HI, 0); 912 bus_write_4(sc->sc_res[0], GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0)); |
913 |
914 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_HI, 0); 915 bus_write_4(sc->sc_res[0], GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0)); |
916#ifdef GEM_DEBUG 917 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx", 918 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma); 919#endif 920 921 /* step 8. Global Configuration & Interrupt Mask */ |
922 bus_write_4(sc->sc_res[0], GEM_INTMASK, |
923 ~(GEM_INTR_TX_INTME| 924 GEM_INTR_TX_EMPTY| 925 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF| 926 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS| 927 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF| 928 GEM_INTR_BERR)); |
929 bus_write_4(sc->sc_res[0], GEM_MAC_RX_MASK, |
930 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT); |
931 bus_write_4(sc->sc_res[0], GEM_MAC_TX_MASK, 0xffff); /* XXXX */ 932 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_MASK, 0); /* XXXX */ |
933 934 /* step 9. ETX Configuration: use mostly default values */ 935 936 /* Enable DMA */ 937 v = gem_ringsize(GEM_NTXDESC /*XXX*/); |
938 bus_write_4(sc->sc_res[0], GEM_TX_CONFIG, |
939 v|GEM_TX_CONFIG_TXDMA_EN| 940 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH)); 941 942 /* step 10. ERX Configuration */ 943 944 /* Encode Receive Descriptor ring size: four possible values */ 945 v = gem_ringsize(GEM_NRXDESC /*XXX*/); 946 947 /* Enable DMA */ |
948 bus_write_4(sc->sc_res[0], GEM_RX_CONFIG, |
949 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)| 950 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN| 951 (0<<GEM_RX_CONFIG_CXM_START_SHFT)); 952 /* 953 * The following value is for an OFF Threshold of about 3/4 full 954 * and an ON Threshold of 1/4 full. 955 */ |
956 bus_write_4(sc->sc_res[0], GEM_RX_PAUSE_THRESH, |
957 (3 * sc->sc_rxfifosize / 256) | 958 ( (sc->sc_rxfifosize / 256) << 12)); |
959 bus_write_4(sc->sc_res[0], GEM_RX_BLANKING, (6<<12)|6); |
960 961 /* step 11. Configure Media */ 962 mii_mediachg(sc->sc_mii); 963 964 /* step 12. RX_MAC Configuration Register */ |
965 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG); |
966 v |= GEM_MAC_RX_ENABLE; |
967 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v); |
968 969 /* step 14. Issue Transmit Pending command */ 970 971 /* step 15. Give the reciever a swift kick */ |
972 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_NRXDESC-4); |
973 974 /* Start the one second timer. */ 975 sc->sc_wdog_timer = 0; 976 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc); 977 978 ifp->if_drv_flags |= IFF_DRV_RUNNING; 979 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 980 sc->sc_ifflags = ifp->if_flags; --- 49 unchanged lines hidden (view full) --- 1030 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1031 return (error); 1032} 1033 1034static void 1035gem_init_regs(sc) 1036 struct gem_softc *sc; 1037{ |
1038 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1039 u_int32_t v; 1040 1041 /* These regs are not cleared on reset */ 1042 if (!sc->sc_inited) { 1043 1044 /* Wooo. Magic values. */ |
1045 bus_write_4(sc->sc_res[0], GEM_MAC_IPG0, 0); 1046 bus_write_4(sc->sc_res[0], GEM_MAC_IPG1, 8); 1047 bus_write_4(sc->sc_res[0], GEM_MAC_IPG2, 4); |
1048 |
1049 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN); |
1050 /* Max frame and max burst size */ |
1051 bus_write_4(sc->sc_res[0], GEM_MAC_MAC_MAX_FRAME, |
1052 (ETHER_MAX_LEN + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) | 1053 (0x2000 << 16)); 1054 |
1055 bus_write_4(sc->sc_res[0], GEM_MAC_PREAMBLE_LEN, 0x7); 1056 bus_write_4(sc->sc_res[0], GEM_MAC_JAM_SIZE, 0x4); 1057 bus_write_4(sc->sc_res[0], GEM_MAC_ATTEMPT_LIMIT, 0x10); |
1058 /* Dunno.... */ |
1059 bus_write_4(sc->sc_res[0], GEM_MAC_CONTROL_TYPE, 0x8088); 1060 bus_write_4(sc->sc_res[0], GEM_MAC_RANDOM_SEED, |
1061 ((laddr[5]<<8)|laddr[4])&0x3ff); 1062 1063 /* Secondary MAC addr set to 0:0:0:0:0:0 */ |
1064 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR3, 0); 1065 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR4, 0); 1066 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR5, 0); |
1067 1068 /* MAC control addr set to 01:80:c2:00:00:01 */ |
1069 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR6, 0x0001); 1070 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR7, 0xc200); 1071 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR8, 0x0180); |
1072 1073 /* MAC filter addr set to 0:0:0:0:0:0 */ |
1074 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER0, 0); 1075 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER1, 0); 1076 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR_FILTER2, 0); |
1077 |
1078 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK1_2, 0); 1079 bus_write_4(sc->sc_res[0], GEM_MAC_ADR_FLT_MASK0, 0); |
1080 1081 sc->sc_inited = 1; 1082 } 1083 1084 /* Counters need to be zeroed */ |
1085 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0); 1086 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0); 1087 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0); 1088 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0); 1089 bus_write_4(sc->sc_res[0], GEM_MAC_DEFER_TMR_CNT, 0); 1090 bus_write_4(sc->sc_res[0], GEM_MAC_PEAK_ATTEMPTS, 0); 1091 bus_write_4(sc->sc_res[0], GEM_MAC_RX_FRAME_COUNT, 0); 1092 bus_write_4(sc->sc_res[0], GEM_MAC_RX_LEN_ERR_CNT, 0); 1093 bus_write_4(sc->sc_res[0], GEM_MAC_RX_ALIGN_ERR, 0); 1094 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CRC_ERR_CNT, 0); 1095 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CODE_VIOL, 0); |
1096 1097 /* Un-pause stuff */ 1098#if 0 |
1099 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0x1BF0); |
1100#else |
1101 bus_write_4(sc->sc_res[0], GEM_MAC_SEND_PAUSE_CMD, 0); |
1102#endif 1103 1104 /* 1105 * Set the station address. 1106 */ |
1107 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]); 1108 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]); 1109 bus_write_4(sc->sc_res[0], GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]); |
1110 1111 /* 1112 * Enable MII outputs. Enable GMII if there is a gigabit PHY. 1113 */ |
1114 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG); |
1115 v = GEM_MAC_XIF_TX_MII_ENA; 1116 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) { 1117 v |= GEM_MAC_XIF_FDPLX_LED; 1118 if (sc->sc_flags & GEM_GIGABIT) 1119 v |= GEM_MAC_XIF_GMII_MODE; 1120 } |
1121 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v); |
1122} 1123 1124static void 1125gem_start(ifp) 1126 struct ifnet *ifp; 1127{ 1128 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc; 1129 --- 56 unchanged lines hidden (view full) --- 1186 } 1187 1188 ntx++; 1189 /* Kick the transmitter. */ 1190#ifdef GEM_DEBUG 1191 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d", 1192 device_get_name(sc->sc_dev), sc->sc_txnext); 1193#endif |
1194 bus_write_4(sc->sc_res[0], GEM_TX_KICK, |
1195 sc->sc_txnext); 1196 1197 BPF_MTAP(ifp, m0); 1198 } while (1); 1199 1200 if (txmfail == -1 || sc->sc_txfree == 0) { 1201 /* No more slots left; notify upper layer. */ 1202 ifp->if_drv_flags |= IFF_DRV_OACTIVE; --- 19 unchanged lines hidden (view full) --- 1222/* 1223 * Transmit interrupt. 1224 */ 1225static void 1226gem_tint(sc) 1227 struct gem_softc *sc; 1228{ 1229 struct ifnet *ifp = sc->sc_ifp; |
1230 struct gem_txsoft *txs; 1231 int txlast; 1232 int progress = 0; 1233 1234 1235#ifdef GEM_DEBUG 1236 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev)); 1237#endif 1238 1239 /* 1240 * Unload collision counters 1241 */ 1242 ifp->if_collisions += |
1243 bus_read_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT) + 1244 bus_read_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT) + 1245 bus_read_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT) + 1246 bus_read_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT); |
1247 1248 /* 1249 * then clear the hardware counters. 1250 */ |
1251 bus_write_4(sc->sc_res[0], GEM_MAC_NORM_COLL_CNT, 0); 1252 bus_write_4(sc->sc_res[0], GEM_MAC_FIRST_COLL_CNT, 0); 1253 bus_write_4(sc->sc_res[0], GEM_MAC_EXCESS_COLL_CNT, 0); 1254 bus_write_4(sc->sc_res[0], GEM_MAC_LATE_COLL_CNT, 0); |
1255 1256 /* 1257 * Go through our Tx list and free mbufs for those 1258 * frames that have been transmitted. 1259 */ 1260 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1261 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1262 --- 15 unchanged lines hidden (view full) --- 1278 1279 /* 1280 * In theory, we could harveast some descriptors before 1281 * the ring is empty, but that's a bit complicated. 1282 * 1283 * GEM_TX_COMPLETION points to the last descriptor 1284 * processed +1. 1285 */ |
1286 txlast = bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION); |
1287#ifdef GEM_DEBUG 1288 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, " 1289 "txs->txs_lastdesc = %d, txlast = %d", 1290 txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1291#endif 1292 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1293 if ((txlast >= txs->txs_firstdesc) && 1294 (txlast <= txs->txs_lastdesc)) --- 25 unchanged lines hidden (view full) --- 1320 ifp->if_opackets++; 1321 progress = 1; 1322 } 1323 1324#ifdef GEM_DEBUG 1325 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x " 1326 "GEM_TX_DATA_PTR %llx " 1327 "GEM_TX_COMPLETION %x", |
1328 bus_read_4(sc->sc_res[0], GEM_TX_STATE_MACHINE), 1329 ((long long) bus_read_4(sc->sc_res[0], |
1330 GEM_TX_DATA_PTR_HI) << 32) | |
1331 bus_read_4(sc->sc_res[0], |
1332 GEM_TX_DATA_PTR_LO), |
1333 bus_read_4(sc->sc_res[0], GEM_TX_COMPLETION)); |
1334#endif 1335 1336 if (progress) { 1337 if (sc->sc_txfree == GEM_NTXDESC - 1) 1338 sc->sc_txwin = 0; 1339 1340 /* Freed some descriptors, so reset IFF_DRV_OACTIVE and restart. */ 1341 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; --- 23 unchanged lines hidden (view full) --- 1365/* 1366 * Receive interrupt. 1367 */ 1368static void 1369gem_rint(sc) 1370 struct gem_softc *sc; 1371{ 1372 struct ifnet *ifp = sc->sc_ifp; |
1373 struct gem_rxsoft *rxs; 1374 struct mbuf *m; 1375 u_int64_t rxstat; 1376 u_int32_t rxcomp; 1377 int i, len, progress = 0; 1378 1379#ifdef GEM_RINT_TIMEOUT 1380 callout_stop(&sc->sc_rx_ch); 1381#endif 1382#ifdef GEM_DEBUG 1383 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev)); 1384#endif 1385 1386 /* 1387 * Read the completion register once. This limits 1388 * how long the following loop can execute. 1389 */ |
1390 rxcomp = bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION); |
1391 1392#ifdef GEM_DEBUG 1393 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d", 1394 sc->sc_rxptr, rxcomp); 1395#endif 1396 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1397 for (i = sc->sc_rxptr; i != rxcomp; 1398 i = GEM_NEXTRX(i)) { --- 67 unchanged lines hidden (view full) --- 1466 1467 if (progress) { 1468 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE); 1469 /* Update the receive pointer. */ 1470 if (i == sc->sc_rxptr) { 1471 device_printf(sc->sc_dev, "rint: ring wrap\n"); 1472 } 1473 sc->sc_rxptr = i; |
1474 bus_write_4(sc->sc_res[0], GEM_RX_KICK, GEM_PREVRX(i)); |
1475 } 1476 1477#ifdef GEM_DEBUG 1478 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d", |
1479 sc->sc_rxptr, bus_read_4(sc->sc_res[0], GEM_RX_COMPLETION)); |
1480#endif 1481} 1482 1483 1484/* 1485 * gem_add_rxbuf: 1486 * 1487 * Add a receive buffer to the indicated descriptor. --- 61 unchanged lines hidden (view full) --- 1549} 1550 1551 1552void 1553gem_intr(v) 1554 void *v; 1555{ 1556 struct gem_softc *sc = (struct gem_softc *)v; |
1557 u_int32_t status; 1558 1559 GEM_LOCK(sc); |
1560 status = bus_read_4(sc->sc_res[0], GEM_STATUS); |
1561#ifdef GEM_DEBUG 1562 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x", 1563 device_get_name(sc->sc_dev), (status>>19), 1564 (u_int)status); 1565#endif 1566 1567 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0) 1568 gem_eint(sc, status); 1569 1570 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0) 1571 gem_tint(sc); 1572 1573 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0) 1574 gem_rint(sc); 1575 1576 /* We should eventually do more than just print out error stats. */ 1577 if (status & GEM_INTR_TX_MAC) { |
1578 int txstat = bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS); |
1579 if (txstat & ~GEM_MAC_TX_XMIT_DONE) 1580 device_printf(sc->sc_dev, "MAC tx fault, status %x\n", 1581 txstat); 1582 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG)) 1583 gem_init_locked(sc); 1584 } 1585 if (status & GEM_INTR_RX_MAC) { |
1586 int rxstat = bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS); |
1587 /* 1588 * On some chip revisions GEM_MAC_RX_OVERFLOW happen often 1589 * due to a silicon bug so handle them silently. 1590 */ 1591 if (rxstat & GEM_MAC_RX_OVERFLOW) 1592 gem_init_locked(sc); 1593 else if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT)) 1594 device_printf(sc->sc_dev, "MAC rx fault, status %x\n", --- 7 unchanged lines hidden (view full) --- 1602 struct gem_softc *sc; 1603{ 1604 1605 GEM_LOCK_ASSERT(sc, MA_OWNED); 1606 1607#ifdef GEM_DEBUG 1608 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x " 1609 "GEM_MAC_RX_CONFIG %x", |
1610 bus_read_4(sc->sc_res[0], GEM_RX_CONFIG), 1611 bus_read_4(sc->sc_res[0], GEM_MAC_RX_STATUS), 1612 bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG)); |
1613 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x " 1614 "GEM_MAC_TX_CONFIG %x", |
1615 bus_read_4(sc->sc_res[0], GEM_TX_CONFIG), 1616 bus_read_4(sc->sc_res[0], GEM_MAC_TX_STATUS), 1617 bus_read_4(sc->sc_res[0], GEM_MAC_TX_CONFIG)); |
1618#endif 1619 1620 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 1621 return (0); 1622 1623 device_printf(sc->sc_dev, "device timeout\n"); 1624 ++sc->sc_ifp->if_oerrors; 1625 --- 4 unchanged lines hidden (view full) --- 1630 1631/* 1632 * Initialize the MII Management Interface 1633 */ 1634static void 1635gem_mifinit(sc) 1636 struct gem_softc *sc; 1637{ |
1638 1639 /* Configure the MIF in frame mode */ |
1640 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG); |
1641 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA; |
1642 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, sc->sc_mif_config); |
1643} 1644 1645/* 1646 * MII interface 1647 * 1648 * The GEM MII interface supports at least three different operating modes: 1649 * 1650 * Bitbang mode is implemented using data, clock and output enable registers. --- 6 unchanged lines hidden (view full) --- 1657 * 1658 */ 1659int 1660gem_mii_readreg(dev, phy, reg) 1661 device_t dev; 1662 int phy, reg; 1663{ 1664 struct gem_softc *sc = device_get_softc(dev); |
1665 int n; 1666 u_int32_t v; 1667 1668#ifdef GEM_DEBUG_PHY 1669 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg); 1670#endif 1671 1672#if 0 1673 /* Select the desired PHY in the MIF configuration register */ |
1674 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG); |
1675 /* Clear PHY select bit */ 1676 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1677 if (phy == GEM_PHYAD_EXTERNAL) 1678 /* Set PHY select bit to get at external device */ 1679 v |= GEM_MIF_CONFIG_PHY_SEL; |
1680 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v); |
1681#endif 1682 1683 /* Construct the frame command */ 1684 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) | 1685 GEM_MIF_FRAME_READ; 1686 |
1687 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v); |
1688 for (n = 0; n < 100; n++) { 1689 DELAY(1); |
1690 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME); |
1691 if (v & GEM_MIF_FRAME_TA0) 1692 return (v & GEM_MIF_FRAME_DATA); 1693 } 1694 1695 device_printf(sc->sc_dev, "mii_read timeout\n"); 1696 return (0); 1697} 1698 1699int 1700gem_mii_writereg(dev, phy, reg, val) 1701 device_t dev; 1702 int phy, reg, val; 1703{ 1704 struct gem_softc *sc = device_get_softc(dev); |
1705 int n; 1706 u_int32_t v; 1707 1708#ifdef GEM_DEBUG_PHY 1709 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val); 1710#endif 1711 1712#if 0 1713 /* Select the desired PHY in the MIF configuration register */ |
1714 v = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG); |
1715 /* Clear PHY select bit */ 1716 v &= ~GEM_MIF_CONFIG_PHY_SEL; 1717 if (phy == GEM_PHYAD_EXTERNAL) 1718 /* Set PHY select bit to get at external device */ 1719 v |= GEM_MIF_CONFIG_PHY_SEL; |
1720 bus_write_4(sc->sc_res[0], GEM_MIF_CONFIG, v); |
1721#endif 1722 /* Construct the frame command */ 1723 v = GEM_MIF_FRAME_WRITE | 1724 (phy << GEM_MIF_PHY_SHIFT) | 1725 (reg << GEM_MIF_REG_SHIFT) | 1726 (val & GEM_MIF_FRAME_DATA); 1727 |
1728 bus_write_4(sc->sc_res[0], GEM_MIF_FRAME, v); |
1729 for (n = 0; n < 100; n++) { 1730 DELAY(1); |
1731 v = bus_read_4(sc->sc_res[0], GEM_MIF_FRAME); |
1732 if (v & GEM_MIF_FRAME_TA0) 1733 return (1); 1734 } 1735 1736 device_printf(sc->sc_dev, "mii_write timeout\n"); 1737 return (0); 1738} 1739 1740void 1741gem_mii_statchg(dev) 1742 device_t dev; 1743{ 1744 struct gem_softc *sc = device_get_softc(dev); 1745#ifdef GEM_DEBUG 1746 int instance; 1747#endif |
1748 u_int32_t v; 1749 1750#ifdef GEM_DEBUG 1751 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media); 1752 if (sc->sc_debug) 1753 printf("gem_mii_statchg: status change: phy = %d\n", 1754 sc->sc_phys[instance]); 1755#endif 1756 1757 /* Set tx full duplex options */ |
1758 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, 0); |
1759 DELAY(10000); /* reg must be cleared and delay before changing. */ 1760 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT| 1761 GEM_MAC_TX_ENABLE; 1762 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) { 1763 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS; 1764 } |
1765 bus_write_4(sc->sc_res[0], GEM_MAC_TX_CONFIG, v); |
1766 1767 /* XIF Configuration */ 1768 v = GEM_MAC_XIF_LINK_LED; 1769 v |= GEM_MAC_XIF_TX_MII_ENA; 1770 1771 /* If an external transceiver is connected, enable its MII drivers */ |
1772 sc->sc_mif_config = bus_read_4(sc->sc_res[0], GEM_MIF_CONFIG); |
1773 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) { 1774 /* External MII needs echo disable if half duplex. */ 1775 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 1776 /* turn on full duplex LED */ 1777 v |= GEM_MAC_XIF_FDPLX_LED; 1778 else 1779 /* half duplex -- disable echo */ 1780 v |= GEM_MAC_XIF_ECHO_DISABL; 1781 1782 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T) 1783 v |= GEM_MAC_XIF_GMII_MODE; 1784 else 1785 v &= ~GEM_MAC_XIF_GMII_MODE; 1786 } else { 1787 /* Internal MII needs buf enable */ 1788 v |= GEM_MAC_XIF_MII_BUF_ENA; 1789 } |
1790 bus_write_4(sc->sc_res[0], GEM_MAC_XIF_CONFIG, v); |
1791} 1792 1793int 1794gem_mediachange(ifp) 1795 struct ifnet *ifp; 1796{ 1797 struct gem_softc *sc = ifp->if_softc; 1798 int error; --- 80 unchanged lines hidden (view full) --- 1879 * Set up the logical address filter. 1880 */ 1881static void 1882gem_setladrf(sc) 1883 struct gem_softc *sc; 1884{ 1885 struct ifnet *ifp = sc->sc_ifp; 1886 struct ifmultiaddr *inm; |
1887 u_int32_t crc; 1888 u_int32_t hash[16]; 1889 u_int32_t v; 1890 int i; 1891 1892 GEM_LOCK_ASSERT(sc, MA_OWNED); 1893 1894 /* Get current RX configuration */ |
1895 v = bus_read_4(sc->sc_res[0], GEM_MAC_RX_CONFIG); |
1896 1897 /* 1898 * Turn off promiscuous mode, promiscuous group mode (all multicast), 1899 * and hash filter. Depending on the case, the right bit will be 1900 * enabled. 1901 */ 1902 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER| 1903 GEM_MAC_RX_PROMISC_GRP); --- 36 unchanged lines hidden (view full) --- 1940 } 1941 IF_ADDR_UNLOCK(ifp); 1942 1943 v |= GEM_MAC_RX_HASH_FILTER; 1944 ifp->if_flags &= ~IFF_ALLMULTI; 1945 1946 /* Now load the hash table into the chip (if we are using it) */ 1947 for (i = 0; i < 16; i++) { |
1948 bus_write_4(sc->sc_res[0], |
1949 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0), 1950 hash[i]); 1951 } 1952 1953chipit: |
1954 bus_write_4(sc->sc_res[0], GEM_MAC_RX_CONFIG, v); |
1955} |