32
33/*
34 * Driver for Sun GEM ethernet controllers.
35 */
36
37#if 0
38#define GEM_DEBUG
39#endif
40
41#if 0 /* XXX: In case of emergency, re-enable this. */
42#define GEM_RINT_TIMEOUT
43#endif
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48#include <sys/callout.h>
49#include <sys/endian.h>
50#include <sys/mbuf.h>
51#include <sys/malloc.h>
52#include <sys/kernel.h>
53#include <sys/lock.h>
54#include <sys/module.h>
55#include <sys/mutex.h>
56#include <sys/socket.h>
57#include <sys/sockio.h>
58
59#include <net/bpf.h>
60#include <net/ethernet.h>
61#include <net/if.h>
62#include <net/if_arp.h>
63#include <net/if_dl.h>
64#include <net/if_media.h>
65#include <net/if_types.h>
66
67#include <machine/bus.h>
68
69#include <dev/mii/mii.h>
70#include <dev/mii/miivar.h>
71
72#include <dev/gem/if_gemreg.h>
73#include <dev/gem/if_gemvar.h>
74
75#define TRIES 10000
76
77static void gem_start(struct ifnet *);
78static void gem_start_locked(struct ifnet *);
79static void gem_stop(struct ifnet *, int);
80static int gem_ioctl(struct ifnet *, u_long, caddr_t);
81static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int);
82static void gem_txdma_callback(void *, bus_dma_segment_t *, int,
83 bus_size_t, int);
84static void gem_tick(void *);
85static void gem_watchdog(struct ifnet *);
86static void gem_init(void *);
87static void gem_init_locked(struct gem_softc *sc);
88static void gem_init_regs(struct gem_softc *sc);
89static int gem_ringsize(int sz);
90static int gem_meminit(struct gem_softc *);
91static int gem_load_txmbuf(struct gem_softc *, struct mbuf *);
92static void gem_mifinit(struct gem_softc *);
93static int gem_bitwait(struct gem_softc *sc, bus_addr_t r,
94 u_int32_t clr, u_int32_t set);
95static int gem_reset_rx(struct gem_softc *);
96static int gem_reset_tx(struct gem_softc *);
97static int gem_disable_rx(struct gem_softc *);
98static int gem_disable_tx(struct gem_softc *);
99static void gem_rxdrain(struct gem_softc *);
100static int gem_add_rxbuf(struct gem_softc *, int);
101static void gem_setladrf(struct gem_softc *);
102
103struct mbuf *gem_get(struct gem_softc *, int, int);
104static void gem_eint(struct gem_softc *, u_int);
105static void gem_rint(struct gem_softc *);
106#ifdef GEM_RINT_TIMEOUT
107static void gem_rint_timeout(void *);
108#endif
109static void gem_tint(struct gem_softc *);
110#ifdef notyet
111static void gem_power(int, void *);
112#endif
113
114devclass_t gem_devclass;
115DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
116MODULE_DEPEND(gem, miibus, 1, 1, 1);
117
118#ifdef GEM_DEBUG
119#include <sys/ktr.h>
120#define KTR_GEM KTR_CT2
121#endif
122
123#define GEM_NSEGS GEM_NTXDESC
124
125/*
126 * gem_attach:
127 *
128 * Attach a Gem interface to the system.
129 */
130int
131gem_attach(sc)
132 struct gem_softc *sc;
133{
134 struct ifnet *ifp;
135 struct mii_softc *child;
136 int i, error;
137 u_int32_t v;
138
139 GEM_LOCK_ASSERT(sc, MA_NOTOWNED);
140
141 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
142 if (ifp == NULL)
143 return (ENOSPC);
144
145 /* Make sure the chip is stopped. */
146 ifp->if_softc = sc;
147 GEM_LOCK(sc);
148 gem_reset(sc);
149 GEM_UNLOCK(sc);
150
151 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
152 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS,
153 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag);
154 if (error)
155 goto fail_ifnet;
156
157 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
158 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE,
159 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL,
160 &sc->sc_rdmatag);
161 if (error)
162 goto fail_ptag;
163
164 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
165 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
166 GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT,
167 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
168 if (error)
169 goto fail_rtag;
170
171 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0,
172 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
173 sizeof(struct gem_control_data), 1,
174 sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW,
175 busdma_lock_mutex, &Giant, &sc->sc_cdmatag);
176 if (error)
177 goto fail_ttag;
178
179 /*
180 * Allocate the control data structures, and create and load the
181 * DMA map for it.
182 */
183 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
184 (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) {
185 device_printf(sc->sc_dev, "unable to allocate control data,"
186 " error = %d\n", error);
187 goto fail_ctag;
188 }
189
190 sc->sc_cddma = 0;
191 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
192 sc->sc_control_data, sizeof(struct gem_control_data),
193 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
194 device_printf(sc->sc_dev, "unable to load control data DMA "
195 "map, error = %d\n", error);
196 goto fail_cmem;
197 }
198
199 /*
200 * Initialize the transmit job descriptors.
201 */
202 STAILQ_INIT(&sc->sc_txfreeq);
203 STAILQ_INIT(&sc->sc_txdirtyq);
204
205 /*
206 * Create the transmit buffer DMA maps.
207 */
208 error = ENOMEM;
209 for (i = 0; i < GEM_TXQUEUELEN; i++) {
210 struct gem_txsoft *txs;
211
212 txs = &sc->sc_txsoft[i];
213 txs->txs_mbuf = NULL;
214 txs->txs_ndescs = 0;
215 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
216 &txs->txs_dmamap)) != 0) {
217 device_printf(sc->sc_dev, "unable to create tx DMA map "
218 "%d, error = %d\n", i, error);
219 goto fail_txd;
220 }
221 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
222 }
223
224 /*
225 * Create the receive buffer DMA maps.
226 */
227 for (i = 0; i < GEM_NRXDESC; i++) {
228 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0,
229 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
230 device_printf(sc->sc_dev, "unable to create rx DMA map "
231 "%d, error = %d\n", i, error);
232 goto fail_rxd;
233 }
234 sc->sc_rxsoft[i].rxs_mbuf = NULL;
235 }
236
237 GEM_LOCK(sc);
238 gem_mifinit(sc);
239 GEM_UNLOCK(sc);
240
241 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange,
242 gem_mediastatus)) != 0) {
243 device_printf(sc->sc_dev, "phy probe failed: %d\n", error);
244 goto fail_rxd;
245 }
246 sc->sc_mii = device_get_softc(sc->sc_miibus);
247
248 /*
249 * From this point forward, the attachment cannot fail. A failure
250 * before this point releases all resources that may have been
251 * allocated.
252 */
253
254 /* Get RX FIFO size */
255 sc->sc_rxfifosize = 64 *
256 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
257
258 /* Get TX FIFO size */
259 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
260 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
261 sc->sc_rxfifosize / 1024, v / 16);
262
263 /* Initialize ifnet structure. */
264 ifp->if_softc = sc;
265 if_initname(ifp, device_get_name(sc->sc_dev),
266 device_get_unit(sc->sc_dev));
267 ifp->if_mtu = ETHERMTU;
268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
269 ifp->if_start = gem_start;
270 ifp->if_ioctl = gem_ioctl;
271 ifp->if_watchdog = gem_watchdog;
272 ifp->if_init = gem_init;
273 ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN;
274 /*
275 * Walk along the list of attached MII devices and
276 * establish an `MII instance' to `phy number'
277 * mapping. We'll use this mapping in media change
278 * requests to determine which phy to use to program
279 * the MIF configuration register.
280 */
281 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL;
282 child = LIST_NEXT(child, mii_list)) {
283 /*
284 * Note: we support just two PHYs: the built-in
285 * internal device and an external on the MII
286 * connector.
287 */
288 if (child->mii_phy > 1 || child->mii_inst > 1) {
289 device_printf(sc->sc_dev, "cannot accomodate "
290 "MII device %s at phy %d, instance %d\n",
291 device_get_name(child->mii_dev),
292 child->mii_phy, child->mii_inst);
293 continue;
294 }
295
296 sc->sc_phys[child->mii_inst] = child->mii_phy;
297 }
298
299 /*
300 * Now select and activate the PHY we will use.
301 *
302 * The order of preference is External (MDI1),
303 * Internal (MDI0), Serial Link (no MII).
304 */
305 if (sc->sc_phys[1]) {
306#ifdef GEM_DEBUG
307 printf("using external phy\n");
308#endif
309 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
310 } else {
311#ifdef GEM_DEBUG
312 printf("using internal phy\n");
313#endif
314 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
315 }
316 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
317 sc->sc_mif_config);
318 /* Attach the interface. */
319 ether_ifattach(ifp, sc->sc_enaddr);
320
321#if notyet
322 /*
323 * Add a suspend hook to make sure we come back up after a
324 * resume.
325 */
326 sc->sc_powerhook = powerhook_establish(gem_power, sc);
327 if (sc->sc_powerhook == NULL)
328 device_printf(sc->sc_dev, "WARNING: unable to establish power "
329 "hook\n");
330#endif
331
332 callout_init(&sc->sc_tick_ch, CALLOUT_MPSAFE);
333#ifdef GEM_RINT_TIMEOUT
334 callout_init(&sc->sc_rx_ch, CALLOUT_MPSAFE);
335#endif
336 return (0);
337
338 /*
339 * Free any resources we've allocated during the failed attach
340 * attempt. Do this in reverse order and fall through.
341 */
342fail_rxd:
343 for (i = 0; i < GEM_NRXDESC; i++) {
344 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
345 bus_dmamap_destroy(sc->sc_rdmatag,
346 sc->sc_rxsoft[i].rxs_dmamap);
347 }
348fail_txd:
349 for (i = 0; i < GEM_TXQUEUELEN; i++) {
350 if (sc->sc_txsoft[i].txs_dmamap != NULL)
351 bus_dmamap_destroy(sc->sc_tdmatag,
352 sc->sc_txsoft[i].txs_dmamap);
353 }
354 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
355fail_cmem:
356 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
357 sc->sc_cddmamap);
358fail_ctag:
359 bus_dma_tag_destroy(sc->sc_cdmatag);
360fail_ttag:
361 bus_dma_tag_destroy(sc->sc_tdmatag);
362fail_rtag:
363 bus_dma_tag_destroy(sc->sc_rdmatag);
364fail_ptag:
365 bus_dma_tag_destroy(sc->sc_pdmatag);
366fail_ifnet:
367 if_free(ifp);
368 return (error);
369}
370
371void
372gem_detach(sc)
373 struct gem_softc *sc;
374{
375 struct ifnet *ifp = sc->sc_ifp;
376 int i;
377
378 GEM_LOCK_ASSERT(sc, MA_NOTOWNED);
379
380 GEM_LOCK(sc);
381 gem_stop(ifp, 1);
382 GEM_UNLOCK(sc);
383 ether_ifdetach(ifp);
384 if_free(ifp);
385 device_delete_child(sc->sc_dev, sc->sc_miibus);
386
387 for (i = 0; i < GEM_NRXDESC; i++) {
388 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
389 bus_dmamap_destroy(sc->sc_rdmatag,
390 sc->sc_rxsoft[i].rxs_dmamap);
391 }
392 for (i = 0; i < GEM_TXQUEUELEN; i++) {
393 if (sc->sc_txsoft[i].txs_dmamap != NULL)
394 bus_dmamap_destroy(sc->sc_tdmatag,
395 sc->sc_txsoft[i].txs_dmamap);
396 }
397 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
398 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE);
399 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
400 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
401 sc->sc_cddmamap);
402 bus_dma_tag_destroy(sc->sc_cdmatag);
403 bus_dma_tag_destroy(sc->sc_tdmatag);
404 bus_dma_tag_destroy(sc->sc_rdmatag);
405 bus_dma_tag_destroy(sc->sc_pdmatag);
406}
407
408void
409gem_suspend(sc)
410 struct gem_softc *sc;
411{
412 struct ifnet *ifp = sc->sc_ifp;
413
414 GEM_LOCK(sc);
415 gem_stop(ifp, 0);
416 GEM_UNLOCK(sc);
417}
418
419void
420gem_resume(sc)
421 struct gem_softc *sc;
422{
423 struct ifnet *ifp = sc->sc_ifp;
424
425 GEM_LOCK(sc);
426 if (ifp->if_flags & IFF_UP)
427 gem_init_locked(sc);
428 GEM_UNLOCK(sc);
429}
430
431static void
432gem_cddma_callback(xsc, segs, nsegs, error)
433 void *xsc;
434 bus_dma_segment_t *segs;
435 int nsegs;
436 int error;
437{
438 struct gem_softc *sc = (struct gem_softc *)xsc;
439
440 if (error != 0)
441 return;
442 if (nsegs != 1) {
443 /* can't happen... */
444 panic("gem_cddma_callback: bad control buffer segment count");
445 }
446 sc->sc_cddma = segs[0].ds_addr;
447}
448
449static void
450gem_txdma_callback(xsc, segs, nsegs, totsz, error)
451 void *xsc;
452 bus_dma_segment_t *segs;
453 int nsegs;
454 bus_size_t totsz;
455 int error;
456{
457 struct gem_txdma *txd = (struct gem_txdma *)xsc;
458 struct gem_softc *sc = txd->txd_sc;
459 struct gem_txsoft *txs = txd->txd_txs;
460 bus_size_t len = 0;
461 uint64_t flags = 0;
462 int seg, nexttx;
463
464 if (error != 0)
465 return;
466 /*
467 * Ensure we have enough descriptors free to describe
468 * the packet. Note, we always reserve one descriptor
469 * at the end of the ring as a termination point, to
470 * prevent wrap-around.
471 */
472 if (nsegs > sc->sc_txfree - 1) {
473 txs->txs_ndescs = -1;
474 return;
475 }
476 txs->txs_ndescs = nsegs;
477
478 nexttx = txs->txs_firstdesc;
479 /*
480 * Initialize the transmit descriptors.
481 */
482 for (seg = 0; seg < nsegs;
483 seg++, nexttx = GEM_NEXTTX(nexttx)) {
484#ifdef GEM_DEBUG
485 CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len "
486 "%lx, addr %#lx (%#lx)", seg, nexttx,
487 segs[seg].ds_len, segs[seg].ds_addr,
488 GEM_DMA_WRITE(sc, segs[seg].ds_addr));
489#endif
490
491 if (segs[seg].ds_len == 0)
492 continue;
493 sc->sc_txdescs[nexttx].gd_addr =
494 GEM_DMA_WRITE(sc, segs[seg].ds_addr);
495 KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE,
496 ("gem_txdma_callback: segment size too large!"));
497 flags = segs[seg].ds_len & GEM_TD_BUFSIZE;
498 if (len == 0) {
499#ifdef GEM_DEBUG
500 CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, "
501 "tx %d", seg, nexttx);
502#endif
503 flags |= GEM_TD_START_OF_PACKET;
504 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
505 sc->sc_txwin = 0;
506 flags |= GEM_TD_INTERRUPT_ME;
507 }
508 }
509 if (len + segs[seg].ds_len == totsz) {
510#ifdef GEM_DEBUG
511 CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, "
512 "tx %d", seg, nexttx);
513#endif
514 flags |= GEM_TD_END_OF_PACKET;
515 }
516 sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags);
517 txs->txs_lastdesc = nexttx;
518 len += segs[seg].ds_len;
519 }
520 KASSERT((flags & GEM_TD_END_OF_PACKET) != 0,
521 ("gem_txdma_callback: missed end of packet!"));
522}
523
524static void
525gem_tick(arg)
526 void *arg;
527{
528 struct gem_softc *sc = arg;
529
530 mii_tick(sc->sc_mii);
531
532 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
533}
534
535static int
536gem_bitwait(sc, r, clr, set)
537 struct gem_softc *sc;
538 bus_addr_t r;
539 u_int32_t clr;
540 u_int32_t set;
541{
542 int i;
543 u_int32_t reg;
544
545 for (i = TRIES; i--; DELAY(100)) {
546 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r);
547 if ((r & clr) == 0 && (r & set) == set)
548 return (1);
549 }
550 return (0);
551}
552
553void
554gem_reset(sc)
555 struct gem_softc *sc;
556{
557 bus_space_tag_t t = sc->sc_bustag;
558 bus_space_handle_t h = sc->sc_h;
559
560#ifdef GEM_DEBUG
561 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
562#endif
563 gem_reset_rx(sc);
564 gem_reset_tx(sc);
565
566 /* Do a full reset */
567 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
568 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
569 device_printf(sc->sc_dev, "cannot reset device\n");
570}
571
572
573/*
574 * gem_rxdrain:
575 *
576 * Drain the receive queue.
577 */
578static void
579gem_rxdrain(sc)
580 struct gem_softc *sc;
581{
582 struct gem_rxsoft *rxs;
583 int i;
584
585 for (i = 0; i < GEM_NRXDESC; i++) {
586 rxs = &sc->sc_rxsoft[i];
587 if (rxs->rxs_mbuf != NULL) {
588 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
589 BUS_DMASYNC_POSTREAD);
590 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
591 m_freem(rxs->rxs_mbuf);
592 rxs->rxs_mbuf = NULL;
593 }
594 }
595}
596
597/*
598 * Reset the whole thing.
599 */
600static void
601gem_stop(ifp, disable)
602 struct ifnet *ifp;
603 int disable;
604{
605 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
606 struct gem_txsoft *txs;
607
608#ifdef GEM_DEBUG
609 CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev));
610#endif
611
612 callout_stop(&sc->sc_tick_ch);
613
614 /* XXX - Should we reset these instead? */
615 gem_disable_tx(sc);
616 gem_disable_rx(sc);
617
618 /*
619 * Release any queued transmit buffers.
620 */
621 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
622 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
623 if (txs->txs_ndescs != 0) {
624 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
625 BUS_DMASYNC_POSTWRITE);
626 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
627 if (txs->txs_mbuf != NULL) {
628 m_freem(txs->txs_mbuf);
629 txs->txs_mbuf = NULL;
630 }
631 }
632 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
633 }
634
635 if (disable)
636 gem_rxdrain(sc);
637
638 /*
639 * Mark the interface down and cancel the watchdog timer.
640 */
641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
642 ifp->if_timer = 0;
643}
644
645/*
646 * Reset the receiver
647 */
648int
649gem_reset_rx(sc)
650 struct gem_softc *sc;
651{
652 bus_space_tag_t t = sc->sc_bustag;
653 bus_space_handle_t h = sc->sc_h;
654
655 /*
656 * Resetting while DMA is in progress can cause a bus hang, so we
657 * disable DMA first.
658 */
659 gem_disable_rx(sc);
660 bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
661 /* Wait till it finishes */
662 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
663 device_printf(sc->sc_dev, "cannot disable read dma\n");
664
665 /* Wait 5ms extra. */
666 DELAY(5000);
667
668 /* Finally, reset the ERX */
669 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
670 /* Wait till it finishes */
671 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
672 device_printf(sc->sc_dev, "cannot reset receiver\n");
673 return (1);
674 }
675 return (0);
676}
677
678
679/*
680 * Reset the transmitter
681 */
682static int
683gem_reset_tx(sc)
684 struct gem_softc *sc;
685{
686 bus_space_tag_t t = sc->sc_bustag;
687 bus_space_handle_t h = sc->sc_h;
688 int i;
689
690 /*
691 * Resetting while DMA is in progress can cause a bus hang, so we
692 * disable DMA first.
693 */
694 gem_disable_tx(sc);
695 bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
696 /* Wait till it finishes */
697 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
698 device_printf(sc->sc_dev, "cannot disable read dma\n");
699
700 /* Wait 5ms extra. */
701 DELAY(5000);
702
703 /* Finally, reset the ETX */
704 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
705 /* Wait till it finishes */
706 for (i = TRIES; i--; DELAY(100))
707 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
708 break;
709 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
710 device_printf(sc->sc_dev, "cannot reset receiver\n");
711 return (1);
712 }
713 return (0);
714}
715
716/*
717 * disable receiver.
718 */
719static int
720gem_disable_rx(sc)
721 struct gem_softc *sc;
722{
723 bus_space_tag_t t = sc->sc_bustag;
724 bus_space_handle_t h = sc->sc_h;
725 u_int32_t cfg;
726
727 /* Flip the enable bit */
728 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
729 cfg &= ~GEM_MAC_RX_ENABLE;
730 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
731
732 /* Wait for it to finish */
733 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
734}
735
736/*
737 * disable transmitter.
738 */
739static int
740gem_disable_tx(sc)
741 struct gem_softc *sc;
742{
743 bus_space_tag_t t = sc->sc_bustag;
744 bus_space_handle_t h = sc->sc_h;
745 u_int32_t cfg;
746
747 /* Flip the enable bit */
748 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
749 cfg &= ~GEM_MAC_TX_ENABLE;
750 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
751
752 /* Wait for it to finish */
753 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
754}
755
756/*
757 * Initialize interface.
758 */
759static int
760gem_meminit(sc)
761 struct gem_softc *sc;
762{
763 struct gem_rxsoft *rxs;
764 int i, error;
765
766 /*
767 * Initialize the transmit descriptor ring.
768 */
769 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
770 for (i = 0; i < GEM_NTXDESC; i++) {
771 sc->sc_txdescs[i].gd_flags = 0;
772 sc->sc_txdescs[i].gd_addr = 0;
773 }
774 sc->sc_txfree = GEM_MAXTXFREE;
775 sc->sc_txnext = 0;
776 sc->sc_txwin = 0;
777
778 /*
779 * Initialize the receive descriptor and receive job
780 * descriptor rings.
781 */
782 for (i = 0; i < GEM_NRXDESC; i++) {
783 rxs = &sc->sc_rxsoft[i];
784 if (rxs->rxs_mbuf == NULL) {
785 if ((error = gem_add_rxbuf(sc, i)) != 0) {
786 device_printf(sc->sc_dev, "unable to "
787 "allocate or map rx buffer %d, error = "
788 "%d\n", i, error);
789 /*
790 * XXX Should attempt to run with fewer receive
791 * XXX buffers instead of just failing.
792 */
793 gem_rxdrain(sc);
794 return (1);
795 }
796 } else
797 GEM_INIT_RXDESC(sc, i);
798 }
799 sc->sc_rxptr = 0;
800 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
801 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
802
803 return (0);
804}
805
806static int
807gem_ringsize(sz)
808 int sz;
809{
810 int v = 0;
811
812 switch (sz) {
813 case 32:
814 v = GEM_RING_SZ_32;
815 break;
816 case 64:
817 v = GEM_RING_SZ_64;
818 break;
819 case 128:
820 v = GEM_RING_SZ_128;
821 break;
822 case 256:
823 v = GEM_RING_SZ_256;
824 break;
825 case 512:
826 v = GEM_RING_SZ_512;
827 break;
828 case 1024:
829 v = GEM_RING_SZ_1024;
830 break;
831 case 2048:
832 v = GEM_RING_SZ_2048;
833 break;
834 case 4096:
835 v = GEM_RING_SZ_4096;
836 break;
837 case 8192:
838 v = GEM_RING_SZ_8192;
839 break;
840 default:
841 printf("gem: invalid Receive Descriptor ring size\n");
842 break;
843 }
844 return (v);
845}
846
847static void
848gem_init(xsc)
849 void *xsc;
850{
851 struct gem_softc *sc = (struct gem_softc *)xsc;
852
853 GEM_LOCK(sc);
854 gem_init_locked(sc);
855 GEM_UNLOCK(sc);
856}
857
858/*
859 * Initialization of interface; set up initialization block
860 * and transmit/receive descriptor rings.
861 */
862static void
863gem_init_locked(sc)
864 struct gem_softc *sc;
865{
866 struct ifnet *ifp = sc->sc_ifp;
867 bus_space_tag_t t = sc->sc_bustag;
868 bus_space_handle_t h = sc->sc_h;
869 u_int32_t v;
870
871 GEM_LOCK_ASSERT(sc, MA_OWNED);
872
873#ifdef GEM_DEBUG
874 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev));
875#endif
876 /*
877 * Initialization sequence. The numbered steps below correspond
878 * to the sequence outlined in section 6.3.5.1 in the Ethernet
879 * Channel Engine manual (part of the PCIO manual).
880 * See also the STP2002-STQ document from Sun Microsystems.
881 */
882
883 /* step 1 & 2. Reset the Ethernet Channel */
884 gem_stop(sc->sc_ifp, 0);
885 gem_reset(sc);
886#ifdef GEM_DEBUG
887 CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev));
888#endif
889
890 /* Re-initialize the MIF */
891 gem_mifinit(sc);
892
893 /* step 3. Setup data structures in host memory */
894 gem_meminit(sc);
895
896 /* step 4. TX MAC registers & counters */
897 gem_init_regs(sc);
898 /* XXX: VLAN code from NetBSD temporarily removed. */
899 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
900 (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16));
901
902 /* step 5. RX MAC registers & counters */
903 gem_setladrf(sc);
904
905 /* step 6 & 7. Program Descriptor Ring Base Addresses */
906 /* NOTE: we use only 32-bit DMA addresses here. */
907 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
908 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
909
910 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
911 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
912#ifdef GEM_DEBUG
913 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
914 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
915#endif
916
917 /* step 8. Global Configuration & Interrupt Mask */
918 bus_space_write_4(t, h, GEM_INTMASK,
919 ~(GEM_INTR_TX_INTME|
920 GEM_INTR_TX_EMPTY|
921 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
922 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
923 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
924 GEM_INTR_BERR));
925 bus_space_write_4(t, h, GEM_MAC_RX_MASK,
926 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
927 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
928 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
929
930 /* step 9. ETX Configuration: use mostly default values */
931
932 /* Enable DMA */
933 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
934 bus_space_write_4(t, h, GEM_TX_CONFIG,
935 v|GEM_TX_CONFIG_TXDMA_EN|
936 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
937
938 /* step 10. ERX Configuration */
939
940 /* Encode Receive Descriptor ring size: four possible values */
941 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
942
943 /* Enable DMA */
944 bus_space_write_4(t, h, GEM_RX_CONFIG,
945 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
946 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
947 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
948 /*
949 * The following value is for an OFF Threshold of about 3/4 full
950 * and an ON Threshold of 1/4 full.
951 */
952 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
953 (3 * sc->sc_rxfifosize / 256) |
954 ( (sc->sc_rxfifosize / 256) << 12));
955 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
956
957 /* step 11. Configure Media */
958 GEM_UNLOCK(sc);
959 mii_mediachg(sc->sc_mii);
960 GEM_LOCK(sc);
961
962 /* step 12. RX_MAC Configuration Register */
963 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
964 v |= GEM_MAC_RX_ENABLE;
965 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
966
967 /* step 14. Issue Transmit Pending command */
968
969 /* step 15. Give the reciever a swift kick */
970 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
971
972 /* Start the one second timer. */
973 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
974
975 ifp->if_flags |= IFF_RUNNING;
976 ifp->if_flags &= ~IFF_OACTIVE;
977 ifp->if_timer = 0;
978 sc->sc_ifflags = ifp->if_flags;
979}
980
981static int
982gem_load_txmbuf(sc, m0)
983 struct gem_softc *sc;
984 struct mbuf *m0;
985{
986 struct gem_txdma txd;
987 struct gem_txsoft *txs;
988 int error;
989
990 /* Get a work queue entry. */
991 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
992 /* Ran out of descriptors. */
993 return (-1);
994 }
995 txd.txd_sc = sc;
996 txd.txd_txs = txs;
997 txs->txs_firstdesc = sc->sc_txnext;
998 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0,
999 gem_txdma_callback, &txd, BUS_DMA_NOWAIT);
1000 if (error != 0)
1001 goto fail;
1002 if (txs->txs_ndescs == -1) {
1003 error = -1;
1004 goto fail;
1005 }
1006
1007 /* Sync the DMA map. */
1008 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1009 BUS_DMASYNC_PREWRITE);
1010
1011#ifdef GEM_DEBUG
1012 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, "
1013 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc,
1014 txs->txs_ndescs);
1015#endif
1016 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1017 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1018 txs->txs_mbuf = m0;
1019
1020 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
1021 sc->sc_txfree -= txs->txs_ndescs;
1022 return (0);
1023
1024fail:
1025#ifdef GEM_DEBUG
1026 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error);
1027#endif
1028 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1029 return (error);
1030}
1031
1032static void
1033gem_init_regs(sc)
1034 struct gem_softc *sc;
1035{
1036 bus_space_tag_t t = sc->sc_bustag;
1037 bus_space_handle_t h = sc->sc_h;
1038 const u_char *laddr = IFP2ENADDR(sc->sc_ifp);
1039 u_int32_t v;
1040
1041 /* These regs are not cleared on reset */
1042 if (!sc->sc_inited) {
1043
1044 /* Wooo. Magic values. */
1045 bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
1046 bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
1047 bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
1048
1049 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1050 /* Max frame and max burst size */
1051 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
1052 ETHER_MAX_LEN | (0x2000<<16));
1053
1054 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
1055 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
1056 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1057 /* Dunno.... */
1058 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
1059 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
1060 ((laddr[5]<<8)|laddr[4])&0x3ff);
1061
1062 /* Secondary MAC addr set to 0:0:0:0:0:0 */
1063 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
1064 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
1065 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
1066
1067 /* MAC control addr set to 01:80:c2:00:00:01 */
1068 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
1069 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
1070 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
1071
1072 /* MAC filter addr set to 0:0:0:0:0:0 */
1073 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
1074 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
1075 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
1076
1077 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
1078 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
1079
1080 sc->sc_inited = 1;
1081 }
1082
1083 /* Counters need to be zeroed */
1084 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
1085 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
1086 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
1087 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
1088 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
1089 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
1090 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
1091 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
1092 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
1093 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
1094 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
1095
1096 /* Un-pause stuff */
1097#if 0
1098 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1099#else
1100 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
1101#endif
1102
1103 /*
1104 * Set the station address.
1105 */
1106 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1107 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1108 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1109
1110 /*
1111 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1112 */
1113 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
1114 v = GEM_MAC_XIF_TX_MII_ENA;
1115 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
1116 v |= GEM_MAC_XIF_FDPLX_LED;
1117 if (sc->sc_flags & GEM_GIGABIT)
1118 v |= GEM_MAC_XIF_GMII_MODE;
1119 }
1120 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
1121}
1122
1123static void
1124gem_start(ifp)
1125 struct ifnet *ifp;
1126{
1127 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1128
1129 GEM_LOCK(sc);
1130 gem_start_locked(ifp);
1131 GEM_UNLOCK(sc);
1132}
1133
1134static void
1135gem_start_locked(ifp)
1136 struct ifnet *ifp;
1137{
1138 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1139 struct mbuf *m0 = NULL;
1140 int firsttx, ntx = 0, ofree, txmfail;
1141
1142 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1143 return;
1144
1145 /*
1146 * Remember the previous number of free descriptors and
1147 * the first descriptor we'll use.
1148 */
1149 ofree = sc->sc_txfree;
1150 firsttx = sc->sc_txnext;
1151
1152#ifdef GEM_DEBUG
1153 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d",
1154 device_get_name(sc->sc_dev), ofree, firsttx);
1155#endif
1156
1157 /*
1158 * Loop through the send queue, setting up transmit descriptors
1159 * until we drain the queue, or use up all available transmit
1160 * descriptors.
1161 */
1162 txmfail = 0;
1163 do {
1164 /*
1165 * Grab a packet off the queue.
1166 */
1167 IF_DEQUEUE(&ifp->if_snd, m0);
1168 if (m0 == NULL)
1169 break;
1170
1171 txmfail = gem_load_txmbuf(sc, m0);
1172 if (txmfail > 0) {
1173 /* Drop the mbuf and complain. */
1174 printf("gem_start: error %d while loading mbuf dma "
1175 "map\n", txmfail);
1176 continue;
1177 }
1178 /* Not enough descriptors. */
1179 if (txmfail == -1) {
1180 if (sc->sc_txfree == GEM_MAXTXFREE)
1181 panic("gem_start: mbuf chain too long!");
1182 IF_PREPEND(&ifp->if_snd, m0);
1183 break;
1184 }
1185
1186 ntx++;
1187 /* Kick the transmitter. */
1188#ifdef GEM_DEBUG
1189 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
1190 device_get_name(sc->sc_dev), sc->sc_txnext);
1191#endif
1192 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK,
1193 sc->sc_txnext);
1194
1195 if (ifp->if_bpf != NULL)
1196 bpf_mtap(ifp->if_bpf, m0);
1197 } while (1);
1198
1199 if (txmfail == -1 || sc->sc_txfree == 0) {
1200 /* No more slots left; notify upper layer. */
1201 ifp->if_flags |= IFF_OACTIVE;
1202 }
1203
1204 if (ntx > 0) {
1205 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1206
1207#ifdef GEM_DEBUG
1208 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1209 device_get_name(sc->sc_dev), firsttx);
1210#endif
1211
1212 /* Set a watchdog timer in case the chip flakes out. */
1213 ifp->if_timer = 5;
1214#ifdef GEM_DEBUG
1215 CTR2(KTR_GEM, "%s: gem_start: watchdog %d",
1216 device_get_name(sc->sc_dev), ifp->if_timer);
1217#endif
1218 }
1219}
1220
1221/*
1222 * Transmit interrupt.
1223 */
1224static void
1225gem_tint(sc)
1226 struct gem_softc *sc;
1227{
1228 struct ifnet *ifp = sc->sc_ifp;
1229 bus_space_tag_t t = sc->sc_bustag;
1230 bus_space_handle_t mac = sc->sc_h;
1231 struct gem_txsoft *txs;
1232 int txlast;
1233 int progress = 0;
1234
1235
1236#ifdef GEM_DEBUG
1237 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev));
1238#endif
1239
1240 /*
1241 * Unload collision counters
1242 */
1243 ifp->if_collisions +=
1244 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
1245 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
1246 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
1247 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
1248
1249 /*
1250 * then clear the hardware counters.
1251 */
1252 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
1253 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
1254 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
1255 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
1256
1257 /*
1258 * Go through our Tx list and free mbufs for those
1259 * frames that have been transmitted.
1260 */
1261 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1262 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1263
1264#ifdef GEM_DEBUG
1265 if (ifp->if_flags & IFF_DEBUG) {
1266 int i;
1267 printf(" txsoft %p transmit chain:\n", txs);
1268 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1269 printf("descriptor %d: ", i);
1270 printf("gd_flags: 0x%016llx\t", (long long)
1271 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
1272 printf("gd_addr: 0x%016llx\n", (long long)
1273 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
1274 if (i == txs->txs_lastdesc)
1275 break;
1276 }
1277 }
1278#endif
1279
1280 /*
1281 * In theory, we could harveast some descriptors before
1282 * the ring is empty, but that's a bit complicated.
1283 *
1284 * GEM_TX_COMPLETION points to the last descriptor
1285 * processed +1.
1286 */
1287 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
1288#ifdef GEM_DEBUG
1289 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
1290 "txs->txs_lastdesc = %d, txlast = %d",
1291 txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1292#endif
1293 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1294 if ((txlast >= txs->txs_firstdesc) &&
1295 (txlast <= txs->txs_lastdesc))
1296 break;
1297 } else {
1298 /* Ick -- this command wraps */
1299 if ((txlast >= txs->txs_firstdesc) ||
1300 (txlast <= txs->txs_lastdesc))
1301 break;
1302 }
1303
1304#ifdef GEM_DEBUG
1305 CTR0(KTR_GEM, "gem_tint: releasing a desc");
1306#endif
1307 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1308
1309 sc->sc_txfree += txs->txs_ndescs;
1310
1311 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1312 BUS_DMASYNC_POSTWRITE);
1313 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1314 if (txs->txs_mbuf != NULL) {
1315 m_freem(txs->txs_mbuf);
1316 txs->txs_mbuf = NULL;
1317 }
1318
1319 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1320
1321 ifp->if_opackets++;
1322 progress = 1;
1323 }
1324
1325#ifdef GEM_DEBUG
1326 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
1327 "GEM_TX_DATA_PTR %llx "
1328 "GEM_TX_COMPLETION %x",
1329 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE),
1330 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h,
1331 GEM_TX_DATA_PTR_HI) << 32) |
1332 bus_space_read_4(sc->sc_bustag, sc->sc_h,
1333 GEM_TX_DATA_PTR_LO),
1334 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
1335#endif
1336
1337 if (progress) {
1338 if (sc->sc_txfree == GEM_NTXDESC - 1)
1339 sc->sc_txwin = 0;
1340
1341 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */
1342 ifp->if_flags &= ~IFF_OACTIVE;
1343 gem_start_locked(ifp);
1344
1345 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1346 ifp->if_timer = 0;
1347 }
1348
1349#ifdef GEM_DEBUG
1350 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d",
1351 device_get_name(sc->sc_dev), ifp->if_timer);
1352#endif
1353}
1354
1355#ifdef GEM_RINT_TIMEOUT
1356static void
1357gem_rint_timeout(arg)
1358 void *arg;
1359{
1360 struct gem_softc *sc = (struct gem_softc *)arg;
1361
1362 GEM_LOCK(sc);
1363 gem_rint(sc);
1364 GEM_UNLOCK(sc);
1365}
1366#endif
1367
1368/*
1369 * Receive interrupt.
1370 */
1371static void
1372gem_rint(sc)
1373 struct gem_softc *sc;
1374{
1375 struct ifnet *ifp = sc->sc_ifp;
1376 bus_space_tag_t t = sc->sc_bustag;
1377 bus_space_handle_t h = sc->sc_h;
1378 struct gem_rxsoft *rxs;
1379 struct mbuf *m;
1380 u_int64_t rxstat;
1381 u_int32_t rxcomp;
1382 int i, len, progress = 0;
1383
1384#ifdef GEM_RINT_TIMEOUT
1385 callout_stop(&sc->sc_rx_ch);
1386#endif
1387#ifdef GEM_DEBUG
1388 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
1389#endif
1390
1391 /*
1392 * Read the completion register once. This limits
1393 * how long the following loop can execute.
1394 */
1395 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
1396
1397#ifdef GEM_DEBUG
1398 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1399 sc->sc_rxptr, rxcomp);
1400#endif
1401 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1402 for (i = sc->sc_rxptr; i != rxcomp;
1403 i = GEM_NEXTRX(i)) {
1404 rxs = &sc->sc_rxsoft[i];
1405
1406 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
1407
1408 if (rxstat & GEM_RD_OWN) {
1409#ifdef GEM_RINT_TIMEOUT
1410 /*
1411 * The descriptor is still marked as owned, although
1412 * it is supposed to have completed. This has been
1413 * observed on some machines. Just exiting here
1414 * might leave the packet sitting around until another
1415 * one arrives to trigger a new interrupt, which is
1416 * generally undesirable, so set up a timeout.
1417 */
1418 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
1419 gem_rint_timeout, sc);
1420#endif
1421 break;
1422 }
1423
1424 progress++;
1425 ifp->if_ipackets++;
1426
1427 if (rxstat & GEM_RD_BAD_CRC) {
1428 ifp->if_ierrors++;
1429 device_printf(sc->sc_dev, "receive error: CRC error\n");
1430 GEM_INIT_RXDESC(sc, i);
1431 continue;
1432 }
1433
1434#ifdef GEM_DEBUG
1435 if (ifp->if_flags & IFF_DEBUG) {
1436 printf(" rxsoft %p descriptor %d: ", rxs, i);
1437 printf("gd_flags: 0x%016llx\t", (long long)
1438 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
1439 printf("gd_addr: 0x%016llx\n", (long long)
1440 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
1441 }
1442#endif
1443
1444 /*
1445 * No errors; receive the packet. Note the Gem
1446 * includes the CRC with every packet.
1447 */
1448 len = GEM_RD_BUFLEN(rxstat);
1449
1450 /*
1451 * Allocate a new mbuf cluster. If that fails, we are
1452 * out of memory, and must drop the packet and recycle
1453 * the buffer that's already attached to this descriptor.
1454 */
1455 m = rxs->rxs_mbuf;
1456 if (gem_add_rxbuf(sc, i) != 0) {
1457 ifp->if_ierrors++;
1458 GEM_INIT_RXDESC(sc, i);
1459 continue;
1460 }
1461 m->m_data += 2; /* We're already off by two */
1462
1463 m->m_pkthdr.rcvif = ifp;
1464 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
1465
1466 /* Pass it on. */
1467 GEM_UNLOCK(sc);
1468 (*ifp->if_input)(ifp, m);
1469 GEM_LOCK(sc);
1470 }
1471
1472 if (progress) {
1473 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1474 /* Update the receive pointer. */
1475 if (i == sc->sc_rxptr) {
1476 device_printf(sc->sc_dev, "rint: ring wrap\n");
1477 }
1478 sc->sc_rxptr = i;
1479 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
1480 }
1481
1482#ifdef GEM_DEBUG
1483 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
1484 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
1485#endif
1486}
1487
1488
1489/*
1490 * gem_add_rxbuf:
1491 *
1492 * Add a receive buffer to the indicated descriptor.
1493 */
1494static int
1495gem_add_rxbuf(sc, idx)
1496 struct gem_softc *sc;
1497 int idx;
1498{
1499 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1500 struct mbuf *m;
1501 bus_dma_segment_t segs[1];
1502 int error, nsegs;
1503
1504 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1505 if (m == NULL)
1506 return (ENOBUFS);
1507 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1508
1509#ifdef GEM_DEBUG
1510 /* bzero the packet to check dma */
1511 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1512#endif
1513
1514 if (rxs->rxs_mbuf != NULL) {
1515 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1516 BUS_DMASYNC_POSTREAD);
1517 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1518 }
1519
1520 rxs->rxs_mbuf = m;
1521
1522 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap,
1523 m, segs, &nsegs, BUS_DMA_NOWAIT);
1524 /* If nsegs is wrong then the stack is corrupt. */
1525 KASSERT(nsegs == 1, ("Too many segments returned!"));
1526 if (error != 0) {
1527 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1528 "%d\n", idx, error);
1529 m_freem(m);
1530 return (ENOBUFS);
1531 }
1532 rxs->rxs_paddr = segs[0].ds_addr;
1533
1534 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1535
1536 GEM_INIT_RXDESC(sc, idx);
1537
1538 return (0);
1539}
1540
1541
1542static void
1543gem_eint(sc, status)
1544 struct gem_softc *sc;
1545 u_int status;
1546{
1547
1548 if ((status & GEM_INTR_MIF) != 0) {
1549 device_printf(sc->sc_dev, "XXXlink status changed\n");
1550 return;
1551 }
1552
1553 device_printf(sc->sc_dev, "status=%x\n", status);
1554}
1555
1556
1557void
1558gem_intr(v)
1559 void *v;
1560{
1561 struct gem_softc *sc = (struct gem_softc *)v;
1562 bus_space_tag_t t = sc->sc_bustag;
1563 bus_space_handle_t seb = sc->sc_h;
1564 u_int32_t status;
1565
1566 GEM_LOCK(sc);
1567 status = bus_space_read_4(t, seb, GEM_STATUS);
1568#ifdef GEM_DEBUG
1569 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
1570 device_get_name(sc->sc_dev), (status>>19),
1571 (u_int)status);
1572#endif
1573
1574 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1575 gem_eint(sc, status);
1576
1577 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1578 gem_tint(sc);
1579
1580 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1581 gem_rint(sc);
1582
1583 /* We should eventually do more than just print out error stats. */
1584 if (status & GEM_INTR_TX_MAC) {
1585 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
1586 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1587 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1588 txstat);
1589 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1590 gem_init_locked(sc);
1591 }
1592 if (status & GEM_INTR_RX_MAC) {
1593 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
1594 if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1595 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
1596 rxstat);
1597 if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0)
1598 gem_init_locked(sc);
1599 }
1600 GEM_UNLOCK(sc);
1601}
1602
1603
1604static void
1605gem_watchdog(ifp)
1606 struct ifnet *ifp;
1607{
1608 struct gem_softc *sc = ifp->if_softc;
1609
1610 GEM_LOCK(sc);
1611#ifdef GEM_DEBUG
1612 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
1613 "GEM_MAC_RX_CONFIG %x",
1614 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
1615 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
1616 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG));
1617 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
1618 "GEM_MAC_TX_CONFIG %x",
1619 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
1620 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS),
1621 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG));
1622#endif
1623
1624 device_printf(sc->sc_dev, "device timeout\n");
1625 ++ifp->if_oerrors;
1626
1627 /* Try to get more packets going. */
1628 gem_init_locked(sc);
1629 GEM_UNLOCK(sc);
1630}
1631
1632/*
1633 * Initialize the MII Management Interface
1634 */
1635static void
1636gem_mifinit(sc)
1637 struct gem_softc *sc;
1638{
1639 bus_space_tag_t t = sc->sc_bustag;
1640 bus_space_handle_t mif = sc->sc_h;
1641
1642 GEM_LOCK_ASSERT(sc, MA_OWNED);
1643
1644 /* Configure the MIF in frame mode */
1645 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1646 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1647 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
1648}
1649
1650/*
1651 * MII interface
1652 *
1653 * The GEM MII interface supports at least three different operating modes:
1654 *
1655 * Bitbang mode is implemented using data, clock and output enable registers.
1656 *
1657 * Frame mode is implemented by loading a complete frame into the frame
1658 * register and polling the valid bit for completion.
1659 *
1660 * Polling mode uses the frame register but completion is indicated by
1661 * an interrupt.
1662 *
1663 */
1664int
1665gem_mii_readreg(dev, phy, reg)
1666 device_t dev;
1667 int phy, reg;
1668{
1669 struct gem_softc *sc = device_get_softc(dev);
1670 bus_space_tag_t t = sc->sc_bustag;
1671 bus_space_handle_t mif = sc->sc_h;
1672 int n;
1673 u_int32_t v;
1674
1675 GEM_LOCK(sc);
1676#ifdef GEM_DEBUG_PHY
1677 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1678#endif
1679
1680#if 0
1681 /* Select the desired PHY in the MIF configuration register */
1682 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1683 /* Clear PHY select bit */
1684 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1685 if (phy == GEM_PHYAD_EXTERNAL)
1686 /* Set PHY select bit to get at external device */
1687 v |= GEM_MIF_CONFIG_PHY_SEL;
1688 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1689#endif
1690
1691 /* Construct the frame command */
1692 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1693 GEM_MIF_FRAME_READ;
1694
1695 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1696 for (n = 0; n < 100; n++) {
1697 DELAY(1);
1698 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1699 if (v & GEM_MIF_FRAME_TA0) {
1700 GEM_UNLOCK(sc);
1701 return (v & GEM_MIF_FRAME_DATA);
1702 }
1703 }
1704
1705 device_printf(sc->sc_dev, "mii_read timeout\n");
1706 GEM_UNLOCK(sc);
1707 return (0);
1708}
1709
1710int
1711gem_mii_writereg(dev, phy, reg, val)
1712 device_t dev;
1713 int phy, reg, val;
1714{
1715 struct gem_softc *sc = device_get_softc(dev);
1716 bus_space_tag_t t = sc->sc_bustag;
1717 bus_space_handle_t mif = sc->sc_h;
1718 int n;
1719 u_int32_t v;
1720
1721 GEM_LOCK(sc);
1722#ifdef GEM_DEBUG_PHY
1723 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
1724#endif
1725
1726#if 0
1727 /* Select the desired PHY in the MIF configuration register */
1728 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1729 /* Clear PHY select bit */
1730 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1731 if (phy == GEM_PHYAD_EXTERNAL)
1732 /* Set PHY select bit to get at external device */
1733 v |= GEM_MIF_CONFIG_PHY_SEL;
1734 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1735#endif
1736 /* Construct the frame command */
1737 v = GEM_MIF_FRAME_WRITE |
1738 (phy << GEM_MIF_PHY_SHIFT) |
1739 (reg << GEM_MIF_REG_SHIFT) |
1740 (val & GEM_MIF_FRAME_DATA);
1741
1742 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1743 for (n = 0; n < 100; n++) {
1744 DELAY(1);
1745 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1746 if (v & GEM_MIF_FRAME_TA0) {
1747 GEM_UNLOCK(sc);
1748 return (1);
1749 }
1750 }
1751
1752 device_printf(sc->sc_dev, "mii_write timeout\n");
1753 GEM_UNLOCK(sc);
1754 return (0);
1755}
1756
1757void
1758gem_mii_statchg(dev)
1759 device_t dev;
1760{
1761 struct gem_softc *sc = device_get_softc(dev);
1762#ifdef GEM_DEBUG
1763 int instance;
1764#endif
1765 bus_space_tag_t t = sc->sc_bustag;
1766 bus_space_handle_t mac = sc->sc_h;
1767 u_int32_t v;
1768
1769 GEM_LOCK(sc);
1770#ifdef GEM_DEBUG
1771 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
1772 if (sc->sc_debug)
1773 printf("gem_mii_statchg: status change: phy = %d\n",
1774 sc->sc_phys[instance]);
1775#endif
1776
1777 /* Set tx full duplex options */
1778 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
1779 DELAY(10000); /* reg must be cleared and delay before changing. */
1780 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1781 GEM_MAC_TX_ENABLE;
1782 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
1783 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
1784 }
1785 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
1786
1787 /* XIF Configuration */
1788 v = GEM_MAC_XIF_LINK_LED;
1789 v |= GEM_MAC_XIF_TX_MII_ENA;
1790
1791 /* If an external transceiver is connected, enable its MII drivers */
1792 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
1793 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1794 /* External MII needs echo disable if half duplex. */
1795 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1796 /* turn on full duplex LED */
1797 v |= GEM_MAC_XIF_FDPLX_LED;
1798 else
1799 /* half duplex -- disable echo */
1800 v |= GEM_MAC_XIF_ECHO_DISABL;
1801
1802 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
1803 v |= GEM_MAC_XIF_GMII_MODE;
1804 else
1805 v &= ~GEM_MAC_XIF_GMII_MODE;
1806 } else {
1807 /* Internal MII needs buf enable */
1808 v |= GEM_MAC_XIF_MII_BUF_ENA;
1809 }
1810 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
1811 GEM_UNLOCK(sc);
1812}
1813
1814int
1815gem_mediachange(ifp)
1816 struct ifnet *ifp;
1817{
1818 struct gem_softc *sc = ifp->if_softc;
1819
1820 /* XXX Add support for serial media. */
1821
1822 return (mii_mediachg(sc->sc_mii));
1823}
1824
1825void
1826gem_mediastatus(ifp, ifmr)
1827 struct ifnet *ifp;
1828 struct ifmediareq *ifmr;
1829{
1830 struct gem_softc *sc = ifp->if_softc;
1831
1832 GEM_LOCK(sc);
1833 if ((ifp->if_flags & IFF_UP) == 0) {
1834 GEM_UNLOCK(sc);
1835 return;
1836 }
1837
1838 GEM_UNLOCK(sc);
1839 mii_pollstat(sc->sc_mii);
1840 GEM_LOCK(sc);
1841 ifmr->ifm_active = sc->sc_mii->mii_media_active;
1842 ifmr->ifm_status = sc->sc_mii->mii_media_status;
1843 GEM_UNLOCK(sc);
1844}
1845
1846/*
1847 * Process an ioctl request.
1848 */
1849static int
1850gem_ioctl(ifp, cmd, data)
1851 struct ifnet *ifp;
1852 u_long cmd;
1853 caddr_t data;
1854{
1855 struct gem_softc *sc = ifp->if_softc;
1856 struct ifreq *ifr = (struct ifreq *)data;
1857 int error = 0;
1858
1859 GEM_LOCK(sc);
1860
1861 switch (cmd) {
1862 case SIOCSIFADDR:
1863 case SIOCGIFADDR:
1864 case SIOCSIFMTU:
1865 GEM_UNLOCK(sc);
1866 error = ether_ioctl(ifp, cmd, data);
1867 GEM_LOCK(sc);
1868 break;
1869 case SIOCSIFFLAGS:
1870 if (ifp->if_flags & IFF_UP) {
1871 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC)
1872 gem_setladrf(sc);
1873 else
1874 gem_init_locked(sc);
1875 } else {
1876 if (ifp->if_flags & IFF_RUNNING)
1877 gem_stop(ifp, 0);
1878 }
1879 sc->sc_ifflags = ifp->if_flags;
1880 error = 0;
1881 break;
1882 case SIOCADDMULTI:
1883 case SIOCDELMULTI:
1884 gem_setladrf(sc);
1885 error = 0;
1886 break;
1887 case SIOCGIFMEDIA:
1888 case SIOCSIFMEDIA:
1889 GEM_UNLOCK(sc);
1890 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
1891 GEM_LOCK(sc);
1892 break;
1893 default:
1894 error = ENOTTY;
1895 break;
1896 }
1897
1898 /* Try to get things going again */
1899 if (ifp->if_flags & IFF_UP)
1900 gem_start_locked(ifp);
1901 GEM_UNLOCK(sc);
1902 return (error);
1903}
1904
1905/*
1906 * Set up the logical address filter.
1907 */
1908static void
1909gem_setladrf(sc)
1910 struct gem_softc *sc;
1911{
1912 struct ifnet *ifp = sc->sc_ifp;
1913 struct ifmultiaddr *inm;
1914 bus_space_tag_t t = sc->sc_bustag;
1915 bus_space_handle_t h = sc->sc_h;
1916 u_int32_t crc;
1917 u_int32_t hash[16];
1918 u_int32_t v;
1919 int i;
1920
1921 GEM_LOCK_ASSERT(sc, MA_OWNED);
1922
1923 /* Get current RX configuration */
1924 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
1925
1926 /*
1927 * Turn off promiscuous mode, promiscuous group mode (all multicast),
1928 * and hash filter. Depending on the case, the right bit will be
1929 * enabled.
1930 */
1931 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
1932 GEM_MAC_RX_PROMISC_GRP);
1933
1934 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1935 /* Turn on promiscuous mode */
1936 v |= GEM_MAC_RX_PROMISCUOUS;
1937 goto chipit;
1938 }
1939 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
1940 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1941 ifp->if_flags |= IFF_ALLMULTI;
1942 v |= GEM_MAC_RX_PROMISC_GRP;
1943 goto chipit;
1944 }
1945
1946 /*
1947 * Set up multicast address filter by passing all multicast addresses
1948 * through a crc generator, and then using the high order 8 bits as an
1949 * index into the 256 bit logical address filter. The high order 4
1950 * bits selects the word, while the other 4 bits select the bit within
1951 * the word (where bit 0 is the MSB).
1952 */
1953
1954 /* Clear hash table */
1955 memset(hash, 0, sizeof(hash));
1956
| 32
33/*
34 * Driver for Sun GEM ethernet controllers.
35 */
36
37#if 0
38#define GEM_DEBUG
39#endif
40
41#if 0 /* XXX: In case of emergency, re-enable this. */
42#define GEM_RINT_TIMEOUT
43#endif
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48#include <sys/callout.h>
49#include <sys/endian.h>
50#include <sys/mbuf.h>
51#include <sys/malloc.h>
52#include <sys/kernel.h>
53#include <sys/lock.h>
54#include <sys/module.h>
55#include <sys/mutex.h>
56#include <sys/socket.h>
57#include <sys/sockio.h>
58
59#include <net/bpf.h>
60#include <net/ethernet.h>
61#include <net/if.h>
62#include <net/if_arp.h>
63#include <net/if_dl.h>
64#include <net/if_media.h>
65#include <net/if_types.h>
66
67#include <machine/bus.h>
68
69#include <dev/mii/mii.h>
70#include <dev/mii/miivar.h>
71
72#include <dev/gem/if_gemreg.h>
73#include <dev/gem/if_gemvar.h>
74
75#define TRIES 10000
76
77static void gem_start(struct ifnet *);
78static void gem_start_locked(struct ifnet *);
79static void gem_stop(struct ifnet *, int);
80static int gem_ioctl(struct ifnet *, u_long, caddr_t);
81static void gem_cddma_callback(void *, bus_dma_segment_t *, int, int);
82static void gem_txdma_callback(void *, bus_dma_segment_t *, int,
83 bus_size_t, int);
84static void gem_tick(void *);
85static void gem_watchdog(struct ifnet *);
86static void gem_init(void *);
87static void gem_init_locked(struct gem_softc *sc);
88static void gem_init_regs(struct gem_softc *sc);
89static int gem_ringsize(int sz);
90static int gem_meminit(struct gem_softc *);
91static int gem_load_txmbuf(struct gem_softc *, struct mbuf *);
92static void gem_mifinit(struct gem_softc *);
93static int gem_bitwait(struct gem_softc *sc, bus_addr_t r,
94 u_int32_t clr, u_int32_t set);
95static int gem_reset_rx(struct gem_softc *);
96static int gem_reset_tx(struct gem_softc *);
97static int gem_disable_rx(struct gem_softc *);
98static int gem_disable_tx(struct gem_softc *);
99static void gem_rxdrain(struct gem_softc *);
100static int gem_add_rxbuf(struct gem_softc *, int);
101static void gem_setladrf(struct gem_softc *);
102
103struct mbuf *gem_get(struct gem_softc *, int, int);
104static void gem_eint(struct gem_softc *, u_int);
105static void gem_rint(struct gem_softc *);
106#ifdef GEM_RINT_TIMEOUT
107static void gem_rint_timeout(void *);
108#endif
109static void gem_tint(struct gem_softc *);
110#ifdef notyet
111static void gem_power(int, void *);
112#endif
113
114devclass_t gem_devclass;
115DRIVER_MODULE(miibus, gem, miibus_driver, miibus_devclass, 0, 0);
116MODULE_DEPEND(gem, miibus, 1, 1, 1);
117
118#ifdef GEM_DEBUG
119#include <sys/ktr.h>
120#define KTR_GEM KTR_CT2
121#endif
122
123#define GEM_NSEGS GEM_NTXDESC
124
125/*
126 * gem_attach:
127 *
128 * Attach a Gem interface to the system.
129 */
130int
131gem_attach(sc)
132 struct gem_softc *sc;
133{
134 struct ifnet *ifp;
135 struct mii_softc *child;
136 int i, error;
137 u_int32_t v;
138
139 GEM_LOCK_ASSERT(sc, MA_NOTOWNED);
140
141 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
142 if (ifp == NULL)
143 return (ENOSPC);
144
145 /* Make sure the chip is stopped. */
146 ifp->if_softc = sc;
147 GEM_LOCK(sc);
148 gem_reset(sc);
149 GEM_UNLOCK(sc);
150
151 error = bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
152 BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, GEM_NSEGS,
153 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &sc->sc_pdmatag);
154 if (error)
155 goto fail_ifnet;
156
157 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
158 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MAXBSIZE,
159 1, BUS_SPACE_MAXSIZE_32BIT, BUS_DMA_ALLOCNOW, NULL, NULL,
160 &sc->sc_rdmatag);
161 if (error)
162 goto fail_ptag;
163
164 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
165 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
166 GEM_TD_BUFSIZE, GEM_NTXDESC, BUS_SPACE_MAXSIZE_32BIT,
167 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
168 if (error)
169 goto fail_rtag;
170
171 error = bus_dma_tag_create(sc->sc_pdmatag, PAGE_SIZE, 0,
172 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
173 sizeof(struct gem_control_data), 1,
174 sizeof(struct gem_control_data), BUS_DMA_ALLOCNOW,
175 busdma_lock_mutex, &Giant, &sc->sc_cdmatag);
176 if (error)
177 goto fail_ttag;
178
179 /*
180 * Allocate the control data structures, and create and load the
181 * DMA map for it.
182 */
183 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
184 (void **)&sc->sc_control_data, 0, &sc->sc_cddmamap))) {
185 device_printf(sc->sc_dev, "unable to allocate control data,"
186 " error = %d\n", error);
187 goto fail_ctag;
188 }
189
190 sc->sc_cddma = 0;
191 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
192 sc->sc_control_data, sizeof(struct gem_control_data),
193 gem_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
194 device_printf(sc->sc_dev, "unable to load control data DMA "
195 "map, error = %d\n", error);
196 goto fail_cmem;
197 }
198
199 /*
200 * Initialize the transmit job descriptors.
201 */
202 STAILQ_INIT(&sc->sc_txfreeq);
203 STAILQ_INIT(&sc->sc_txdirtyq);
204
205 /*
206 * Create the transmit buffer DMA maps.
207 */
208 error = ENOMEM;
209 for (i = 0; i < GEM_TXQUEUELEN; i++) {
210 struct gem_txsoft *txs;
211
212 txs = &sc->sc_txsoft[i];
213 txs->txs_mbuf = NULL;
214 txs->txs_ndescs = 0;
215 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
216 &txs->txs_dmamap)) != 0) {
217 device_printf(sc->sc_dev, "unable to create tx DMA map "
218 "%d, error = %d\n", i, error);
219 goto fail_txd;
220 }
221 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
222 }
223
224 /*
225 * Create the receive buffer DMA maps.
226 */
227 for (i = 0; i < GEM_NRXDESC; i++) {
228 if ((error = bus_dmamap_create(sc->sc_rdmatag, 0,
229 &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
230 device_printf(sc->sc_dev, "unable to create rx DMA map "
231 "%d, error = %d\n", i, error);
232 goto fail_rxd;
233 }
234 sc->sc_rxsoft[i].rxs_mbuf = NULL;
235 }
236
237 GEM_LOCK(sc);
238 gem_mifinit(sc);
239 GEM_UNLOCK(sc);
240
241 if ((error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, gem_mediachange,
242 gem_mediastatus)) != 0) {
243 device_printf(sc->sc_dev, "phy probe failed: %d\n", error);
244 goto fail_rxd;
245 }
246 sc->sc_mii = device_get_softc(sc->sc_miibus);
247
248 /*
249 * From this point forward, the attachment cannot fail. A failure
250 * before this point releases all resources that may have been
251 * allocated.
252 */
253
254 /* Get RX FIFO size */
255 sc->sc_rxfifosize = 64 *
256 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
257
258 /* Get TX FIFO size */
259 v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
260 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
261 sc->sc_rxfifosize / 1024, v / 16);
262
263 /* Initialize ifnet structure. */
264 ifp->if_softc = sc;
265 if_initname(ifp, device_get_name(sc->sc_dev),
266 device_get_unit(sc->sc_dev));
267 ifp->if_mtu = ETHERMTU;
268 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
269 ifp->if_start = gem_start;
270 ifp->if_ioctl = gem_ioctl;
271 ifp->if_watchdog = gem_watchdog;
272 ifp->if_init = gem_init;
273 ifp->if_snd.ifq_maxlen = GEM_TXQUEUELEN;
274 /*
275 * Walk along the list of attached MII devices and
276 * establish an `MII instance' to `phy number'
277 * mapping. We'll use this mapping in media change
278 * requests to determine which phy to use to program
279 * the MIF configuration register.
280 */
281 for (child = LIST_FIRST(&sc->sc_mii->mii_phys); child != NULL;
282 child = LIST_NEXT(child, mii_list)) {
283 /*
284 * Note: we support just two PHYs: the built-in
285 * internal device and an external on the MII
286 * connector.
287 */
288 if (child->mii_phy > 1 || child->mii_inst > 1) {
289 device_printf(sc->sc_dev, "cannot accomodate "
290 "MII device %s at phy %d, instance %d\n",
291 device_get_name(child->mii_dev),
292 child->mii_phy, child->mii_inst);
293 continue;
294 }
295
296 sc->sc_phys[child->mii_inst] = child->mii_phy;
297 }
298
299 /*
300 * Now select and activate the PHY we will use.
301 *
302 * The order of preference is External (MDI1),
303 * Internal (MDI0), Serial Link (no MII).
304 */
305 if (sc->sc_phys[1]) {
306#ifdef GEM_DEBUG
307 printf("using external phy\n");
308#endif
309 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
310 } else {
311#ifdef GEM_DEBUG
312 printf("using internal phy\n");
313#endif
314 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
315 }
316 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
317 sc->sc_mif_config);
318 /* Attach the interface. */
319 ether_ifattach(ifp, sc->sc_enaddr);
320
321#if notyet
322 /*
323 * Add a suspend hook to make sure we come back up after a
324 * resume.
325 */
326 sc->sc_powerhook = powerhook_establish(gem_power, sc);
327 if (sc->sc_powerhook == NULL)
328 device_printf(sc->sc_dev, "WARNING: unable to establish power "
329 "hook\n");
330#endif
331
332 callout_init(&sc->sc_tick_ch, CALLOUT_MPSAFE);
333#ifdef GEM_RINT_TIMEOUT
334 callout_init(&sc->sc_rx_ch, CALLOUT_MPSAFE);
335#endif
336 return (0);
337
338 /*
339 * Free any resources we've allocated during the failed attach
340 * attempt. Do this in reverse order and fall through.
341 */
342fail_rxd:
343 for (i = 0; i < GEM_NRXDESC; i++) {
344 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
345 bus_dmamap_destroy(sc->sc_rdmatag,
346 sc->sc_rxsoft[i].rxs_dmamap);
347 }
348fail_txd:
349 for (i = 0; i < GEM_TXQUEUELEN; i++) {
350 if (sc->sc_txsoft[i].txs_dmamap != NULL)
351 bus_dmamap_destroy(sc->sc_tdmatag,
352 sc->sc_txsoft[i].txs_dmamap);
353 }
354 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
355fail_cmem:
356 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
357 sc->sc_cddmamap);
358fail_ctag:
359 bus_dma_tag_destroy(sc->sc_cdmatag);
360fail_ttag:
361 bus_dma_tag_destroy(sc->sc_tdmatag);
362fail_rtag:
363 bus_dma_tag_destroy(sc->sc_rdmatag);
364fail_ptag:
365 bus_dma_tag_destroy(sc->sc_pdmatag);
366fail_ifnet:
367 if_free(ifp);
368 return (error);
369}
370
371void
372gem_detach(sc)
373 struct gem_softc *sc;
374{
375 struct ifnet *ifp = sc->sc_ifp;
376 int i;
377
378 GEM_LOCK_ASSERT(sc, MA_NOTOWNED);
379
380 GEM_LOCK(sc);
381 gem_stop(ifp, 1);
382 GEM_UNLOCK(sc);
383 ether_ifdetach(ifp);
384 if_free(ifp);
385 device_delete_child(sc->sc_dev, sc->sc_miibus);
386
387 for (i = 0; i < GEM_NRXDESC; i++) {
388 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
389 bus_dmamap_destroy(sc->sc_rdmatag,
390 sc->sc_rxsoft[i].rxs_dmamap);
391 }
392 for (i = 0; i < GEM_TXQUEUELEN; i++) {
393 if (sc->sc_txsoft[i].txs_dmamap != NULL)
394 bus_dmamap_destroy(sc->sc_tdmatag,
395 sc->sc_txsoft[i].txs_dmamap);
396 }
397 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
398 GEM_CDSYNC(sc, BUS_DMASYNC_POSTWRITE);
399 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
400 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
401 sc->sc_cddmamap);
402 bus_dma_tag_destroy(sc->sc_cdmatag);
403 bus_dma_tag_destroy(sc->sc_tdmatag);
404 bus_dma_tag_destroy(sc->sc_rdmatag);
405 bus_dma_tag_destroy(sc->sc_pdmatag);
406}
407
408void
409gem_suspend(sc)
410 struct gem_softc *sc;
411{
412 struct ifnet *ifp = sc->sc_ifp;
413
414 GEM_LOCK(sc);
415 gem_stop(ifp, 0);
416 GEM_UNLOCK(sc);
417}
418
419void
420gem_resume(sc)
421 struct gem_softc *sc;
422{
423 struct ifnet *ifp = sc->sc_ifp;
424
425 GEM_LOCK(sc);
426 if (ifp->if_flags & IFF_UP)
427 gem_init_locked(sc);
428 GEM_UNLOCK(sc);
429}
430
431static void
432gem_cddma_callback(xsc, segs, nsegs, error)
433 void *xsc;
434 bus_dma_segment_t *segs;
435 int nsegs;
436 int error;
437{
438 struct gem_softc *sc = (struct gem_softc *)xsc;
439
440 if (error != 0)
441 return;
442 if (nsegs != 1) {
443 /* can't happen... */
444 panic("gem_cddma_callback: bad control buffer segment count");
445 }
446 sc->sc_cddma = segs[0].ds_addr;
447}
448
449static void
450gem_txdma_callback(xsc, segs, nsegs, totsz, error)
451 void *xsc;
452 bus_dma_segment_t *segs;
453 int nsegs;
454 bus_size_t totsz;
455 int error;
456{
457 struct gem_txdma *txd = (struct gem_txdma *)xsc;
458 struct gem_softc *sc = txd->txd_sc;
459 struct gem_txsoft *txs = txd->txd_txs;
460 bus_size_t len = 0;
461 uint64_t flags = 0;
462 int seg, nexttx;
463
464 if (error != 0)
465 return;
466 /*
467 * Ensure we have enough descriptors free to describe
468 * the packet. Note, we always reserve one descriptor
469 * at the end of the ring as a termination point, to
470 * prevent wrap-around.
471 */
472 if (nsegs > sc->sc_txfree - 1) {
473 txs->txs_ndescs = -1;
474 return;
475 }
476 txs->txs_ndescs = nsegs;
477
478 nexttx = txs->txs_firstdesc;
479 /*
480 * Initialize the transmit descriptors.
481 */
482 for (seg = 0; seg < nsegs;
483 seg++, nexttx = GEM_NEXTTX(nexttx)) {
484#ifdef GEM_DEBUG
485 CTR5(KTR_GEM, "txdma_cb: mapping seg %d (txd %d), len "
486 "%lx, addr %#lx (%#lx)", seg, nexttx,
487 segs[seg].ds_len, segs[seg].ds_addr,
488 GEM_DMA_WRITE(sc, segs[seg].ds_addr));
489#endif
490
491 if (segs[seg].ds_len == 0)
492 continue;
493 sc->sc_txdescs[nexttx].gd_addr =
494 GEM_DMA_WRITE(sc, segs[seg].ds_addr);
495 KASSERT(segs[seg].ds_len < GEM_TD_BUFSIZE,
496 ("gem_txdma_callback: segment size too large!"));
497 flags = segs[seg].ds_len & GEM_TD_BUFSIZE;
498 if (len == 0) {
499#ifdef GEM_DEBUG
500 CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, "
501 "tx %d", seg, nexttx);
502#endif
503 flags |= GEM_TD_START_OF_PACKET;
504 if (++sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
505 sc->sc_txwin = 0;
506 flags |= GEM_TD_INTERRUPT_ME;
507 }
508 }
509 if (len + segs[seg].ds_len == totsz) {
510#ifdef GEM_DEBUG
511 CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, "
512 "tx %d", seg, nexttx);
513#endif
514 flags |= GEM_TD_END_OF_PACKET;
515 }
516 sc->sc_txdescs[nexttx].gd_flags = GEM_DMA_WRITE(sc, flags);
517 txs->txs_lastdesc = nexttx;
518 len += segs[seg].ds_len;
519 }
520 KASSERT((flags & GEM_TD_END_OF_PACKET) != 0,
521 ("gem_txdma_callback: missed end of packet!"));
522}
523
524static void
525gem_tick(arg)
526 void *arg;
527{
528 struct gem_softc *sc = arg;
529
530 mii_tick(sc->sc_mii);
531
532 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
533}
534
535static int
536gem_bitwait(sc, r, clr, set)
537 struct gem_softc *sc;
538 bus_addr_t r;
539 u_int32_t clr;
540 u_int32_t set;
541{
542 int i;
543 u_int32_t reg;
544
545 for (i = TRIES; i--; DELAY(100)) {
546 reg = bus_space_read_4(sc->sc_bustag, sc->sc_h, r);
547 if ((r & clr) == 0 && (r & set) == set)
548 return (1);
549 }
550 return (0);
551}
552
553void
554gem_reset(sc)
555 struct gem_softc *sc;
556{
557 bus_space_tag_t t = sc->sc_bustag;
558 bus_space_handle_t h = sc->sc_h;
559
560#ifdef GEM_DEBUG
561 CTR1(KTR_GEM, "%s: gem_reset", device_get_name(sc->sc_dev));
562#endif
563 gem_reset_rx(sc);
564 gem_reset_tx(sc);
565
566 /* Do a full reset */
567 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX);
568 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_RX | GEM_RESET_TX, 0))
569 device_printf(sc->sc_dev, "cannot reset device\n");
570}
571
572
573/*
574 * gem_rxdrain:
575 *
576 * Drain the receive queue.
577 */
578static void
579gem_rxdrain(sc)
580 struct gem_softc *sc;
581{
582 struct gem_rxsoft *rxs;
583 int i;
584
585 for (i = 0; i < GEM_NRXDESC; i++) {
586 rxs = &sc->sc_rxsoft[i];
587 if (rxs->rxs_mbuf != NULL) {
588 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
589 BUS_DMASYNC_POSTREAD);
590 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
591 m_freem(rxs->rxs_mbuf);
592 rxs->rxs_mbuf = NULL;
593 }
594 }
595}
596
597/*
598 * Reset the whole thing.
599 */
600static void
601gem_stop(ifp, disable)
602 struct ifnet *ifp;
603 int disable;
604{
605 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
606 struct gem_txsoft *txs;
607
608#ifdef GEM_DEBUG
609 CTR1(KTR_GEM, "%s: gem_stop", device_get_name(sc->sc_dev));
610#endif
611
612 callout_stop(&sc->sc_tick_ch);
613
614 /* XXX - Should we reset these instead? */
615 gem_disable_tx(sc);
616 gem_disable_rx(sc);
617
618 /*
619 * Release any queued transmit buffers.
620 */
621 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
622 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
623 if (txs->txs_ndescs != 0) {
624 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
625 BUS_DMASYNC_POSTWRITE);
626 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
627 if (txs->txs_mbuf != NULL) {
628 m_freem(txs->txs_mbuf);
629 txs->txs_mbuf = NULL;
630 }
631 }
632 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
633 }
634
635 if (disable)
636 gem_rxdrain(sc);
637
638 /*
639 * Mark the interface down and cancel the watchdog timer.
640 */
641 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
642 ifp->if_timer = 0;
643}
644
645/*
646 * Reset the receiver
647 */
648int
649gem_reset_rx(sc)
650 struct gem_softc *sc;
651{
652 bus_space_tag_t t = sc->sc_bustag;
653 bus_space_handle_t h = sc->sc_h;
654
655 /*
656 * Resetting while DMA is in progress can cause a bus hang, so we
657 * disable DMA first.
658 */
659 gem_disable_rx(sc);
660 bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
661 /* Wait till it finishes */
662 if (!gem_bitwait(sc, GEM_RX_CONFIG, 1, 0))
663 device_printf(sc->sc_dev, "cannot disable read dma\n");
664
665 /* Wait 5ms extra. */
666 DELAY(5000);
667
668 /* Finally, reset the ERX */
669 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
670 /* Wait till it finishes */
671 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
672 device_printf(sc->sc_dev, "cannot reset receiver\n");
673 return (1);
674 }
675 return (0);
676}
677
678
679/*
680 * Reset the transmitter
681 */
682static int
683gem_reset_tx(sc)
684 struct gem_softc *sc;
685{
686 bus_space_tag_t t = sc->sc_bustag;
687 bus_space_handle_t h = sc->sc_h;
688 int i;
689
690 /*
691 * Resetting while DMA is in progress can cause a bus hang, so we
692 * disable DMA first.
693 */
694 gem_disable_tx(sc);
695 bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
696 /* Wait till it finishes */
697 if (!gem_bitwait(sc, GEM_TX_CONFIG, 1, 0))
698 device_printf(sc->sc_dev, "cannot disable read dma\n");
699
700 /* Wait 5ms extra. */
701 DELAY(5000);
702
703 /* Finally, reset the ETX */
704 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
705 /* Wait till it finishes */
706 for (i = TRIES; i--; DELAY(100))
707 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
708 break;
709 if (!gem_bitwait(sc, GEM_RESET, GEM_RESET_TX, 0)) {
710 device_printf(sc->sc_dev, "cannot reset receiver\n");
711 return (1);
712 }
713 return (0);
714}
715
716/*
717 * disable receiver.
718 */
719static int
720gem_disable_rx(sc)
721 struct gem_softc *sc;
722{
723 bus_space_tag_t t = sc->sc_bustag;
724 bus_space_handle_t h = sc->sc_h;
725 u_int32_t cfg;
726
727 /* Flip the enable bit */
728 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
729 cfg &= ~GEM_MAC_RX_ENABLE;
730 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
731
732 /* Wait for it to finish */
733 return (gem_bitwait(sc, GEM_MAC_RX_CONFIG, GEM_MAC_RX_ENABLE, 0));
734}
735
736/*
737 * disable transmitter.
738 */
739static int
740gem_disable_tx(sc)
741 struct gem_softc *sc;
742{
743 bus_space_tag_t t = sc->sc_bustag;
744 bus_space_handle_t h = sc->sc_h;
745 u_int32_t cfg;
746
747 /* Flip the enable bit */
748 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
749 cfg &= ~GEM_MAC_TX_ENABLE;
750 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
751
752 /* Wait for it to finish */
753 return (gem_bitwait(sc, GEM_MAC_TX_CONFIG, GEM_MAC_TX_ENABLE, 0));
754}
755
756/*
757 * Initialize interface.
758 */
759static int
760gem_meminit(sc)
761 struct gem_softc *sc;
762{
763 struct gem_rxsoft *rxs;
764 int i, error;
765
766 /*
767 * Initialize the transmit descriptor ring.
768 */
769 memset((void *)sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
770 for (i = 0; i < GEM_NTXDESC; i++) {
771 sc->sc_txdescs[i].gd_flags = 0;
772 sc->sc_txdescs[i].gd_addr = 0;
773 }
774 sc->sc_txfree = GEM_MAXTXFREE;
775 sc->sc_txnext = 0;
776 sc->sc_txwin = 0;
777
778 /*
779 * Initialize the receive descriptor and receive job
780 * descriptor rings.
781 */
782 for (i = 0; i < GEM_NRXDESC; i++) {
783 rxs = &sc->sc_rxsoft[i];
784 if (rxs->rxs_mbuf == NULL) {
785 if ((error = gem_add_rxbuf(sc, i)) != 0) {
786 device_printf(sc->sc_dev, "unable to "
787 "allocate or map rx buffer %d, error = "
788 "%d\n", i, error);
789 /*
790 * XXX Should attempt to run with fewer receive
791 * XXX buffers instead of just failing.
792 */
793 gem_rxdrain(sc);
794 return (1);
795 }
796 } else
797 GEM_INIT_RXDESC(sc, i);
798 }
799 sc->sc_rxptr = 0;
800 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
801 GEM_CDSYNC(sc, BUS_DMASYNC_PREREAD);
802
803 return (0);
804}
805
806static int
807gem_ringsize(sz)
808 int sz;
809{
810 int v = 0;
811
812 switch (sz) {
813 case 32:
814 v = GEM_RING_SZ_32;
815 break;
816 case 64:
817 v = GEM_RING_SZ_64;
818 break;
819 case 128:
820 v = GEM_RING_SZ_128;
821 break;
822 case 256:
823 v = GEM_RING_SZ_256;
824 break;
825 case 512:
826 v = GEM_RING_SZ_512;
827 break;
828 case 1024:
829 v = GEM_RING_SZ_1024;
830 break;
831 case 2048:
832 v = GEM_RING_SZ_2048;
833 break;
834 case 4096:
835 v = GEM_RING_SZ_4096;
836 break;
837 case 8192:
838 v = GEM_RING_SZ_8192;
839 break;
840 default:
841 printf("gem: invalid Receive Descriptor ring size\n");
842 break;
843 }
844 return (v);
845}
846
847static void
848gem_init(xsc)
849 void *xsc;
850{
851 struct gem_softc *sc = (struct gem_softc *)xsc;
852
853 GEM_LOCK(sc);
854 gem_init_locked(sc);
855 GEM_UNLOCK(sc);
856}
857
858/*
859 * Initialization of interface; set up initialization block
860 * and transmit/receive descriptor rings.
861 */
862static void
863gem_init_locked(sc)
864 struct gem_softc *sc;
865{
866 struct ifnet *ifp = sc->sc_ifp;
867 bus_space_tag_t t = sc->sc_bustag;
868 bus_space_handle_t h = sc->sc_h;
869 u_int32_t v;
870
871 GEM_LOCK_ASSERT(sc, MA_OWNED);
872
873#ifdef GEM_DEBUG
874 CTR1(KTR_GEM, "%s: gem_init: calling stop", device_get_name(sc->sc_dev));
875#endif
876 /*
877 * Initialization sequence. The numbered steps below correspond
878 * to the sequence outlined in section 6.3.5.1 in the Ethernet
879 * Channel Engine manual (part of the PCIO manual).
880 * See also the STP2002-STQ document from Sun Microsystems.
881 */
882
883 /* step 1 & 2. Reset the Ethernet Channel */
884 gem_stop(sc->sc_ifp, 0);
885 gem_reset(sc);
886#ifdef GEM_DEBUG
887 CTR1(KTR_GEM, "%s: gem_init: restarting", device_get_name(sc->sc_dev));
888#endif
889
890 /* Re-initialize the MIF */
891 gem_mifinit(sc);
892
893 /* step 3. Setup data structures in host memory */
894 gem_meminit(sc);
895
896 /* step 4. TX MAC registers & counters */
897 gem_init_regs(sc);
898 /* XXX: VLAN code from NetBSD temporarily removed. */
899 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
900 (ETHER_MAX_LEN + sizeof(struct ether_header)) | (0x2000<<16));
901
902 /* step 5. RX MAC registers & counters */
903 gem_setladrf(sc);
904
905 /* step 6 & 7. Program Descriptor Ring Base Addresses */
906 /* NOTE: we use only 32-bit DMA addresses here. */
907 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI, 0);
908 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
909
910 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI, 0);
911 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
912#ifdef GEM_DEBUG
913 CTR3(KTR_GEM, "loading rx ring %lx, tx ring %lx, cddma %lx",
914 GEM_CDRXADDR(sc, 0), GEM_CDTXADDR(sc, 0), sc->sc_cddma);
915#endif
916
917 /* step 8. Global Configuration & Interrupt Mask */
918 bus_space_write_4(t, h, GEM_INTMASK,
919 ~(GEM_INTR_TX_INTME|
920 GEM_INTR_TX_EMPTY|
921 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
922 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
923 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
924 GEM_INTR_BERR));
925 bus_space_write_4(t, h, GEM_MAC_RX_MASK,
926 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
927 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
928 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
929
930 /* step 9. ETX Configuration: use mostly default values */
931
932 /* Enable DMA */
933 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
934 bus_space_write_4(t, h, GEM_TX_CONFIG,
935 v|GEM_TX_CONFIG_TXDMA_EN|
936 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
937
938 /* step 10. ERX Configuration */
939
940 /* Encode Receive Descriptor ring size: four possible values */
941 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
942
943 /* Enable DMA */
944 bus_space_write_4(t, h, GEM_RX_CONFIG,
945 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
946 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
947 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
948 /*
949 * The following value is for an OFF Threshold of about 3/4 full
950 * and an ON Threshold of 1/4 full.
951 */
952 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
953 (3 * sc->sc_rxfifosize / 256) |
954 ( (sc->sc_rxfifosize / 256) << 12));
955 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
956
957 /* step 11. Configure Media */
958 GEM_UNLOCK(sc);
959 mii_mediachg(sc->sc_mii);
960 GEM_LOCK(sc);
961
962 /* step 12. RX_MAC Configuration Register */
963 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
964 v |= GEM_MAC_RX_ENABLE;
965 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
966
967 /* step 14. Issue Transmit Pending command */
968
969 /* step 15. Give the reciever a swift kick */
970 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
971
972 /* Start the one second timer. */
973 callout_reset(&sc->sc_tick_ch, hz, gem_tick, sc);
974
975 ifp->if_flags |= IFF_RUNNING;
976 ifp->if_flags &= ~IFF_OACTIVE;
977 ifp->if_timer = 0;
978 sc->sc_ifflags = ifp->if_flags;
979}
980
981static int
982gem_load_txmbuf(sc, m0)
983 struct gem_softc *sc;
984 struct mbuf *m0;
985{
986 struct gem_txdma txd;
987 struct gem_txsoft *txs;
988 int error;
989
990 /* Get a work queue entry. */
991 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
992 /* Ran out of descriptors. */
993 return (-1);
994 }
995 txd.txd_sc = sc;
996 txd.txd_txs = txs;
997 txs->txs_firstdesc = sc->sc_txnext;
998 error = bus_dmamap_load_mbuf(sc->sc_tdmatag, txs->txs_dmamap, m0,
999 gem_txdma_callback, &txd, BUS_DMA_NOWAIT);
1000 if (error != 0)
1001 goto fail;
1002 if (txs->txs_ndescs == -1) {
1003 error = -1;
1004 goto fail;
1005 }
1006
1007 /* Sync the DMA map. */
1008 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1009 BUS_DMASYNC_PREWRITE);
1010
1011#ifdef GEM_DEBUG
1012 CTR3(KTR_GEM, "load_mbuf: setting firstdesc=%d, lastdesc=%d, "
1013 "ndescs=%d", txs->txs_firstdesc, txs->txs_lastdesc,
1014 txs->txs_ndescs);
1015#endif
1016 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1017 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1018 txs->txs_mbuf = m0;
1019
1020 sc->sc_txnext = GEM_NEXTTX(txs->txs_lastdesc);
1021 sc->sc_txfree -= txs->txs_ndescs;
1022 return (0);
1023
1024fail:
1025#ifdef GEM_DEBUG
1026 CTR1(KTR_GEM, "gem_load_txmbuf failed (%d)", error);
1027#endif
1028 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1029 return (error);
1030}
1031
1032static void
1033gem_init_regs(sc)
1034 struct gem_softc *sc;
1035{
1036 bus_space_tag_t t = sc->sc_bustag;
1037 bus_space_handle_t h = sc->sc_h;
1038 const u_char *laddr = IFP2ENADDR(sc->sc_ifp);
1039 u_int32_t v;
1040
1041 /* These regs are not cleared on reset */
1042 if (!sc->sc_inited) {
1043
1044 /* Wooo. Magic values. */
1045 bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
1046 bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
1047 bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
1048
1049 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
1050 /* Max frame and max burst size */
1051 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
1052 ETHER_MAX_LEN | (0x2000<<16));
1053
1054 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
1055 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
1056 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
1057 /* Dunno.... */
1058 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
1059 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
1060 ((laddr[5]<<8)|laddr[4])&0x3ff);
1061
1062 /* Secondary MAC addr set to 0:0:0:0:0:0 */
1063 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
1064 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
1065 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
1066
1067 /* MAC control addr set to 01:80:c2:00:00:01 */
1068 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
1069 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
1070 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
1071
1072 /* MAC filter addr set to 0:0:0:0:0:0 */
1073 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
1074 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
1075 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
1076
1077 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
1078 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
1079
1080 sc->sc_inited = 1;
1081 }
1082
1083 /* Counters need to be zeroed */
1084 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
1085 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
1086 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
1087 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
1088 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
1089 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
1090 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
1091 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
1092 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
1093 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
1094 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
1095
1096 /* Un-pause stuff */
1097#if 0
1098 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0x1BF0);
1099#else
1100 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
1101#endif
1102
1103 /*
1104 * Set the station address.
1105 */
1106 bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
1107 bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
1108 bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
1109
1110 /*
1111 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1112 */
1113 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
1114 v = GEM_MAC_XIF_TX_MII_ENA;
1115 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
1116 v |= GEM_MAC_XIF_FDPLX_LED;
1117 if (sc->sc_flags & GEM_GIGABIT)
1118 v |= GEM_MAC_XIF_GMII_MODE;
1119 }
1120 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
1121}
1122
1123static void
1124gem_start(ifp)
1125 struct ifnet *ifp;
1126{
1127 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1128
1129 GEM_LOCK(sc);
1130 gem_start_locked(ifp);
1131 GEM_UNLOCK(sc);
1132}
1133
1134static void
1135gem_start_locked(ifp)
1136 struct ifnet *ifp;
1137{
1138 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
1139 struct mbuf *m0 = NULL;
1140 int firsttx, ntx = 0, ofree, txmfail;
1141
1142 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1143 return;
1144
1145 /*
1146 * Remember the previous number of free descriptors and
1147 * the first descriptor we'll use.
1148 */
1149 ofree = sc->sc_txfree;
1150 firsttx = sc->sc_txnext;
1151
1152#ifdef GEM_DEBUG
1153 CTR3(KTR_GEM, "%s: gem_start: txfree %d, txnext %d",
1154 device_get_name(sc->sc_dev), ofree, firsttx);
1155#endif
1156
1157 /*
1158 * Loop through the send queue, setting up transmit descriptors
1159 * until we drain the queue, or use up all available transmit
1160 * descriptors.
1161 */
1162 txmfail = 0;
1163 do {
1164 /*
1165 * Grab a packet off the queue.
1166 */
1167 IF_DEQUEUE(&ifp->if_snd, m0);
1168 if (m0 == NULL)
1169 break;
1170
1171 txmfail = gem_load_txmbuf(sc, m0);
1172 if (txmfail > 0) {
1173 /* Drop the mbuf and complain. */
1174 printf("gem_start: error %d while loading mbuf dma "
1175 "map\n", txmfail);
1176 continue;
1177 }
1178 /* Not enough descriptors. */
1179 if (txmfail == -1) {
1180 if (sc->sc_txfree == GEM_MAXTXFREE)
1181 panic("gem_start: mbuf chain too long!");
1182 IF_PREPEND(&ifp->if_snd, m0);
1183 break;
1184 }
1185
1186 ntx++;
1187 /* Kick the transmitter. */
1188#ifdef GEM_DEBUG
1189 CTR2(KTR_GEM, "%s: gem_start: kicking tx %d",
1190 device_get_name(sc->sc_dev), sc->sc_txnext);
1191#endif
1192 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK,
1193 sc->sc_txnext);
1194
1195 if (ifp->if_bpf != NULL)
1196 bpf_mtap(ifp->if_bpf, m0);
1197 } while (1);
1198
1199 if (txmfail == -1 || sc->sc_txfree == 0) {
1200 /* No more slots left; notify upper layer. */
1201 ifp->if_flags |= IFF_OACTIVE;
1202 }
1203
1204 if (ntx > 0) {
1205 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1206
1207#ifdef GEM_DEBUG
1208 CTR2(KTR_GEM, "%s: packets enqueued, OWN on %d",
1209 device_get_name(sc->sc_dev), firsttx);
1210#endif
1211
1212 /* Set a watchdog timer in case the chip flakes out. */
1213 ifp->if_timer = 5;
1214#ifdef GEM_DEBUG
1215 CTR2(KTR_GEM, "%s: gem_start: watchdog %d",
1216 device_get_name(sc->sc_dev), ifp->if_timer);
1217#endif
1218 }
1219}
1220
1221/*
1222 * Transmit interrupt.
1223 */
1224static void
1225gem_tint(sc)
1226 struct gem_softc *sc;
1227{
1228 struct ifnet *ifp = sc->sc_ifp;
1229 bus_space_tag_t t = sc->sc_bustag;
1230 bus_space_handle_t mac = sc->sc_h;
1231 struct gem_txsoft *txs;
1232 int txlast;
1233 int progress = 0;
1234
1235
1236#ifdef GEM_DEBUG
1237 CTR1(KTR_GEM, "%s: gem_tint", device_get_name(sc->sc_dev));
1238#endif
1239
1240 /*
1241 * Unload collision counters
1242 */
1243 ifp->if_collisions +=
1244 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
1245 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
1246 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
1247 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
1248
1249 /*
1250 * then clear the hardware counters.
1251 */
1252 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
1253 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
1254 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
1255 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
1256
1257 /*
1258 * Go through our Tx list and free mbufs for those
1259 * frames that have been transmitted.
1260 */
1261 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1262 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1263
1264#ifdef GEM_DEBUG
1265 if (ifp->if_flags & IFF_DEBUG) {
1266 int i;
1267 printf(" txsoft %p transmit chain:\n", txs);
1268 for (i = txs->txs_firstdesc;; i = GEM_NEXTTX(i)) {
1269 printf("descriptor %d: ", i);
1270 printf("gd_flags: 0x%016llx\t", (long long)
1271 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_flags));
1272 printf("gd_addr: 0x%016llx\n", (long long)
1273 GEM_DMA_READ(sc, sc->sc_txdescs[i].gd_addr));
1274 if (i == txs->txs_lastdesc)
1275 break;
1276 }
1277 }
1278#endif
1279
1280 /*
1281 * In theory, we could harveast some descriptors before
1282 * the ring is empty, but that's a bit complicated.
1283 *
1284 * GEM_TX_COMPLETION points to the last descriptor
1285 * processed +1.
1286 */
1287 txlast = bus_space_read_4(t, mac, GEM_TX_COMPLETION);
1288#ifdef GEM_DEBUG
1289 CTR3(KTR_GEM, "gem_tint: txs->txs_firstdesc = %d, "
1290 "txs->txs_lastdesc = %d, txlast = %d",
1291 txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1292#endif
1293 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1294 if ((txlast >= txs->txs_firstdesc) &&
1295 (txlast <= txs->txs_lastdesc))
1296 break;
1297 } else {
1298 /* Ick -- this command wraps */
1299 if ((txlast >= txs->txs_firstdesc) ||
1300 (txlast <= txs->txs_lastdesc))
1301 break;
1302 }
1303
1304#ifdef GEM_DEBUG
1305 CTR0(KTR_GEM, "gem_tint: releasing a desc");
1306#endif
1307 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1308
1309 sc->sc_txfree += txs->txs_ndescs;
1310
1311 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1312 BUS_DMASYNC_POSTWRITE);
1313 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1314 if (txs->txs_mbuf != NULL) {
1315 m_freem(txs->txs_mbuf);
1316 txs->txs_mbuf = NULL;
1317 }
1318
1319 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1320
1321 ifp->if_opackets++;
1322 progress = 1;
1323 }
1324
1325#ifdef GEM_DEBUG
1326 CTR3(KTR_GEM, "gem_tint: GEM_TX_STATE_MACHINE %x "
1327 "GEM_TX_DATA_PTR %llx "
1328 "GEM_TX_COMPLETION %x",
1329 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_STATE_MACHINE),
1330 ((long long) bus_space_read_4(sc->sc_bustag, sc->sc_h,
1331 GEM_TX_DATA_PTR_HI) << 32) |
1332 bus_space_read_4(sc->sc_bustag, sc->sc_h,
1333 GEM_TX_DATA_PTR_LO),
1334 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
1335#endif
1336
1337 if (progress) {
1338 if (sc->sc_txfree == GEM_NTXDESC - 1)
1339 sc->sc_txwin = 0;
1340
1341 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */
1342 ifp->if_flags &= ~IFF_OACTIVE;
1343 gem_start_locked(ifp);
1344
1345 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1346 ifp->if_timer = 0;
1347 }
1348
1349#ifdef GEM_DEBUG
1350 CTR2(KTR_GEM, "%s: gem_tint: watchdog %d",
1351 device_get_name(sc->sc_dev), ifp->if_timer);
1352#endif
1353}
1354
1355#ifdef GEM_RINT_TIMEOUT
1356static void
1357gem_rint_timeout(arg)
1358 void *arg;
1359{
1360 struct gem_softc *sc = (struct gem_softc *)arg;
1361
1362 GEM_LOCK(sc);
1363 gem_rint(sc);
1364 GEM_UNLOCK(sc);
1365}
1366#endif
1367
1368/*
1369 * Receive interrupt.
1370 */
1371static void
1372gem_rint(sc)
1373 struct gem_softc *sc;
1374{
1375 struct ifnet *ifp = sc->sc_ifp;
1376 bus_space_tag_t t = sc->sc_bustag;
1377 bus_space_handle_t h = sc->sc_h;
1378 struct gem_rxsoft *rxs;
1379 struct mbuf *m;
1380 u_int64_t rxstat;
1381 u_int32_t rxcomp;
1382 int i, len, progress = 0;
1383
1384#ifdef GEM_RINT_TIMEOUT
1385 callout_stop(&sc->sc_rx_ch);
1386#endif
1387#ifdef GEM_DEBUG
1388 CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
1389#endif
1390
1391 /*
1392 * Read the completion register once. This limits
1393 * how long the following loop can execute.
1394 */
1395 rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
1396
1397#ifdef GEM_DEBUG
1398 CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
1399 sc->sc_rxptr, rxcomp);
1400#endif
1401 GEM_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1402 for (i = sc->sc_rxptr; i != rxcomp;
1403 i = GEM_NEXTRX(i)) {
1404 rxs = &sc->sc_rxsoft[i];
1405
1406 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
1407
1408 if (rxstat & GEM_RD_OWN) {
1409#ifdef GEM_RINT_TIMEOUT
1410 /*
1411 * The descriptor is still marked as owned, although
1412 * it is supposed to have completed. This has been
1413 * observed on some machines. Just exiting here
1414 * might leave the packet sitting around until another
1415 * one arrives to trigger a new interrupt, which is
1416 * generally undesirable, so set up a timeout.
1417 */
1418 callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
1419 gem_rint_timeout, sc);
1420#endif
1421 break;
1422 }
1423
1424 progress++;
1425 ifp->if_ipackets++;
1426
1427 if (rxstat & GEM_RD_BAD_CRC) {
1428 ifp->if_ierrors++;
1429 device_printf(sc->sc_dev, "receive error: CRC error\n");
1430 GEM_INIT_RXDESC(sc, i);
1431 continue;
1432 }
1433
1434#ifdef GEM_DEBUG
1435 if (ifp->if_flags & IFF_DEBUG) {
1436 printf(" rxsoft %p descriptor %d: ", rxs, i);
1437 printf("gd_flags: 0x%016llx\t", (long long)
1438 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
1439 printf("gd_addr: 0x%016llx\n", (long long)
1440 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
1441 }
1442#endif
1443
1444 /*
1445 * No errors; receive the packet. Note the Gem
1446 * includes the CRC with every packet.
1447 */
1448 len = GEM_RD_BUFLEN(rxstat);
1449
1450 /*
1451 * Allocate a new mbuf cluster. If that fails, we are
1452 * out of memory, and must drop the packet and recycle
1453 * the buffer that's already attached to this descriptor.
1454 */
1455 m = rxs->rxs_mbuf;
1456 if (gem_add_rxbuf(sc, i) != 0) {
1457 ifp->if_ierrors++;
1458 GEM_INIT_RXDESC(sc, i);
1459 continue;
1460 }
1461 m->m_data += 2; /* We're already off by two */
1462
1463 m->m_pkthdr.rcvif = ifp;
1464 m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
1465
1466 /* Pass it on. */
1467 GEM_UNLOCK(sc);
1468 (*ifp->if_input)(ifp, m);
1469 GEM_LOCK(sc);
1470 }
1471
1472 if (progress) {
1473 GEM_CDSYNC(sc, BUS_DMASYNC_PREWRITE);
1474 /* Update the receive pointer. */
1475 if (i == sc->sc_rxptr) {
1476 device_printf(sc->sc_dev, "rint: ring wrap\n");
1477 }
1478 sc->sc_rxptr = i;
1479 bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
1480 }
1481
1482#ifdef GEM_DEBUG
1483 CTR2(KTR_GEM, "gem_rint: done sc->rxptr %d, complete %d",
1484 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
1485#endif
1486}
1487
1488
1489/*
1490 * gem_add_rxbuf:
1491 *
1492 * Add a receive buffer to the indicated descriptor.
1493 */
1494static int
1495gem_add_rxbuf(sc, idx)
1496 struct gem_softc *sc;
1497 int idx;
1498{
1499 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1500 struct mbuf *m;
1501 bus_dma_segment_t segs[1];
1502 int error, nsegs;
1503
1504 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1505 if (m == NULL)
1506 return (ENOBUFS);
1507 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1508
1509#ifdef GEM_DEBUG
1510 /* bzero the packet to check dma */
1511 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1512#endif
1513
1514 if (rxs->rxs_mbuf != NULL) {
1515 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap,
1516 BUS_DMASYNC_POSTREAD);
1517 bus_dmamap_unload(sc->sc_rdmatag, rxs->rxs_dmamap);
1518 }
1519
1520 rxs->rxs_mbuf = m;
1521
1522 error = bus_dmamap_load_mbuf_sg(sc->sc_rdmatag, rxs->rxs_dmamap,
1523 m, segs, &nsegs, BUS_DMA_NOWAIT);
1524 /* If nsegs is wrong then the stack is corrupt. */
1525 KASSERT(nsegs == 1, ("Too many segments returned!"));
1526 if (error != 0) {
1527 device_printf(sc->sc_dev, "can't load rx DMA map %d, error = "
1528 "%d\n", idx, error);
1529 m_freem(m);
1530 return (ENOBUFS);
1531 }
1532 rxs->rxs_paddr = segs[0].ds_addr;
1533
1534 bus_dmamap_sync(sc->sc_rdmatag, rxs->rxs_dmamap, BUS_DMASYNC_PREREAD);
1535
1536 GEM_INIT_RXDESC(sc, idx);
1537
1538 return (0);
1539}
1540
1541
1542static void
1543gem_eint(sc, status)
1544 struct gem_softc *sc;
1545 u_int status;
1546{
1547
1548 if ((status & GEM_INTR_MIF) != 0) {
1549 device_printf(sc->sc_dev, "XXXlink status changed\n");
1550 return;
1551 }
1552
1553 device_printf(sc->sc_dev, "status=%x\n", status);
1554}
1555
1556
1557void
1558gem_intr(v)
1559 void *v;
1560{
1561 struct gem_softc *sc = (struct gem_softc *)v;
1562 bus_space_tag_t t = sc->sc_bustag;
1563 bus_space_handle_t seb = sc->sc_h;
1564 u_int32_t status;
1565
1566 GEM_LOCK(sc);
1567 status = bus_space_read_4(t, seb, GEM_STATUS);
1568#ifdef GEM_DEBUG
1569 CTR3(KTR_GEM, "%s: gem_intr: cplt %x, status %x",
1570 device_get_name(sc->sc_dev), (status>>19),
1571 (u_int)status);
1572#endif
1573
1574 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1575 gem_eint(sc, status);
1576
1577 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1578 gem_tint(sc);
1579
1580 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1581 gem_rint(sc);
1582
1583 /* We should eventually do more than just print out error stats. */
1584 if (status & GEM_INTR_TX_MAC) {
1585 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
1586 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1587 device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
1588 txstat);
1589 if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
1590 gem_init_locked(sc);
1591 }
1592 if (status & GEM_INTR_RX_MAC) {
1593 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
1594 if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
1595 device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
1596 rxstat);
1597 if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0)
1598 gem_init_locked(sc);
1599 }
1600 GEM_UNLOCK(sc);
1601}
1602
1603
1604static void
1605gem_watchdog(ifp)
1606 struct ifnet *ifp;
1607{
1608 struct gem_softc *sc = ifp->if_softc;
1609
1610 GEM_LOCK(sc);
1611#ifdef GEM_DEBUG
1612 CTR3(KTR_GEM, "gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
1613 "GEM_MAC_RX_CONFIG %x",
1614 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
1615 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
1616 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG));
1617 CTR3(KTR_GEM, "gem_watchdog: GEM_TX_CONFIG %x GEM_MAC_TX_STATUS %x "
1618 "GEM_MAC_TX_CONFIG %x",
1619 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_CONFIG),
1620 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_STATUS),
1621 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_TX_CONFIG));
1622#endif
1623
1624 device_printf(sc->sc_dev, "device timeout\n");
1625 ++ifp->if_oerrors;
1626
1627 /* Try to get more packets going. */
1628 gem_init_locked(sc);
1629 GEM_UNLOCK(sc);
1630}
1631
1632/*
1633 * Initialize the MII Management Interface
1634 */
1635static void
1636gem_mifinit(sc)
1637 struct gem_softc *sc;
1638{
1639 bus_space_tag_t t = sc->sc_bustag;
1640 bus_space_handle_t mif = sc->sc_h;
1641
1642 GEM_LOCK_ASSERT(sc, MA_OWNED);
1643
1644 /* Configure the MIF in frame mode */
1645 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1646 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1647 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
1648}
1649
1650/*
1651 * MII interface
1652 *
1653 * The GEM MII interface supports at least three different operating modes:
1654 *
1655 * Bitbang mode is implemented using data, clock and output enable registers.
1656 *
1657 * Frame mode is implemented by loading a complete frame into the frame
1658 * register and polling the valid bit for completion.
1659 *
1660 * Polling mode uses the frame register but completion is indicated by
1661 * an interrupt.
1662 *
1663 */
1664int
1665gem_mii_readreg(dev, phy, reg)
1666 device_t dev;
1667 int phy, reg;
1668{
1669 struct gem_softc *sc = device_get_softc(dev);
1670 bus_space_tag_t t = sc->sc_bustag;
1671 bus_space_handle_t mif = sc->sc_h;
1672 int n;
1673 u_int32_t v;
1674
1675 GEM_LOCK(sc);
1676#ifdef GEM_DEBUG_PHY
1677 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1678#endif
1679
1680#if 0
1681 /* Select the desired PHY in the MIF configuration register */
1682 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1683 /* Clear PHY select bit */
1684 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1685 if (phy == GEM_PHYAD_EXTERNAL)
1686 /* Set PHY select bit to get at external device */
1687 v |= GEM_MIF_CONFIG_PHY_SEL;
1688 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1689#endif
1690
1691 /* Construct the frame command */
1692 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1693 GEM_MIF_FRAME_READ;
1694
1695 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1696 for (n = 0; n < 100; n++) {
1697 DELAY(1);
1698 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1699 if (v & GEM_MIF_FRAME_TA0) {
1700 GEM_UNLOCK(sc);
1701 return (v & GEM_MIF_FRAME_DATA);
1702 }
1703 }
1704
1705 device_printf(sc->sc_dev, "mii_read timeout\n");
1706 GEM_UNLOCK(sc);
1707 return (0);
1708}
1709
1710int
1711gem_mii_writereg(dev, phy, reg, val)
1712 device_t dev;
1713 int phy, reg, val;
1714{
1715 struct gem_softc *sc = device_get_softc(dev);
1716 bus_space_tag_t t = sc->sc_bustag;
1717 bus_space_handle_t mif = sc->sc_h;
1718 int n;
1719 u_int32_t v;
1720
1721 GEM_LOCK(sc);
1722#ifdef GEM_DEBUG_PHY
1723 printf("gem_mii_writereg: phy %d reg %d val %x\n", phy, reg, val);
1724#endif
1725
1726#if 0
1727 /* Select the desired PHY in the MIF configuration register */
1728 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1729 /* Clear PHY select bit */
1730 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1731 if (phy == GEM_PHYAD_EXTERNAL)
1732 /* Set PHY select bit to get at external device */
1733 v |= GEM_MIF_CONFIG_PHY_SEL;
1734 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1735#endif
1736 /* Construct the frame command */
1737 v = GEM_MIF_FRAME_WRITE |
1738 (phy << GEM_MIF_PHY_SHIFT) |
1739 (reg << GEM_MIF_REG_SHIFT) |
1740 (val & GEM_MIF_FRAME_DATA);
1741
1742 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1743 for (n = 0; n < 100; n++) {
1744 DELAY(1);
1745 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1746 if (v & GEM_MIF_FRAME_TA0) {
1747 GEM_UNLOCK(sc);
1748 return (1);
1749 }
1750 }
1751
1752 device_printf(sc->sc_dev, "mii_write timeout\n");
1753 GEM_UNLOCK(sc);
1754 return (0);
1755}
1756
1757void
1758gem_mii_statchg(dev)
1759 device_t dev;
1760{
1761 struct gem_softc *sc = device_get_softc(dev);
1762#ifdef GEM_DEBUG
1763 int instance;
1764#endif
1765 bus_space_tag_t t = sc->sc_bustag;
1766 bus_space_handle_t mac = sc->sc_h;
1767 u_int32_t v;
1768
1769 GEM_LOCK(sc);
1770#ifdef GEM_DEBUG
1771 instance = IFM_INST(sc->sc_mii->mii_media.ifm_cur->ifm_media);
1772 if (sc->sc_debug)
1773 printf("gem_mii_statchg: status change: phy = %d\n",
1774 sc->sc_phys[instance]);
1775#endif
1776
1777 /* Set tx full duplex options */
1778 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
1779 DELAY(10000); /* reg must be cleared and delay before changing. */
1780 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1781 GEM_MAC_TX_ENABLE;
1782 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) {
1783 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
1784 }
1785 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
1786
1787 /* XIF Configuration */
1788 v = GEM_MAC_XIF_LINK_LED;
1789 v |= GEM_MAC_XIF_TX_MII_ENA;
1790
1791 /* If an external transceiver is connected, enable its MII drivers */
1792 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
1793 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1794 /* External MII needs echo disable if half duplex. */
1795 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
1796 /* turn on full duplex LED */
1797 v |= GEM_MAC_XIF_FDPLX_LED;
1798 else
1799 /* half duplex -- disable echo */
1800 v |= GEM_MAC_XIF_ECHO_DISABL;
1801
1802 if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
1803 v |= GEM_MAC_XIF_GMII_MODE;
1804 else
1805 v &= ~GEM_MAC_XIF_GMII_MODE;
1806 } else {
1807 /* Internal MII needs buf enable */
1808 v |= GEM_MAC_XIF_MII_BUF_ENA;
1809 }
1810 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
1811 GEM_UNLOCK(sc);
1812}
1813
1814int
1815gem_mediachange(ifp)
1816 struct ifnet *ifp;
1817{
1818 struct gem_softc *sc = ifp->if_softc;
1819
1820 /* XXX Add support for serial media. */
1821
1822 return (mii_mediachg(sc->sc_mii));
1823}
1824
1825void
1826gem_mediastatus(ifp, ifmr)
1827 struct ifnet *ifp;
1828 struct ifmediareq *ifmr;
1829{
1830 struct gem_softc *sc = ifp->if_softc;
1831
1832 GEM_LOCK(sc);
1833 if ((ifp->if_flags & IFF_UP) == 0) {
1834 GEM_UNLOCK(sc);
1835 return;
1836 }
1837
1838 GEM_UNLOCK(sc);
1839 mii_pollstat(sc->sc_mii);
1840 GEM_LOCK(sc);
1841 ifmr->ifm_active = sc->sc_mii->mii_media_active;
1842 ifmr->ifm_status = sc->sc_mii->mii_media_status;
1843 GEM_UNLOCK(sc);
1844}
1845
1846/*
1847 * Process an ioctl request.
1848 */
1849static int
1850gem_ioctl(ifp, cmd, data)
1851 struct ifnet *ifp;
1852 u_long cmd;
1853 caddr_t data;
1854{
1855 struct gem_softc *sc = ifp->if_softc;
1856 struct ifreq *ifr = (struct ifreq *)data;
1857 int error = 0;
1858
1859 GEM_LOCK(sc);
1860
1861 switch (cmd) {
1862 case SIOCSIFADDR:
1863 case SIOCGIFADDR:
1864 case SIOCSIFMTU:
1865 GEM_UNLOCK(sc);
1866 error = ether_ioctl(ifp, cmd, data);
1867 GEM_LOCK(sc);
1868 break;
1869 case SIOCSIFFLAGS:
1870 if (ifp->if_flags & IFF_UP) {
1871 if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC)
1872 gem_setladrf(sc);
1873 else
1874 gem_init_locked(sc);
1875 } else {
1876 if (ifp->if_flags & IFF_RUNNING)
1877 gem_stop(ifp, 0);
1878 }
1879 sc->sc_ifflags = ifp->if_flags;
1880 error = 0;
1881 break;
1882 case SIOCADDMULTI:
1883 case SIOCDELMULTI:
1884 gem_setladrf(sc);
1885 error = 0;
1886 break;
1887 case SIOCGIFMEDIA:
1888 case SIOCSIFMEDIA:
1889 GEM_UNLOCK(sc);
1890 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
1891 GEM_LOCK(sc);
1892 break;
1893 default:
1894 error = ENOTTY;
1895 break;
1896 }
1897
1898 /* Try to get things going again */
1899 if (ifp->if_flags & IFF_UP)
1900 gem_start_locked(ifp);
1901 GEM_UNLOCK(sc);
1902 return (error);
1903}
1904
1905/*
1906 * Set up the logical address filter.
1907 */
1908static void
1909gem_setladrf(sc)
1910 struct gem_softc *sc;
1911{
1912 struct ifnet *ifp = sc->sc_ifp;
1913 struct ifmultiaddr *inm;
1914 bus_space_tag_t t = sc->sc_bustag;
1915 bus_space_handle_t h = sc->sc_h;
1916 u_int32_t crc;
1917 u_int32_t hash[16];
1918 u_int32_t v;
1919 int i;
1920
1921 GEM_LOCK_ASSERT(sc, MA_OWNED);
1922
1923 /* Get current RX configuration */
1924 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
1925
1926 /*
1927 * Turn off promiscuous mode, promiscuous group mode (all multicast),
1928 * and hash filter. Depending on the case, the right bit will be
1929 * enabled.
1930 */
1931 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
1932 GEM_MAC_RX_PROMISC_GRP);
1933
1934 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1935 /* Turn on promiscuous mode */
1936 v |= GEM_MAC_RX_PROMISCUOUS;
1937 goto chipit;
1938 }
1939 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
1940 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1941 ifp->if_flags |= IFF_ALLMULTI;
1942 v |= GEM_MAC_RX_PROMISC_GRP;
1943 goto chipit;
1944 }
1945
1946 /*
1947 * Set up multicast address filter by passing all multicast addresses
1948 * through a crc generator, and then using the high order 8 bits as an
1949 * index into the 256 bit logical address filter. The high order 4
1950 * bits selects the word, while the other 4 bits select the bit within
1951 * the word (where bit 0 is the MSB).
1952 */
1953
1954 /* Clear hash table */
1955 memset(hash, 0, sizeof(hash));
1956
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