1/* 2 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the acknowledgement as bellow: 15 * 16 * This product includes software developed by K. Kobayashi and H. Shimokawa 17 * 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 *
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33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108530 2003-01-01 08:25:32Z simokawa $
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33 * $FreeBSD: head/sys/dev/firewire/fwohci.c 108642 2003-01-04 06:40:57Z simokawa $ |
34 * 35 */ 36 37#define ATRQ_CH 0 38#define ATRS_CH 1 39#define ARRQ_CH 2 40#define ARRS_CH 3 41#define ITX_CH 4 42#define IRX_CH 0x24 43 44#include <sys/param.h> 45#include <sys/systm.h> 46#include <sys/types.h> 47#include <sys/mbuf.h> 48#include <sys/mman.h> 49#include <sys/socket.h> 50#include <sys/socketvar.h> 51#include <sys/signalvar.h> 52#include <sys/malloc.h> 53#include <sys/uio.h> 54#include <sys/sockio.h> 55#include <sys/bus.h> 56#include <sys/kernel.h> 57#include <sys/conf.h> 58 59#include <machine/bus.h> 60#include <machine/resource.h> 61#include <sys/rman.h> 62 63#include <machine/cpufunc.h> /* for rdtsc proto for clock.h below */ 64#include <machine/clock.h> 65#include <pci/pcivar.h> 66#include <pci/pcireg.h> 67#include <vm/vm.h> 68#include <vm/vm_extern.h> 69#include <vm/pmap.h> /* for vtophys proto */ 70 71#include <dev/firewire/firewire.h> 72#include <dev/firewire/firewirebusreg.h> 73#include <dev/firewire/firewirereg.h> 74#include <dev/firewire/fwohcireg.h> 75#include <dev/firewire/fwohcivar.h> 76#include <dev/firewire/firewire_phy.h> 77 78#undef OHCI_DEBUG 79 80static char dbcode[16][0x10]={"OUTM", "OUTL","INPM","INPL", 81 "STOR","LOAD","NOP ","STOP",}; 82static char dbkey[8][0x10]={"ST0", "ST1","ST2","ST3", 83 "UNDEF","REG","SYS","DEV"}; 84char fwohcicode[32][0x20]={ 85 "No stat","Undef","long","miss Ack err", 86 "underrun","overrun","desc err", "data read err", 87 "data write err","bus reset","timeout","tcode err", 88 "Undef","Undef","unknown event","flushed", 89 "Undef","ack complete","ack pend","Undef", 90 "ack busy_X","ack busy_A","ack busy_B","Undef", 91 "Undef","Undef","Undef","ack tardy", 92 "Undef","ack data_err","ack type_err",""}; 93#define MAX_SPEED 2 94extern char linkspeed[MAX_SPEED+1][0x10]; 95extern int maxrec[MAX_SPEED+1]; 96static char dbcond[4][0x10]={"NEV","C=1", "C=0", "ALL"}; 97u_int32_t tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31}; 98 99static struct tcode_info tinfo[] = { 100/* hdr_len block flag*/ 101/* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL}, 102/* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 103/* 2 WRES */ {12, FWTI_RES}, 104/* 3 XXX */ { 0, 0}, 105/* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL}, 106/* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL}, 107/* 6 RRESQ */ {16, FWTI_RES}, 108/* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 109/* 8 CYCS */ { 0, 0}, 110/* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY}, 111/* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR}, 112/* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY}, 113/* c XXX */ { 0, 0}, 114/* d XXX */ { 0, 0}, 115/* e PHY */ {12, FWTI_REQ}, 116/* f XXX */ { 0, 0} 117}; 118 119#define OHCI_WRITE_SIGMASK 0xffff0000 120#define OHCI_READ_SIGMASK 0xffff0000 121 122#define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x)) 123#define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r)) 124 125static void fwohci_ibr __P((struct firewire_comm *)); 126static void fwohci_db_init __P((struct fwohci_dbch *)); 127static void fwohci_db_free __P((struct fwohci_dbch *)); 128static void fwohci_arcv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 129static void fwohci_ircv __P((struct fwohci_softc *, struct fwohci_dbch *, int)); 130static void fwohci_txd __P((struct fwohci_softc *, struct fwohci_dbch *)); 131static void fwohci_start_atq __P((struct firewire_comm *)); 132static void fwohci_start_ats __P((struct firewire_comm *)); 133static void fwohci_start __P((struct fwohci_softc *, struct fwohci_dbch *)); 134static void fwohci_drain_atq __P((struct firewire_comm *, struct fw_xfer *)); 135static void fwohci_drain_ats __P((struct firewire_comm *, struct fw_xfer *)); 136static void fwohci_drain __P((struct firewire_comm *, struct fw_xfer *, struct fwohci_dbch *)); 137static u_int32_t fwphy_wrdata __P(( struct fwohci_softc *, u_int32_t, u_int32_t)); 138static u_int32_t fwphy_rddata __P(( struct fwohci_softc *, u_int32_t)); 139static int fwohci_rx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 140static int fwohci_tx_enable __P((struct fwohci_softc *, struct fwohci_dbch *)); 141static int fwohci_irx_enable __P((struct firewire_comm *, int)); 142static int fwohci_irxpp_enable __P((struct firewire_comm *, int)); 143static int fwohci_irxbuf_enable __P((struct firewire_comm *, int)); 144static int fwohci_irx_disable __P((struct firewire_comm *, int)); 145static void fwohci_irx_post __P((struct firewire_comm *, u_int32_t *)); 146static int fwohci_itxbuf_enable __P((struct firewire_comm *, int)); 147static int fwohci_itx_disable __P((struct firewire_comm *, int)); 148static void fwohci_timeout __P((void *)); 149static void fwohci_poll __P((struct firewire_comm *, int, int)); 150static void fwohci_set_intr __P((struct firewire_comm *, int)); 151static int fwohci_add_rx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *, void *)); 152static int fwohci_add_tx_buf __P((struct fwohcidb_tr *, unsigned short, int, void *)); 153static void dump_db __P((struct fwohci_softc *, u_int32_t)); 154static void print_db __P((volatile struct fwohcidb *, u_int32_t , u_int32_t)); 155static void dump_dma __P((struct fwohci_softc *, u_int32_t)); 156static u_int32_t fwohci_cyctimer __P((struct firewire_comm *)); 157static void fwohci_rbuf_update __P((struct fwohci_softc *, int)); 158static void fwohci_tbuf_update __P((struct fwohci_softc *, int)); 159void fwohci_txbufdb __P((struct fwohci_softc *, int , struct fw_bulkxfer *)); 160 161/* 162 * memory allocated for DMA programs 163 */ 164#define DMA_PROG_ALLOC (8 * PAGE_SIZE) 165 166/* #define NDB 1024 */ 167#define NDB FWMAXQUEUE 168#define NDVDB (DVBUF * NDB) 169 170#define OHCI_VERSION 0x00 171#define OHCI_CROMHDR 0x18 172#define OHCI_BUS_OPT 0x20 173#define OHCI_BUSIRMC (1 << 31) 174#define OHCI_BUSCMC (1 << 30) 175#define OHCI_BUSISC (1 << 29) 176#define OHCI_BUSBMC (1 << 28) 177#define OHCI_BUSPMC (1 << 27) 178#define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\ 179 OHCI_BUSBMC | OHCI_BUSPMC 180 181#define OHCI_EUID_HI 0x24 182#define OHCI_EUID_LO 0x28 183 184#define OHCI_CROMPTR 0x34 185#define OHCI_HCCCTL 0x50 186#define OHCI_HCCCTLCLR 0x54 187#define OHCI_AREQHI 0x100 188#define OHCI_AREQHICLR 0x104 189#define OHCI_AREQLO 0x108 190#define OHCI_AREQLOCLR 0x10c 191#define OHCI_PREQHI 0x110 192#define OHCI_PREQHICLR 0x114 193#define OHCI_PREQLO 0x118 194#define OHCI_PREQLOCLR 0x11c 195#define OHCI_PREQUPPER 0x120 196 197#define OHCI_SID_BUF 0x64 198#define OHCI_SID_CNT 0x68 199#define OHCI_SID_CNT_MASK 0xffc 200 201#define OHCI_IT_STAT 0x90 202#define OHCI_IT_STATCLR 0x94 203#define OHCI_IT_MASK 0x98 204#define OHCI_IT_MASKCLR 0x9c 205 206#define OHCI_IR_STAT 0xa0 207#define OHCI_IR_STATCLR 0xa4 208#define OHCI_IR_MASK 0xa8 209#define OHCI_IR_MASKCLR 0xac 210 211#define OHCI_LNKCTL 0xe0 212#define OHCI_LNKCTLCLR 0xe4 213 214#define OHCI_PHYACCESS 0xec 215#define OHCI_CYCLETIMER 0xf0 216 217#define OHCI_DMACTL(off) (off) 218#define OHCI_DMACTLCLR(off) (off + 4) 219#define OHCI_DMACMD(off) (off + 0xc) 220#define OHCI_DMAMATCH(off) (off + 0x10) 221 222#define OHCI_ATQOFF 0x180 223#define OHCI_ATQCTL OHCI_ATQOFF 224#define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4) 225#define OHCI_ATQCMD (OHCI_ATQOFF + 0xc) 226#define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10) 227 228#define OHCI_ATSOFF 0x1a0 229#define OHCI_ATSCTL OHCI_ATSOFF 230#define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4) 231#define OHCI_ATSCMD (OHCI_ATSOFF + 0xc) 232#define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10) 233 234#define OHCI_ARQOFF 0x1c0 235#define OHCI_ARQCTL OHCI_ARQOFF 236#define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4) 237#define OHCI_ARQCMD (OHCI_ARQOFF + 0xc) 238#define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10) 239 240#define OHCI_ARSOFF 0x1e0 241#define OHCI_ARSCTL OHCI_ARSOFF 242#define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4) 243#define OHCI_ARSCMD (OHCI_ARSOFF + 0xc) 244#define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10) 245 246#define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH)) 247#define OHCI_ITCTL(CH) (OHCI_ITOFF(CH)) 248#define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4) 249#define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc) 250 251#define OHCI_IROFF(CH) (0x400 + 0x20 * (CH)) 252#define OHCI_IRCTL(CH) (OHCI_IROFF(CH)) 253#define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4) 254#define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc) 255#define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10) 256 257d_ioctl_t fwohci_ioctl; 258 259/* 260 * Communication with PHY device 261 */ 262static u_int32_t 263fwphy_wrdata( struct fwohci_softc *sc, u_int32_t addr, u_int32_t data) 264{ 265 u_int32_t fun; 266 267 addr &= 0xf; 268 data &= 0xff; 269 270 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA)); 271 OWRITE(sc, OHCI_PHYACCESS, fun); 272 DELAY(100); 273 274 return(fwphy_rddata( sc, addr)); 275} 276 277static u_int32_t 278fwohci_set_bus_manager(struct firewire_comm *fc, u_int node) 279{ 280 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 281 int i; 282 u_int32_t bm; 283 284#define OHCI_CSR_DATA 0x0c 285#define OHCI_CSR_COMP 0x10 286#define OHCI_CSR_CONT 0x14 287#define OHCI_BUS_MANAGER_ID 0 288 289 OWRITE(sc, OHCI_CSR_DATA, node); 290 OWRITE(sc, OHCI_CSR_COMP, 0x3f); 291 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID); 292 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++) 293 DELAY(100); 294 bm = OREAD(sc, OHCI_CSR_DATA); 295 if((bm & 0x3f) == 0x3f) 296 bm = node; 297 if (bootverbose) 298 device_printf(sc->fc.dev, 299 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i); 300 301 return(bm); 302} 303 304static u_int32_t 305fwphy_rddata(struct fwohci_softc *sc, u_int addr) 306{ 307 u_int32_t fun, stat; 308 u_int i, retry = 0; 309 310 addr &= 0xf; 311#define MAX_RETRY 100 312again: 313 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL); 314 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR); 315 OWRITE(sc, OHCI_PHYACCESS, fun); 316 for ( i = 0 ; i < MAX_RETRY ; i ++ ){ 317 fun = OREAD(sc, OHCI_PHYACCESS); 318 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0) 319 break; 320 DELAY(1000); 321 } 322 if(i >= MAX_RETRY) { 323 device_printf(sc->fc.dev, "cannot read phy\n"); 324#if 0 325 return 0; /* XXX */ 326#else 327 if (++retry < MAX_RETRY) { 328 DELAY(1000); 329 goto again; 330 } 331#endif 332 } 333 /* Make sure that SCLK is started */ 334 stat = OREAD(sc, FWOHCI_INTSTAT); 335 if ((stat & OHCI_INT_REG_FAIL) != 0 || 336 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) { 337 if (++retry < MAX_RETRY) { 338 DELAY(1000); 339 goto again; 340 } 341 } 342 if (bootverbose || retry >= MAX_RETRY) 343 device_printf(sc->fc.dev, 344 "fwphy_rddata: loop=%d, retry=%d\n", i, retry); 345#undef MAX_RETRY 346 return((fun >> PHYDEV_RDDATA )& 0xff); 347} 348/* Device specific ioctl. */ 349int 350fwohci_ioctl (dev_t dev, u_long cmd, caddr_t data, int flag, fw_proc *td) 351{ 352 struct firewire_softc *sc; 353 struct fwohci_softc *fc; 354 int unit = DEV2UNIT(dev); 355 int err = 0; 356 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data; 357 u_int32_t *dmach = (u_int32_t *) data; 358 359 sc = devclass_get_softc(firewire_devclass, unit); 360 if(sc == NULL){ 361 return(EINVAL); 362 } 363 fc = (struct fwohci_softc *)sc->fc; 364 365 if (!data) 366 return(EINVAL); 367 368 switch (cmd) { 369 case FWOHCI_WRREG: 370#define OHCI_MAX_REG 0x800 371 if(reg->addr <= OHCI_MAX_REG){ 372 OWRITE(fc, reg->addr, reg->data); 373 reg->data = OREAD(fc, reg->addr); 374 }else{ 375 err = EINVAL; 376 } 377 break; 378 case FWOHCI_RDREG: 379 if(reg->addr <= OHCI_MAX_REG){ 380 reg->data = OREAD(fc, reg->addr); 381 }else{ 382 err = EINVAL; 383 } 384 break; 385/* Read DMA descriptors for debug */ 386 case DUMPDMA: 387 if(*dmach <= OHCI_MAX_DMA_CH ){ 388 dump_dma(fc, *dmach); 389 dump_db(fc, *dmach); 390 }else{ 391 err = EINVAL; 392 } 393 break; 394 default: 395 break; 396 } 397 return err; 398} 399 400static int 401fwohci_probe_phy(struct fwohci_softc *sc, device_t dev) 402{ 403 u_int32_t reg, reg2; 404 int e1394a = 1; 405/* 406 * probe PHY parameters 407 * 0. to prove PHY version, whether compliance of 1394a. 408 * 1. to probe maximum speed supported by the PHY and 409 * number of port supported by core-logic. 410 * It is not actually available port on your PC . 411 */ 412 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS); 413#if 0 414 /* XXX wait for SCLK. */ 415 DELAY(100000); 416#endif 417 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 418 419 if((reg >> 5) != 7 ){ 420 sc->fc.mode &= ~FWPHYASYST; 421 sc->fc.nport = reg & FW_PHY_NP; 422 sc->fc.speed = reg & FW_PHY_SPD >> 6; 423 if (sc->fc.speed > MAX_SPEED) { 424 device_printf(dev, "invalid speed %d (fixed to %d).\n", 425 sc->fc.speed, MAX_SPEED); 426 sc->fc.speed = MAX_SPEED; 427 } 428 sc->fc.maxrec = maxrec[sc->fc.speed]; 429 device_printf(dev, 430 "Link 1394 only %s, %d ports, maxrec %d bytes.\n", 431 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 432 }else{ 433 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG); 434 sc->fc.mode |= FWPHYASYST; 435 sc->fc.nport = reg & FW_PHY_NP; 436 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5; 437 if (sc->fc.speed > MAX_SPEED) { 438 device_printf(dev, "invalid speed %d (fixed to %d).\n", 439 sc->fc.speed, MAX_SPEED); 440 sc->fc.speed = MAX_SPEED; 441 } 442 sc->fc.maxrec = maxrec[sc->fc.speed]; 443 device_printf(dev, 444 "Link 1394a available %s, %d ports, maxrec %d bytes.\n", 445 linkspeed[sc->fc.speed], sc->fc.nport, sc->fc.maxrec); 446 447 /* check programPhyEnable */ 448 reg2 = fwphy_rddata(sc, 5); 449#if 0 450 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) { 451#else /* XXX force to enable 1394a */ 452 if (e1394a) { 453#endif 454 if (bootverbose) 455 device_printf(dev, 456 "Enable 1394a Enhancements\n"); 457 /* enable EAA EMC */ 458 reg2 |= 0x03; 459 /* set aPhyEnhanceEnable */ 460 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN); 461 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY); 462 } else { 463 /* for safe */ 464 reg2 &= ~0x83; 465 } 466 reg2 = fwphy_wrdata(sc, 5, reg2); 467 } 468 469 reg = fwphy_rddata(sc, FW_PHY_SPD_REG); 470 if((reg >> 5) == 7 ){ 471 reg = fwphy_rddata(sc, 4); 472 reg |= 1 << 6; 473 fwphy_wrdata(sc, 4, reg); 474 reg = fwphy_rddata(sc, 4); 475 } 476 return 0; 477} 478 479 480void 481fwohci_reset(struct fwohci_softc *sc, device_t dev) 482{ 483 int i; 484 u_int32_t reg, reg2; 485 struct fwohcidb_tr *db_tr; 486 487/* Disable interrupt */ 488 OWRITE(sc, FWOHCI_INTMASKCLR, ~0); 489 490/* Now stopping all DMA channel */ 491 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 492 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 493 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 494 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 495 496 OWRITE(sc, OHCI_IR_MASKCLR, ~0); 497 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 498 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 499 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 500 } 501 502/* FLUSH FIFO and reset Transmitter/Reciever */ 503 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 504 if (bootverbose) 505 device_printf(dev, "resetting OHCI..."); 506 i = 0; 507 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) { 508 if (i++ > 100) break; 509 DELAY(1000); 510 } 511 if (bootverbose) 512 printf("done (loop=%d)\n", i); 513 514 reg = OREAD(sc, OHCI_BUS_OPT); 515 reg2 = reg | OHCI_BUSFNC; 516 /* XXX */ 517 if (((reg & 0x0000f000) >> 12) < 10) 518 reg2 = (reg2 & 0xffff0fff) | (10 << 12); 519 if (bootverbose) 520 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2); 521 OWRITE(sc, OHCI_BUS_OPT, reg2); 522 523 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]); 524 OWRITE(sc, OHCI_CROMPTR, vtophys(&sc->fc.config_rom[0])); 525 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND); 526 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR); 527 528 fwohci_probe_phy(sc, dev); 529
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530 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf));
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530 OWRITE(sc, OHCI_SID_BUF, vtophys(sc->fc.sid_buf)); |
531 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID); 532 533 /* enable link */ 534 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN); 535 fw_busreset(&sc->fc);
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536 537 /* force to start rx dma */ 538 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING; 539 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING; |
540 fwohci_rx_enable(sc, &sc->arrq); 541 fwohci_rx_enable(sc, &sc->arrs); 542 543 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ; 544 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 545 db_tr->xfer = NULL; 546 } 547 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ; 548 i ++, db_tr = STAILQ_NEXT(db_tr, link)){ 549 db_tr->xfer = NULL; 550 } 551 552 OWRITE(sc, FWOHCI_RETRY, 553 (0xffff << 16 )| (0x0f << 8) | (0x0f << 4) | 0x0f) ; 554 OWRITE(sc, FWOHCI_INTMASK, 555 OHCI_INT_ERR | OHCI_INT_PHY_SID 556 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 557 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 558 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR); 559 fwohci_set_intr(&sc->fc, 1); 560 561 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 562 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD); 563} 564 565int 566fwohci_init(struct fwohci_softc *sc, device_t dev) 567{ 568 int i; 569 u_int32_t reg; 570 571 reg = OREAD(sc, OHCI_VERSION); 572 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n", 573 (reg>>16) & 0xff, reg & 0xff, (reg>>24) & 1); 574 575/* XXX: Available Isochrounous DMA channel probe */ 576 for( i = 0 ; i < 0x20 ; i ++ ){ 577 OWRITE(sc, OHCI_IRCTL(i), OHCI_CNTL_DMA_RUN); 578 reg = OREAD(sc, OHCI_IRCTL(i)); 579 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 580 OWRITE(sc, OHCI_ITCTL(i), OHCI_CNTL_DMA_RUN); 581 reg = OREAD(sc, OHCI_ITCTL(i)); 582 if(!(reg & OHCI_CNTL_DMA_RUN)) break; 583 } 584 sc->fc.nisodma = i; 585 device_printf(dev, "No. of Isochronous channel is %d.\n", i); 586 587 sc->fc.arq = &sc->arrq.xferq; 588 sc->fc.ars = &sc->arrs.xferq; 589 sc->fc.atq = &sc->atrq.xferq; 590 sc->fc.ats = &sc->atrs.xferq; 591 592 sc->arrq.xferq.start = NULL; 593 sc->arrs.xferq.start = NULL; 594 sc->atrq.xferq.start = fwohci_start_atq; 595 sc->atrs.xferq.start = fwohci_start_ats; 596 597 sc->arrq.xferq.drain = NULL; 598 sc->arrs.xferq.drain = NULL; 599 sc->atrq.xferq.drain = fwohci_drain_atq; 600 sc->atrs.xferq.drain = fwohci_drain_ats; 601 602 sc->arrq.ndesc = 1; 603 sc->arrs.ndesc = 1; 604 sc->atrq.ndesc = 10; 605 sc->atrs.ndesc = 10 / 2; 606 607 sc->arrq.ndb = NDB; 608 sc->arrs.ndb = NDB / 2; 609 sc->atrq.ndb = NDB; 610 sc->atrs.ndb = NDB / 2; 611 612 sc->arrq.dummy = NULL; 613 sc->arrs.dummy = NULL; 614 sc->atrq.dummy = NULL; 615 sc->atrs.dummy = NULL; 616 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 617 sc->fc.it[i] = &sc->it[i].xferq; 618 sc->fc.ir[i] = &sc->ir[i].xferq; 619 sc->it[i].ndb = 0; 620 sc->ir[i].ndb = 0; 621 } 622 623 sc->fc.tcode = tinfo; 624 625 sc->cromptr = (u_int32_t *) 626 contigmalloc(CROMSIZE * 2, M_DEVBUF, M_NOWAIT, 0, ~0, 1<<10, 0); 627 628 if(sc->cromptr == NULL){ 629 device_printf(dev, "cromptr alloc failed."); 630 return ENOMEM; 631 } 632 sc->fc.dev = dev; 633 sc->fc.config_rom = &(sc->cromptr[CROMSIZE/4]); 634 635 sc->fc.config_rom[1] = 0x31333934; 636 sc->fc.config_rom[2] = 0xf000a002; 637 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI); 638 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO); 639 sc->fc.config_rom[5] = 0; 640 sc->fc.config_rom[0] = (4 << 24) | (5 << 16); 641 642 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4); 643 644 645/* SID recieve buffer must allign 2^11 */ 646#define OHCI_SIDSIZE (1 << 11) 647 sc->fc.sid_buf = (u_int32_t *) vm_page_alloc_contig( OHCI_SIDSIZE, 648 0x10000, 0xffffffff, OHCI_SIDSIZE); 649 if (sc->fc.sid_buf == NULL) { 650 device_printf(dev, "sid_buf alloc failed.\n"); 651 return ENOMEM; 652 } 653 654 655 fwohci_db_init(&sc->arrq); 656 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0) 657 return ENOMEM; 658 659 fwohci_db_init(&sc->arrs); 660 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0) 661 return ENOMEM; 662 663 fwohci_db_init(&sc->atrq); 664 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0) 665 return ENOMEM; 666 667 fwohci_db_init(&sc->atrs); 668 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0) 669 return ENOMEM; 670 671 reg = OREAD(sc, FWOHCIGUID_H); 672 for( i = 0 ; i < 4 ; i ++){ 673 sc->fc.eui[3 - i] = reg & 0xff; 674 reg = reg >> 8; 675 } 676 reg = OREAD(sc, FWOHCIGUID_L); 677 for( i = 0 ; i < 4 ; i ++){ 678 sc->fc.eui[7 - i] = reg & 0xff; 679 reg = reg >> 8; 680 } 681 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n", 682 sc->fc.eui[0], sc->fc.eui[1], sc->fc.eui[2], sc->fc.eui[3], 683 sc->fc.eui[4], sc->fc.eui[5], sc->fc.eui[6], sc->fc.eui[7]); 684 sc->fc.ioctl = fwohci_ioctl; 685 sc->fc.cyctimer = fwohci_cyctimer; 686 sc->fc.set_bmr = fwohci_set_bus_manager; 687 sc->fc.ibr = fwohci_ibr; 688 sc->fc.irx_enable = fwohci_irx_enable; 689 sc->fc.irx_disable = fwohci_irx_disable; 690 691 sc->fc.itx_enable = fwohci_itxbuf_enable; 692 sc->fc.itx_disable = fwohci_itx_disable; 693 sc->fc.irx_post = fwohci_irx_post; 694 sc->fc.itx_post = NULL; 695 sc->fc.timeout = fwohci_timeout; 696 sc->fc.poll = fwohci_poll; 697 sc->fc.set_intr = fwohci_set_intr; 698 699 fw_init(&sc->fc); 700 fwohci_reset(sc, dev); 701 702 return 0; 703} 704 705void 706fwohci_timeout(void *arg) 707{ 708 struct fwohci_softc *sc; 709 710 sc = (struct fwohci_softc *)arg; 711 sc->fc.timeouthandle = timeout(fwohci_timeout, 712 (void *)sc, FW_XFERTIMEOUT * hz * 10); 713} 714 715u_int32_t 716fwohci_cyctimer(struct firewire_comm *fc) 717{ 718 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 719 return(OREAD(sc, OHCI_CYCLETIMER)); 720} 721 722#define LAST_DB(dbtr, db) do { \ 723 struct fwohcidb_tr *_dbtr = (dbtr); \ 724 int _cnt = _dbtr->dbcnt; \ 725 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \ 726} while (0) 727 728int 729fwohci_detach(struct fwohci_softc *sc, device_t dev) 730{ 731 int i; 732 733 if (sc->fc.sid_buf != NULL) 734 contigfree((void *)(uintptr_t)sc->fc.sid_buf, 735 OHCI_SIDSIZE, M_DEVBUF); 736 if (sc->cromptr != NULL) 737 contigfree((void *)sc->cromptr, CROMSIZE * 2, M_DEVBUF); 738 739 fwohci_db_free(&sc->arrq); 740 fwohci_db_free(&sc->arrs); 741 742 fwohci_db_free(&sc->atrq); 743 fwohci_db_free(&sc->atrs); 744 745 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 746 fwohci_db_free(&sc->it[i]); 747 fwohci_db_free(&sc->ir[i]); 748 } 749 750 return 0; 751} 752 753static void 754fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 755{ 756 int i, s; 757 int tcode, hdr_len, hdr_off, len; 758 int fsegment = -1; 759 u_int32_t off; 760 struct fw_xfer *xfer; 761 struct fw_pkt *fp; 762 volatile struct fwohci_txpkthdr *ohcifp; 763 struct fwohcidb_tr *db_tr; 764 volatile struct fwohcidb *db; 765 struct mbuf *m; 766 struct tcode_info *info; 767 768 if(&sc->atrq == dbch){ 769 off = OHCI_ATQOFF; 770 }else if(&sc->atrs == dbch){ 771 off = OHCI_ATSOFF; 772 }else{ 773 return; 774 } 775 776 if (dbch->flags & FWOHCI_DBCH_FULL) 777 return; 778 779 s = splfw(); 780 db_tr = dbch->top; 781txloop: 782 xfer = STAILQ_FIRST(&dbch->xferq.q); 783 if(xfer == NULL){ 784 goto kick; 785 } 786 if(dbch->xferq.queued == 0 ){ 787 device_printf(sc->fc.dev, "TX queue empty\n"); 788 } 789 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link); 790 db_tr->xfer = xfer; 791 xfer->state = FWXF_START; 792 dbch->xferq.packets++; 793 794 fp = (struct fw_pkt *)(xfer->send.buf + xfer->send.off); 795 tcode = fp->mode.common.tcode; 796 797 ohcifp = (volatile struct fwohci_txpkthdr *) db_tr->db[1].db.immed; 798 info = &tinfo[tcode]; 799 hdr_len = hdr_off = info->hdr_len; 800 /* fw_asyreq must pass valid send.len */ 801 len = xfer->send.len; 802 for( i = 0 ; i < hdr_off ; i+= 4){ 803 ohcifp->mode.ld[i/4] = ntohl(fp->mode.ld[i/4]); 804 } 805 ohcifp->mode.common.spd = xfer->spd; 806 if (tcode == FWTCODE_STREAM ){ 807 hdr_len = 8; 808 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 809 } else if (tcode == FWTCODE_PHY) { 810 hdr_len = 12; 811 ohcifp->mode.ld[1] = ntohl(fp->mode.ld[1]); 812 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[2]); 813 ohcifp->mode.common.spd = 0; 814 ohcifp->mode.common.tcode = FWOHCITCODE_PHY; 815 } else { 816 ohcifp->mode.asycomm.dst = ntohs(fp->mode.hdr.dst); 817 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS; 818 ohcifp->mode.asycomm.tlrt |= FWRETRY_X; 819 } 820 db = &db_tr->db[0]; 821 db->db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len; 822 db->db.desc.status = 0; 823/* Specify bound timer of asy. responce */ 824 if(&sc->atrs == dbch){ 825 db->db.desc.count 826 = (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13); 827 } 828 829 db_tr->dbcnt = 2; 830 db = &db_tr->db[db_tr->dbcnt]; 831 if(len > hdr_off){ 832 if (xfer->mbuf == NULL) { 833 db->db.desc.addr 834 = vtophys(xfer->send.buf + xfer->send.off) + hdr_off; 835 db->db.desc.cmd 836 = OHCI_OUTPUT_MORE | ((len - hdr_off) & 0xffff); 837 db->db.desc.status = 0; 838 839 db_tr->dbcnt++; 840 } else { 841 /* XXX we assume mbuf chain is shorter than ndesc */ 842 m = xfer->mbuf; 843 do { 844 db->db.desc.addr 845 = vtophys(mtod(m, caddr_t)); 846 db->db.desc.cmd = OHCI_OUTPUT_MORE | m->m_len; 847 db->db.desc.status = 0; 848 db++; 849 db_tr->dbcnt++; 850 m = m->m_next; 851 } while (m != NULL); 852 } 853 } 854 /* last db */ 855 LAST_DB(db_tr, db); 856 db->db.desc.cmd |= OHCI_OUTPUT_LAST 857 | OHCI_INTERRUPT_ALWAYS 858 | OHCI_BRANCH_ALWAYS; 859 db->db.desc.depend = vtophys(STAILQ_NEXT(db_tr, link)->db); 860 861 if(fsegment == -1 ) 862 fsegment = db_tr->dbcnt; 863 if (dbch->pdb_tr != NULL) { 864 LAST_DB(dbch->pdb_tr, db); 865 db->db.desc.depend |= db_tr->dbcnt; 866 } 867 dbch->pdb_tr = db_tr; 868 db_tr = STAILQ_NEXT(db_tr, link); 869 if(db_tr != dbch->bottom){ 870 goto txloop; 871 } else { 872 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n"); 873 dbch->flags |= FWOHCI_DBCH_FULL; 874 } 875kick: 876 if (firewire_debug) printf("kick\n"); 877 /* kick asy q */ 878 879 if(dbch->xferq.flag & FWXFERQ_RUNNING) { 880 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE); 881 } else { 882 if (bootverbose) 883 device_printf(sc->fc.dev, "start AT DMA status=%x\n", 884 OREAD(sc, OHCI_DMACTL(off))); 885 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | fsegment); 886 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 887 dbch->xferq.flag |= FWXFERQ_RUNNING; 888 } 889 890 dbch->top = db_tr; 891 splx(s); 892 return; 893} 894 895static void 896fwohci_drain_atq(struct firewire_comm *fc, struct fw_xfer *xfer) 897{ 898 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 899 fwohci_drain(&sc->fc, xfer, &(sc->atrq)); 900 return; 901} 902 903static void 904fwohci_drain_ats(struct firewire_comm *fc, struct fw_xfer *xfer) 905{ 906 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 907 fwohci_drain(&sc->fc, xfer, &(sc->atrs)); 908 return; 909} 910 911static void 912fwohci_start_atq(struct firewire_comm *fc) 913{ 914 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 915 fwohci_start( sc, &(sc->atrq)); 916 return; 917} 918 919static void 920fwohci_start_ats(struct firewire_comm *fc) 921{ 922 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 923 fwohci_start( sc, &(sc->atrs)); 924 return; 925} 926 927void 928fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 929{ 930 int s, err = 0; 931 struct fwohcidb_tr *tr; 932 volatile struct fwohcidb *db; 933 struct fw_xfer *xfer; 934 u_int32_t off; 935 u_int stat; 936 int packets; 937 struct firewire_comm *fc = (struct firewire_comm *)sc; 938 if(&sc->atrq == dbch){ 939 off = OHCI_ATQOFF; 940 }else if(&sc->atrs == dbch){ 941 off = OHCI_ATSOFF; 942 }else{ 943 return; 944 } 945 s = splfw(); 946 tr = dbch->bottom; 947 packets = 0; 948 while(dbch->xferq.queued > 0){ 949 LAST_DB(tr, db); 950 if(!(db->db.desc.status & OHCI_CNTL_DMA_ACTIVE)){ 951 if (fc->status != FWBUSRESET) 952 /* maybe out of order?? */ 953 goto out; 954 } 955 if(db->db.desc.status & OHCI_CNTL_DMA_DEAD) { 956#ifdef OHCI_DEBUG 957 dump_dma(sc, ch); 958 dump_db(sc, ch); 959#endif 960/* Stop DMA */ 961 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 962 device_printf(sc->fc.dev, "force reset AT FIFO\n"); 963 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN); 964 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN); 965 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN); 966 } 967 stat = db->db.desc.status & FWOHCIEV_MASK; 968 switch(stat){ 969 case FWOHCIEV_ACKCOMPL: 970 case FWOHCIEV_ACKPEND: 971 err = 0; 972 break; 973 case FWOHCIEV_ACKBSA: 974 case FWOHCIEV_ACKBSB: 975 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 976 case FWOHCIEV_ACKBSX: 977 err = EBUSY; 978 break; 979 case FWOHCIEV_FLUSHED: 980 case FWOHCIEV_ACKTARD: 981 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]); 982 err = EAGAIN; 983 break; 984 case FWOHCIEV_MISSACK: 985 case FWOHCIEV_UNDRRUN: 986 case FWOHCIEV_OVRRUN: 987 case FWOHCIEV_DESCERR: 988 case FWOHCIEV_DTRDERR: 989 case FWOHCIEV_TIMEOUT: 990 case FWOHCIEV_TCODERR: 991 case FWOHCIEV_UNKNOWN: 992 case FWOHCIEV_ACKDERR: 993 case FWOHCIEV_ACKTERR: 994 default: 995 device_printf(sc->fc.dev, "txd err=%2x %s\n", 996 stat, fwohcicode[stat]); 997 err = EINVAL; 998 break; 999 } 1000 if(tr->xfer != NULL){ 1001 xfer = tr->xfer; 1002 xfer->state = FWXF_SENT; 1003 if(err == EBUSY && fc->status != FWBUSRESET){ 1004 xfer->state = FWXF_BUSY; 1005 switch(xfer->act_type){ 1006 case FWACT_XFER: 1007 xfer->resp = err; 1008 if(xfer->retry_req != NULL){ 1009 xfer->retry_req(xfer); 1010 } 1011 break; 1012 default: 1013 break; 1014 } 1015 } else if( stat != FWOHCIEV_ACKPEND){ 1016 if (stat != FWOHCIEV_ACKCOMPL) 1017 xfer->state = FWXF_SENTERR; 1018 xfer->resp = err; 1019 switch(xfer->act_type){ 1020 case FWACT_XFER: 1021 fw_xfer_done(xfer); 1022 break; 1023 default: 1024 break; 1025 } 1026 } 1027 dbch->xferq.queued --; 1028 } 1029 tr->xfer = NULL; 1030 1031 packets ++; 1032 tr = STAILQ_NEXT(tr, link); 1033 dbch->bottom = tr; 1034 } 1035out: 1036 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) { 1037 printf("make free slot\n"); 1038 dbch->flags &= ~FWOHCI_DBCH_FULL; 1039 fwohci_start(sc, dbch); 1040 } 1041 splx(s); 1042} 1043 1044static void 1045fwohci_drain(struct firewire_comm *fc, struct fw_xfer *xfer, struct fwohci_dbch *dbch) 1046{ 1047 int i, s; 1048 struct fwohcidb_tr *tr; 1049 1050 if(xfer->state != FWXF_START) return; 1051 1052 s = splfw(); 1053 tr = dbch->bottom; 1054 for( i = 0 ; i <= dbch->xferq.queued ; i ++){ 1055 if(tr->xfer == xfer){ 1056 s = splfw(); 1057 tr->xfer = NULL; 1058 dbch->xferq.queued --; 1059#if 1 1060 /* XXX */ 1061 if (tr == dbch->bottom) 1062 dbch->bottom = STAILQ_NEXT(tr, link); 1063#endif 1064 if (dbch->flags & FWOHCI_DBCH_FULL) { 1065 printf("fwohci_drain: make slot\n"); 1066 dbch->flags &= ~FWOHCI_DBCH_FULL; 1067 fwohci_start((struct fwohci_softc *)fc, dbch); 1068 } 1069 1070 splx(s); 1071 break; 1072 } 1073 tr = STAILQ_NEXT(tr, link); 1074 } 1075 splx(s); 1076 return; 1077} 1078 1079static void 1080fwohci_db_free(struct fwohci_dbch *dbch) 1081{ 1082 struct fwohcidb_tr *db_tr; 1083 int idb; 1084 1085 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) 1086 return; 1087 1088 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1089 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; 1090 idb < dbch->ndb; 1091 db_tr = STAILQ_NEXT(db_tr, link), idb++){ 1092 if (db_tr->buf != NULL) { 1093 free(db_tr->buf, M_DEVBUF); 1094 db_tr->buf = NULL; 1095 } 1096 } 1097 } 1098 dbch->ndb = 0; 1099 db_tr = STAILQ_FIRST(&dbch->db_trq); 1100 contigfree((void *)(uintptr_t)(volatile void *)db_tr->db, 1101 sizeof(struct fwohcidb) * dbch->ndesc * dbch->ndb, M_DEVBUF); 1102 free(db_tr, M_DEVBUF); 1103 STAILQ_INIT(&dbch->db_trq); 1104 dbch->flags &= ~FWOHCI_DBCH_INIT; 1105} 1106 1107static void 1108fwohci_db_init(struct fwohci_dbch *dbch) 1109{ 1110 int idb; 1111 struct fwohcidb *db; 1112 struct fwohcidb_tr *db_tr;
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1113 1114 1115 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0) 1116 goto out; 1117 |
1118 /* allocate DB entries and attach one to each DMA channels */ 1119 /* DB entry must start at 16 bytes bounary. */
|
1111 dbch->frag.buf = NULL;
1112 dbch->frag.len = 0;
1113 dbch->frag.plen = 0;
1114 dbch->xferq.queued = 0;
1115 dbch->pdb_tr = NULL;
1116
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1120 STAILQ_INIT(&dbch->db_trq); 1121 db_tr = (struct fwohcidb_tr *) 1122 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb, 1123 M_DEVBUF, M_DONTWAIT | M_ZERO); 1124 if(db_tr == NULL){
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1122 printf("fwochi_db_init: malloc failed\n");
|
1125 printf("fwohci_db_init: malloc failed\n"); |
1126 return; 1127 } 1128 db = (struct fwohcidb *) 1129 contigmalloc(sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb, 1130 M_DEVBUF, M_DONTWAIT, 0x10000, 0xffffffff, PAGE_SIZE, 0ul); 1131 if(db == NULL){
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1129 printf("fwochi_db_init: contigmalloc failed\n");
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1132 printf("fwohci_db_init: contigmalloc failed\n"); |
1133 free(db_tr, M_DEVBUF); 1134 return; 1135 } 1136 bzero(db, sizeof (struct fwohcidb) * dbch->ndesc * dbch->ndb); 1137 /* Attach DB to DMA ch. */ 1138 for(idb = 0 ; idb < dbch->ndb ; idb++){ 1139 db_tr->dbcnt = 0; 1140 db_tr->db = &db[idb * dbch->ndesc]; 1141 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link); 1142 if (!(dbch->xferq.flag & FWXFERQ_PACKET) && 1143 dbch->xferq.bnpacket != 0) { 1144 /* XXX what thoes for? */ 1145 if (idb % dbch->xferq.bnpacket == 0) 1146 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1147 ].start = (caddr_t)db_tr; 1148 if ((idb + 1) % dbch->xferq.bnpacket == 0) 1149 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket 1150 ].end = (caddr_t)db_tr; 1151 } 1152 db_tr++; 1153 } 1154 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next 1155 = STAILQ_FIRST(&dbch->db_trq);
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1156out: 1157 dbch->frag.buf = NULL; 1158 dbch->frag.len = 0; 1159 dbch->frag.plen = 0; 1160 dbch->xferq.queued = 0; 1161 dbch->pdb_tr = NULL; |
1162 dbch->top = STAILQ_FIRST(&dbch->db_trq); 1163 dbch->bottom = dbch->top; 1164 dbch->flags = FWOHCI_DBCH_INIT; 1165} 1166 1167static int 1168fwohci_itx_disable(struct firewire_comm *fc, int dmach) 1169{ 1170 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1171 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1172 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1173 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1174 fwohci_db_free(&sc->it[dmach]); 1175 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1176 return 0; 1177} 1178 1179static int 1180fwohci_irx_disable(struct firewire_comm *fc, int dmach) 1181{ 1182 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1183 1184 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1185 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1186 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1187 if(sc->ir[dmach].dummy != NULL){ 1188 free(sc->ir[dmach].dummy, M_DEVBUF); 1189 } 1190 sc->ir[dmach].dummy = NULL; 1191 fwohci_db_free(&sc->ir[dmach]); 1192 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING; 1193 return 0; 1194} 1195 1196static void 1197fwohci_irx_post (struct firewire_comm *fc , u_int32_t *qld) 1198{ 1199 qld[0] = ntohl(qld[0]); 1200 return; 1201} 1202 1203static int 1204fwohci_irxpp_enable(struct firewire_comm *fc, int dmach) 1205{ 1206 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1207 int err = 0; 1208 unsigned short tag, ich; 1209 1210 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1211 ich = sc->ir[dmach].xferq.flag & 0x3f; 1212 1213#if 0 1214 if(STAILQ_FIRST(&fc->ir[dmach]->q) != NULL){ 1215 wakeup(fc->ir[dmach]); 1216 return err; 1217 } 1218#endif 1219 1220 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1221 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1222 sc->ir[dmach].xferq.queued = 0; 1223 sc->ir[dmach].ndb = NDB; 1224 sc->ir[dmach].xferq.psize = FWPMAX_S400; 1225 sc->ir[dmach].ndesc = 1; 1226 fwohci_db_init(&sc->ir[dmach]); 1227 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1228 } 1229 if(err){ 1230 device_printf(sc->fc.dev, "err in IRX setting\n"); 1231 return err; 1232 } 1233 if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1234 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1235 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1236 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1237 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1238 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf8000000); 1239 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1240 OWRITE(sc, OHCI_IRCMD(dmach), 1241 vtophys(sc->ir[dmach].top->db) | 1); 1242 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1243 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1244 } 1245 return err; 1246} 1247 1248static int 1249fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1250{ 1251 int err = 0; 1252 int idb, z, i, dmach = 0; 1253 u_int32_t off = NULL; 1254 struct fwohcidb_tr *db_tr; 1255 1256 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1257 err = EINVAL; 1258 return err; 1259 } 1260 z = dbch->ndesc; 1261 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1262 if( &sc->it[dmach] == dbch){ 1263 off = OHCI_ITOFF(dmach); 1264 break; 1265 } 1266 } 1267 if(off == NULL){ 1268 err = EINVAL; 1269 return err; 1270 } 1271 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1272 return err; 1273 dbch->xferq.flag |= FWXFERQ_RUNNING; 1274 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1275 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1276 } 1277 db_tr = dbch->top; 1278 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1279 fwohci_add_tx_buf(db_tr, 1280 dbch->xferq.psize, dbch->xferq.flag, 1281 dbch->xferq.buf + dbch->xferq.psize * idb); 1282 if(STAILQ_NEXT(db_tr, link) == NULL){ 1283 break; 1284 } 1285 db_tr->db[0].db.desc.depend 1286 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1287 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1288 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1289 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1290 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1291 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1292 |= OHCI_INTERRUPT_ALWAYS; 1293 db_tr->db[0].db.desc.depend &= ~0xf; 1294 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1295 ~0xf; 1296 } 1297 } 1298 db_tr = STAILQ_NEXT(db_tr, link); 1299 } 1300 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1301 return err; 1302} 1303 1304static int 1305fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch) 1306{ 1307 int err = 0; 1308 int idb, z, i, dmach = 0; 1309 u_int32_t off = NULL; 1310 struct fwohcidb_tr *db_tr; 1311 1312 z = dbch->ndesc; 1313 if(&sc->arrq == dbch){ 1314 off = OHCI_ARQOFF; 1315 }else if(&sc->arrs == dbch){ 1316 off = OHCI_ARSOFF; 1317 }else{ 1318 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 1319 if( &sc->ir[dmach] == dbch){ 1320 off = OHCI_IROFF(dmach); 1321 break; 1322 } 1323 } 1324 } 1325 if(off == NULL){ 1326 err = EINVAL; 1327 return err; 1328 } 1329 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1330 if(dbch->xferq.flag & FWXFERQ_RUNNING) 1331 return err; 1332 }else{ 1333 if(dbch->xferq.flag & FWXFERQ_RUNNING){ 1334 err = EBUSY; 1335 return err; 1336 } 1337 } 1338 dbch->xferq.flag |= FWXFERQ_RUNNING;
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1339 dbch->top = STAILQ_FIRST(&dbch->db_trq); |
1340 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){ 1341 dbch->bottom = STAILQ_NEXT(dbch->bottom, link); 1342 } 1343 db_tr = dbch->top; 1344 for( idb = 0 ; idb < dbch->ndb ; idb ++){ 1345 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){ 1346 fwohci_add_rx_buf(db_tr, 1347 dbch->xferq.psize, dbch->xferq.flag, 0, NULL); 1348 }else{ 1349 fwohci_add_rx_buf(db_tr, 1350 dbch->xferq.psize, dbch->xferq.flag, 1351 dbch->xferq.buf + dbch->xferq.psize * idb, 1352 dbch->dummy + sizeof(u_int32_t) * idb); 1353 } 1354 if(STAILQ_NEXT(db_tr, link) == NULL){ 1355 break; 1356 } 1357 db_tr->db[db_tr->dbcnt - 1].db.desc.depend 1358 = vtophys(STAILQ_NEXT(db_tr, link)->db) | z; 1359 if(dbch->xferq.flag & FWXFERQ_EXTBUF){ 1360 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){ 1361 db_tr->db[db_tr->dbcnt - 1].db.desc.cmd 1362 |= OHCI_INTERRUPT_ALWAYS; 1363 db_tr->db[db_tr->dbcnt - 1].db.desc.depend &= 1364 ~0xf; 1365 } 1366 } 1367 db_tr = STAILQ_NEXT(db_tr, link); 1368 } 1369 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend &= 0xfffffff0; 1370 dbch->buf_offset = 0; 1371 if(dbch->xferq.flag & FWXFERQ_STREAM){ 1372 return err; 1373 }else{ 1374 OWRITE(sc, OHCI_DMACMD(off), vtophys(dbch->top->db) | z); 1375 } 1376 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN); 1377 return err; 1378} 1379 1380static int 1381fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach) 1382{ 1383 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1384 int err = 0; 1385 unsigned short tag, ich; 1386 struct fwohci_dbch *dbch; 1387 struct fw_pkt *fp; 1388 struct fwohcidb_tr *db_tr; 1389 1390 tag = (sc->it[dmach].xferq.flag >> 6) & 3; 1391 ich = sc->it[dmach].xferq.flag & 0x3f; 1392 dbch = &sc->it[dmach]; 1393 if(dbch->ndb == 0){ 1394 dbch->xferq.queued = 0; 1395 dbch->ndb = dbch->xferq.bnpacket * dbch->xferq.bnchunk; 1396 dbch->ndesc = 3; 1397 fwohci_db_init(dbch); 1398 err = fwohci_tx_enable(sc, dbch); 1399 } 1400 if(err) 1401 return err; 1402 if(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1403 if(dbch->xferq.stdma2 != NULL){ 1404 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1405 ((struct fwohcidb_tr *) 1406 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1407 |= OHCI_BRANCH_ALWAYS; 1408 ((struct fwohcidb_tr *) 1409 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1410 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1411 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1412 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1413 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1414 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1415 } 1416 }else if(!(OREAD(sc, OHCI_ITCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE)){ 1417 fw_tbuf_update(&sc->fc, dmach, 0); 1418 if(dbch->xferq.stdma == NULL){ 1419 return err; 1420 } 1421 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1422 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach); 1423 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach); 1424 OWRITE(sc, OHCI_IT_MASK, 1 << dmach); 1425 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xf0000000); 1426 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma); 1427 if(dbch->xferq.stdma2 != NULL){ 1428 fwohci_txbufdb(sc, dmach, dbch->xferq.stdma2); 1429 ((struct fwohcidb_tr *) 1430 (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.cmd 1431 |= OHCI_BRANCH_ALWAYS; 1432 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend = 1433 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1434 ((struct fwohcidb_tr *)(dbch->xferq.stdma->end))->db[0].db.desc.depend = 1435 vtophys(((struct fwohcidb_tr *)(dbch->xferq.stdma2->start))->db) | dbch->ndesc; 1436 ((struct fwohcidb_tr *)(dbch->xferq.stdma2->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1437 ((struct fwohcidb_tr *) (dbch->xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1438 }else{ 1439 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 1440 ((struct fwohcidb_tr *) (dbch->xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1441 } 1442 OWRITE(sc, OHCI_ITCMD(dmach), 1443 vtophys(((struct fwohcidb_tr *) 1444 (dbch->xferq.stdma->start))->db) | dbch->ndesc); 1445 if(dbch->xferq.flag & FWXFERQ_DV){ 1446 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma->start; 1447 fp = (struct fw_pkt *)db_tr->buf; 1448 fp->mode.ld[2] = htonl(0x80000000 + 1449 ((fc->cyctimer(fc) + 0x3000) & 0xf000)); 1450 } 1451 1452 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN); 1453 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT); 1454 } 1455 return err; 1456} 1457 1458static int 1459fwohci_irxbuf_enable(struct firewire_comm *fc, int dmach) 1460{ 1461 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1462 int err = 0; 1463 unsigned short tag, ich; 1464 tag = (sc->ir[dmach].xferq.flag >> 6) & 3; 1465 ich = sc->ir[dmach].xferq.flag & 0x3f; 1466 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich); 1467 1468 if(!(sc->ir[dmach].xferq.flag & FWXFERQ_RUNNING)){ 1469 sc->ir[dmach].xferq.queued = 0; 1470 sc->ir[dmach].ndb = sc->ir[dmach].xferq.bnpacket * 1471 sc->ir[dmach].xferq.bnchunk; 1472 sc->ir[dmach].dummy = 1473 malloc(sizeof(u_int32_t) * sc->ir[dmach].ndb, 1474 M_DEVBUF, M_DONTWAIT); 1475 if(sc->ir[dmach].dummy == NULL){ 1476 err = ENOMEM; 1477 return err; 1478 } 1479 sc->ir[dmach].ndesc = 2; 1480 fwohci_db_init(&sc->ir[dmach]); 1481 err = fwohci_rx_enable(sc, &sc->ir[dmach]); 1482 } 1483 if(err) 1484 return err; 1485 1486 if(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE){ 1487 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1488 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1489 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1490 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1491 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1492 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1493 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[0].db.desc.depend &= ~0xf; 1494 } 1495 }else if(!(OREAD(sc, OHCI_IRCTL(dmach)) & OHCI_CNTL_DMA_ACTIVE) 1496 && !(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET)){ 1497 fw_rbuf_update(&sc->fc, dmach, 0); 1498 1499 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN); 1500 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach); 1501 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach); 1502 OWRITE(sc, OHCI_IR_MASK, 1 << dmach); 1503 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000); 1504 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR); 1505 if(sc->ir[dmach].xferq.stdma2 != NULL){ 1506 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend = 1507 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db) | sc->ir[dmach].ndesc; 1508 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend = 1509 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->start))->db); 1510 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma2->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1511 }else{ 1512 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[sc->ir[dmach].ndesc - 1].db.desc.depend &= ~0xf; 1513 ((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->end))->db[0].db.desc.depend &= ~0xf; 1514 } 1515 OWRITE(sc, OHCI_IRCMD(dmach), 1516 vtophys(((struct fwohcidb_tr *)(sc->ir[dmach].xferq.stdma->start))->db) | sc->ir[dmach].ndesc); 1517 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN); 1518 } 1519 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR); 1520 return err; 1521} 1522 1523static int 1524fwohci_irx_enable(struct firewire_comm *fc, int dmach) 1525{ 1526 struct fwohci_softc *sc = (struct fwohci_softc *)fc; 1527 int err = 0; 1528 1529 if(sc->ir[dmach].xferq.flag & FWXFERQ_PACKET){ 1530 err = fwohci_irxpp_enable(fc, dmach); 1531 return err; 1532 }else{ 1533 err = fwohci_irxbuf_enable(fc, dmach); 1534 return err; 1535 } 1536} 1537 1538int
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1529fwohci_shutdown(device_t dev)
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1539fwohci_shutdown(struct fwohci_softc *sc, device_t dev) |
1540{ 1541 u_int i;
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1532 struct fwohci_softc *sc = device_get_softc(dev);
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1542 1543/* Now stopping all DMA channel */ 1544 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN); 1545 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN); 1546 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1547 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1548 1549 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){ 1550 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1551 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1552 } 1553 1554/* FLUSH FIFO and reset Transmitter/Reciever */ 1555 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET); 1556 1557/* Stop interrupt */ 1558 OWRITE(sc, FWOHCI_INTMASKCLR, 1559 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID 1560 | OHCI_INT_PHY_INT 1561 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS 1562 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS 1563 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS 1564 | OHCI_INT_PHY_BUS_R);
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1565/* XXX Link down? Bus reset? */ |
1566 return 0; 1567} 1568
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1569int 1570fwohci_resume(struct fwohci_softc *sc, device_t dev) 1571{ 1572 int i; 1573 1574 fwohci_reset(sc, dev); 1575 /* XXX resume isochronus receive automatically. (how about TX?) */ 1576 for(i = 0; i < sc->fc.nisodma; i ++) { 1577 if((sc->ir[i].xferq.flag & FWXFERQ_RUNNING) != 0) { 1578 device_printf(sc->fc.dev, 1579 "resume iso receive ch: %d\n", i); 1580 sc->ir[i].xferq.flag &= ~FWXFERQ_RUNNING; 1581 sc->fc.irx_enable(&sc->fc, i); 1582 } 1583 } 1584 1585 bus_generic_resume(dev); 1586 sc->fc.ibr(&sc->fc); 1587 return 0; 1588} 1589 |
1590#define ACK_ALL 1591static void 1592fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count) 1593{ 1594 u_int32_t irstat, itstat; 1595 u_int i; 1596 struct firewire_comm *fc = (struct firewire_comm *)sc; 1597 1598#ifdef OHCI_DEBUG 1599 if(stat & OREAD(sc, FWOHCI_INTMASK)) 1600 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n", 1601 stat & OHCI_INT_EN ? "DMA_EN ":"", 1602 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"", 1603 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"", 1604 stat & OHCI_INT_ERR ? "INT_ERR ":"", 1605 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"", 1606 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"", 1607 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"", 1608 stat & OHCI_INT_CYC_START ? "CYC_START ":"", 1609 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"", 1610 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"", 1611 stat & OHCI_INT_PHY_SID ? "SID ":"", 1612 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"", 1613 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"", 1614 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"", 1615 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"", 1616 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"", 1617 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"", 1618 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"", 1619 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"", 1620 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"", 1621 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"", 1622 stat, OREAD(sc, FWOHCI_INTMASK) 1623 ); 1624#endif 1625/* Bus reset */ 1626 if(stat & OHCI_INT_PHY_BUS_R ){ 1627 device_printf(fc->dev, "BUS reset\n"); 1628 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST); 1629 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC); 1630 1631 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN); 1632 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING; 1633 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN); 1634 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING; 1635 1636#if 0 1637 for( i = 0 ; i < fc->nisodma ; i ++ ){ 1638 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN); 1639 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN); 1640 } 1641 1642#endif 1643 fw_busreset(fc); 1644 1645 /* XXX need to wait DMA to stop */ 1646#ifndef ACK_ALL 1647 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R); 1648#endif 1649#if 1 1650 /* pending all pre-bus_reset packets */ 1651 fwohci_txd(sc, &sc->atrq); 1652 fwohci_txd(sc, &sc->atrs); 1653 fwohci_arcv(sc, &sc->arrs, -1); 1654 fwohci_arcv(sc, &sc->arrq, -1); 1655#endif 1656 1657 1658 OWRITE(sc, OHCI_AREQHI, 1 << 31); 1659 /* XXX insecure ?? */ 1660 OWRITE(sc, OHCI_PREQHI, 0x7fffffff); 1661 OWRITE(sc, OHCI_PREQLO, 0xffffffff); 1662 OWRITE(sc, OHCI_PREQUPPER, 0x10000); 1663 1664 } 1665 if((stat & OHCI_INT_DMA_IR )){ 1666#ifndef ACK_ALL 1667 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR); 1668#endif 1669 irstat = OREAD(sc, OHCI_IR_STAT); 1670 OWRITE(sc, OHCI_IR_STATCLR, ~0); 1671 for(i = 0; i < fc->nisodma ; i++){ 1672 if((irstat & (1 << i)) != 0){ 1673 if(sc->ir[i].xferq.flag & FWXFERQ_PACKET){ 1674 fwohci_ircv(sc, &sc->ir[i], count); 1675 }else{ 1676 fwohci_rbuf_update(sc, i); 1677 } 1678 } 1679 } 1680 } 1681 if((stat & OHCI_INT_DMA_IT )){ 1682#ifndef ACK_ALL 1683 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT); 1684#endif 1685 itstat = OREAD(sc, OHCI_IT_STAT); 1686 OWRITE(sc, OHCI_IT_STATCLR, ~0); 1687 for(i = 0; i < fc->nisodma ; i++){ 1688 if((itstat & (1 << i)) != 0){ 1689 fwohci_tbuf_update(sc, i); 1690 } 1691 } 1692 } 1693 if((stat & OHCI_INT_DMA_PRRS )){ 1694#ifndef ACK_ALL 1695 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS); 1696#endif 1697#if 0 1698 dump_dma(sc, ARRS_CH); 1699 dump_db(sc, ARRS_CH); 1700#endif 1701 fwohci_arcv(sc, &sc->arrs, count); 1702 } 1703 if((stat & OHCI_INT_DMA_PRRQ )){ 1704#ifndef ACK_ALL 1705 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ); 1706#endif 1707#if 0 1708 dump_dma(sc, ARRQ_CH); 1709 dump_db(sc, ARRQ_CH); 1710#endif 1711 fwohci_arcv(sc, &sc->arrq, count); 1712 } 1713 if(stat & OHCI_INT_PHY_SID){ 1714 caddr_t buf; 1715 int plen; 1716 1717#ifndef ACK_ALL 1718 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID); 1719#endif 1720/* 1721** Checking whether the node is root or not. If root, turn on 1722** cycle master. 1723*/ 1724 device_printf(fc->dev, "node_id = 0x%08x, ", OREAD(sc, FWOHCI_NODEID)); 1725 if(!(OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_VALID)){ 1726 printf("Bus reset failure\n"); 1727 goto sidout; 1728 } 1729 if( OREAD(sc, FWOHCI_NODEID) & OHCI_NODE_ROOT ){ 1730 printf("CYCLEMASTER mode\n"); 1731 OWRITE(sc, OHCI_LNKCTL, 1732 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER); 1733 }else{ 1734 printf("non CYCLEMASTER mode\n"); 1735 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR); 1736 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER); 1737 } 1738 fc->nodeid = OREAD(sc, FWOHCI_NODEID) & 0x3f; 1739 1740 plen = OREAD(sc, OHCI_SID_CNT) & OHCI_SID_CNT_MASK; 1741 plen -= 4; /* chop control info */ 1742 buf = malloc( FWPMAX_S400, M_DEVBUF, M_NOWAIT); 1743 if(buf == NULL) goto sidout; 1744 bcopy((void *)(uintptr_t)(volatile void *)(fc->sid_buf + 1), 1745 buf, plen); 1746 fw_sidrcv(fc, buf, plen, 0); 1747 } 1748sidout: 1749 if((stat & OHCI_INT_DMA_ATRQ )){ 1750#ifndef ACK_ALL 1751 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ); 1752#endif 1753 fwohci_txd(sc, &(sc->atrq)); 1754 } 1755 if((stat & OHCI_INT_DMA_ATRS )){ 1756#ifndef ACK_ALL 1757 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS); 1758#endif 1759 fwohci_txd(sc, &(sc->atrs)); 1760 } 1761 if((stat & OHCI_INT_PW_ERR )){ 1762#ifndef ACK_ALL 1763 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR); 1764#endif 1765 device_printf(fc->dev, "posted write error\n"); 1766 } 1767 if((stat & OHCI_INT_ERR )){ 1768#ifndef ACK_ALL 1769 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR); 1770#endif 1771 device_printf(fc->dev, "unrecoverable error\n"); 1772 } 1773 if((stat & OHCI_INT_PHY_INT)) { 1774#ifndef ACK_ALL 1775 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT); 1776#endif 1777 device_printf(fc->dev, "phy int\n"); 1778 } 1779 1780 return; 1781} 1782 1783void 1784fwohci_intr(void *arg) 1785{ 1786 struct fwohci_softc *sc = (struct fwohci_softc *)arg; 1787 u_int32_t stat; 1788 1789 if (!(sc->intmask & OHCI_INT_EN)) { 1790 /* polling mode */ 1791 return; 1792 } 1793 1794 while ((stat = OREAD(sc, FWOHCI_INTSTAT)) != 0) { 1795 if (stat == 0xffffffff) { 1796 device_printf(sc->fc.dev, 1797 "device physically ejected?\n"); 1798 return; 1799 } 1800#ifdef ACK_ALL 1801 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1802#endif 1803 fwohci_intr_body(sc, stat, -1); 1804 } 1805} 1806 1807static void 1808fwohci_poll(struct firewire_comm *fc, int quick, int count) 1809{ 1810 int s; 1811 u_int32_t stat; 1812 struct fwohci_softc *sc; 1813 1814 1815 sc = (struct fwohci_softc *)fc; 1816 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT | 1817 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ | 1818 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS; 1819#if 0 1820 if (!quick) { 1821#else 1822 if (1) { 1823#endif 1824 stat = OREAD(sc, FWOHCI_INTSTAT); 1825 if (stat == 0) 1826 return; 1827 if (stat == 0xffffffff) { 1828 device_printf(sc->fc.dev, 1829 "device physically ejected?\n"); 1830 return; 1831 } 1832#ifdef ACK_ALL 1833 OWRITE(sc, FWOHCI_INTSTATCLR, stat); 1834#endif 1835 } 1836 s = splfw(); 1837 fwohci_intr_body(sc, stat, count); 1838 splx(s); 1839} 1840 1841static void 1842fwohci_set_intr(struct firewire_comm *fc, int enable) 1843{ 1844 struct fwohci_softc *sc; 1845 1846 sc = (struct fwohci_softc *)fc; 1847 if (bootverbose)
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1817 device_printf(sc->fc.dev, "fwochi_set_intr: %d\n", enable);
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1848 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable); |
1849 if (enable) { 1850 sc->intmask |= OHCI_INT_EN; 1851 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN); 1852 } else { 1853 sc->intmask &= ~OHCI_INT_EN; 1854 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN); 1855 } 1856} 1857 1858static void 1859fwohci_tbuf_update(struct fwohci_softc *sc, int dmach) 1860{ 1861 int stat; 1862 struct firewire_comm *fc = &sc->fc; 1863 struct fw_pkt *fp; 1864 struct fwohci_dbch *dbch; 1865 struct fwohcidb_tr *db_tr; 1866 1867 dbch = &sc->it[dmach]; 1868 if((dbch->xferq.flag & FWXFERQ_DV) && (dbch->xferq.stdma2 != NULL)){ 1869 db_tr = (struct fwohcidb_tr *)dbch->xferq.stdma2->start; 1870/* 1871 * Overwrite highest significant 4 bits timestamp information 1872 */ 1873 fp = (struct fw_pkt *)db_tr->buf; 1874 fp->mode.ld[2] |= htonl(0x80000000 | 1875 ((fc->cyctimer(fc) + 0x4000) & 0xf000)); 1876 } 1877 stat = OREAD(sc, OHCI_ITCTL(dmach)) & 0x1f; 1878 switch(stat){ 1879 case FWOHCIEV_ACKCOMPL: 1880 fw_tbuf_update(fc, dmach, 1); 1881 break; 1882 default: 1883 fw_tbuf_update(fc, dmach, 0); 1884 break; 1885 } 1886 fwohci_itxbuf_enable(&sc->fc, dmach); 1887} 1888 1889static void 1890fwohci_rbuf_update(struct fwohci_softc *sc, int dmach) 1891{ 1892 int stat; 1893 stat = OREAD(sc, OHCI_IRCTL(dmach)) & 0x1f; 1894 switch(stat){ 1895 case FWOHCIEV_ACKCOMPL: 1896 fw_rbuf_update(&sc->fc, dmach, 1); 1897 wakeup(sc->fc.ir[dmach]); 1898 fwohci_irx_enable(&sc->fc, dmach); 1899 break; 1900 default: 1901 break; 1902 } 1903} 1904 1905void 1906dump_dma(struct fwohci_softc *sc, u_int32_t ch) 1907{ 1908 u_int32_t off, cntl, stat, cmd, match; 1909 1910 if(ch == 0){ 1911 off = OHCI_ATQOFF; 1912 }else if(ch == 1){ 1913 off = OHCI_ATSOFF; 1914 }else if(ch == 2){ 1915 off = OHCI_ARQOFF; 1916 }else if(ch == 3){ 1917 off = OHCI_ARSOFF; 1918 }else if(ch < IRX_CH){ 1919 off = OHCI_ITCTL(ch - ITX_CH); 1920 }else{ 1921 off = OHCI_IRCTL(ch - IRX_CH); 1922 } 1923 cntl = stat = OREAD(sc, off); 1924 cmd = OREAD(sc, off + 0xc); 1925 match = OREAD(sc, off + 0x10); 1926 1927 device_printf(sc->fc.dev, "dma ch %1x:dma regs 0x%08x 0x%08x 0x%08x 0x%08x \n", 1928 ch, 1929 cntl, 1930 stat, 1931 cmd, 1932 match); 1933 stat &= 0xffff ; 1934 if(stat & 0xff00){ 1935 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n", 1936 ch, 1937 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 1938 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 1939 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 1940 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 1941 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 1942 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 1943 fwohcicode[stat & 0x1f], 1944 stat & 0x1f 1945 ); 1946 }else{ 1947 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch); 1948 } 1949} 1950 1951void 1952dump_db(struct fwohci_softc *sc, u_int32_t ch) 1953{ 1954 struct fwohci_dbch *dbch; 1955 struct fwohcidb_tr *cp = NULL, *pp, *np; 1956 volatile struct fwohcidb *curr = NULL, *prev, *next = NULL; 1957 int idb, jdb; 1958 u_int32_t cmd, off; 1959 if(ch == 0){ 1960 off = OHCI_ATQOFF; 1961 dbch = &sc->atrq; 1962 }else if(ch == 1){ 1963 off = OHCI_ATSOFF; 1964 dbch = &sc->atrs; 1965 }else if(ch == 2){ 1966 off = OHCI_ARQOFF; 1967 dbch = &sc->arrq; 1968 }else if(ch == 3){ 1969 off = OHCI_ARSOFF; 1970 dbch = &sc->arrs; 1971 }else if(ch < IRX_CH){ 1972 off = OHCI_ITCTL(ch - ITX_CH); 1973 dbch = &sc->it[ch - ITX_CH]; 1974 }else { 1975 off = OHCI_IRCTL(ch - IRX_CH); 1976 dbch = &sc->ir[ch - IRX_CH]; 1977 } 1978 cmd = OREAD(sc, off + 0xc); 1979 1980 if( dbch->ndb == 0 ){ 1981 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch); 1982 return; 1983 } 1984 pp = dbch->top; 1985 prev = pp->db; 1986 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){ 1987 if(pp == NULL){ 1988 curr = NULL; 1989 goto outdb; 1990 } 1991 cp = STAILQ_NEXT(pp, link); 1992 if(cp == NULL){ 1993 curr = NULL; 1994 goto outdb; 1995 } 1996 np = STAILQ_NEXT(cp, link); 1997 if(cp == NULL) break; 1998 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){ 1999 if((cmd & 0xfffffff0) 2000 == vtophys(&(cp->db[jdb]))){ 2001 curr = cp->db; 2002 if(np != NULL){ 2003 next = np->db; 2004 }else{ 2005 next = NULL; 2006 } 2007 goto outdb; 2008 } 2009 } 2010 pp = STAILQ_NEXT(pp, link); 2011 prev = pp->db; 2012 } 2013outdb: 2014 if( curr != NULL){ 2015 printf("Prev DB %d\n", ch); 2016 print_db(prev, ch, dbch->ndesc); 2017 printf("Current DB %d\n", ch); 2018 print_db(curr, ch, dbch->ndesc); 2019 printf("Next DB %d\n", ch); 2020 print_db(next, ch, dbch->ndesc); 2021 }else{ 2022 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd); 2023 } 2024 return; 2025} 2026 2027void 2028print_db(volatile struct fwohcidb *db, u_int32_t ch, u_int32_t max) 2029{ 2030 fwohcireg_t stat; 2031 int i, key; 2032 2033 if(db == NULL){ 2034 printf("No Descriptor is found\n"); 2035 return; 2036 } 2037 2038 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n", 2039 ch, 2040 "Current", 2041 "OP ", 2042 "KEY", 2043 "INT", 2044 "BR ", 2045 "len", 2046 "Addr", 2047 "Depend", 2048 "Stat", 2049 "Cnt"); 2050 for( i = 0 ; i <= max ; i ++){ 2051 key = db[i].db.desc.cmd & OHCI_KEY_MASK; 2052 printf("%08tx %s %s %s %s %5d %08x %08x %04x:%04x", 2053 vtophys(&db[i]), 2054 dbcode[(db[i].db.desc.cmd >> 28) & 0xf], 2055 dbkey[(db[i].db.desc.cmd >> 24) & 0x7], 2056 dbcond[(db[i].db.desc.cmd >> 20) & 0x3], 2057 dbcond[(db[i].db.desc.cmd >> 18) & 0x3], 2058 db[i].db.desc.cmd & 0xffff, 2059 db[i].db.desc.addr, 2060 db[i].db.desc.depend, 2061 db[i].db.desc.status, 2062 db[i].db.desc.count); 2063 stat = db[i].db.desc.status; 2064 if(stat & 0xff00){ 2065 printf(" %s%s%s%s%s%s %s(%x)\n", 2066 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "", 2067 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "", 2068 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "", 2069 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "", 2070 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "", 2071 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "", 2072 fwohcicode[stat & 0x1f], 2073 stat & 0x1f 2074 ); 2075 }else{ 2076 printf(" Nostat\n"); 2077 } 2078 if(key == OHCI_KEY_ST2 ){ 2079 printf("0x%08x 0x%08x 0x%08x 0x%08x\n", 2080 db[i+1].db.immed[0], 2081 db[i+1].db.immed[1], 2082 db[i+1].db.immed[2], 2083 db[i+1].db.immed[3]); 2084 } 2085 if(key == OHCI_KEY_DEVICE){ 2086 return; 2087 } 2088 if((db[i].db.desc.cmd & OHCI_BRANCH_MASK) 2089 == OHCI_BRANCH_ALWAYS){ 2090 return; 2091 } 2092 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2093 == OHCI_OUTPUT_LAST){ 2094 return; 2095 } 2096 if((db[i].db.desc.cmd & OHCI_CMD_MASK) 2097 == OHCI_INPUT_LAST){ 2098 return; 2099 } 2100 if(key == OHCI_KEY_ST2 ){ 2101 i++; 2102 } 2103 } 2104 return; 2105} 2106 2107void 2108fwohci_ibr(struct firewire_comm *fc) 2109{ 2110 struct fwohci_softc *sc; 2111 u_int32_t fun; 2112 2113 sc = (struct fwohci_softc *)fc; 2114 2115 /* 2116 * Set root hold-off bit so that non cyclemaster capable node 2117 * shouldn't became the root node. 2118 */ 2119 fun = fwphy_rddata(sc, FW_PHY_RHB_REG); 2120 fun |= FW_PHY_RHB; 2121 fun = fwphy_wrdata(sc, FW_PHY_RHB_REG, fun); 2122#if 1 2123 fun = fwphy_rddata(sc, FW_PHY_IBR_REG); 2124 fun |= FW_PHY_IBR; 2125 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun); 2126#else 2127 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG); 2128 fun |= FW_PHY_ISBR; 2129 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun); 2130#endif 2131} 2132 2133void 2134fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer) 2135{ 2136 struct fwohcidb_tr *db_tr, *fdb_tr; 2137 struct fwohci_dbch *dbch; 2138 struct fw_pkt *fp; 2139 volatile struct fwohci_txpkthdr *ohcifp; 2140 unsigned short chtag; 2141 int idb; 2142 2143 dbch = &sc->it[dmach]; 2144 chtag = sc->it[dmach].xferq.flag & 0xff; 2145 2146 db_tr = (struct fwohcidb_tr *)(bulkxfer->start); 2147 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end); 2148/* 2149device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2150*/ 2151 if(bulkxfer->flag != 0){ 2152 return; 2153 } 2154 bulkxfer->flag = 1; 2155 for( idb = 0 ; idb < bulkxfer->npacket ; idb ++){ 2156 db_tr->db[0].db.desc.cmd 2157 = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2158 fp = (struct fw_pkt *)db_tr->buf; 2159 ohcifp = (volatile struct fwohci_txpkthdr *) 2160 db_tr->db[1].db.immed; 2161 ohcifp->mode.ld[0] = ntohl(fp->mode.ld[0]); 2162 ohcifp->mode.stream.len = ntohs(fp->mode.stream.len); 2163 ohcifp->mode.stream.chtag = chtag; 2164 ohcifp->mode.stream.tcode = 0xa; 2165 ohcifp->mode.stream.spd = 4; 2166 ohcifp->mode.ld[2] = ntohl(fp->mode.ld[1]); 2167 ohcifp->mode.ld[3] = ntohl(fp->mode.ld[2]); 2168 2169 db_tr->db[2].db.desc.cmd 2170 = OHCI_OUTPUT_LAST 2171 | OHCI_UPDATE 2172 | OHCI_BRANCH_ALWAYS 2173 | ((ntohs(fp->mode.stream.len) ) & 0xffff); 2174 db_tr->db[2].db.desc.status = 0; 2175 db_tr->db[2].db.desc.count = 0; 2176 if(dbch->xferq.flag & FWXFERQ_DV){ 2177 db_tr->db[0].db.desc.depend 2178 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2179 db_tr->db[dbch->ndesc - 1].db.desc.depend 2180 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2181 }else{ 2182 db_tr->db[0].db.desc.depend 2183 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2184 db_tr->db[dbch->ndesc - 1].db.desc.depend 2185 = vtophys(STAILQ_NEXT(db_tr, link)->db) | dbch->ndesc; 2186 } 2187 bulkxfer->end = (caddr_t)db_tr; 2188 db_tr = STAILQ_NEXT(db_tr, link); 2189 } 2190 db_tr = (struct fwohcidb_tr *)bulkxfer->end; 2191 db_tr->db[0].db.desc.depend &= ~0xf; 2192 db_tr->db[dbch->ndesc - 1].db.desc.depend &= ~0xf; 2193/**/ 2194 db_tr->db[dbch->ndesc - 1].db.desc.cmd &= ~OHCI_BRANCH_ALWAYS; 2195 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_BRANCH_NEVER; 2196/**/ 2197 db_tr->db[dbch->ndesc - 1].db.desc.cmd |= OHCI_INTERRUPT_ALWAYS; 2198 2199 db_tr = (struct fwohcidb_tr *)bulkxfer->start; 2200 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end; 2201/* 2202device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, vtophys(db_tr->db), vtophys(fdb_tr->db)); 2203*/ 2204 return; 2205} 2206 2207static int 2208fwohci_add_tx_buf(struct fwohcidb_tr *db_tr, unsigned short size, 2209 int mode, void *buf) 2210{ 2211 volatile struct fwohcidb *db = db_tr->db; 2212 int err = 0; 2213 if(buf == 0){ 2214 err = EINVAL; 2215 return err; 2216 } 2217 db_tr->buf = buf; 2218 db_tr->dbcnt = 3; 2219 db_tr->dummy = NULL; 2220 2221 db[0].db.desc.cmd = OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8; 2222 2223 db[2].db.desc.depend = 0; 2224 db[2].db.desc.addr = vtophys(buf) + sizeof(u_int32_t); 2225 db[2].db.desc.cmd = OHCI_OUTPUT_MORE; 2226 2227 db[0].db.desc.status = 0; 2228 db[0].db.desc.count = 0; 2229 2230 db[2].db.desc.status = 0; 2231 db[2].db.desc.count = 0; 2232 if( mode & FWXFERQ_STREAM ){ 2233 db[2].db.desc.cmd |= OHCI_OUTPUT_LAST; 2234 if(mode & FWXFERQ_PACKET ){ 2235 db[2].db.desc.cmd 2236 |= OHCI_INTERRUPT_ALWAYS; 2237 } 2238 } 2239 db[2].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2240 return 1; 2241} 2242 2243int 2244fwohci_add_rx_buf(struct fwohcidb_tr *db_tr, unsigned short size, int mode, 2245 void *buf, void *dummy) 2246{ 2247 volatile struct fwohcidb *db = db_tr->db; 2248 int i; 2249 void *dbuf[2]; 2250 int dsiz[2]; 2251 2252 if(buf == 0){ 2253 buf = malloc(size, M_DEVBUF, M_NOWAIT); 2254 if(buf == NULL) return 0; 2255 db_tr->buf = buf; 2256 db_tr->dbcnt = 1; 2257 db_tr->dummy = NULL; 2258 dsiz[0] = size; 2259 dbuf[0] = buf; 2260 }else if(dummy == NULL){ 2261 db_tr->buf = buf; 2262 db_tr->dbcnt = 1; 2263 db_tr->dummy = NULL; 2264 dsiz[0] = size; 2265 dbuf[0] = buf; 2266 }else{ 2267 db_tr->buf = buf; 2268 db_tr->dbcnt = 2; 2269 db_tr->dummy = dummy; 2270 dsiz[0] = sizeof(u_int32_t); 2271 dsiz[1] = size; 2272 dbuf[0] = dummy; 2273 dbuf[1] = buf; 2274 } 2275 for(i = 0 ; i < db_tr->dbcnt ; i++){ 2276 db[i].db.desc.addr = vtophys(dbuf[i]) ; 2277 db[i].db.desc.cmd = OHCI_INPUT_MORE | dsiz[i]; 2278 if( mode & FWXFERQ_STREAM ){ 2279 db[i].db.desc.cmd |= OHCI_UPDATE; 2280 } 2281 db[i].db.desc.status = 0; 2282 db[i].db.desc.count = dsiz[i]; 2283 } 2284 if( mode & FWXFERQ_STREAM ){ 2285 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_INPUT_LAST; 2286 if(mode & FWXFERQ_PACKET ){ 2287 db[db_tr->dbcnt - 1].db.desc.cmd 2288 |= OHCI_INTERRUPT_ALWAYS; 2289 } 2290 } 2291 db[db_tr->dbcnt - 1].db.desc.cmd |= OHCI_BRANCH_ALWAYS; 2292 return 1; 2293} 2294 2295static void 2296fwohci_ircv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2297{ 2298 struct fwohcidb_tr *db_tr = dbch->top, *odb_tr; 2299 struct firewire_comm *fc = (struct firewire_comm *)sc; 2300 int z = 1; 2301 struct fw_pkt *fp; 2302 u_int8_t *ld; 2303 u_int32_t off = NULL; 2304 u_int32_t stat; 2305 u_int32_t *qld; 2306 u_int32_t reg; 2307 u_int spd; 2308 u_int dmach; 2309 int len, i, plen; 2310 caddr_t buf; 2311 2312 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){ 2313 if( &sc->ir[dmach] == dbch){ 2314 off = OHCI_IROFF(dmach); 2315 break; 2316 } 2317 } 2318 if(off == NULL){ 2319 return; 2320 } 2321 if(!(dbch->xferq.flag & FWXFERQ_RUNNING)){ 2322 fwohci_irx_disable(&sc->fc, dmach); 2323 return; 2324 } 2325 2326 odb_tr = NULL; 2327 db_tr = dbch->top; 2328 i = 0; 2329 while ((reg = db_tr->db[0].db.desc.status) & 0x1f) { 2330 if (count >= 0 && count-- == 0) 2331 break; 2332 ld = (u_int8_t *)db_tr->buf; 2333 if (dbch->xferq.flag & FWXFERQ_PACKET) { 2334 /* skip timeStamp */ 2335 ld += sizeof(struct fwohci_trailer); 2336 } 2337 qld = (u_int32_t *)ld; 2338 len = dbch->xferq.psize - (db_tr->db[0].db.desc.count); 2339/* 2340{ 2341device_printf(sc->fc.dev, "%04x %2x 0x%08x 0x%08x 0x%08x 0x%08x\n", len, 2342 db_tr->db[0].db.desc.status & 0x1f, qld[0],qld[1],qld[2],qld[3]); 2343} 2344*/ 2345 fp=(struct fw_pkt *)ld; 2346 qld[0] = htonl(qld[0]); 2347 plen = sizeof(struct fw_isohdr) 2348 + ntohs(fp->mode.stream.len) + sizeof(u_int32_t); 2349 ld += plen; 2350 len -= plen; 2351 buf = db_tr->buf; 2352 db_tr->buf = NULL; 2353 stat = reg & 0x1f; 2354 spd = reg & 0x3; 2355 switch(stat){ 2356 case FWOHCIEV_ACKCOMPL: 2357 case FWOHCIEV_ACKPEND: 2358 fw_rcv(&sc->fc, buf, plen - sizeof(u_int32_t), dmach, sizeof(u_int32_t), spd); 2359 break; 2360 default: 2361 free(buf, M_DEVBUF); 2362 device_printf(sc->fc.dev, "Isochronous receive err %02x\n", stat); 2363 break; 2364 } 2365 i++; 2366 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2367 dbch->xferq.flag, 0, NULL); 2368 db_tr->db[0].db.desc.depend &= ~0xf; 2369 if(dbch->pdb_tr != NULL){ 2370 dbch->pdb_tr->db[0].db.desc.depend |= z; 2371 } else { 2372 /* XXX should be rewritten in better way */ 2373 dbch->bottom->db[0].db.desc.depend |= z; 2374 } 2375 dbch->pdb_tr = db_tr; 2376 db_tr = STAILQ_NEXT(db_tr, link); 2377 } 2378 dbch->top = db_tr; 2379 reg = OREAD(sc, OHCI_DMACTL(off)); 2380 if (reg & OHCI_CNTL_DMA_ACTIVE) 2381 return; 2382 device_printf(sc->fc.dev, "IR DMA %d stopped at %x status=%x (%d)\n", 2383 dmach, OREAD(sc, OHCI_DMACMD(off)), reg, i); 2384 dbch->top = db_tr; 2385 fwohci_irx_enable(fc, dmach); 2386} 2387 2388#define PLEN(x) (((ntohs(x))+0x3) & ~0x3) 2389static int 2390fwohci_get_plen(struct fwohci_softc *sc, struct fw_pkt *fp, int hlen) 2391{ 2392 int i; 2393 2394 for( i = 4; i < hlen ; i+=4){ 2395 fp->mode.ld[i/4] = htonl(fp->mode.ld[i/4]); 2396 } 2397 2398 switch(fp->mode.common.tcode){ 2399 case FWTCODE_RREQQ: 2400 return sizeof(fp->mode.rreqq) + sizeof(u_int32_t); 2401 case FWTCODE_WRES: 2402 return sizeof(fp->mode.wres) + sizeof(u_int32_t); 2403 case FWTCODE_WREQQ: 2404 return sizeof(fp->mode.wreqq) + sizeof(u_int32_t); 2405 case FWTCODE_RREQB: 2406 return sizeof(fp->mode.rreqb) + sizeof(u_int32_t); 2407 case FWTCODE_RRESQ: 2408 return sizeof(fp->mode.rresq) + sizeof(u_int32_t); 2409 case FWTCODE_WREQB: 2410 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.wreqb.len) 2411 + sizeof(u_int32_t); 2412 case FWTCODE_LREQ: 2413 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lreq.len) 2414 + sizeof(u_int32_t); 2415 case FWTCODE_RRESB: 2416 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.rresb.len) 2417 + sizeof(u_int32_t); 2418 case FWTCODE_LRES: 2419 return sizeof(struct fw_asyhdr) + PLEN(fp->mode.lres.len) 2420 + sizeof(u_int32_t); 2421 case FWOHCITCODE_PHY: 2422 return 16; 2423 } 2424 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2425 return 0; 2426} 2427 2428static void 2429fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count) 2430{ 2431 struct fwohcidb_tr *db_tr; 2432 int z = 1; 2433 struct fw_pkt *fp; 2434 u_int8_t *ld; 2435 u_int32_t stat, off; 2436 u_int spd; 2437 int len, plen, hlen, pcnt, poff = 0, rlen; 2438 int s; 2439 caddr_t buf; 2440 int resCount; 2441 2442 if(&sc->arrq == dbch){ 2443 off = OHCI_ARQOFF; 2444 }else if(&sc->arrs == dbch){ 2445 off = OHCI_ARSOFF; 2446 }else{ 2447 return; 2448 } 2449 2450 s = splfw(); 2451 db_tr = dbch->top; 2452 pcnt = 0; 2453 /* XXX we cannot handle a packet which lies in more than two buf */ 2454 while (db_tr->db[0].db.desc.status & OHCI_CNTL_DMA_ACTIVE) { 2455 ld = (u_int8_t *)db_tr->buf + dbch->buf_offset; 2456 resCount = db_tr->db[0].db.desc.count; 2457 len = dbch->xferq.psize - resCount 2458 - dbch->buf_offset; 2459 while (len > 0 ) { 2460 if (count >= 0 && count-- == 0) 2461 goto out; 2462 if(dbch->frag.buf != NULL){ 2463 buf = dbch->frag.buf; 2464 if (dbch->frag.plen < 0) { 2465 /* incomplete header */ 2466 int hlen; 2467 2468 hlen = - dbch->frag.plen; 2469 rlen = hlen - dbch->frag.len; 2470 bcopy(ld, dbch->frag.buf + dbch->frag.len, rlen); 2471 ld += rlen; 2472 len -= rlen; 2473 dbch->frag.len += rlen; 2474#if 0 2475 printf("(1)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2476#endif 2477 fp=(struct fw_pkt *)dbch->frag.buf; 2478 dbch->frag.plen 2479 = fwohci_get_plen(sc, fp, hlen); 2480 if (dbch->frag.plen == 0) 2481 goto out; 2482 } 2483 rlen = dbch->frag.plen - dbch->frag.len; 2484#if 0 2485 printf("(2)frag.plen=%d frag.len=%d rlen=%d len=%d\n", dbch->frag.plen, dbch->frag.len, rlen, len); 2486#endif 2487 bcopy(ld, dbch->frag.buf + dbch->frag.len, 2488 rlen); 2489 ld += rlen; 2490 len -= rlen; 2491 plen = dbch->frag.plen; 2492 dbch->frag.buf = NULL; 2493 dbch->frag.plen = 0; 2494 dbch->frag.len = 0; 2495 poff = 0; 2496 }else{ 2497 fp=(struct fw_pkt *)ld; 2498 fp->mode.ld[0] = htonl(fp->mode.ld[0]); 2499 switch(fp->mode.common.tcode){ 2500 case FWTCODE_RREQQ: 2501 case FWTCODE_WRES: 2502 case FWTCODE_WREQQ: 2503 case FWTCODE_RRESQ: 2504 case FWOHCITCODE_PHY: 2505 hlen = 12; 2506 break; 2507 case FWTCODE_RREQB: 2508 case FWTCODE_WREQB: 2509 case FWTCODE_LREQ: 2510 case FWTCODE_RRESB: 2511 case FWTCODE_LRES: 2512 hlen = 16; 2513 break; 2514 default: 2515 device_printf(sc->fc.dev, "Unknown tcode %d\n", fp->mode.common.tcode); 2516 goto out; 2517 } 2518 if (len >= hlen) { 2519 plen = fwohci_get_plen(sc, fp, hlen); 2520 if (plen == 0) 2521 goto out; 2522 plen = (plen + 3) & ~3; 2523 len -= plen; 2524 } else { 2525 plen = -hlen; 2526 len -= hlen; 2527 } 2528 if(resCount > 0 || len > 0){ 2529 buf = malloc( dbch->xferq.psize, 2530 M_DEVBUF, M_NOWAIT); 2531 if(buf == NULL){ 2532 printf("cannot malloc!\n"); 2533 free(db_tr->buf, M_DEVBUF); 2534 goto out; 2535 } 2536 bcopy(ld, buf, plen); 2537 poff = 0; 2538 dbch->frag.buf = NULL; 2539 dbch->frag.plen = 0; 2540 dbch->frag.len = 0; 2541 }else if(len < 0){ 2542 dbch->frag.buf = db_tr->buf; 2543 if (plen < 0) { 2544#if 0 2545 printf("plen < 0:" 2546 "hlen: %d len: %d\n", 2547 hlen, len); 2548#endif 2549 dbch->frag.len = hlen + len; 2550 dbch->frag.plen = -hlen; 2551 } else { 2552 dbch->frag.len = plen + len; 2553 dbch->frag.plen = plen; 2554 } 2555 bcopy(ld, db_tr->buf, dbch->frag.len); 2556 buf = NULL; 2557 }else{ 2558 buf = db_tr->buf; 2559 poff = ld - (u_int8_t *)buf; 2560 dbch->frag.buf = NULL; 2561 dbch->frag.plen = 0; 2562 dbch->frag.len = 0; 2563 } 2564 ld += plen; 2565 } 2566 if( buf != NULL){ 2567/* DMA result-code will be written at the tail of packet */ 2568 stat = ((struct fwohci_trailer *)(ld - sizeof(struct fwohci_trailer)))->stat; 2569 spd = (stat >> 5) & 0x3; 2570 stat &= 0x1f; 2571 switch(stat){ 2572 case FWOHCIEV_ACKPEND: 2573#if 0 2574 printf("fwohci_arcv: ack pending..\n"); 2575#endif 2576 /* fall through */ 2577 case FWOHCIEV_ACKCOMPL: 2578 if( poff != 0 ) 2579 bcopy(buf+poff, buf, plen - 4); 2580 fw_rcv(&sc->fc, buf, plen - sizeof(struct fwohci_trailer), 0, 0, spd); 2581 break; 2582 case FWOHCIEV_BUSRST: 2583 free(buf, M_DEVBUF); 2584 if (sc->fc.status != FWBUSRESET) 2585 printf("got BUSRST packet!?\n"); 2586 break; 2587 default: 2588 device_printf(sc->fc.dev, "Async DMA Receive error err = %02x %s\n", stat, fwohcicode[stat]); 2589#if 0 /* XXX */ 2590 goto out; 2591#endif 2592 break; 2593 } 2594 } 2595 pcnt ++; 2596 }; 2597out: 2598 if (resCount == 0) { 2599 /* done on this buffer */ 2600 fwohci_add_rx_buf(db_tr, dbch->xferq.psize, 2601 dbch->xferq.flag, 0, NULL); 2602 dbch->bottom->db[0].db.desc.depend |= z; 2603 dbch->bottom = db_tr; 2604 db_tr = STAILQ_NEXT(db_tr, link); 2605 dbch->top = db_tr; 2606 dbch->buf_offset = 0; 2607 } else { 2608 dbch->buf_offset = dbch->xferq.psize - resCount; 2609 break; 2610 } 2611 /* XXX make sure DMA is not dead */ 2612 } 2613#if 0 2614 if (pcnt < 1) 2615 printf("fwohci_arcv: no packets\n"); 2616#endif 2617 splx(s); 2618}
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