1/*
2 * Copyright (c) 2001-2003
3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus).
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Author: Hartmut Brandt <harti@freebsd.org>
28 *
29 * Fore PCA200E driver for NATM
30 */
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/fatm/if_fatm.c 118168 2003-07-29 14:00:59Z harti $");
33
34#include "opt_inet.h"
35#include "opt_natm.h"
36
37#include <sys/types.h>
38#include <sys/param.h>
39#include <sys/systm.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/bus.h>
43#include <sys/errno.h>
44#include <sys/conf.h>
45#include <sys/module.h>
46#include <sys/queue.h>
47#include <sys/syslog.h>
48#include <sys/endian.h>
49#include <sys/sysctl.h>
50#include <sys/condvar.h>
51
52#include <sys/sockio.h>
53#include <sys/mbuf.h>
54#include <sys/socket.h>
55
56#include <net/if.h>
57#include <net/if_media.h>
58#include <net/if_atm.h>
59#include <net/route.h>
60#ifdef INET
61#include <netinet/in.h>
62#include <netinet/if_atm.h>
63#endif
64
65#include <machine/bus.h>
66#include <machine/resource.h>
67#include <sys/bus.h>
68#include <sys/rman.h>
69#include <pci/pcireg.h>
70#include <pci/pcivar.h>
71
72#include <dev/utopia/utopia.h>
73
74#include <dev/fatm/if_fatmreg.h>
75#include <dev/fatm/if_fatmvar.h>
76
77#include <dev/fatm/firmware.h>
78
79devclass_t fatm_devclass;
80
81static const struct {
82 uint16_t vid;
83 uint16_t did;
84 const char *name;
85} fatm_devs[] = {
86 { 0x1127, 0x300,
87 "FORE PCA200E" },
88 { 0, 0, NULL }
89};
90
91static const struct rate {
92 uint32_t ratio;
93 uint32_t cell_rate;
94} rate_table[] = {
95#include <dev/fatm/if_fatm_rate.h>
96};
97#define RATE_TABLE_SIZE (sizeof(rate_table) / sizeof(rate_table[0]))
98
99SYSCTL_DECL(_hw_atm);
100
101MODULE_DEPEND(fatm, utopia, 1, 1, 1);
102
103static int fatm_utopia_readregs(struct ifatm *, u_int, uint8_t *, u_int *);
104static int fatm_utopia_writereg(struct ifatm *, u_int, u_int, u_int);
105
106static const struct utopia_methods fatm_utopia_methods = {
107 fatm_utopia_readregs,
108 fatm_utopia_writereg
109};
110
111#define VC_OK(SC, VPI, VCI) \
112 (((VPI) & ~((1 << (SC)->ifatm.mib.vpi_bits) - 1)) == 0 && \
113 (VCI) != 0 && ((VCI) & ~((1 << (SC)->ifatm.mib.vci_bits) - 1)) == 0)
114
115/*
116 * Probing is easy: step trough the list of known vendor and device
117 * ids and compare. If one is found - it's our.
118 */
119static int
120fatm_probe(device_t dev)
121{
122 int i;
123
124 for (i = 0; fatm_devs[i].name; i++)
125 if (pci_get_vendor(dev) == fatm_devs[i].vid &&
126 pci_get_device(dev) == fatm_devs[i].did) {
127 device_set_desc(dev, fatm_devs[i].name);
128 return (0);
129 }
130 return (ENXIO);
131}
132
133/*
134 * Function called at completion of a SUNI writeregs/readregs command.
135 * This is called from the interrupt handler while holding the softc lock.
136 * We use the queue entry as the randevouze point.
137 */
138static void
139fatm_utopia_writeregs_complete(struct fatm_softc *sc, struct cmdqueue *q)
140{
141
142 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
143 if(H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
144 sc->istats.suni_reg_errors++;
145 q->error = EIO;
146 }
147 wakeup(q);
148}
149
150/*
151 * Write a SUNI register. The bits that are 1 in mask are written from val
152 * into register reg. We wait for the command to complete by sleeping on
153 * the register memory.
154 *
155 * We assume, that we already hold the softc mutex.
156 */
157static int
158fatm_utopia_writereg(struct ifatm *ifatm, u_int reg, u_int mask, u_int val)
159{
160 int error;
161 struct cmdqueue *q;
162 struct fatm_softc *sc;
163
164 sc = ifatm->ifnet.if_softc;
165 FATM_CHECKLOCK(sc);
166 if (!(ifatm->ifnet.if_flags & IFF_RUNNING))
167 return (EIO);
168
169 /* get queue element and fill it */
170 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, sc->cmdqueue.head);
171
172 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
173 if (!(H_GETSTAT(q->q.statp) & FATM_STAT_FREE)) {
174 sc->istats.cmd_queue_full++;
175 return (EIO);
176 }
177 NEXT_QUEUE_ENTRY(sc->cmdqueue.head, FATM_CMD_QLEN);
178
179 q->error = 0;
180 q->cb = fatm_utopia_writeregs_complete;
181 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
182 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
183
184 WRITE4(sc, q->q.card + FATMOC_GETOC3_BUF, 0);
185 BARRIER_W(sc);
186 WRITE4(sc, q->q.card + FATMOC_OP,
187 FATM_MAKE_SETOC3(reg, val, mask) | FATM_OP_INTERRUPT_SEL);
188 BARRIER_W(sc);
189
190 /*
191 * Wait for the command to complete
192 */
193 error = msleep(q, &sc->mtx, PZERO | PCATCH, "fatm_setreg", hz);
194
195 switch(error) {
196
197 case EWOULDBLOCK:
198 error = EIO;
199 break;
200
201 case ERESTART:
202 error = EINTR;
203 break;
204
205 case 0:
206 error = q->error;
207 break;
208 }
209
210 return (error);
211}
212
213/*
214 * Function called at completion of a SUNI readregs command.
215 * This is called from the interrupt handler while holding the softc lock.
216 * We use reg_mem as the randevouze point.
217 */
218static void
219fatm_utopia_readregs_complete(struct fatm_softc *sc, struct cmdqueue *q)
220{
221
222 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
223 if (H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
224 sc->istats.suni_reg_errors++;
225 q->error = EIO;
226 }
227 wakeup(&sc->reg_mem);
228}
229
230/*
231 * Read SUNI registers
232 *
233 * We use a preallocated buffer to read the registers. Therefor we need
234 * to protect against multiple threads trying to read registers. We do this
235 * with a condition variable and a flag. We wait for the command to complete by sleeping on
236 * the register memory.
237 *
238 * We assume, that we already hold the softc mutex.
239 */
240static int
241fatm_utopia_readregs_internal(struct fatm_softc *sc)
242{
243 int error, i;
244 uint32_t *ptr;
245 struct cmdqueue *q;
246
247 /* get the buffer */
248 for (;;) {
249 if (!(sc->ifatm.ifnet.if_flags & IFF_RUNNING))
250 return (EIO);
251 if (!(sc->flags & FATM_REGS_INUSE))
252 break;
253 cv_wait(&sc->cv_regs, &sc->mtx);
254 }
255 sc->flags |= FATM_REGS_INUSE;
256
257 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, sc->cmdqueue.head);
258
259 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
260 if (!(H_GETSTAT(q->q.statp) & FATM_STAT_FREE)) {
261 sc->istats.cmd_queue_full++;
262 return (EIO);
263 }
264 NEXT_QUEUE_ENTRY(sc->cmdqueue.head, FATM_CMD_QLEN);
265
266 q->error = 0;
267 q->cb = fatm_utopia_readregs_complete;
268 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
269 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
270
271 bus_dmamap_sync(sc->reg_mem.dmat, sc->reg_mem.map, BUS_DMASYNC_PREREAD);
272
273 WRITE4(sc, q->q.card + FATMOC_GETOC3_BUF, sc->reg_mem.paddr);
274 BARRIER_W(sc);
275 WRITE4(sc, q->q.card + FATMOC_OP,
276 FATM_OP_OC3_GET_REG | FATM_OP_INTERRUPT_SEL);
277 BARRIER_W(sc);
278
279 /*
280 * Wait for the command to complete
281 */
282 error = msleep(&sc->reg_mem, &sc->mtx, PZERO | PCATCH,
283 "fatm_getreg", hz);
284
285 switch(error) {
286
287 case EWOULDBLOCK:
288 error = EIO;
289 break;
290
291 case ERESTART:
292 error = EINTR;
293 break;
294
295 case 0:
296 bus_dmamap_sync(sc->reg_mem.dmat, sc->reg_mem.map,
297 BUS_DMASYNC_POSTREAD);
298 error = q->error;
299 break;
300 }
301
302 if (error != 0) {
303 /* declare buffer to be free */
304 sc->flags &= ~FATM_REGS_INUSE;
305 cv_signal(&sc->cv_regs);
306 return (error);
307 }
308
309 /* swap if needed */
310 ptr = (uint32_t *)sc->reg_mem.mem;
311 for (i = 0; i < FATM_NREGS; i++)
312 ptr[i] = le32toh(ptr[i]) & 0xff;
313
314 return (0);
315}
316
317/*
318 * Read SUNI registers for the SUNI module.
319 *
320 * We assume, that we already hold the mutex.
321 */
322static int
323fatm_utopia_readregs(struct ifatm *ifatm, u_int reg, uint8_t *valp, u_int *np)
324{
325 int err;
326 int i;
327 struct fatm_softc *sc;
328
329 if (reg >= FATM_NREGS)
330 return (EINVAL);
331 if (reg + *np > FATM_NREGS)
332 *np = FATM_NREGS - reg;
333 sc = ifatm->ifnet.if_softc;
334 FATM_CHECKLOCK(sc);
335
336 err = fatm_utopia_readregs_internal(sc);
337 if (err != 0)
338 return (err);
339
340 for (i = 0; i < *np; i++)
341 valp[i] = ((uint32_t *)sc->reg_mem.mem)[reg + i];
342
343 /* declare buffer to be free */
344 sc->flags &= ~FATM_REGS_INUSE;
345 cv_signal(&sc->cv_regs);
346
347 return (0);
348}
349
350/*
351 * Check whether the hard is beating. We remember the last heart beat and
352 * compare it to the current one. If it appears stuck for 10 times, we have
353 * a problem.
354 *
355 * Assume we hold the lock.
356 */
357static void
358fatm_check_heartbeat(struct fatm_softc *sc)
359{
360 uint32_t h;
361
362 FATM_CHECKLOCK(sc);
363
364 h = READ4(sc, FATMO_HEARTBEAT);
365 DBG(sc, BEAT, ("heartbeat %08x", h));
366
367 if (sc->stop_cnt == 10)
368 return;
369
370 if (h == sc->heartbeat) {
371 if (++sc->stop_cnt == 10) {
372 log(LOG_ERR, "i960 stopped???\n");
373 WRITE4(sc, FATMO_HIMR, 1);
374 }
375 return;
376 }
377
378 sc->stop_cnt = 0;
379 sc->heartbeat = h;
380}
381
382/*
383 * Ensure that the heart is still beating.
384 */
385static void
386fatm_watchdog(struct ifnet *ifp)
387{
388 struct fatm_softc *sc = ifp->if_softc;
389
390 FATM_LOCK(sc);
391 if (ifp->if_flags & IFF_RUNNING) {
392 fatm_check_heartbeat(sc);
393 ifp->if_timer = 5;
394 }
395 FATM_UNLOCK(sc);
396}
397
398/*
399 * Hard reset the i960 on the board. This is done by initializing registers,
400 * clearing interrupts and waiting for the selftest to finish. Not sure,
401 * whether all these barriers are actually needed.
402 *
403 * Assumes that we hold the lock.
404 */
405static int
406fatm_reset(struct fatm_softc *sc)
407{
408 int w;
409 uint32_t val;
410
411 FATM_CHECKLOCK(sc);
412
413 WRITE4(sc, FATMO_APP_BASE, FATMO_COMMON_ORIGIN);
414 BARRIER_W(sc);
415
416 WRITE4(sc, FATMO_UART_TO_960, XMIT_READY);
417 BARRIER_W(sc);
418
419 WRITE4(sc, FATMO_UART_TO_HOST, XMIT_READY);
420 BARRIER_W(sc);
421
422 WRITE4(sc, FATMO_BOOT_STATUS, COLD_START);
423 BARRIER_W(sc);
424
425 WRITE1(sc, FATMO_HCR, FATM_HCR_RESET);
426 BARRIER_W(sc);
427
428 DELAY(1000);
429
430 WRITE1(sc, FATMO_HCR, 0);
431 BARRIER_RW(sc);
432
433 DELAY(1000);
434
435 for (w = 100; w; w--) {
436 BARRIER_R(sc);
437 val = READ4(sc, FATMO_BOOT_STATUS);
438 switch (val) {
439 case SELF_TEST_OK:
440 return (0);
441 case SELF_TEST_FAIL:
442 return (EIO);
443 }
444 DELAY(1000);
445 }
446 return (EIO);
447}
448
449/*
450 * Stop the card. Must be called WITH the lock held
451 * Reset, free transmit and receive buffers. Wakeup everybody that may sleep.
452 */
453static void
454fatm_stop(struct fatm_softc *sc)
455{
456 int i;
457 struct cmdqueue *q;
458 struct rbuf *rb;
459 struct txqueue *tx;
460 uint32_t stat;
461
462 FATM_CHECKLOCK(sc);
463
464 /* Stop the board */
465 utopia_stop(&sc->utopia);
466 (void)fatm_reset(sc);
467
468 /* stop watchdog */
469 sc->ifatm.ifnet.if_timer = 0;
470
471 if (sc->ifatm.ifnet.if_flags & IFF_RUNNING) {
472 sc->ifatm.ifnet.if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
473 ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm,
474 sc->utopia.carrier == UTP_CARR_OK);
475
476 /*
477 * Collect transmit mbufs, partial receive mbufs and
478 * supplied mbufs
479 */
480 for (i = 0; i < FATM_TX_QLEN; i++) {
481 tx = GET_QUEUE(sc->txqueue, struct txqueue, i);
482 if (tx->m) {
483 bus_dmamap_unload(sc->tx_tag, tx->map);
484 m_freem(tx->m);
485 tx->m = NULL;
486 }
487 }
488
489 /* Collect supplied mbufs */
490 while ((rb = LIST_FIRST(&sc->rbuf_used)) != NULL) {
491 LIST_REMOVE(rb, link);
492 bus_dmamap_unload(sc->rbuf_tag, rb->map);
493 m_free(rb->m);
494 rb->m = NULL;
495 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
496 }
497
498 /* Unwait any waiters */
499 wakeup(&sc->sadi_mem);
500
501 /* wakeup all threads waiting for STAT or REG buffers */
502 cv_broadcast(&sc->cv_stat);
503 cv_broadcast(&sc->cv_regs);
504
505 sc->flags &= ~(FATM_STAT_INUSE | FATM_REGS_INUSE);
506
507 /* wakeup all threads waiting on commands */
508 for (i = 0; i < FATM_CMD_QLEN; i++) {
509 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, i);
510
511 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
512 if ((stat = H_GETSTAT(q->q.statp)) != FATM_STAT_FREE) {
513 H_SETSTAT(q->q.statp, stat | FATM_STAT_ERROR);
514 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
515 wakeup(q);
516 }
517 }
518 utopia_reset_media(&sc->utopia);
519 }
520 sc->small_cnt = sc->large_cnt = 0;
521
522 /* Reset vcc info */
523 if (sc->vccs != NULL)
524 for (i = 0; i <= FORE_MAX_VCC; i++)
525 sc->vccs[i].flags = 0;
526
527 sc->open_vccs = 0;
528}
529
530/*
531 * Load the firmware into the board and save the entry point.
532 */
533static uint32_t
534firmware_load(struct fatm_softc *sc)
535{
536 struct firmware *fw = (struct firmware *)firmware;
537
538 DBG(sc, INIT, ("loading - entry=%x", fw->entry));
539 bus_space_write_region_4(sc->memt, sc->memh, fw->offset, firmware,
540 sizeof(firmware) / sizeof(firmware[0]));
541 BARRIER_RW(sc);
542
543 return (fw->entry);
544}
545
546/*
547 * Read a character from the virtual UART. The availability of a character
548 * is signaled by a non-null value of the 32 bit register. The eating of
549 * the character by us is signalled to the card by setting that register
550 * to zero.
551 */
552static int
553rx_getc(struct fatm_softc *sc)
554{
555 int w = 50;
556 int c;
557
558 while (w--) {
559 c = READ4(sc, FATMO_UART_TO_HOST);
560 BARRIER_RW(sc);
561 if (c != 0) {
562 WRITE4(sc, FATMO_UART_TO_HOST, 0);
563 DBGC(sc, UART, ("%c", c & 0xff));
564 return (c & 0xff);
565 }
566 DELAY(1000);
567 }
568 return (-1);
569}
570
571/*
572 * Eat up characters from the board and stuff them in the bit-bucket.
573 */
574static void
575rx_flush(struct fatm_softc *sc)
576{
577 int w = 10000;
578
579 while (w-- && rx_getc(sc) >= 0)
580 ;
581}
582
583/*
584 * Write a character to the card. The UART is available if the register
585 * is zero.
586 */
587static int
588tx_putc(struct fatm_softc *sc, u_char c)
589{
590 int w = 10;
591 int c1;
592
593 while (w--) {
594 c1 = READ4(sc, FATMO_UART_TO_960);
595 BARRIER_RW(sc);
596 if (c1 == 0) {
597 WRITE4(sc, FATMO_UART_TO_960, c | CHAR_AVAIL);
598 DBGC(sc, UART, ("%c", c & 0xff));
599 return (0);
600 }
601 DELAY(1000);
602 }
603 return (-1);
604}
605
606/*
607 * Start the firmware. This is doing by issuing a 'go' command with
608 * the hex entry address of the firmware. Then we wait for the self-test to
609 * succeed.
610 */
611static int
612fatm_start_firmware(struct fatm_softc *sc, uint32_t start)
613{
614 static char hex[] = "0123456789abcdef";
615 u_int w, val;
616
617 DBG(sc, INIT, ("starting"));
618 rx_flush(sc);
619 tx_putc(sc, '\r');
620 DELAY(1000);
621
622 rx_flush(sc);
623
624 tx_putc(sc, 'g');
625 (void)rx_getc(sc);
626 tx_putc(sc, 'o');
627 (void)rx_getc(sc);
628 tx_putc(sc, ' ');
629 (void)rx_getc(sc);
630
631 tx_putc(sc, hex[(start >> 12) & 0xf]);
632 (void)rx_getc(sc);
633 tx_putc(sc, hex[(start >> 8) & 0xf]);
634 (void)rx_getc(sc);
635 tx_putc(sc, hex[(start >> 4) & 0xf]);
636 (void)rx_getc(sc);
637 tx_putc(sc, hex[(start >> 0) & 0xf]);
638 (void)rx_getc(sc);
639
640 tx_putc(sc, '\r');
641 rx_flush(sc);
642
643 for (w = 100; w; w--) {
644 BARRIER_R(sc);
645 val = READ4(sc, FATMO_BOOT_STATUS);
646 switch (val) {
647 case CP_RUNNING:
648 return (0);
649 case SELF_TEST_FAIL:
650 return (EIO);
651 }
652 DELAY(1000);
653 }
654 return (EIO);
655}
656
657/*
658 * Initialize one card and host queue.
659 */
660static void
661init_card_queue(struct fatm_softc *sc, struct fqueue *queue, int qlen,
662 size_t qel_size, size_t desc_size, cardoff_t off,
663 u_char **statpp, uint32_t *cardstat, u_char *descp, uint32_t carddesc)
664{
665 struct fqelem *el = queue->chunk;
666
667 while (qlen--) {
668 el->card = off;
669 off += 8; /* size of card entry */
670
671 el->statp = (uint32_t *)(*statpp);
672 (*statpp) += sizeof(uint32_t);
673 H_SETSTAT(el->statp, FATM_STAT_FREE);
674 H_SYNCSTAT_PREWRITE(sc, el->statp);
675
676 WRITE4(sc, el->card + FATMOS_STATP, (*cardstat));
677 (*cardstat) += sizeof(uint32_t);
678
679 el->ioblk = descp;
680 descp += desc_size;
681 el->card_ioblk = carddesc;
682 carddesc += desc_size;
683
684 el = (struct fqelem *)((u_char *)el + qel_size);
685 }
686 queue->tail = queue->head = 0;
687}
688
689/*
690 * Issue the initialize operation to the card, wait for completion and
691 * initialize the on-board and host queue structures with offsets and
692 * addresses.
693 */
694static int
695fatm_init_cmd(struct fatm_softc *sc)
696{
697 int w, c;
698 u_char *statp;
699 uint32_t card_stat;
700 u_int cnt;
701 struct fqelem *el;
702 cardoff_t off;
703
704 DBG(sc, INIT, ("command"));
705 WRITE4(sc, FATMO_ISTAT, 0);
706 WRITE4(sc, FATMO_IMASK, 1);
707 WRITE4(sc, FATMO_HLOGGER, 0);
708
709 WRITE4(sc, FATMO_INIT + FATMOI_RECEIVE_TRESHOLD, 0);
710 WRITE4(sc, FATMO_INIT + FATMOI_NUM_CONNECT, FORE_MAX_VCC);
711 WRITE4(sc, FATMO_INIT + FATMOI_CQUEUE_LEN, FATM_CMD_QLEN);
712 WRITE4(sc, FATMO_INIT + FATMOI_TQUEUE_LEN, FATM_TX_QLEN);
713 WRITE4(sc, FATMO_INIT + FATMOI_RQUEUE_LEN, FATM_RX_QLEN);
714 WRITE4(sc, FATMO_INIT + FATMOI_RPD_EXTENSION, RPD_EXTENSIONS);
715 WRITE4(sc, FATMO_INIT + FATMOI_TPD_EXTENSION, TPD_EXTENSIONS);
716
717 /*
718 * initialize buffer descriptors
719 */
720 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B1 + FATMOB_QUEUE_LENGTH,
721 SMALL_SUPPLY_QLEN);
722 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B1 + FATMOB_BUFFER_SIZE,
723 SMALL_BUFFER_LEN);
724 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B1 + FATMOB_POOL_SIZE,
725 SMALL_POOL_SIZE);
726 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B1 + FATMOB_SUPPLY_BLKSIZE,
727 SMALL_SUPPLY_BLKSIZE);
728
729 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B1 + FATMOB_QUEUE_LENGTH,
730 LARGE_SUPPLY_QLEN);
731 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B1 + FATMOB_BUFFER_SIZE,
732 LARGE_BUFFER_LEN);
733 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B1 + FATMOB_POOL_SIZE,
734 LARGE_POOL_SIZE);
735 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B1 + FATMOB_SUPPLY_BLKSIZE,
736 LARGE_SUPPLY_BLKSIZE);
737
738 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B2 + FATMOB_QUEUE_LENGTH, 0);
739 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B2 + FATMOB_BUFFER_SIZE, 0);
740 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B2 + FATMOB_POOL_SIZE, 0);
741 WRITE4(sc, FATMO_INIT + FATMOI_SMALL_B2 + FATMOB_SUPPLY_BLKSIZE, 0);
742
743 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B2 + FATMOB_QUEUE_LENGTH, 0);
744 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B2 + FATMOB_BUFFER_SIZE, 0);
745 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B2 + FATMOB_POOL_SIZE, 0);
746 WRITE4(sc, FATMO_INIT + FATMOI_LARGE_B2 + FATMOB_SUPPLY_BLKSIZE, 0);
747
748 /*
749 * Start the command
750 */
751 BARRIER_W(sc);
752 WRITE4(sc, FATMO_INIT + FATMOI_STATUS, FATM_STAT_PENDING);
753 BARRIER_W(sc);
754 WRITE4(sc, FATMO_INIT + FATMOI_OP, FATM_OP_INITIALIZE);
755 BARRIER_W(sc);
756
757 /*
758 * Busy wait for completion
759 */
760 w = 100;
761 while (w--) {
762 c = READ4(sc, FATMO_INIT + FATMOI_STATUS);
763 BARRIER_R(sc);
764 if (c & FATM_STAT_COMPLETE)
765 break;
766 DELAY(1000);
767 }
768
769 if (c & FATM_STAT_ERROR)
770 return (EIO);
771
772 /*
773 * Initialize the queues
774 */
775 statp = sc->stat_mem.mem;
776 card_stat = sc->stat_mem.paddr;
777
778 /*
779 * Command queue. This is special in that it's on the card.
780 */
781 el = sc->cmdqueue.chunk;
782 off = READ4(sc, FATMO_COMMAND_QUEUE);
783 DBG(sc, INIT, ("cmd queue=%x", off));
784 for (cnt = 0; cnt < FATM_CMD_QLEN; cnt++) {
785 el = &((struct cmdqueue *)sc->cmdqueue.chunk + cnt)->q;
786
787 el->card = off;
788 off += 32; /* size of card structure */
789
790 el->statp = (uint32_t *)statp;
791 statp += sizeof(uint32_t);
792 H_SETSTAT(el->statp, FATM_STAT_FREE);
793 H_SYNCSTAT_PREWRITE(sc, el->statp);
794
795 WRITE4(sc, el->card + FATMOC_STATP, card_stat);
796 card_stat += sizeof(uint32_t);
797 }
798 sc->cmdqueue.tail = sc->cmdqueue.head = 0;
799
800 /*
801 * Now the other queues. These are in memory
802 */
803 init_card_queue(sc, &sc->txqueue, FATM_TX_QLEN,
804 sizeof(struct txqueue), TPD_SIZE,
805 READ4(sc, FATMO_TRANSMIT_QUEUE),
806 &statp, &card_stat, sc->txq_mem.mem, sc->txq_mem.paddr);
807
808 init_card_queue(sc, &sc->rxqueue, FATM_RX_QLEN,
809 sizeof(struct rxqueue), RPD_SIZE,
810 READ4(sc, FATMO_RECEIVE_QUEUE),
811 &statp, &card_stat, sc->rxq_mem.mem, sc->rxq_mem.paddr);
812
813 init_card_queue(sc, &sc->s1queue, SMALL_SUPPLY_QLEN,
814 sizeof(struct supqueue), BSUP_BLK2SIZE(SMALL_SUPPLY_BLKSIZE),
815 READ4(sc, FATMO_SMALL_B1_QUEUE),
816 &statp, &card_stat, sc->s1q_mem.mem, sc->s1q_mem.paddr);
817
818 init_card_queue(sc, &sc->l1queue, LARGE_SUPPLY_QLEN,
819 sizeof(struct supqueue), BSUP_BLK2SIZE(LARGE_SUPPLY_BLKSIZE),
820 READ4(sc, FATMO_LARGE_B1_QUEUE),
821 &statp, &card_stat, sc->l1q_mem.mem, sc->l1q_mem.paddr);
822
823 sc->txcnt = 0;
824
825 return (0);
826}
827
828/*
829 * Read PROM. Called only from attach code. Here we spin because the interrupt
830 * handler is not yet set up.
831 */
832static int
833fatm_getprom(struct fatm_softc *sc)
834{
835 int i;
836 struct prom *prom;
837 struct cmdqueue *q;
838
839 DBG(sc, INIT, ("reading prom"));
840 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, sc->cmdqueue.head);
841 NEXT_QUEUE_ENTRY(sc->cmdqueue.head, FATM_CMD_QLEN);
842
843 q->error = 0;
844 q->cb = NULL;;
845 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
846 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
847
848 bus_dmamap_sync(sc->prom_mem.dmat, sc->prom_mem.map,
849 BUS_DMASYNC_PREREAD);
850
851 WRITE4(sc, q->q.card + FATMOC_GPROM_BUF, sc->prom_mem.paddr);
852 BARRIER_W(sc);
853 WRITE4(sc, q->q.card + FATMOC_OP, FATM_OP_GET_PROM_DATA);
854 BARRIER_W(sc);
855
856 for (i = 0; i < 1000; i++) {
857 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
858 if (H_GETSTAT(q->q.statp) &
859 (FATM_STAT_COMPLETE | FATM_STAT_ERROR))
860 break;
861 DELAY(1000);
862 }
863 if (i == 1000) {
864 if_printf(&sc->ifatm.ifnet, "getprom timeout\n");
865 return (EIO);
866 }
867 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
868 if (H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
869 if_printf(&sc->ifatm.ifnet, "getprom error\n");
870 return (EIO);
871 }
872 H_SETSTAT(q->q.statp, FATM_STAT_FREE);
873 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
874 NEXT_QUEUE_ENTRY(sc->cmdqueue.tail, FATM_CMD_QLEN);
875
876 bus_dmamap_sync(sc->prom_mem.dmat, sc->prom_mem.map,
877 BUS_DMASYNC_POSTREAD);
878
879
880#ifdef notdef
881 {
882 u_int i;
883
884 printf("PROM: ");
885 u_char *ptr = (u_char *)sc->prom_mem.mem;
886 for (i = 0; i < sizeof(struct prom); i++)
887 printf("%02x ", *ptr++);
888 printf("\n");
889 }
890#endif
891
892 prom = (struct prom *)sc->prom_mem.mem;
893
894 bcopy(prom->mac + 2, sc->ifatm.mib.esi, 6);
895 sc->ifatm.mib.serial = le32toh(prom->serial);
896 sc->ifatm.mib.hw_version = le32toh(prom->version);
897 sc->ifatm.mib.sw_version = READ4(sc, FATMO_FIRMWARE_RELEASE);
898
899 if_printf(&sc->ifatm.ifnet, "ESI=%02x:%02x:%02x:%02x:%02x:%02x "
900 "serial=%u hw=0x%x sw=0x%x\n", sc->ifatm.mib.esi[0],
901 sc->ifatm.mib.esi[1], sc->ifatm.mib.esi[2], sc->ifatm.mib.esi[3],
902 sc->ifatm.mib.esi[4], sc->ifatm.mib.esi[5], sc->ifatm.mib.serial,
903 sc->ifatm.mib.hw_version, sc->ifatm.mib.sw_version);
904
905 return (0);
906}
907
908/*
909 * This is the callback function for bus_dmamap_load. We assume, that we
910 * have a 32-bit bus and so have always one segment.
911 */
912static void
913dmaload_helper(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
914{
915 bus_addr_t *ptr = (bus_addr_t *)arg;
916
917 if (error != 0) {
918 printf("%s: error=%d\n", __func__, error);
919 return;
920 }
921 KASSERT(nsegs == 1, ("too many DMA segments"));
922 KASSERT(segs[0].ds_addr <= 0xffffffff, ("DMA address too large %lx",
923 (u_long)segs[0].ds_addr));
924
925 *ptr = segs[0].ds_addr;
926}
927
928/*
929 * Allocate a chunk of DMA-able memory and map it.
930 */
931static int
932alloc_dma_memory(struct fatm_softc *sc, const char *nm, struct fatm_mem *mem)
933{
934 int error;
935
936 mem->mem = NULL;
937
938 if (bus_dma_tag_create(sc->parent_dmat, mem->align, 0,
939 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
940 NULL, NULL, mem->size, 1, BUS_SPACE_MAXSIZE_32BIT,
941 BUS_DMA_ALLOCNOW, NULL, NULL, &mem->dmat)) {
942 if_printf(&sc->ifatm.ifnet, "could not allocate %s DMA tag\n",
943 nm);
944 return (ENOMEM);
945 }
946
947 error = bus_dmamem_alloc(mem->dmat, &mem->mem, 0, &mem->map);
948 if (error) {
949 if_printf(&sc->ifatm.ifnet, "could not allocate %s DMA memory: "
950 "%d\n", nm, error);
951 bus_dma_tag_destroy(mem->dmat);
952 mem->mem = NULL;
953 return (error);
954 }
955
956 error = bus_dmamap_load(mem->dmat, mem->map, mem->mem, mem->size,
957 dmaload_helper, &mem->paddr, BUS_DMA_NOWAIT);
958 if (error) {
959 if_printf(&sc->ifatm.ifnet, "could not load %s DMA memory: "
960 "%d\n", nm, error);
961 bus_dmamem_free(mem->dmat, mem->mem, mem->map);
962 bus_dma_tag_destroy(mem->dmat);
963 mem->mem = NULL;
964 return (error);
965 }
966
967 DBG(sc, DMA, ("DMA %s V/P/S/Z %p/%lx/%x/%x", nm, mem->mem,
968 (u_long)mem->paddr, mem->size, mem->align));
969
970 return (0);
971}
972
973#ifdef TEST_DMA_SYNC
974static int
975alloc_dma_memoryX(struct fatm_softc *sc, const char *nm, struct fatm_mem *mem)
976{
977 int error;
978
979 mem->mem = NULL;
980
981 if (bus_dma_tag_create(NULL, mem->align, 0,
982 BUS_SPACE_MAXADDR_24BIT, BUS_SPACE_MAXADDR,
983 NULL, NULL, mem->size, 1, mem->size,
984 BUS_DMA_ALLOCNOW, NULL, NULL, &mem->dmat)) {
985 if_printf(&sc->ifatm.ifnet, "could not allocate %s DMA tag\n",
986 nm);
987 return (ENOMEM);
988 }
989
990 mem->mem = contigmalloc(mem->size, M_DEVBUF, M_WAITOK,
991 BUS_SPACE_MAXADDR_24BIT, BUS_SPACE_MAXADDR_32BIT, mem->align, 0);
992
993 error = bus_dmamap_create(mem->dmat, 0, &mem->map);
994 if (error) {
995 if_printf(&sc->ifatm.ifnet, "could not allocate %s DMA map: "
996 "%d\n", nm, error);
997 contigfree(mem->mem, mem->size, M_DEVBUF);
998 bus_dma_tag_destroy(mem->dmat);
999 mem->mem = NULL;
1000 return (error);
1001 }
1002
1003 error = bus_dmamap_load(mem->dmat, mem->map, mem->mem, mem->size,
1004 dmaload_helper, &mem->paddr, BUS_DMA_NOWAIT);
1005 if (error) {
1006 if_printf(&sc->ifatm.ifnet, "could not load %s DMA memory: "
1007 "%d\n", nm, error);
1008 bus_dmamap_destroy(mem->dmat, mem->map);
1009 contigfree(mem->mem, mem->size, M_DEVBUF);
1010 bus_dma_tag_destroy(mem->dmat);
1011 mem->mem = NULL;
1012 return (error);
1013 }
1014
1015 DBG(sc, DMA, ("DMAX %s V/P/S/Z %p/%lx/%x/%x", nm, mem->mem,
1016 (u_long)mem->paddr, mem->size, mem->align));
1017
1018 printf("DMAX: %s V/P/S/Z %p/%lx/%x/%x", nm, mem->mem,
1019 (u_long)mem->paddr, mem->size, mem->align);
1020
1021 return (0);
1022}
1023#endif /* TEST_DMA_SYNC */
1024
1025/*
1026 * Destroy all resources of an dma-able memory chunk
1027 */
1028static void
1029destroy_dma_memory(struct fatm_mem *mem)
1030{
1031 if (mem->mem != NULL) {
1032 bus_dmamap_unload(mem->dmat, mem->map);
1033 bus_dmamem_free(mem->dmat, mem->mem, mem->map);
1034 bus_dma_tag_destroy(mem->dmat);
1035 mem->mem = NULL;
1036 }
1037}
1038#ifdef TEST_DMA_SYNC
1039static void
1040destroy_dma_memoryX(struct fatm_mem *mem)
1041{
1042 if (mem->mem != NULL) {
1043 bus_dmamap_unload(mem->dmat, mem->map);
1044 bus_dmamap_destroy(mem->dmat, mem->map);
1045 contigfree(mem->mem, mem->size, M_DEVBUF);
1046 bus_dma_tag_destroy(mem->dmat);
1047 mem->mem = NULL;
1048 }
1049}
1050#endif /* TEST_DMA_SYNC */
1051
1052/*
1053 * Try to supply buffers to the card if there are free entries in the queues
1054 */
1055static void
1056fatm_supply_small_buffers(struct fatm_softc *sc)
1057{
1058 int nblocks, nbufs;
1059 struct supqueue *q;
1060 struct rbd *bd;
1061 int i, j, error, cnt;
1062 struct mbuf *m;
1063 struct rbuf *rb;
1064 bus_addr_t phys;
1065
1066 nbufs = max(4 * sc->open_vccs, 32);
1067 nbufs = min(nbufs, SMALL_POOL_SIZE);
1068 nbufs -= sc->small_cnt;
1069
1070 nblocks = (nbufs + SMALL_SUPPLY_BLKSIZE - 1) / SMALL_SUPPLY_BLKSIZE;
1071 for (cnt = 0; cnt < nblocks; cnt++) {
1072 q = GET_QUEUE(sc->s1queue, struct supqueue, sc->s1queue.head);
1073
1074 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1075 if (H_GETSTAT(q->q.statp) != FATM_STAT_FREE)
1076 break;
1077
1078 bd = (struct rbd *)q->q.ioblk;
1079
1080 for (i = 0; i < SMALL_SUPPLY_BLKSIZE; i++) {
1081 if ((rb = LIST_FIRST(&sc->rbuf_free)) == NULL) {
1082 if_printf(&sc->ifatm.ifnet, "out of rbufs\n");
1083 break;
1084 }
1085 MGETHDR(m, M_DONTWAIT, MT_DATA);
1086 if (m == NULL) {
1087 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1088 break;
1089 }
1090 MH_ALIGN(m, SMALL_BUFFER_LEN);
1091 error = bus_dmamap_load(sc->rbuf_tag, rb->map,
1092 m->m_data, SMALL_BUFFER_LEN, dmaload_helper,
1093 &phys, BUS_DMA_NOWAIT);
1094 if (error) {
1095 if_printf(&sc->ifatm.ifnet,
1096 "dmamap_load mbuf failed %d", error);
1097 m_freem(m);
1098 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1099 break;
1100 }
1101 bus_dmamap_sync(sc->rbuf_tag, rb->map,
1102 BUS_DMASYNC_PREREAD);
1103
1104 LIST_REMOVE(rb, link);
1105 LIST_INSERT_HEAD(&sc->rbuf_used, rb, link);
1106
1107 rb->m = m;
1108 bd[i].handle = rb - sc->rbufs;
1109 H_SETDESC(bd[i].buffer, phys);
1110 }
1111
1112 if (i < SMALL_SUPPLY_BLKSIZE) {
1113 for (j = 0; j < i; j++) {
1114 rb = sc->rbufs + bd[j].handle;
1115 bus_dmamap_unload(sc->rbuf_tag, rb->map);
1116 m_free(rb->m);
1117 rb->m = NULL;
1118
1119 LIST_REMOVE(rb, link);
1120 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1121 }
1122 break;
1123 }
1124 H_SYNCQ_PREWRITE(&sc->s1q_mem, bd,
1125 sizeof(struct rbd) * SMALL_SUPPLY_BLKSIZE);
1126
1127 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
1128 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1129
1130 WRITE4(sc, q->q.card, q->q.card_ioblk);
1131 BARRIER_W(sc);
1132
1133 sc->small_cnt += SMALL_SUPPLY_BLKSIZE;
1134
1135 NEXT_QUEUE_ENTRY(sc->s1queue.head, SMALL_SUPPLY_QLEN);
1136 }
1137}
1138
1139/*
1140 * Try to supply buffers to the card if there are free entries in the queues
1141 * We assume that all buffers are within the address space accessible by the
1142 * card (32-bit), so we don't need bounce buffers.
1143 */
1144static void
1145fatm_supply_large_buffers(struct fatm_softc *sc)
1146{
1147 int nbufs, nblocks, cnt;
1148 struct supqueue *q;
1149 struct rbd *bd;
1150 int i, j, error;
1151 struct mbuf *m;
1152 struct rbuf *rb;
1153 bus_addr_t phys;
1154
1155 nbufs = max(4 * sc->open_vccs, 32);
1156 nbufs = min(nbufs, LARGE_POOL_SIZE);
1157 nbufs -= sc->large_cnt;
1158
1159 nblocks = (nbufs + LARGE_SUPPLY_BLKSIZE - 1) / LARGE_SUPPLY_BLKSIZE;
1160
1161 for (cnt = 0; cnt < nblocks; cnt++) {
1162 q = GET_QUEUE(sc->l1queue, struct supqueue, sc->l1queue.head);
1163
1164 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1165 if (H_GETSTAT(q->q.statp) != FATM_STAT_FREE)
1166 break;
1167
1168 bd = (struct rbd *)q->q.ioblk;
1169
1170 for (i = 0; i < LARGE_SUPPLY_BLKSIZE; i++) {
1171 if ((rb = LIST_FIRST(&sc->rbuf_free)) == NULL) {
1172 if_printf(&sc->ifatm.ifnet, "out of rbufs\n");
1173 break;
1174 }
1175 if ((m = m_getcl(M_DONTWAIT, MT_DATA,
1176 M_PKTHDR)) == NULL) {
1177 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1178 break;
1179 }
1180 /* No MEXT_ALIGN */
1181 m->m_data += MCLBYTES - LARGE_BUFFER_LEN;
1182 error = bus_dmamap_load(sc->rbuf_tag, rb->map,
1183 m->m_data, LARGE_BUFFER_LEN, dmaload_helper,
1184 &phys, BUS_DMA_NOWAIT);
1185 if (error) {
1186 if_printf(&sc->ifatm.ifnet,
1187 "dmamap_load mbuf failed %d", error);
1188 m_freem(m);
1189 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1190 break;
1191 }
1192
1193 bus_dmamap_sync(sc->rbuf_tag, rb->map,
1194 BUS_DMASYNC_PREREAD);
1195
1196 LIST_REMOVE(rb, link);
1197 LIST_INSERT_HEAD(&sc->rbuf_used, rb, link);
1198
1199 rb->m = m;
1200 bd[i].handle = rb - sc->rbufs;
1201 H_SETDESC(bd[i].buffer, phys);
1202 }
1203
1204 if (i < LARGE_SUPPLY_BLKSIZE) {
1205 for (j = 0; j < i; j++) {
1206 rb = sc->rbufs + bd[j].handle;
1207 bus_dmamap_unload(sc->rbuf_tag, rb->map);
1208 m_free(rb->m);
1209 rb->m = NULL;
1210
1211 LIST_REMOVE(rb, link);
1212 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1213 }
1214 break;
1215 }
1216 H_SYNCQ_PREWRITE(&sc->l1q_mem, bd,
1217 sizeof(struct rbd) * LARGE_SUPPLY_BLKSIZE);
1218
1219 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
1220 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1221 WRITE4(sc, q->q.card, q->q.card_ioblk);
1222 BARRIER_W(sc);
1223
1224 sc->large_cnt += LARGE_SUPPLY_BLKSIZE;
1225
1226 NEXT_QUEUE_ENTRY(sc->l1queue.head, LARGE_SUPPLY_QLEN);
1227 }
1228}
1229
1230
1231/*
1232 * Actually start the card. The lock must be held here.
1233 * Reset, load the firmware, start it, initializes queues, read the PROM
1234 * and supply receive buffers to the card.
1235 */
1236static void
1237fatm_init_locked(struct fatm_softc *sc)
1238{
1239 struct rxqueue *q;
1240 int i, c;
1241 uint32_t start;
1242
1243 DBG(sc, INIT, ("initialize"));
1244 if (sc->ifatm.ifnet.if_flags & IFF_RUNNING)
1245 fatm_stop(sc);
1246
1247 /*
1248 * Hard reset the board
1249 */
1250 if (fatm_reset(sc))
1251 return;
1252
1253 start = firmware_load(sc);
1254 if (fatm_start_firmware(sc, start) || fatm_init_cmd(sc) ||
1255 fatm_getprom(sc)) {
1256 fatm_reset(sc);
1257 return;
1258 }
1259
1260 /*
1261 * Handle media
1262 */
1263 c = READ4(sc, FATMO_MEDIA_TYPE);
1264 switch (c) {
1265
1266 case FORE_MT_TAXI_100:
1267 sc->ifatm.mib.media = IFM_ATM_TAXI_100;
1268 sc->ifatm.mib.pcr = 227273;
1269 break;
1270
1271 case FORE_MT_TAXI_140:
1272 sc->ifatm.mib.media = IFM_ATM_TAXI_140;
1273 sc->ifatm.mib.pcr = 318181;
1274 break;
1275
1276 case FORE_MT_UTP_SONET:
1277 sc->ifatm.mib.media = IFM_ATM_UTP_155;
1278 sc->ifatm.mib.pcr = 353207;
1279 break;
1280
1281 case FORE_MT_MM_OC3_ST:
1282 case FORE_MT_MM_OC3_SC:
1283 sc->ifatm.mib.media = IFM_ATM_MM_155;
1284 sc->ifatm.mib.pcr = 353207;
1285 break;
1286
1287 case FORE_MT_SM_OC3_ST:
1288 case FORE_MT_SM_OC3_SC:
1289 sc->ifatm.mib.media = IFM_ATM_SM_155;
1290 sc->ifatm.mib.pcr = 353207;
1291 break;
1292
1293 default:
1294 log(LOG_ERR, "fatm: unknown media type %d\n", c);
1295 sc->ifatm.mib.media = IFM_ATM_UNKNOWN;
1296 sc->ifatm.mib.pcr = 353207;
1297 break;
1298 }
1299 sc->ifatm.ifnet.if_baudrate = 53 * 8 * sc->ifatm.mib.pcr;
1300 utopia_init_media(&sc->utopia);
1301
1302 /*
1303 * Initialize the RBDs
1304 */
1305 for (i = 0; i < FATM_RX_QLEN; i++) {
1306 q = GET_QUEUE(sc->rxqueue, struct rxqueue, i);
1307 WRITE4(sc, q->q.card + 0, q->q.card_ioblk);
1308 }
1309 BARRIER_W(sc);
1310
1311 /*
1312 * Supply buffers to the card
1313 */
1314 fatm_supply_small_buffers(sc);
1315 fatm_supply_large_buffers(sc);
1316
1317 /*
1318 * Now set flags, that we are ready
1319 */
1320 sc->ifatm.ifnet.if_flags |= IFF_RUNNING;
1321
1322 /*
1323 * Start the watchdog timer
1324 */
1325 sc->ifatm.ifnet.if_timer = 5;
1326
1327 /* start SUNI */
1328 utopia_start(&sc->utopia);
1329
1330 ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm,
1331 sc->utopia.carrier == UTP_CARR_OK);
1332
1333 DBG(sc, INIT, ("done"));
1334}
1335
1336/*
1337 * This is the exported as initialisation function.
1338 */
1339static void
1340fatm_init(void *p)
1341{
1342 struct fatm_softc *sc = p;
1343
1344 FATM_LOCK(sc);
1345 fatm_init_locked(sc);
1346 FATM_UNLOCK(sc);
1347}
1348
1349/************************************************************/
1350/*
1351 * The INTERRUPT handling
1352 */
1353/*
1354 * Check the command queue. If a command was completed, call the completion
1355 * function for that command.
1356 */
1357static void
1358fatm_intr_drain_cmd(struct fatm_softc *sc)
1359{
1360 struct cmdqueue *q;
1361 int stat;
1362
1363 /*
1364 * Drain command queue
1365 */
1366 for (;;) {
1367 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, sc->cmdqueue.tail);
1368
1369 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1370 stat = H_GETSTAT(q->q.statp);
1371
1372 if (stat != FATM_STAT_COMPLETE &&
1373 stat != (FATM_STAT_COMPLETE | FATM_STAT_ERROR) &&
1374 stat != FATM_STAT_ERROR)
1375 break;
1376
1377 (*q->cb)(sc, q);
1378
1379 H_SETSTAT(q->q.statp, FATM_STAT_FREE);
1380 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1381
1382 NEXT_QUEUE_ENTRY(sc->cmdqueue.tail, FATM_CMD_QLEN);
1383 }
1384}
1385
1386/*
1387 * Drain the small buffer supply queue.
1388 */
1389static void
1390fatm_intr_drain_small_buffers(struct fatm_softc *sc)
1391{
1392 struct supqueue *q;
1393 int stat;
1394
1395 for (;;) {
1396 q = GET_QUEUE(sc->s1queue, struct supqueue, sc->s1queue.tail);
1397
1398 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1399 stat = H_GETSTAT(q->q.statp);
1400
1401 if ((stat & FATM_STAT_COMPLETE) == 0)
1402 break;
1403 if (stat & FATM_STAT_ERROR)
1404 log(LOG_ERR, "%s: status %x\n", __func__, stat);
1405
1406 H_SETSTAT(q->q.statp, FATM_STAT_FREE);
1407 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1408
1409 NEXT_QUEUE_ENTRY(sc->s1queue.tail, SMALL_SUPPLY_QLEN);
1410 }
1411}
1412
1413/*
1414 * Drain the large buffer supply queue.
1415 */
1416static void
1417fatm_intr_drain_large_buffers(struct fatm_softc *sc)
1418{
1419 struct supqueue *q;
1420 int stat;
1421
1422 for (;;) {
1423 q = GET_QUEUE(sc->l1queue, struct supqueue, sc->l1queue.tail);
1424
1425 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1426 stat = H_GETSTAT(q->q.statp);
1427
1428 if ((stat & FATM_STAT_COMPLETE) == 0)
1429 break;
1430 if (stat & FATM_STAT_ERROR)
1431 log(LOG_ERR, "%s status %x\n", __func__, stat);
1432
1433 H_SETSTAT(q->q.statp, FATM_STAT_FREE);
1434 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1435
1436 NEXT_QUEUE_ENTRY(sc->l1queue.tail, LARGE_SUPPLY_QLEN);
1437 }
1438}
1439
1440/*
1441 * Check the receive queue. Send any received PDU up the protocol stack
1442 * (except when there was an error or the VCI appears to be closed. In this
1443 * case discard the PDU).
1444 */
1445static void
1446fatm_intr_drain_rx(struct fatm_softc *sc)
1447{
1448 struct rxqueue *q;
1449 int stat, mlen, drop;
1450 u_int i;
1451 uint32_t h;
1452 struct mbuf *last, *m0;
1453 struct rpd *rpd;
1454 struct rbuf *rb;
1455 u_int vci, vpi, pt;
1456 struct atm_pseudohdr aph;
1457 struct ifnet *ifp;
1458
1459 for (;;) {
1460 q = GET_QUEUE(sc->rxqueue, struct rxqueue, sc->rxqueue.tail);
1461
1462 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1463 stat = H_GETSTAT(q->q.statp);
1464
1465 if ((stat & FATM_STAT_COMPLETE) == 0)
1466 break;
1467
1468 rpd = (struct rpd *)q->q.ioblk;
1469 H_SYNCQ_POSTREAD(&sc->rxq_mem, rpd, RPD_SIZE);
1470
1471 rpd->nseg = le32toh(rpd->nseg);
1472 drop = 0;
1473 mlen = 0;
1474 m0 = last = 0;
1475 for (i = 0; i < rpd->nseg; i++) {
1476 rb = sc->rbufs + rpd->segment[i].handle;
1477 if (m0 == NULL) {
1478 m0 = last = rb->m;
1479 } else {
1480 last->m_next = rb->m;
1481 last = rb->m;
1482 }
1483 last->m_next = NULL;
1484 if (last->m_flags & M_EXT)
1485 sc->large_cnt--;
1486 else
1487 sc->small_cnt--;
1488 bus_dmamap_sync(sc->rbuf_tag, rb->map,
1489 BUS_DMASYNC_POSTREAD);
1490 bus_dmamap_unload(sc->rbuf_tag, rb->map);
1491 rb->m = NULL;
1492
1493 LIST_REMOVE(rb, link);
1494 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
1495
1496 last->m_len = le32toh(rpd->segment[i].length);
1497 mlen += last->m_len;
1498 }
1499
1500 m0->m_pkthdr.len = mlen;
1501 m0->m_pkthdr.rcvif = &sc->ifatm.ifnet;
1502
1503 h = le32toh(rpd->atm_header);
1504 vpi = (h >> 20) & 0xff;
1505 vci = (h >> 4 ) & 0xffff;
1506 pt = (h >> 1 ) & 0x7;
1507
1508 /*
1509 * Locate the VCC this packet belongs to
1510 */
1511 if (!VC_OK(sc, vpi, vci))
1512 drop = 1;
1513 else if ((sc->vccs[vci].flags & FATM_VCC_OPEN) == 0) {
1514 sc->istats.rx_closed++;
1515 drop = 1;
1516 }
1517
1518 DBG(sc, RCV, ("RCV: vc=%u.%u pt=%u mlen=%d %s", vpi, vci,
1519 pt, mlen, drop ? "dropped" : ""));
1520
1521 if (drop) {
1522 m_freem(m0);
1523 } else {
1524 ATM_PH_FLAGS(&aph) = sc->vccs[vci].flags & 0xff;
1525 ATM_PH_VPI(&aph) = vpi;
1526 ATM_PH_SETVCI(&aph, vci);
1527
1528 ifp = &sc->ifatm.ifnet;
1529 ifp->if_ipackets++;
1530
1531 atm_input(ifp, &aph, m0, sc->vccs[vci].rxhand);
1532 }
1533
1534 H_SETSTAT(q->q.statp, FATM_STAT_FREE);
1535 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1536
1537 WRITE4(sc, q->q.card, q->q.card_ioblk);
1538 BARRIER_W(sc);
1539
1540 NEXT_QUEUE_ENTRY(sc->rxqueue.tail, FATM_RX_QLEN);
1541 }
1542}
1543
1544/*
1545 * Check the transmit queue. Free the mbuf chains that we were transmitting.
1546 */
1547static void
1548fatm_intr_drain_tx(struct fatm_softc *sc)
1549{
1550 struct txqueue *q;
1551 int stat;
1552
1553 /*
1554 * Drain tx queue
1555 */
1556 for (;;) {
1557 q = GET_QUEUE(sc->txqueue, struct txqueue, sc->txqueue.tail);
1558
1559 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1560 stat = H_GETSTAT(q->q.statp);
1561
1562 if (stat != FATM_STAT_COMPLETE &&
1563 stat != (FATM_STAT_COMPLETE | FATM_STAT_ERROR) &&
1564 stat != FATM_STAT_ERROR)
1565 break;
1566
1567 H_SETSTAT(q->q.statp, FATM_STAT_FREE);
1568 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1569
1570 bus_dmamap_sync(sc->tx_tag, q->map, BUS_DMASYNC_POSTWRITE);
1571 bus_dmamap_unload(sc->tx_tag, q->map);
1572
1573 m_freem(q->m);
1574 q->m = NULL;
1575 sc->txcnt--;
1576
1577 NEXT_QUEUE_ENTRY(sc->txqueue.tail, FATM_TX_QLEN);
1578 }
1579}
1580
1581/*
1582 * Interrupt handler
1583 */
1584static void
1585fatm_intr(void *p)
1586{
1587 struct fatm_softc *sc = (struct fatm_softc *)p;
1588
1589 FATM_LOCK(sc);
1590 if (!READ4(sc, FATMO_PSR)) {
1591 FATM_UNLOCK(sc);
1592 return;
1593 }
1594 WRITE4(sc, FATMO_HCR, FATM_HCR_CLRIRQ);
1595
1596 if (!(sc->ifatm.ifnet.if_flags & IFF_RUNNING)) {
1597 FATM_UNLOCK(sc);
1598 return;
1599 }
1600 fatm_intr_drain_cmd(sc);
1601 fatm_intr_drain_rx(sc);
1602 fatm_intr_drain_tx(sc);
1603 fatm_intr_drain_small_buffers(sc);
1604 fatm_intr_drain_large_buffers(sc);
1605 fatm_supply_small_buffers(sc);
1606 fatm_supply_large_buffers(sc);
1607
1608 FATM_UNLOCK(sc);
1609
1610 if (sc->retry_tx && _IF_QLEN(&sc->ifatm.ifnet.if_snd))
1611 (*sc->ifatm.ifnet.if_start)(&sc->ifatm.ifnet);
1612}
1613
1614/*
1615 * Get device statistics. This must be called with the softc locked.
1616 * We use a preallocated buffer, so we need to protect this buffer.
1617 * We do this by using a condition variable and a flag. If the flag is set
1618 * the buffer is in use by one thread (one thread is executing a GETSTAT
1619 * card command). In this case all other threads that are trying to get
1620 * statistics block on that condition variable. When the thread finishes
1621 * using the buffer it resets the flag and signals the condition variable. This
1622 * will wakeup the next thread that is waiting for the buffer. If the interface
1623 * is stopped the stopping function will broadcast the cv. All threads will
1624 * find that the interface has been stopped and return.
1625 *
1626 * Aquiring of the buffer is done by the fatm_getstat() function. The freeing
1627 * must be done by the caller when he has finished using the buffer.
1628 */
1629static void
1630fatm_getstat_complete(struct fatm_softc *sc, struct cmdqueue *q)
1631{
1632
1633 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1634 if (H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
1635 sc->istats.get_stat_errors++;
1636 q->error = EIO;
1637 }
1638 wakeup(&sc->sadi_mem);
1639}
1640static int
1641fatm_getstat(struct fatm_softc *sc)
1642{
1643 int error;
1644 struct cmdqueue *q;
1645
1646 /*
1647 * Wait until either the interface is stopped or we can get the
1648 * statistics buffer
1649 */
1650 for (;;) {
1651 if (!(sc->ifatm.ifnet.if_flags & IFF_RUNNING))
1652 return (EIO);
1653 if (!(sc->flags & FATM_STAT_INUSE))
1654 break;
1655 cv_wait(&sc->cv_stat, &sc->mtx);
1656 }
1657 sc->flags |= FATM_STAT_INUSE;
1658
1659 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, sc->cmdqueue.head);
1660
1661 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1662 if (!(H_GETSTAT(q->q.statp) & FATM_STAT_FREE)) {
1663 sc->istats.cmd_queue_full++;
1664 return (EIO);
1665 }
1666 NEXT_QUEUE_ENTRY(sc->cmdqueue.head, FATM_CMD_QLEN);
1667
1668 q->error = 0;
1669 q->cb = fatm_getstat_complete;
1670 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
1671 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1672
1673 bus_dmamap_sync(sc->sadi_mem.dmat, sc->sadi_mem.map,
1674 BUS_DMASYNC_PREREAD);
1675
1676 WRITE4(sc, q->q.card + FATMOC_GSTAT_BUF,
1677 sc->sadi_mem.paddr);
1678 BARRIER_W(sc);
1679 WRITE4(sc, q->q.card + FATMOC_OP,
1680 FATM_OP_REQUEST_STATS | FATM_OP_INTERRUPT_SEL);
1681 BARRIER_W(sc);
1682
1683 /*
1684 * Wait for the command to complete
1685 */
1686 error = msleep(&sc->sadi_mem, &sc->mtx, PZERO | PCATCH,
1687 "fatm_stat", hz);
1688
1689 switch (error) {
1690
1691 case EWOULDBLOCK:
1692 error = EIO;
1693 break;
1694
1695 case ERESTART:
1696 error = EINTR;
1697 break;
1698
1699 case 0:
1700 bus_dmamap_sync(sc->sadi_mem.dmat, sc->sadi_mem.map,
1701 BUS_DMASYNC_POSTREAD);
1702 error = q->error;
1703 break;
1704 }
1705
1706 /*
1707 * Swap statistics
1708 */
1709 if (q->error == 0) {
1710 u_int i;
1711 uint32_t *p = (uint32_t *)sc->sadi_mem.mem;
1712
1713 for (i = 0; i < sizeof(struct fatm_stats) / sizeof(uint32_t);
1714 i++, p++)
1715 *p = be32toh(*p);
1716 }
1717
1718 return (error);
1719}
1720
1721/*
1722 * Create a copy of a single mbuf. It can have either internal or
1723 * external data, it may have a packet header. External data is really
1724 * copied, so the new buffer is writeable.
1725 */
1726static struct mbuf *
1727copy_mbuf(struct mbuf *m)
1728{
1729 struct mbuf *new;
1730
1731 MGET(new, M_DONTWAIT, MT_DATA);
1732 if (new == NULL)
1733 return (NULL);
1734
1735 if (m->m_flags & M_PKTHDR) {
1736 M_MOVE_PKTHDR(new, m);
1737 if (m->m_len > MHLEN) {
1738 MCLGET(new, M_TRYWAIT);
1739 if ((m->m_flags & M_EXT) == 0) {
1740 m_free(new);
1741 return (NULL);
1742 }
1743 }
1744 } else {
1745 if (m->m_len > MLEN) {
1746 MCLGET(new, M_TRYWAIT);
1747 if ((m->m_flags & M_EXT) == 0) {
1748 m_free(new);
1749 return (NULL);
1750 }
1751 }
1752 }
1753
1754 bcopy(m->m_data, new->m_data, m->m_len);
1755 new->m_len = m->m_len;
1756 new->m_flags &= ~M_RDONLY;
1757
1758 return (new);
1759}
1760
1761/*
1762 * All segments must have a four byte aligned buffer address and a four
1763 * byte aligned length. Step through an mbuf chain and check these conditions.
1764 * If the buffer address is not aligned and this is a normal mbuf, move
1765 * the data down. Else make a copy of the mbuf with aligned data.
1766 * If the buffer length is not aligned steel data from the next mbuf.
1767 * We don't need to check whether this has more than one external reference,
1768 * because steeling data doesn't change the external cluster.
1769 * If the last mbuf is not aligned, fill with zeroes.
1770 *
1771 * Return packet length (well we should have this in the packet header),
1772 * but be careful not to count the zero fill at the end.
1773 *
1774 * If fixing fails free the chain and zero the pointer.
1775 *
1776 * We assume, that aligning the virtual address also aligns the mapped bus
1777 * address.
1778 */
1779static u_int
1780fatm_fix_chain(struct fatm_softc *sc, struct mbuf **mp)
1781{
1782 struct mbuf *m = *mp, *prev = NULL, *next, *new;
1783 u_int mlen = 0, fill = 0;
1784 int first, off;
1785 u_char *d, *cp;
1786
1787 do {
1788 next = m->m_next;
1789
1790 if ((uintptr_t)mtod(m, void *) % 4 != 0 ||
1791 (m->m_len % 4 != 0 && next)) {
1792 /*
1793 * Needs fixing
1794 */
1795 first = (m == *mp);
1796
1797 d = mtod(m, u_char *);
1798 if ((off = (uintptr_t)(void *)d % 4) != 0) {
1799 if (!(m->m_flags & M_EXT) || !MEXT_IS_REF(m)) {
1800 sc->istats.fix_addr_copy++;
1801 bcopy(d, d - off, m->m_len);
1802 m->m_data = (caddr_t)(d - off);
1803 } else {
1804 if ((new = copy_mbuf(m)) == NULL) {
1805 sc->istats.fix_addr_noext++;
1806 goto fail;
1807 }
1808 sc->istats.fix_addr_ext++;
1809 if (prev)
1810 prev->m_next = new;
1811 new->m_next = next;
1812 m_free(m);
1813 m = new;
1814 }
1815 }
1816
1817 if ((off = m->m_len % 4) != 0) {
1818 if ((m->m_flags & M_EXT) && MEXT_IS_REF(m)) {
1819 if ((new = copy_mbuf(m)) == NULL) {
1820 sc->istats.fix_len_noext++;
1821 goto fail;
1822 }
1823 sc->istats.fix_len_copy++;
1824 if (prev)
1825 prev->m_next = new;
1826 new->m_next = next;
1827 m_free(m);
1828 m = new;
1829 } else
1830 sc->istats.fix_len++;
1831 d = mtod(m, u_char *) + m->m_len;
1832 off = 4 - off;
1833 while (off) {
1834 if (next == NULL) {
1835 *d++ = 0;
1836 fill++;
1837 } else if (next->m_len == 0) {
1838 sc->istats.fix_empty++;
1839 next = m_free(next);
1840 continue;
1841 } else {
1842 cp = mtod(next, u_char *);
1843 *d++ = *cp++;
1844 next->m_len--;
1845 next->m_data = (caddr_t)cp;
1846 }
1847 off--;
1848 m->m_len++;
1849 }
1850 }
1851
1852 if (first)
1853 *mp = m;
1854 }
1855
1856 mlen += m->m_len;
1857 prev = m;
1858 } while ((m = next) != NULL);
1859
1860 return (mlen - fill);
1861
1862 fail:
1863 m_freem(*mp);
1864 *mp = NULL;
1865 return (0);
1866}
1867
1868/*
1869 * The helper function is used to load the computed physical addresses
1870 * into the transmit descriptor.
1871 */
1872static void
1873fatm_tpd_load(void *varg, bus_dma_segment_t *segs, int nsegs,
1874 bus_size_t mapsize, int error)
1875{
1876 struct tpd *tpd = varg;
1877
1878 if (error)
1879 return;
1880
1881 KASSERT(nsegs <= TPD_EXTENSIONS + TXD_FIXED, ("too many segments"));
1882
1883 tpd->spec = 0;
1884 while (nsegs--) {
1885 H_SETDESC(tpd->segment[tpd->spec].buffer, segs->ds_addr);
1886 H_SETDESC(tpd->segment[tpd->spec].length, segs->ds_len);
1887 tpd->spec++;
1888 segs++;
1889 }
1890}
1891
1892/*
1893 * Start output.
1894 *
1895 * Note, that we update the internal statistics without the lock here.
1896 */
1897static int
1898fatm_tx(struct fatm_softc *sc, struct mbuf *m, u_int vpi, u_int vci, u_int mlen)
1899{
1900 struct txqueue *q;
1901 u_int nblks;
1902 int error, aal, nsegs;
1903 struct tpd *tpd;
1904
1905 /*
1906 * Get a queue element.
1907 * If there isn't one - try to drain the transmit queue
1908 * We used to sleep here if that doesn't help, but we
1909 * should not sleep here, because we are called with locks.
1910 */
1911 q = GET_QUEUE(sc->txqueue, struct txqueue, sc->txqueue.head);
1912
1913 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1914 if (H_GETSTAT(q->q.statp) != FATM_STAT_FREE) {
1915 fatm_intr_drain_tx(sc);
1916 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
1917 if (H_GETSTAT(q->q.statp) != FATM_STAT_FREE) {
1918 if (sc->retry_tx) {
1919 sc->istats.tx_retry++;
1920 IF_PREPEND(&sc->ifatm.ifnet.if_snd, m);
1921 return (1);
1922 }
1923 sc->istats.tx_queue_full++;
1924 m_freem(m);
1925 return (0);
1926 }
1927 sc->istats.tx_queue_almost_full++;
1928 }
1929
1930 tpd = q->q.ioblk;
1931
1932 m->m_data += sizeof(struct atm_pseudohdr);
1933 m->m_len -= sizeof(struct atm_pseudohdr);
1934
1935 /* map the mbuf */
1936 error = bus_dmamap_load_mbuf(sc->tx_tag, q->map, m,
1937 fatm_tpd_load, tpd, BUS_DMA_NOWAIT);
1938 if(error) {
1939 sc->ifatm.ifnet.if_oerrors++;
1940 if_printf(&sc->ifatm.ifnet, "mbuf loaded error=%d\n", error);
1941 m_freem(m);
1942 return (0);
1943 }
1944 nsegs = tpd->spec;
1945
1946 bus_dmamap_sync(sc->tx_tag, q->map, BUS_DMASYNC_PREWRITE);
1947
1948 /*
1949 * OK. Now go and do it.
1950 */
1951 aal = (sc->vccs[vci].aal == ATMIO_AAL_5) ? 5 : 0;
1952
1953 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
1954 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
1955 q->m = m;
1956
1957 /*
1958 * If the transmit queue is almost full, schedule a
1959 * transmit interrupt so that transmit descriptors can
1960 * be recycled.
1961 */
1962 H_SETDESC(tpd->spec, TDX_MKSPEC((sc->txcnt >=
1963 (4 * FATM_TX_QLEN) / 5), aal, nsegs, mlen));
1964 H_SETDESC(tpd->atm_header, TDX_MKHDR(vpi, vci, 0, 0));
1965
1966 if (sc->vccs[vci].traffic == ATMIO_TRAFFIC_UBR)
1967 H_SETDESC(tpd->stream, 0);
1968 else {
1969 u_int i;
1970
1971 for (i = 0; i < RATE_TABLE_SIZE; i++)
1972 if (rate_table[i].cell_rate < sc->vccs[vci].pcr)
1973 break;
1974 if (i > 0)
1975 i--;
1976 H_SETDESC(tpd->stream, rate_table[i].ratio);
1977 }
1978 H_SYNCQ_PREWRITE(&sc->txq_mem, tpd, TPD_SIZE);
1979
1980 nblks = TDX_SEGS2BLKS(nsegs);
1981
1982 DBG(sc, XMIT, ("XMIT: mlen=%d spec=0x%x nsegs=%d blocks=%d",
1983 mlen, le32toh(tpd->spec), nsegs, nblks));
1984
1985 WRITE4(sc, q->q.card + 0, q->q.card_ioblk | nblks);
1986 BARRIER_W(sc);
1987
1988 sc->txcnt++;
1989 sc->ifatm.ifnet.if_opackets++;
1990
1991 NEXT_QUEUE_ENTRY(sc->txqueue.head, FATM_TX_QLEN);
1992
1993 return (0);
1994}
1995
1996static void
1997fatm_start(struct ifnet *ifp)
1998{
1999 struct atm_pseudohdr aph;
2000 struct fatm_softc *sc;
2001 struct mbuf *m;
2002 u_int mlen, vpi, vci;
2003
2004 sc = (struct fatm_softc *)ifp->if_softc;
2005
2006 while (1) {
2007 IF_DEQUEUE(&ifp->if_snd, m);
2008 if (m == NULL)
2009 break;
2010
2011 /*
2012 * Loop through the mbuf chain and compute the total length
2013 * of the packet. Check that all data pointer are
2014 * 4 byte aligned. If they are not, call fatm_mfix to
2015 * fix that problem. This comes more or less from the
2016 * en driver.
2017 */
2018 mlen = fatm_fix_chain(sc, &m);
2019 if (m == NULL)
2020 continue;
2021
2022 if (m->m_len < sizeof(struct atm_pseudohdr) &&
2023 (m = m_pullup(m, sizeof(struct atm_pseudohdr))) == NULL)
2024 continue;
2025
2026 aph = *mtod(m, struct atm_pseudohdr *);
2027 mlen -= sizeof(struct atm_pseudohdr);
2028
2029 if (mlen == 0) {
2030 m_freem(m);
2031 continue;
2032 }
2033 if (mlen > FATM_MAXPDU) {
2034 sc->istats.tx_pdu2big++;
2035 m_freem(m);
2036 continue;
2037 }
2038
2039 vci = ATM_PH_VCI(&aph);
2040 vpi = ATM_PH_VPI(&aph);
2041
2042 /*
2043 * From here on we need the softc
2044 */
2045 FATM_LOCK(sc);
2046 if (!(ifp->if_flags & IFF_RUNNING)) {
2047 FATM_UNLOCK(sc);
2048 m_freem(m);
2049 break;
2050 }
2051 if (!VC_OK(sc, vpi, vci) ||
2052 !(sc->vccs[vci].flags & FATM_VCC_OPEN)) {
2053 FATM_UNLOCK(sc);
2054 m_freem(m);
2055 continue;
2056 }
2057 if (fatm_tx(sc, m, vpi, vci, mlen)) {
2058 FATM_UNLOCK(sc);
2059 break;
2060 }
2061 FATM_UNLOCK(sc);
2062 }
2063}
2064
2065/*
2066 * Return a table of all currently open VCCs.
2067 */
2068static struct atmio_vcctable *
2069get_vccs(struct fatm_softc *sc, int flags)
2070{
2071 struct atmio_vcctable *vccs;
2072 struct atmio_vcc *v;
2073 u_int i, alloc;
2074
2075 alloc = 10;
2076 vccs = NULL;
2077 for (;;) {
2078 vccs = reallocf(vccs,
2079 sizeof(*vccs) + alloc * sizeof(vccs->vccs[0]),
2080 M_DEVBUF, flags);
2081 if (vccs == NULL)
2082 return (NULL);
2083
2084 vccs->count = 0;
2085 FATM_LOCK(sc);
2086 v = vccs->vccs;
2087 for (i = 0; i < (1U << sc->ifatm.mib.vci_bits); i++) {
2088 if (sc->vccs[i].flags & FATM_VCC_OPEN) {
2089 if (vccs->count++ == alloc) {
2090 alloc *= 2;
2091 break;
2092 }
2093 v->vpi = 0;
2094 v->vci = i;
2095 v->flags = sc->vccs[i].flags;
2096 v->aal = sc->vccs[i].aal;
2097 v->traffic = sc->vccs[i].traffic;
2098 bzero(&v->tparam, sizeof(v->tparam));
2099 v->tparam.pcr = sc->vccs[i].pcr;
2100 v++;
2101 }
2102 }
2103 if (i == (1U << sc->ifatm.mib.vci_bits))
2104 break;
2105 FATM_UNLOCK(sc);
2106 }
2107 FATM_UNLOCK(sc);
2108 return (vccs);
2109}
2110
2111/*
2112 * VCC managment
2113 *
2114 * This may seem complicated. The reason for this is, that we need an
2115 * asynchronuous open/close for the NATM VCCs because our ioctl handler
2116 * is called with the radix node head of the routing table locked. Therefor
2117 * we cannot sleep there and wait for the open/close to succeed. For this
2118 * reason we just initiate the operation from the ioctl.
2119 */
2120
2121/*
2122 * Command the card to open/close a VC.
2123 * Return the queue entry for waiting if we are succesful.
2124 */
2125static struct cmdqueue *
2126fatm_start_vcc(struct fatm_softc *sc, u_int vpi, u_int vci, uint32_t cmd,
2127 u_int mtu, void (*func)(struct fatm_softc *, struct cmdqueue *))
2128{
2129 struct cmdqueue *q;
2130
2131 q = GET_QUEUE(sc->cmdqueue, struct cmdqueue, sc->cmdqueue.head);
2132
2133 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
2134 if (!(H_GETSTAT(q->q.statp) & FATM_STAT_FREE)) {
2135 sc->istats.cmd_queue_full++;
2136 return (NULL);
2137 }
2138 NEXT_QUEUE_ENTRY(sc->cmdqueue.head, FATM_CMD_QLEN);
2139
2140 q->error = 0;
2141 q->cb = func;
2142 H_SETSTAT(q->q.statp, FATM_STAT_PENDING);
2143 H_SYNCSTAT_PREWRITE(sc, q->q.statp);
2144
2145 WRITE4(sc, q->q.card + FATMOC_ACTIN_VPVC, MKVPVC(vpi, vci));
2146 BARRIER_W(sc);
2147 WRITE4(sc, q->q.card + FATMOC_ACTIN_MTU, mtu);
2148 BARRIER_W(sc);
2149 WRITE4(sc, q->q.card + FATMOC_OP, cmd);
2150 BARRIER_W(sc);
2151
2152 return (q);
2153}
2154
2155/*
2156 * Start to open a VCC. This just initiates the operation.
2157 */
2158static int
2159fatm_start_open_vcc(struct fatm_softc *sc, u_int vpi, u_int vci, u_int aal,
2160 u_int traffic, u_int pcr, u_int flags, void *rxhand,
2161 void (*func)(struct fatm_softc *, struct cmdqueue *), struct cmdqueue **qp)
2162{
2163 int error;
2164 uint32_t cmd;
2165 struct cmdqueue *q;
2166
2167 error = 0;
2168
2169 if (!(sc->ifatm.ifnet.if_flags & IFF_RUNNING))
2170 return (EIO);
2171 if (!VC_OK(sc, vpi, vci) ||
2172 (aal != ATMIO_AAL_0 && aal != ATMIO_AAL_5) ||
2173 (traffic != ATMIO_TRAFFIC_UBR && traffic != ATMIO_TRAFFIC_CBR))
2174 return (EINVAL);
2175 if (sc->vccs[vci].flags & FATM_VCC_BUSY)
2176 return (EBUSY);
2177
2178 /* Command and buffer strategy */
2179 cmd = FATM_OP_ACTIVATE_VCIN | FATM_OP_INTERRUPT_SEL | (0 << 16);
2180 if (aal == ATMIO_AAL_0)
2181 cmd |= (0 << 8);
2182 else
2183 cmd |= (5 << 8);
2184
2185 if ((q = fatm_start_vcc(sc, vpi, vci, cmd, 1, func)) == NULL)
2186 return (EIO);
2187 if (qp != NULL)
2188 *qp = q;
2189
2190 sc->vccs[vci].aal = aal;
2191 sc->vccs[vci].flags = flags | FATM_VCC_TRY_OPEN;
2192 sc->vccs[vci].rxhand = rxhand;
2193 sc->vccs[vci].pcr = pcr;
2194 sc->vccs[vci].traffic = traffic;
2195
2196 return (0);
2197}
2198
2199/*
2200 * Initiate closing a VCC
2201 */
2202static int
2203fatm_start_close_vcc(struct fatm_softc *sc, u_int vpi, u_int vci,
2204 void (*func)(struct fatm_softc *, struct cmdqueue *), struct cmdqueue **qp)
2205{
2206 int error;
2207 struct cmdqueue *q;
2208
2209 error = 0;
2210
2211 if (!(sc->ifatm.ifnet.if_flags & IFF_RUNNING))
2212 return (EIO);
2213 if (!VC_OK(sc, vpi, vci))
2214 return (EINVAL);
2215 if (!(sc->vccs[vci].flags & (FATM_VCC_OPEN | FATM_VCC_TRY_OPEN)))
2216 return (ENOENT);
2217
2218 if ((q = fatm_start_vcc(sc, vpi, vci,
2219 FATM_OP_DEACTIVATE_VCIN | FATM_OP_INTERRUPT_SEL, 1, func)) == NULL)
2220 return (EIO);
2221
2222 if (qp != NULL)
2223 *qp = q;
2224
2225 sc->vccs[vci].flags &= ~(FATM_VCC_OPEN | FATM_VCC_TRY_OPEN);
2226 sc->vccs[vci].flags |= FATM_VCC_TRY_CLOSE;
2227
2228 return (0);
2229}
2230
2231/*
2232 * Wait on the queue entry until the VCC is opened/closed.
2233 */
2234static int
2235fatm_waitvcc(struct fatm_softc *sc, struct cmdqueue *q)
2236{
2237 int error;
2238
2239 /*
2240 * Wait for the command to complete
2241 */
2242 error = msleep(q, &sc->mtx, PZERO | PCATCH, "fatm_vci", hz);
2243
2244 if (error != 0)
2245 return (error);
2246 return (q->error);
2247}
2248
2249/*
2250 * The VC has been opened/closed and somebody has been waiting for this.
2251 * Wake him up.
2252 */
2253static void
2254fatm_cmd_complete(struct fatm_softc *sc, struct cmdqueue *q)
2255{
2256
2257 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
2258 if (H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
2259 sc->istats.get_stat_errors++;
2260 q->error = EIO;
2261 }
2262 wakeup(q);
2263}
2264
2265/*
2266 * Open a vcc and wait for completion
2267 */
2268static int
2269fatm_open_vcc(struct fatm_softc *sc, u_int vpi, u_int vci, u_int flags,
2270 u_int aal, u_int traffic, u_int pcr, void *rxhand)
2271{
2272 int error;
2273 struct cmdqueue *q;
2274
2275 error = 0;
2276
2277 FATM_LOCK(sc);
2278 error = fatm_start_open_vcc(sc, vpi, vci, aal, traffic, pcr,
2279 flags, rxhand, fatm_cmd_complete, &q);
2280 if (error != 0) {
2281 FATM_UNLOCK(sc);
2282 return (error);
2283 }
2284 error = fatm_waitvcc(sc, q);
2285
2286 if (error == 0) {
2287 sc->vccs[vci].flags &= ~FATM_VCC_TRY_OPEN;
2288 sc->vccs[vci].flags |= FATM_VCC_OPEN;
2289 sc->open_vccs++;
2290
2291 /* inform management if this is not an NG
2292 * VCC or it's an NG PVC. */
2293 if (!(sc->vccs[vci].flags & ATMIO_FLAG_NG) ||
2294 (sc->vccs[vci].flags & ATMIO_FLAG_PVC))
2295 ATMEV_SEND_VCC_CHANGED(&sc->ifatm, 0, vci, 1);
2296 } else
2297 bzero(&sc->vccs[vci], sizeof(sc->vccs[vci]));
2298
2299 FATM_UNLOCK(sc);
2300 return (error);
2301}
2302
2303/*
2304 * Close a VCC synchronuosly
2305 */
2306static int
2307fatm_close_vcc(struct fatm_softc *sc, u_int vpi, u_int vci)
2308{
2309 int error;
2310 struct cmdqueue *q;
2311
2312 error = 0;
2313
2314 FATM_LOCK(sc);
2315 error = fatm_start_close_vcc(sc, vpi, vci, fatm_cmd_complete, &q);
2316 if (error != 0) {
2317 FATM_UNLOCK(sc);
2318 return (error);
2319 }
2320 error = fatm_waitvcc(sc, q);
2321
2322 if (error == 0) {
2323 /* inform management of this is not an NG
2324 * VCC or it's an NG PVC. */
2325 if (!(sc->vccs[vci].flags & ATMIO_FLAG_NG) ||
2326 (sc->vccs[vci].flags & ATMIO_FLAG_PVC))
2327 ATMEV_SEND_VCC_CHANGED(&sc->ifatm, 0, vci, 0);
2328
2329 bzero(&sc->vccs[vci], sizeof(sc->vccs[vci]));
2330 sc->open_vccs--;
2331 }
2332
2333 FATM_UNLOCK(sc);
2334 return (error);
2335}
2336
2337/*
2338 * The VC has been opened.
2339 */
2340static void
2341fatm_open_complete(struct fatm_softc *sc, struct cmdqueue *q)
2342{
2343 u_int vci;
2344
2345 vci = GETVCI(READ4(sc, q->q.card + FATMOC_ACTIN_VPVC));
2346 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
2347 if (H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
2348 sc->istats.get_stat_errors++;
2349 bzero(&sc->vccs[vci], sizeof(sc->vccs[vci]));
2350 if_printf(&sc->ifatm.ifnet, "opening VCI %u failed\n", vci);
2351 return;
2352 }
2353
2354 sc->vccs[vci].flags &= ~FATM_VCC_TRY_OPEN;
2355 sc->vccs[vci].flags |= FATM_VCC_OPEN;
2356 sc->open_vccs++;
2357
2358 /* inform management if this is not an NG
2359 * VCC or it's an NG PVC. */
2360 if (!(sc->vccs[vci].flags & ATMIO_FLAG_NG) ||
2361 (sc->vccs[vci].flags & ATMIO_FLAG_PVC))
2362 ATMEV_SEND_VCC_CHANGED(&sc->ifatm, 0, vci, 1);
2363}
2364
2365/*
2366 * The VC has been closed.
2367 */
2368static void
2369fatm_close_complete(struct fatm_softc *sc, struct cmdqueue *q)
2370{
2371 u_int vci;
2372
2373 vci = GETVCI(READ4(sc, q->q.card + FATMOC_ACTIN_VPVC));
2374 H_SYNCSTAT_POSTREAD(sc, q->q.statp);
2375 if (H_GETSTAT(q->q.statp) & FATM_STAT_ERROR) {
2376 sc->istats.get_stat_errors++;
2377 /* keep the VCC in that state */
2378 if_printf(&sc->ifatm.ifnet, "closing VCI %u failed\n", vci);
2379 return;
2380 }
2381
2382 /* inform management of this is not an NG
2383 * VCC or it's an NG PVC. */
2384 if (!(sc->vccs[vci].flags & ATMIO_FLAG_NG) ||
2385 (sc->vccs[vci].flags & ATMIO_FLAG_PVC))
2386 ATMEV_SEND_VCC_CHANGED(&sc->ifatm, 0, vci, 0);
2387
2388 bzero(&sc->vccs[vci], sizeof(sc->vccs[vci]));
2389 sc->open_vccs--;
2390}
2391
2392/*
2393 * Open a vcc but don't wait.
2394 */
2395static int
2396fatm_open_vcc_nowait(struct fatm_softc *sc, u_int vpi, u_int vci, u_int flags,
2397 u_int aal, void *rxhand)
2398{
2399 int error;
2400
2401 FATM_LOCK(sc);
2402 error = fatm_start_open_vcc(sc, vpi, vci, aal, ATMIO_TRAFFIC_UBR, 0,
2403 flags, rxhand, fatm_open_complete, NULL);
2404 FATM_UNLOCK(sc);
2405 return (error);
2406}
2407
2408/*
2409 * Close a VCC but don't wait
2410 */
2411static int
2412fatm_close_vcc_nowait(struct fatm_softc *sc, u_int vpi, u_int vci)
2413{
2414 int error;
2415
2416 FATM_LOCK(sc);
2417 error = fatm_start_close_vcc(sc, vpi, vci, fatm_close_complete, NULL);
2418 FATM_UNLOCK(sc);
2419 return (error);
2420}
2421
2422/*
2423 * IOCTL handler
2424 */
2425static int
2426fatm_ioctl(struct ifnet *ifp, u_long cmd, caddr_t arg)
2427{
2428 int error;
2429 struct fatm_softc *sc = ifp->if_softc;
2430 struct ifaddr *ifa = (struct ifaddr *)arg;
2431 struct ifreq *ifr = (struct ifreq *)arg;
2432 struct atmio_closevcc *cl = (struct atmio_closevcc *)arg;
2433 struct atmio_openvcc *op = (struct atmio_openvcc *)arg;
2434 struct atm_pseudoioctl *pa = (struct atm_pseudoioctl *)arg;
2435 struct atmio_vcctable *vtab;
2436
2437 error = 0;
2438 switch (cmd) {
2439
2440 case SIOCATMENA: /* internal NATM use */
2441 error = fatm_open_vcc_nowait(sc, ATM_PH_VPI(&pa->aph),
2442 ATM_PH_VCI(&pa->aph), ATM_PH_FLAGS(&pa->aph),
2443 (ATM_PH_FLAGS(&pa->aph) & ATM_PH_AAL5) ? ATMIO_AAL_5 :
2444 ATMIO_AAL_0, pa->rxhand);
2445 break;
2446
2447 case SIOCATMDIS: /* internal NATM use */
2448 error = fatm_close_vcc_nowait(sc, ATM_PH_VPI(&pa->aph),
2449 ATM_PH_VCI(&pa->aph));
2450 break;
2451
2452 case SIOCATMOPENVCC:
2453 error = fatm_open_vcc(sc, op->param.vpi, op->param.vci,
2454 op->param.flags, op->param.aal, op->param.traffic,
2455 op->param.tparam.pcr, op->rxhand);
2456 break;
2457
2458 case SIOCATMCLOSEVCC:
2459 error = fatm_close_vcc(sc, cl->vpi, cl->vci);
2460 break;
2461
2462 case SIOCSIFADDR:
2463 FATM_LOCK(sc);
2464 ifp->if_flags |= IFF_UP;
2465 if (!(ifp->if_flags & IFF_RUNNING))
2466 fatm_init_locked(sc);
2467 switch (ifa->ifa_addr->sa_family) {
2468#ifdef INET
2469 case AF_INET:
2470 case AF_INET6:
2471 ifa->ifa_rtrequest = atm_rtrequest;
2472 break;
2473#endif
2474 default:
2475 break;
2476 }
2477 FATM_UNLOCK(sc);
2478 break;
2479
2480 case SIOCSIFFLAGS:
2481 FATM_LOCK(sc);
2482 if (ifp->if_flags & IFF_UP) {
2483 if (!(ifp->if_flags & IFF_RUNNING)) {
2484 fatm_init_locked(sc);
2485 }
2486 } else {
2487 if (ifp->if_flags & IFF_RUNNING) {
2488 fatm_stop(sc);
2489 }
2490 }
2491 FATM_UNLOCK(sc);
2492 break;
2493
2494 case SIOCGIFMEDIA:
2495 case SIOCSIFMEDIA:
2496 if (ifp->if_flags & IFF_RUNNING)
2497 error = ifmedia_ioctl(ifp, ifr, &sc->media, cmd);
2498 else
2499 error = EINVAL;
2500 break;
2501
2502 case SIOCATMGVCCS:
2503 /* return vcc table */
2504 vtab = get_vccs(sc, M_WAITOK);
2505 if (vtab == NULL) {
2506 error = ENOMEM;
2507 break;
2508 }
2509 error = copyout(vtab, ifr->ifr_data, sizeof(*vtab) +
2510 vtab->count * sizeof(vtab->vccs[0]));
2511 free(vtab, M_DEVBUF);
2512 break;
2513
2514 case SIOCATMGETVCCS: /* internal netgraph use */
2515 vtab = get_vccs(sc, M_NOWAIT);
2516 if (vtab == NULL) {
2517 error = ENOMEM;
2518 break;
2519 }
2520 *(void **)arg = vtab;
2521 break;
2522
2523 default:
2524 DBG(sc, IOCTL, ("+++ cmd=%08lx arg=%p", cmd, arg));
2525 error = EINVAL;
2526 break;
2527 }
2528
2529 return (error);
2530}
2531
2532/*
2533 * Detach from the interface and free all resources allocated during
2534 * initialisation and later.
2535 */
2536static int
2537fatm_detach(device_t dev)
2538{
2539 u_int i;
2540 struct rbuf *rb;
2541 struct fatm_softc *sc;
2542 struct txqueue *tx;
2543
2544 sc = (struct fatm_softc *)device_get_softc(dev);
2545
2546 if (device_is_alive(dev)) {
2547 FATM_LOCK(sc);
2548 fatm_stop(sc);
2549 utopia_detach(&sc->utopia);
2550 FATM_UNLOCK(sc);
2551 atm_ifdetach(&sc->ifatm.ifnet); /* XXX race */
2552 }
2553
2554 if (sc->ih != NULL)
2555 bus_teardown_intr(dev, sc->irqres, sc->ih);
2556
2557 while ((rb = LIST_FIRST(&sc->rbuf_used)) != NULL) {
2558 if_printf(&sc->ifatm.ifnet, "rbuf %p still in use!\n", rb);
2559 bus_dmamap_unload(sc->rbuf_tag, rb->map);
2560 m_freem(rb->m);
2561 LIST_REMOVE(rb, link);
2562 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
2563 }
2564
2565 if (sc->txqueue.chunk != NULL) {
2566 for (i = 0; i < FATM_TX_QLEN; i++) {
2567 tx = GET_QUEUE(sc->txqueue, struct txqueue, i);
2568 bus_dmamap_destroy(sc->tx_tag, tx->map);
2569 }
2570 }
2571
2572 while ((rb = LIST_FIRST(&sc->rbuf_free)) != NULL) {
2573 bus_dmamap_destroy(sc->rbuf_tag, rb->map);
2574 LIST_REMOVE(rb, link);
2575 }
2576
2577 free(sc->rbufs, M_DEVBUF);
2578 free(sc->vccs, M_DEVBUF);
2579
2580 free(sc->l1queue.chunk, M_DEVBUF);
2581 free(sc->s1queue.chunk, M_DEVBUF);
2582 free(sc->rxqueue.chunk, M_DEVBUF);
2583 free(sc->txqueue.chunk, M_DEVBUF);
2584 free(sc->cmdqueue.chunk, M_DEVBUF);
2585
2586 destroy_dma_memory(&sc->reg_mem);
2587 destroy_dma_memory(&sc->sadi_mem);
2588 destroy_dma_memory(&sc->prom_mem);
2589#ifdef TEST_DMA_SYNC
2590 destroy_dma_memoryX(&sc->s1q_mem);
2591 destroy_dma_memoryX(&sc->l1q_mem);
2592 destroy_dma_memoryX(&sc->rxq_mem);
2593 destroy_dma_memoryX(&sc->txq_mem);
2594 destroy_dma_memoryX(&sc->stat_mem);
2595#endif
2596
2597 if (sc->tx_tag != NULL)
2598 if (bus_dma_tag_destroy(sc->tx_tag))
2599 printf("tx DMA tag busy!\n");
2600
2601 if (sc->rbuf_tag != NULL)
2602 if (bus_dma_tag_destroy(sc->rbuf_tag))
2603 printf("rbuf DMA tag busy!\n");
2604
2605 if (sc->parent_dmat != NULL)
2606 if (bus_dma_tag_destroy(sc->parent_dmat))
2607 printf("parent DMA tag busy!\n");
2608
2609 if (sc->irqres != NULL)
2610 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irqres);
2611
2612 if (sc->memres != NULL)
2613 bus_release_resource(dev, SYS_RES_MEMORY,
2614 sc->memid, sc->memres);
2615
2616 (void)sysctl_ctx_free(&sc->sysctl_ctx);
2617
2618 cv_destroy(&sc->cv_stat);
2619 cv_destroy(&sc->cv_regs);
2620
2621 mtx_destroy(&sc->mtx);
2622
2623 return (0);
2624}
2625
2626/*
2627 * Sysctl handler
2628 */
2629static int
2630fatm_sysctl_istats(SYSCTL_HANDLER_ARGS)
2631{
2632 struct fatm_softc *sc = arg1;
2633 u_long *ret;
2634 int error;
2635
2636 ret = malloc(sizeof(sc->istats), M_TEMP, M_WAITOK);
2637
2638 FATM_LOCK(sc);
2639 bcopy(&sc->istats, ret, sizeof(sc->istats));
2640 FATM_UNLOCK(sc);
2641
2642 error = SYSCTL_OUT(req, ret, sizeof(sc->istats));
2643 free(ret, M_TEMP);
2644
2645 return (error);
2646}
2647
2648/*
2649 * Sysctl handler for card statistics
2650 * This is disable because it destroys the PHY statistics.
2651 */
2652static int
2653fatm_sysctl_stats(SYSCTL_HANDLER_ARGS)
2654{
2655 struct fatm_softc *sc = arg1;
2656 int error;
2657 const struct fatm_stats *s;
2658 u_long *ret;
2659 u_int i;
2660
2661 ret = malloc(sizeof(u_long) * FATM_NSTATS, M_TEMP, M_WAITOK);
2662
2663 FATM_LOCK(sc);
2664
2665 if ((error = fatm_getstat(sc)) == 0) {
2666 s = sc->sadi_mem.mem;
2667 i = 0;
2668 ret[i++] = s->phy_4b5b.crc_header_errors;
2669 ret[i++] = s->phy_4b5b.framing_errors;
2670 ret[i++] = s->phy_oc3.section_bip8_errors;
2671 ret[i++] = s->phy_oc3.path_bip8_errors;
2672 ret[i++] = s->phy_oc3.line_bip24_errors;
2673 ret[i++] = s->phy_oc3.line_febe_errors;
2674 ret[i++] = s->phy_oc3.path_febe_errors;
2675 ret[i++] = s->phy_oc3.corr_hcs_errors;
2676 ret[i++] = s->phy_oc3.ucorr_hcs_errors;
2677 ret[i++] = s->atm.cells_transmitted;
2678 ret[i++] = s->atm.cells_received;
2679 ret[i++] = s->atm.vpi_bad_range;
2680 ret[i++] = s->atm.vpi_no_conn;
2681 ret[i++] = s->atm.vci_bad_range;
2682 ret[i++] = s->atm.vci_no_conn;
2683 ret[i++] = s->aal0.cells_transmitted;
2684 ret[i++] = s->aal0.cells_received;
2685 ret[i++] = s->aal0.cells_dropped;
2686 ret[i++] = s->aal4.cells_transmitted;
2687 ret[i++] = s->aal4.cells_received;
2688 ret[i++] = s->aal4.cells_crc_errors;
2689 ret[i++] = s->aal4.cels_protocol_errors;
2690 ret[i++] = s->aal4.cells_dropped;
2691 ret[i++] = s->aal4.cspdus_transmitted;
2692 ret[i++] = s->aal4.cspdus_received;
2693 ret[i++] = s->aal4.cspdus_protocol_errors;
2694 ret[i++] = s->aal4.cspdus_dropped;
2695 ret[i++] = s->aal5.cells_transmitted;
2696 ret[i++] = s->aal5.cells_received;
2697 ret[i++] = s->aal5.congestion_experienced;
2698 ret[i++] = s->aal5.cells_dropped;
2699 ret[i++] = s->aal5.cspdus_transmitted;
2700 ret[i++] = s->aal5.cspdus_received;
2701 ret[i++] = s->aal5.cspdus_crc_errors;
2702 ret[i++] = s->aal5.cspdus_protocol_errors;
2703 ret[i++] = s->aal5.cspdus_dropped;
2704 ret[i++] = s->aux.small_b1_failed;
2705 ret[i++] = s->aux.large_b1_failed;
2706 ret[i++] = s->aux.small_b2_failed;
2707 ret[i++] = s->aux.large_b2_failed;
2708 ret[i++] = s->aux.rpd_alloc_failed;
2709 ret[i++] = s->aux.receive_carrier;
2710 }
2711 /* declare the buffer free */
2712 sc->flags &= ~FATM_STAT_INUSE;
2713 cv_signal(&sc->cv_stat);
2714
2715 FATM_UNLOCK(sc);
2716
2717 if (error == 0)
2718 error = SYSCTL_OUT(req, ret, sizeof(u_long) * FATM_NSTATS);
2719 free(ret, M_TEMP);
2720
2721 return (error);
2722}
2723
2724#define MAXDMASEGS 32 /* maximum number of receive descriptors */
2725
2726/*
2727 * Attach to the device.
2728 *
2729 * We assume, that there is a global lock (Giant in this case) that protects
2730 * multiple threads from entering this function. This makes sense, doesn't it?
2731 */
2732static int
2733fatm_attach(device_t dev)
2734{
2735 struct ifnet *ifp;
2736 struct fatm_softc *sc;
2737 int unit;
2738 uint16_t cfg;
2739 int error = 0;
2740 struct rbuf *rb;
2741 u_int i;
2742 struct txqueue *tx;
2743
2744 sc = device_get_softc(dev);
2745 unit = device_get_unit(dev);
2746
2747 sc->ifatm.mib.device = ATM_DEVICE_PCA200E;
2748 sc->ifatm.mib.serial = 0;
2749 sc->ifatm.mib.hw_version = 0;
2750 sc->ifatm.mib.sw_version = 0;
2751 sc->ifatm.mib.vpi_bits = 0;
2752 sc->ifatm.mib.vci_bits = FORE_VCIBITS;
2753 sc->ifatm.mib.max_vpcs = 0;
2754 sc->ifatm.mib.max_vccs = FORE_MAX_VCC;
2755 sc->ifatm.mib.media = IFM_ATM_UNKNOWN;
2756 sc->ifatm.phy = &sc->utopia;
2757
2758 LIST_INIT(&sc->rbuf_free);
2759 LIST_INIT(&sc->rbuf_used);
2760
2761 /*
2762 * Initialize mutex and condition variables.
2763 */
2764 mtx_init(&sc->mtx, device_get_nameunit(dev),
2765 MTX_NETWORK_LOCK, MTX_DEF);
2766
2767 cv_init(&sc->cv_stat, "fatm_stat");
2768 cv_init(&sc->cv_regs, "fatm_regs");
2769
2770 sysctl_ctx_init(&sc->sysctl_ctx);
2771
2772 /*
2773 * Make the sysctl tree
2774 */
2775 if ((sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
2776 SYSCTL_STATIC_CHILDREN(_hw_atm), OID_AUTO,
2777 device_get_nameunit(dev), CTLFLAG_RD, 0, "")) == NULL)
2778 goto fail;
2779
2780 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2781 OID_AUTO, "istats", CTLFLAG_RD, sc, 0, fatm_sysctl_istats,
2782 "LU", "internal statistics") == NULL)
2783 goto fail;
2784
2785 if (SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2786 OID_AUTO, "stats", CTLFLAG_RD, sc, 0, fatm_sysctl_stats,
2787 "LU", "card statistics") == NULL)
2788 goto fail;
2789
2790 if (SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2791 OID_AUTO, "retry_tx", CTLFLAG_RW, &sc->retry_tx, 0,
2792 "retry flag") == NULL)
2793 goto fail;
2794
2795#ifdef FATM_DEBUG
2796 if (SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
2797 OID_AUTO, "debug", CTLFLAG_RW, &sc->debug, 0, "debug flags")
2798 == NULL)
2799 goto fail;
2800 sc->debug = FATM_DEBUG;
2801#endif
2802
2803 /*
2804 * Network subsystem stuff
2805 */
2806 ifp = &sc->ifatm.ifnet;
2807 ifp->if_softc = sc;
2808 ifp->if_unit = unit;
2809 ifp->if_name = "fatm";
2810 ifp->if_flags = IFF_SIMPLEX;
2811 ifp->if_ioctl = fatm_ioctl;
2812 ifp->if_start = fatm_start;
2813 ifp->if_watchdog = fatm_watchdog;
2814 ifp->if_init = fatm_init;
2815 ifp->if_linkmib = &sc->ifatm.mib;
2816 ifp->if_linkmiblen = sizeof(sc->ifatm.mib);
2817
2818 /*
2819 * Enable memory and bustmaster
2820 */
2821 cfg = pci_read_config(dev, PCIR_COMMAND, 2);
2822 cfg |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
2823 pci_write_config(dev, PCIR_COMMAND, cfg, 2);
2824
2825 /*
2826 * Map memory
2827 */
2828 cfg = pci_read_config(dev, PCIR_COMMAND, 2);
2829 if (!(cfg & PCIM_CMD_MEMEN)) {
2830 if_printf(ifp, "failed to enable memory mapping\n");
2831 error = ENXIO;
2832 goto fail;
2833 }
2834 sc->memid = 0x10;
2835 sc->memres = bus_alloc_resource(dev, SYS_RES_MEMORY, &sc->memid,
2836 0, ~0, 1, RF_ACTIVE);
2837 if (sc->memres == NULL) {
2838 if_printf(ifp, "could not map memory\n");
2839 error = ENXIO;
2840 goto fail;
2841 }
2842 sc->memh = rman_get_bushandle(sc->memres);
2843 sc->memt = rman_get_bustag(sc->memres);
2844
2845 /*
2846 * Convert endianess of slave access
2847 */
2848 cfg = pci_read_config(dev, FATM_PCIR_MCTL, 1);
2849 cfg |= FATM_PCIM_SWAB;
2850 pci_write_config(dev, FATM_PCIR_MCTL, cfg, 1);
2851
2852 /*
2853 * Allocate interrupt (activate at the end)
2854 */
2855 sc->irqid = 0;
2856 sc->irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
2857 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
2858 if (sc->irqres == NULL) {
2859 if_printf(ifp, "could not allocate irq\n");
2860 error = ENXIO;
2861 goto fail;
2862 }
2863
2864 /*
2865 * Allocate the parent DMA tag. This is used simply to hold overall
2866 * restrictions for the controller (and PCI bus) and is never used
2867 * to do anything.
2868 */
2869 if (bus_dma_tag_create(NULL, 1, 0,
2870 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
2871 NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, MAXDMASEGS,
2872 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
2873 &sc->parent_dmat)) {
2874 if_printf(ifp, "could not allocate parent DMA tag\n");
2875 error = ENOMEM;
2876 goto fail;
2877 }
2878
2879 /*
2880 * Allocate the receive buffer DMA tag. This tag must map a maximum of
2881 * a mbuf cluster.
2882 */
2883 if (bus_dma_tag_create(sc->parent_dmat, 1, 0,
2884 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
2885 NULL, NULL, MCLBYTES, 1, MCLBYTES, 0,
2886 NULL, NULL, &sc->rbuf_tag)) {
2887 if_printf(ifp, "could not allocate rbuf DMA tag\n");
2888 error = ENOMEM;
2889 goto fail;
2890 }
2891
2892 /*
2893 * Allocate the transmission DMA tag. Must add 1, because
2894 * rounded up PDU will be 65536 bytes long.
2895 */
2896 if (bus_dma_tag_create(sc->parent_dmat, 1, 0,
2897 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
2898 NULL, NULL,
2899 FATM_MAXPDU + 1, TPD_EXTENSIONS + TXD_FIXED, MCLBYTES, 0,
2900 NULL, NULL, &sc->tx_tag)) {
2901 if_printf(ifp, "could not allocate tx DMA tag\n");
2902 error = ENOMEM;
2903 goto fail;
2904 }
2905
2906 /*
2907 * Allocate DMAable memory.
2908 */
2909 sc->stat_mem.size = sizeof(uint32_t) * (FATM_CMD_QLEN + FATM_TX_QLEN
2910 + FATM_RX_QLEN + SMALL_SUPPLY_QLEN + LARGE_SUPPLY_QLEN);
2911 sc->stat_mem.align = 4;
2912
2913 sc->txq_mem.size = FATM_TX_QLEN * TPD_SIZE;
2914 sc->txq_mem.align = 32;
2915
2916 sc->rxq_mem.size = FATM_RX_QLEN * RPD_SIZE;
2917 sc->rxq_mem.align = 32;
2918
2919 sc->s1q_mem.size = SMALL_SUPPLY_QLEN *
2920 BSUP_BLK2SIZE(SMALL_SUPPLY_BLKSIZE);
2921 sc->s1q_mem.align = 32;
2922
2923 sc->l1q_mem.size = LARGE_SUPPLY_QLEN *
2924 BSUP_BLK2SIZE(LARGE_SUPPLY_BLKSIZE);
2925 sc->l1q_mem.align = 32;
2926
2927#ifdef TEST_DMA_SYNC
2928 if ((error = alloc_dma_memoryX(sc, "STATUS", &sc->stat_mem)) != 0 ||
2929 (error = alloc_dma_memoryX(sc, "TXQ", &sc->txq_mem)) != 0 ||
2930 (error = alloc_dma_memoryX(sc, "RXQ", &sc->rxq_mem)) != 0 ||
2931 (error = alloc_dma_memoryX(sc, "S1Q", &sc->s1q_mem)) != 0 ||
2932 (error = alloc_dma_memoryX(sc, "L1Q", &sc->l1q_mem)) != 0)
2933 goto fail;
2934#else
2935 if ((error = alloc_dma_memory(sc, "STATUS", &sc->stat_mem)) != 0 ||
2936 (error = alloc_dma_memory(sc, "TXQ", &sc->txq_mem)) != 0 ||
2937 (error = alloc_dma_memory(sc, "RXQ", &sc->rxq_mem)) != 0 ||
2938 (error = alloc_dma_memory(sc, "S1Q", &sc->s1q_mem)) != 0 ||
2939 (error = alloc_dma_memory(sc, "L1Q", &sc->l1q_mem)) != 0)
2940 goto fail;
2941#endif
2942
2943 sc->prom_mem.size = sizeof(struct prom);
2944 sc->prom_mem.align = 32;
2945 if ((error = alloc_dma_memory(sc, "PROM", &sc->prom_mem)) != 0)
2946 goto fail;
2947
2948 sc->sadi_mem.size = sizeof(struct fatm_stats);
2949 sc->sadi_mem.align = 32;
2950 if ((error = alloc_dma_memory(sc, "STATISTICS", &sc->sadi_mem)) != 0)
2951 goto fail;
2952
2953 sc->reg_mem.size = sizeof(uint32_t) * FATM_NREGS;
2954 sc->reg_mem.align = 32;
2955 if ((error = alloc_dma_memory(sc, "REGISTERS", &sc->reg_mem)) != 0)
2956 goto fail;
2957
2958 /*
2959 * Allocate queues
2960 */
2961 sc->cmdqueue.chunk = malloc(FATM_CMD_QLEN * sizeof(struct cmdqueue),
2962 M_DEVBUF, M_ZERO | M_WAITOK);
2963 sc->txqueue.chunk = malloc(FATM_TX_QLEN * sizeof(struct txqueue),
2964 M_DEVBUF, M_ZERO | M_WAITOK);
2965 sc->rxqueue.chunk = malloc(FATM_RX_QLEN * sizeof(struct rxqueue),
2966 M_DEVBUF, M_ZERO | M_WAITOK);
2967 sc->s1queue.chunk = malloc(SMALL_SUPPLY_QLEN * sizeof(struct supqueue),
2968 M_DEVBUF, M_ZERO | M_WAITOK);
2969 sc->l1queue.chunk = malloc(LARGE_SUPPLY_QLEN * sizeof(struct supqueue),
2970 M_DEVBUF, M_ZERO | M_WAITOK);
2971
2972 sc->vccs = malloc((FORE_MAX_VCC + 1) * sizeof(struct card_vcc),
2973 M_DEVBUF, M_ZERO | M_WAITOK);
2974
2975 /*
2976 * Allocate memory for the receive buffer headers. The total number
2977 * of headers should probably also include the maximum number of
2978 * buffers on the receive queue.
2979 */
2980 sc->rbuf_total = SMALL_POOL_SIZE + LARGE_POOL_SIZE;
2981 sc->rbufs = malloc(sc->rbuf_total * sizeof(struct rbuf),
2982 M_DEVBUF, M_ZERO | M_WAITOK);
2983
2984 /*
2985 * Put all rbuf headers on the free list and create DMA maps.
2986 */
2987 for (rb = sc->rbufs, i = 0; i < sc->rbuf_total; i++, rb++) {
2988 if ((error = bus_dmamap_create(sc->rbuf_tag, 0, &rb->map))) {
2989 if_printf(&sc->ifatm.ifnet, "creating rx map: %d\n",
2990 error);
2991 goto fail;
2992 }
2993 LIST_INSERT_HEAD(&sc->rbuf_free, rb, link);
2994 }
2995
2996 /*
2997 * Create dma maps for transmission. In case of an error, free the
2998 * allocated DMA maps, because on some architectures maps are NULL
2999 * and we cannot distinguish between a failure and a NULL map in
3000 * the detach routine.
3001 */
3002 for (i = 0; i < FATM_TX_QLEN; i++) {
3003 tx = GET_QUEUE(sc->txqueue, struct txqueue, i);
3004 if ((error = bus_dmamap_create(sc->tx_tag, 0, &tx->map))) {
3005 if_printf(&sc->ifatm.ifnet, "creating tx map: %d\n",
3006 error);
3007 while (i > 0) {
3008 tx = GET_QUEUE(sc->txqueue, struct txqueue,
3009 i - 1);
3010 bus_dmamap_destroy(sc->tx_tag, tx->map);
3011 i--;
3012 }
3013 goto fail;
3014 }
3015 }
3016
3017 utopia_attach(&sc->utopia, &sc->ifatm, &sc->media, &sc->mtx,
3018 &sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3019 &fatm_utopia_methods);
3020 sc->utopia.flags |= UTP_FL_NORESET | UTP_FL_POLL_CARRIER;
3021
3022 /*
3023 * Attach the interface
3024 */
3025 atm_ifattach(ifp);
3026 ifp->if_snd.ifq_maxlen = 512;
3027
3028 error = bus_setup_intr(dev, sc->irqres, INTR_TYPE_NET,
3029 fatm_intr, sc, &sc->ih);
3030 if (error) {
3031 if_printf(ifp, "couldn't setup irq\n");
3032 goto fail;
3033 }
3034
3035 fail:
3036 if (error)
3037 fatm_detach(dev);
3038
3039 return (error);
3040}
3041
3042#if defined(FATM_DEBUG) && 0
3043static void
3044dump_s1_queue(struct fatm_softc *sc)
3045{
3046 int i;
3047 struct supqueue *q;
3048
3049 for(i = 0; i < SMALL_SUPPLY_QLEN; i++) {
3050 q = GET_QUEUE(sc->s1queue, struct supqueue, i);
3051 printf("%2d: card=%x(%x,%x) stat=%x\n", i,
3052 q->q.card,
3053 READ4(sc, q->q.card),
3054 READ4(sc, q->q.card + 4),
3055 *q->q.statp);
3056 }
3057}
3058#endif
3059
3060/*
3061 * Driver infrastructure.
3062 */
3063static device_method_t fatm_methods[] = {
3064 DEVMETHOD(device_probe, fatm_probe),
3065 DEVMETHOD(device_attach, fatm_attach),
3066 DEVMETHOD(device_detach, fatm_detach),
3067 { 0, 0 }
3068};
3069static driver_t fatm_driver = {
3070 "fatm",
3071 fatm_methods,
3072 sizeof(struct fatm_softc),
3073};
3074
3075DRIVER_MODULE(fatm, pci, fatm_driver, fatm_devclass, 0, 0);