1/* $NetBSD: ncr53c9xvar.h,v 1.46 2005/02/04 02:10:36 perry Exp $ */
2
3/*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40/*-
41 * Copyright (c) 1994 Peter Galbavy. All rights reserved.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. All advertising materials mentioning features or use of this software
52 * must display the following acknowledgement:
53 * This product includes software developed by Peter Galbavy.
54 * 4. The name of the author may not be used to endorse or promote products
55 * derived from this software without specific prior written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 */
68
| 1/* $NetBSD: ncr53c9xvar.h,v 1.46 2005/02/04 02:10:36 perry Exp $ */
2
3/*-
4 * Copyright (c) 1997 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40/*-
41 * Copyright (c) 1994 Peter Galbavy. All rights reserved.
42 *
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
45 * are met:
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. All advertising materials mentioning features or use of this software
52 * must display the following acknowledgement:
53 * This product includes software developed by Peter Galbavy.
54 * 4. The name of the author may not be used to endorse or promote products
55 * derived from this software without specific prior written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 */
68
|
69/* $FreeBSD: head/sys/dev/esp/ncr53c9xvar.h 180692 2008-07-22 13:51:21Z marius $ */
| 69/* $FreeBSD: head/sys/dev/esp/ncr53c9xvar.h 182876 2008-09-08 20:20:44Z marius $ */
|
70
71#ifndef _DEV_IC_NCR53C9XVAR_H_
72#define _DEV_IC_NCR53C9XVAR_H_
73
74#include <sys/lock.h>
75
76/* Set this to 1 for normal debug, or 2 for per-target tracing. */
77/* #define NCR53C9X_DEBUG 2 */
78
79/* Wide or differential can have 16 targets */
80#define NCR_NLUN 8
81
82#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
83#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
84
85#define FREQTOCCF(freq) (((freq + 4) / 5))
86
87/*
88 * NCR 53c9x variants. Note these values are used as indexes into
89 * a table; do not modify them unless you know what you are doing.
90 */
91#define NCR_VARIANT_ESP100 0
92#define NCR_VARIANT_ESP100A 1
93#define NCR_VARIANT_ESP200 2
94#define NCR_VARIANT_NCR53C94 3
95#define NCR_VARIANT_NCR53C96 4
96#define NCR_VARIANT_ESP406 5
97#define NCR_VARIANT_FAS408 6
98#define NCR_VARIANT_FAS216 7
99#define NCR_VARIANT_AM53C974 8
100#define NCR_VARIANT_FAS366 9
101#define NCR_VARIANT_NCR53C90_86C01 10
102#define NCR_VARIANT_FAS100A 11
103#define NCR_VARIANT_FAS236 12
104#define NCR_VARIANT_MAX 13
105
106/* XXX Max tag depth. Should this be defined in the register header? */
107#define NCR_TAG_DEPTH 256
108
109/*
110 * ECB. Holds additional information for each SCSI command Comments: We
111 * need a separate scsi command block because we may need to overwrite it
112 * with a request sense command. Basicly, we refrain from fiddling with
| 70
71#ifndef _DEV_IC_NCR53C9XVAR_H_
72#define _DEV_IC_NCR53C9XVAR_H_
73
74#include <sys/lock.h>
75
76/* Set this to 1 for normal debug, or 2 for per-target tracing. */
77/* #define NCR53C9X_DEBUG 2 */
78
79/* Wide or differential can have 16 targets */
80#define NCR_NLUN 8
81
82#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */
83#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */
84
85#define FREQTOCCF(freq) (((freq + 4) / 5))
86
87/*
88 * NCR 53c9x variants. Note these values are used as indexes into
89 * a table; do not modify them unless you know what you are doing.
90 */
91#define NCR_VARIANT_ESP100 0
92#define NCR_VARIANT_ESP100A 1
93#define NCR_VARIANT_ESP200 2
94#define NCR_VARIANT_NCR53C94 3
95#define NCR_VARIANT_NCR53C96 4
96#define NCR_VARIANT_ESP406 5
97#define NCR_VARIANT_FAS408 6
98#define NCR_VARIANT_FAS216 7
99#define NCR_VARIANT_AM53C974 8
100#define NCR_VARIANT_FAS366 9
101#define NCR_VARIANT_NCR53C90_86C01 10
102#define NCR_VARIANT_FAS100A 11
103#define NCR_VARIANT_FAS236 12
104#define NCR_VARIANT_MAX 13
105
106/* XXX Max tag depth. Should this be defined in the register header? */
107#define NCR_TAG_DEPTH 256
108
109/*
110 * ECB. Holds additional information for each SCSI command Comments: We
111 * need a separate scsi command block because we may need to overwrite it
112 * with a request sense command. Basicly, we refrain from fiddling with
|
113 * the scsipi_xfer struct (except do the expected updating of return values).
114 * We'll generally update: xs->{flags,resid,error,sense,status} and
115 * occasionally xs->retries.
| 113 * the ccb union (except do the expected updating of return values).
114 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid,
115 * scsi_status,sense_data}.
|
116 */
117struct ncr53c9x_ecb {
118 /* These fields are preserved between alloc and free */
119 struct ncr53c9x_softc *sc;
120 int tag_id;
121 int flags;
122
123 union ccb *ccb; /* SCSI xfer ctrl block from above */
124 TAILQ_ENTRY(ncr53c9x_ecb) free_links;
125 TAILQ_ENTRY(ncr53c9x_ecb) chain;
126#define ECB_ALLOC 0x01
127#define ECB_READY 0x02
128#define ECB_SENSE 0x04
129#define ECB_ABORT 0x40
130#define ECB_RESET 0x80
131#define ECB_TENTATIVE_DONE 0x100
132 int timeout;
| 116 */
117struct ncr53c9x_ecb {
118 /* These fields are preserved between alloc and free */
119 struct ncr53c9x_softc *sc;
120 int tag_id;
121 int flags;
122
123 union ccb *ccb; /* SCSI xfer ctrl block from above */
124 TAILQ_ENTRY(ncr53c9x_ecb) free_links;
125 TAILQ_ENTRY(ncr53c9x_ecb) chain;
126#define ECB_ALLOC 0x01
127#define ECB_READY 0x02
128#define ECB_SENSE 0x04
129#define ECB_ABORT 0x40
130#define ECB_RESET 0x80
131#define ECB_TENTATIVE_DONE 0x100
132 int timeout;
|
| 133 struct callout ch;
|
133
134 struct {
135 u_char msg[3]; /* Selection Id msg and tags */
136 struct scsi_generic cmd; /* SCSI command block */
137 } cmd;
138 char *daddr; /* Saved data pointer */
139 int clen; /* Size of command in cmd.cmd */
140 int dleft; /* Residue */
141 u_char stat; /* SCSI status byte */
142 u_char tag[2]; /* TAG bytes */
143 u_char pad[1];
144
145#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
146 char trace[1000];
147#endif
148};
149#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
150#define ECB_TRACE(ecb, msg, a, b) do { \
151 const char *f = "[" msg "]"; \
152 int n = strlen((ecb)->trace); \
153 if (n < (sizeof((ecb)->trace)-100)) \
154 sprintf((ecb)->trace + n, f, a, b); \
155} while(0)
156#else
157#define ECB_TRACE(ecb, msg, a, b)
158#endif
159
160/*
161 * Some info about each (possible) target and LUN on the SCSI bus.
162 *
163 * SCSI I and II devices can have up to 8 LUNs, each with up to 256
164 * outstanding tags. SCSI III devices have 64-bit LUN identifiers
165 * that can be sparsely allocated.
166 *
167 * Since SCSI II devices can have up to 8 LUNs, we use an array
168 * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
169 * Longer LUNs need to traverse the linked list.
170 */
171
172struct ncr53c9x_linfo {
173 int64_t lun;
174 LIST_ENTRY(ncr53c9x_linfo) link;
175 time_t last_used;
176 u_char used; /* # slots in use */
177 u_char avail; /* where to start scanning */
178 u_char busy;
179 struct ncr53c9x_ecb *untagged;
180 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
181};
182
| 134
135 struct {
136 u_char msg[3]; /* Selection Id msg and tags */
137 struct scsi_generic cmd; /* SCSI command block */
138 } cmd;
139 char *daddr; /* Saved data pointer */
140 int clen; /* Size of command in cmd.cmd */
141 int dleft; /* Residue */
142 u_char stat; /* SCSI status byte */
143 u_char tag[2]; /* TAG bytes */
144 u_char pad[1];
145
146#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
147 char trace[1000];
148#endif
149};
150#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1
151#define ECB_TRACE(ecb, msg, a, b) do { \
152 const char *f = "[" msg "]"; \
153 int n = strlen((ecb)->trace); \
154 if (n < (sizeof((ecb)->trace)-100)) \
155 sprintf((ecb)->trace + n, f, a, b); \
156} while(0)
157#else
158#define ECB_TRACE(ecb, msg, a, b)
159#endif
160
161/*
162 * Some info about each (possible) target and LUN on the SCSI bus.
163 *
164 * SCSI I and II devices can have up to 8 LUNs, each with up to 256
165 * outstanding tags. SCSI III devices have 64-bit LUN identifiers
166 * that can be sparsely allocated.
167 *
168 * Since SCSI II devices can have up to 8 LUNs, we use an array
169 * of 8 pointers to ncr53c9x_linfo structures for fast lookup.
170 * Longer LUNs need to traverse the linked list.
171 */
172
173struct ncr53c9x_linfo {
174 int64_t lun;
175 LIST_ENTRY(ncr53c9x_linfo) link;
176 time_t last_used;
177 u_char used; /* # slots in use */
178 u_char avail; /* where to start scanning */
179 u_char busy;
180 struct ncr53c9x_ecb *untagged;
181 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH];
182};
183
|
| 184struct ncr53c9x_xinfo {
185 u_char period;
186 u_char offset;
187 u_char width;
188};
189
|
183struct ncr53c9x_tinfo {
184 int cmds; /* # of commands processed */
185 int dconns; /* # of disconnects */
186 int touts; /* # of timeouts */
187 int perrs; /* # of parity errors */
188 int senses; /* # of request sense commands sent */
189 u_char flags;
| 190struct ncr53c9x_tinfo {
191 int cmds; /* # of commands processed */
192 int dconns; /* # of disconnects */
193 int touts; /* # of timeouts */
194 int perrs; /* # of parity errors */
195 int senses; /* # of request sense commands sent */
196 u_char flags;
|
190#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
191#define T_SYNCMODE 0x08 /* SYNC mode has been negotiated */
192#define T_SYNCHOFF 0x10 /* SYNC mode for is permanently off */
193#define T_RSELECTOFF 0x20 /* RE-SELECT mode is off */
194#define T_TAG 0x40 /* Turn on TAG QUEUEs */
195#define T_WIDE 0x80 /* Negotiate wide options */
196#define T_WDTRSENT 0x04 /* WDTR message has been sent to */
197 u_char period; /* Period suggestion */
198 u_char offset; /* Offset suggestion */
199 u_char cfg3; /* per target config 3 */
200 u_char nextag; /* Next available tag */
201 u_char width; /* width suggesion */
| 197#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */
198#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */
199#define T_TAG 0x04 /* Turn on TAG QUEUEs */
200#define T_SDTRSENT 0x08 /* SDTR message has been sent to */
201#define T_WDTRSENT 0x10 /* WDTR message has been sent to */
202 struct ncr53c9x_xinfo curr;
203 struct ncr53c9x_xinfo goal;
|
202 LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
203 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
204};
205
206/* Look up a lun in a tinfo */
207#define TINFO_LUN(t, l) ( \
208 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
209 ? ((t)->lun[(l)]) \
210 : ncr53c9x_lunsearch((t), (int64_t)(l)) \
211)
212
213/* Register a linenumber (for debugging) */
214#define LOGLINE(p)
215
216#define NCR_SHOWECBS 0x01
217#define NCR_SHOWINTS 0x02
218#define NCR_SHOWCMDS 0x04
219#define NCR_SHOWMISC 0x08
220#define NCR_SHOWTRAC 0x10
221#define NCR_SHOWSTART 0x20
222#define NCR_SHOWPHASE 0x40
223#define NCR_SHOWDMA 0x80
224#define NCR_SHOWCCMDS 0x100
225#define NCR_SHOWMSGS 0x200
226
227#ifdef NCR53C9X_DEBUG
228extern int ncr53c9x_debug;
229#define NCR_ECBS(str) \
230 do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
231#define NCR_MISC(str) \
232 do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
233#define NCR_INTS(str) \
234 do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
235#define NCR_TRACE(str) \
236 do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
237#define NCR_CMDS(str) \
238 do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
239#define NCR_START(str) \
240 do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
241#define NCR_PHASE(str) \
242 do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
243#define NCR_DMA(str) \
244 do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
245#define NCR_MSGS(str) \
246 do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
247#else
248#define NCR_ECBS(str)
249#define NCR_MISC(str)
250#define NCR_INTS(str)
251#define NCR_TRACE(str)
252#define NCR_CMDS(str)
253#define NCR_START(str)
254#define NCR_PHASE(str)
255#define NCR_DMA(str)
256#define NCR_MSGS(str)
257#endif
258
259#define NCR_MAX_MSG_LEN 8
260
261struct ncr53c9x_softc;
262
263/*
264 * Function switch used as glue to MD code.
265 */
266struct ncr53c9x_glue {
267 /* Mandatory entry points. */
268 u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
269 void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
270 int (*gl_dma_isintr)(struct ncr53c9x_softc *);
271 void (*gl_dma_reset)(struct ncr53c9x_softc *);
272 int (*gl_dma_intr)(struct ncr53c9x_softc *);
273 int (*gl_dma_setup)(struct ncr53c9x_softc *,
274 caddr_t *, size_t *, int, size_t *);
275 void (*gl_dma_go)(struct ncr53c9x_softc *);
276 void (*gl_dma_stop)(struct ncr53c9x_softc *);
277 int (*gl_dma_isactive)(struct ncr53c9x_softc *);
278
279 /* Optional entry points. */
280 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
281};
282
283struct ncr53c9x_softc {
284 device_t sc_dev; /* us as a device */
285
286 struct cam_sim *sc_sim; /* our scsi adapter */
287 struct cam_path *sc_path; /* our scsi channel */
288 struct callout sc_watchdog; /* periodic timer */
289
290 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
291
292 int sc_cfflags; /* Copy of config flags */
293
294 /* register defaults */
295 u_char sc_cfg1; /* Config 1 */
296 u_char sc_cfg2; /* Config 2, not ESP100 */
297 u_char sc_cfg3; /* Config 3, ESP200,FAS */
298 u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
299 u_char sc_cfg4; /* Config 4, only ESP200 */
300 u_char sc_cfg5; /* Config 5, only ESP200 */
301 u_char sc_ccf; /* Clock Conversion */
302 u_char sc_timeout;
303
304 /* register copies, see espreadregs() */
305 u_char sc_espintr;
306 u_char sc_espstat;
307 u_char sc_espstep;
308 u_char sc_espstat2;
309 u_char sc_espfflags;
310
311 /* Lists of command blocks */
312 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
313
314 struct ncr53c9x_ecb *sc_nexus; /* Current command */
315 int sc_ntarg;
316 struct ncr53c9x_tinfo *sc_tinfo;
317
318 /* Data about the current nexus (updated for every cmd switch) */
319 caddr_t sc_dp; /* Current data pointer */
320 ssize_t sc_dleft; /* Data left to transfer */
321
322 /* Adapter state */
323 int sc_phase; /* Copy of what bus phase we are in */
324 int sc_prevphase; /* Copy of what bus phase we were in */
325 u_char sc_state; /* State applicable to the adapter */
326 u_char sc_flags; /* See below */
327 u_char sc_selid;
328 u_char sc_lastcmd;
329
330 /* Message stuff */
331 u_short sc_msgify; /* IDENTIFY message associated with nexus */
332 u_short sc_msgout; /* What message is on its way out? */
333 u_short sc_msgpriq; /* One or more messages to send (encoded) */
334 u_short sc_msgoutq; /* What messages have been sent so far? */
335
336 u_char *sc_omess; /* MSGOUT buffer */
337 int sc_omess_self; /* MSGOUT buffer is self-allocated */
338 caddr_t sc_omp; /* Message pointer (for multibyte messages) */
339 size_t sc_omlen;
340 u_char *sc_imess; /* MSGIN buffer */
341 int sc_imess_self; /* MSGIN buffer is self-allocated */
342 caddr_t sc_imp; /* Message pointer (for multibyte messages) */
343 size_t sc_imlen;
344
345 caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
346 size_t sc_cmdlen; /* Size of command in transit */
347
348 /* Hardware attributes */
349 int sc_freq; /* SCSI bus frequency in MHz */
350 int sc_id; /* Our SCSI id */
351 int sc_rev; /* Chip revision */
352 int sc_features; /* Chip features */
353 int sc_minsync; /* Minimum sync period / 4 */
354 int sc_maxxfer; /* Maximum transfer size */
| 204 LIST_HEAD(lun_list, ncr53c9x_linfo) luns;
205 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */
206};
207
208/* Look up a lun in a tinfo */
209#define TINFO_LUN(t, l) ( \
210 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \
211 ? ((t)->lun[(l)]) \
212 : ncr53c9x_lunsearch((t), (int64_t)(l)) \
213)
214
215/* Register a linenumber (for debugging) */
216#define LOGLINE(p)
217
218#define NCR_SHOWECBS 0x01
219#define NCR_SHOWINTS 0x02
220#define NCR_SHOWCMDS 0x04
221#define NCR_SHOWMISC 0x08
222#define NCR_SHOWTRAC 0x10
223#define NCR_SHOWSTART 0x20
224#define NCR_SHOWPHASE 0x40
225#define NCR_SHOWDMA 0x80
226#define NCR_SHOWCCMDS 0x100
227#define NCR_SHOWMSGS 0x200
228
229#ifdef NCR53C9X_DEBUG
230extern int ncr53c9x_debug;
231#define NCR_ECBS(str) \
232 do {if (ncr53c9x_debug & NCR_SHOWECBS) printf str;} while (0)
233#define NCR_MISC(str) \
234 do {if (ncr53c9x_debug & NCR_SHOWMISC) printf str;} while (0)
235#define NCR_INTS(str) \
236 do {if (ncr53c9x_debug & NCR_SHOWINTS) printf str;} while (0)
237#define NCR_TRACE(str) \
238 do {if (ncr53c9x_debug & NCR_SHOWTRAC) printf str;} while (0)
239#define NCR_CMDS(str) \
240 do {if (ncr53c9x_debug & NCR_SHOWCMDS) printf str;} while (0)
241#define NCR_START(str) \
242 do {if (ncr53c9x_debug & NCR_SHOWSTART) printf str;}while (0)
243#define NCR_PHASE(str) \
244 do {if (ncr53c9x_debug & NCR_SHOWPHASE) printf str;}while (0)
245#define NCR_DMA(str) \
246 do {if (ncr53c9x_debug & NCR_SHOWDMA) printf str;}while (0)
247#define NCR_MSGS(str) \
248 do {if (ncr53c9x_debug & NCR_SHOWMSGS) printf str;}while (0)
249#else
250#define NCR_ECBS(str)
251#define NCR_MISC(str)
252#define NCR_INTS(str)
253#define NCR_TRACE(str)
254#define NCR_CMDS(str)
255#define NCR_START(str)
256#define NCR_PHASE(str)
257#define NCR_DMA(str)
258#define NCR_MSGS(str)
259#endif
260
261#define NCR_MAX_MSG_LEN 8
262
263struct ncr53c9x_softc;
264
265/*
266 * Function switch used as glue to MD code.
267 */
268struct ncr53c9x_glue {
269 /* Mandatory entry points. */
270 u_char (*gl_read_reg)(struct ncr53c9x_softc *, int);
271 void (*gl_write_reg)(struct ncr53c9x_softc *, int, u_char);
272 int (*gl_dma_isintr)(struct ncr53c9x_softc *);
273 void (*gl_dma_reset)(struct ncr53c9x_softc *);
274 int (*gl_dma_intr)(struct ncr53c9x_softc *);
275 int (*gl_dma_setup)(struct ncr53c9x_softc *,
276 caddr_t *, size_t *, int, size_t *);
277 void (*gl_dma_go)(struct ncr53c9x_softc *);
278 void (*gl_dma_stop)(struct ncr53c9x_softc *);
279 int (*gl_dma_isactive)(struct ncr53c9x_softc *);
280
281 /* Optional entry points. */
282 void (*gl_clear_latched_intr)(struct ncr53c9x_softc *);
283};
284
285struct ncr53c9x_softc {
286 device_t sc_dev; /* us as a device */
287
288 struct cam_sim *sc_sim; /* our scsi adapter */
289 struct cam_path *sc_path; /* our scsi channel */
290 struct callout sc_watchdog; /* periodic timer */
291
292 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */
293
294 int sc_cfflags; /* Copy of config flags */
295
296 /* register defaults */
297 u_char sc_cfg1; /* Config 1 */
298 u_char sc_cfg2; /* Config 2, not ESP100 */
299 u_char sc_cfg3; /* Config 3, ESP200,FAS */
300 u_char sc_cfg3_fscsi; /* Chip-specific FSCSI bit */
301 u_char sc_cfg4; /* Config 4, only ESP200 */
302 u_char sc_cfg5; /* Config 5, only ESP200 */
303 u_char sc_ccf; /* Clock Conversion */
304 u_char sc_timeout;
305
306 /* register copies, see espreadregs() */
307 u_char sc_espintr;
308 u_char sc_espstat;
309 u_char sc_espstep;
310 u_char sc_espstat2;
311 u_char sc_espfflags;
312
313 /* Lists of command blocks */
314 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list;
315
316 struct ncr53c9x_ecb *sc_nexus; /* Current command */
317 int sc_ntarg;
318 struct ncr53c9x_tinfo *sc_tinfo;
319
320 /* Data about the current nexus (updated for every cmd switch) */
321 caddr_t sc_dp; /* Current data pointer */
322 ssize_t sc_dleft; /* Data left to transfer */
323
324 /* Adapter state */
325 int sc_phase; /* Copy of what bus phase we are in */
326 int sc_prevphase; /* Copy of what bus phase we were in */
327 u_char sc_state; /* State applicable to the adapter */
328 u_char sc_flags; /* See below */
329 u_char sc_selid;
330 u_char sc_lastcmd;
331
332 /* Message stuff */
333 u_short sc_msgify; /* IDENTIFY message associated with nexus */
334 u_short sc_msgout; /* What message is on its way out? */
335 u_short sc_msgpriq; /* One or more messages to send (encoded) */
336 u_short sc_msgoutq; /* What messages have been sent so far? */
337
338 u_char *sc_omess; /* MSGOUT buffer */
339 int sc_omess_self; /* MSGOUT buffer is self-allocated */
340 caddr_t sc_omp; /* Message pointer (for multibyte messages) */
341 size_t sc_omlen;
342 u_char *sc_imess; /* MSGIN buffer */
343 int sc_imess_self; /* MSGIN buffer is self-allocated */
344 caddr_t sc_imp; /* Message pointer (for multibyte messages) */
345 size_t sc_imlen;
346
347 caddr_t sc_cmdp; /* Command pointer (for DMAed commands) */
348 size_t sc_cmdlen; /* Size of command in transit */
349
350 /* Hardware attributes */
351 int sc_freq; /* SCSI bus frequency in MHz */
352 int sc_id; /* Our SCSI id */
353 int sc_rev; /* Chip revision */
354 int sc_features; /* Chip features */
355 int sc_minsync; /* Minimum sync period / 4 */
356 int sc_maxxfer; /* Maximum transfer size */
|
355 int sc_maxsync; /* Maximum sync period */
| |
356 int sc_maxoffset; /* Maximum offset */
357 int sc_maxwidth; /* Maximum width */
358 int sc_extended_geom; /* Should we return extended geometry */
359
360 struct mtx sc_lock; /* driver mutex */
361
362 struct ncr53c9x_ecb *ecb_array;
363 TAILQ_HEAD(,ncr53c9x_ecb) free_list;
364};
365
366/* values for sc_state */
367#define NCR_IDLE 1 /* Waiting for something to do */
368#define NCR_SELECTING 2 /* SCSI command is arbiting */
369#define NCR_RESELECTED 3 /* Has been reselected */
370#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
371#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
372#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
373#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
374#define NCR_CLEANING 8
375#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
376
377/* values for sc_flags */
378#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
379#define NCR_ABORTING 0x02 /* Bailing out */
| 357 int sc_maxoffset; /* Maximum offset */
358 int sc_maxwidth; /* Maximum width */
359 int sc_extended_geom; /* Should we return extended geometry */
360
361 struct mtx sc_lock; /* driver mutex */
362
363 struct ncr53c9x_ecb *ecb_array;
364 TAILQ_HEAD(,ncr53c9x_ecb) free_list;
365};
366
367/* values for sc_state */
368#define NCR_IDLE 1 /* Waiting for something to do */
369#define NCR_SELECTING 2 /* SCSI command is arbiting */
370#define NCR_RESELECTED 3 /* Has been reselected */
371#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */
372#define NCR_CONNECTED 5 /* Actively using the SCSI bus */
373#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */
374#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */
375#define NCR_CLEANING 8
376#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */
377
378/* values for sc_flags */
379#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
380#define NCR_ABORTING 0x02 /* Bailing out */
|
380#define NCR_DOINGDMA 0x04 /* The FIFO data path is active! */
381#define NCR_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
382#define NCR_ICCS 0x10 /* Expect status phase results */
383#define NCR_WAITI 0x20 /* Waiting for non-DMA data to arrive */
384#define NCR_ATN 0x40 /* ATN asserted */
385#define NCR_EXPECT_ILLCMD 0x80 /* Expect Illegal Command Interrupt */
| 381#define NCR_ICCS 0x04 /* Expect status phase results */
382#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */
383#define NCR_ATN 0x10 /* ATN asserted */
384#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */
|
386
387/* values for sc_features */
388#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
389#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
390#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
391#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
392
393/* values for sc_msgout */
394#define SEND_DEV_RESET 0x0001
395#define SEND_PARITY_ERROR 0x0002
396#define SEND_INIT_DET_ERR 0x0004
397#define SEND_REJECT 0x0008
398#define SEND_IDENTIFY 0x0010
399#define SEND_ABORT 0x0020
| 385
386/* values for sc_features */
387#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */
388#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */
389#define NCR_F_DMASELECT 0x04 /* can do dmaselect */
390#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */
391
392/* values for sc_msgout */
393#define SEND_DEV_RESET 0x0001
394#define SEND_PARITY_ERROR 0x0002
395#define SEND_INIT_DET_ERR 0x0004
396#define SEND_REJECT 0x0008
397#define SEND_IDENTIFY 0x0010
398#define SEND_ABORT 0x0020
|
400#define SEND_WDTR 0x0040
401#define SEND_SDTR 0x0080
402#define SEND_TAG 0x0100
| 399#define SEND_TAG 0x0040
400#define SEND_WDTR 0x0080
401#define SEND_SDTR 0x0100
|
403
404/* SCSI Status codes */
405#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
406
407/* phase bits */
408#define IOI 0x01
409#define CDI 0x02
410#define MSGI 0x04
411
412/* Information transfer phases */
413#define DATA_OUT_PHASE (0)
414#define DATA_IN_PHASE (IOI)
415#define COMMAND_PHASE (CDI)
416#define STATUS_PHASE (CDI | IOI)
417#define MESSAGE_OUT_PHASE (MSGI | CDI)
418#define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
419
420#define PHASE_MASK (MSGI | CDI | IOI)
421
422/* Some pseudo phases for getphase()*/
423#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
424#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
425#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
426
427/*
428 * Macros to read and write the chip's registers.
429 */
430#define NCR_READ_REG(sc, reg) \
431 (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
432#define NCR_WRITE_REG(sc, reg, val) \
433 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
434
435#ifdef NCR53C9X_DEBUG
436#define NCRCMD(sc, cmd) do { \
437 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
438 printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \
439 sc->sc_lastcmd = cmd; \
440 NCR_WRITE_REG(sc, NCR_CMD, cmd); \
441} while (0)
442#else
443#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
444#endif
445
446/*
| 402
403/* SCSI Status codes */
404#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
405
406/* phase bits */
407#define IOI 0x01
408#define CDI 0x02
409#define MSGI 0x04
410
411/* Information transfer phases */
412#define DATA_OUT_PHASE (0)
413#define DATA_IN_PHASE (IOI)
414#define COMMAND_PHASE (CDI)
415#define STATUS_PHASE (CDI | IOI)
416#define MESSAGE_OUT_PHASE (MSGI | CDI)
417#define MESSAGE_IN_PHASE (MSGI | CDI | IOI)
418
419#define PHASE_MASK (MSGI | CDI | IOI)
420
421/* Some pseudo phases for getphase()*/
422#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
423#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
424#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
425
426/*
427 * Macros to read and write the chip's registers.
428 */
429#define NCR_READ_REG(sc, reg) \
430 (*(sc)->sc_glue->gl_read_reg)((sc), (reg))
431#define NCR_WRITE_REG(sc, reg, val) \
432 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val))
433
434#ifdef NCR53C9X_DEBUG
435#define NCRCMD(sc, cmd) do { \
436 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \
437 printf("<CMD:0x%x %d>", (unsigned)cmd, __LINE__); \
438 sc->sc_lastcmd = cmd; \
439 NCR_WRITE_REG(sc, NCR_CMD, cmd); \
440} while (0)
441#else
442#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd)
443#endif
444
445/*
|
| 446 * Macros for locking
447 */
448#define NCR_LOCK_INIT(_sc) \
449 mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
450#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock)
451#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock)
452#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock)
453#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what))
454#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock)
455
456/*
|
447 * DMA macros for NCR53c9x
448 */
449#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
450#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
451#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
452#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
453 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
454#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
| 457 * DMA macros for NCR53c9x
458 */
459#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc))
460#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc))
461#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc))
462#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \
463 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize))
464#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc))
|
| 465#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc))
|
455#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
456
457/*
458 * Macro to convert the chip register Clock Per Byte value to
459 * Synchronous Transfer Period.
460 */
461#define ncr53c9x_cpb2stp(sc, cpb) \
462 ((250 * (cpb)) / (sc)->sc_freq)
463
464int ncr53c9x_attach(struct ncr53c9x_softc *sc);
465int ncr53c9x_detach(struct ncr53c9x_softc *sc);
| 466#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc))
467
468/*
469 * Macro to convert the chip register Clock Per Byte value to
470 * Synchronous Transfer Period.
471 */
472#define ncr53c9x_cpb2stp(sc, cpb) \
473 ((250 * (cpb)) / (sc)->sc_freq)
474
475int ncr53c9x_attach(struct ncr53c9x_softc *sc);
476int ncr53c9x_detach(struct ncr53c9x_softc *sc);
|
466void ncr53c9x_action(struct cam_sim *sim, union ccb *ccb);
467void ncr53c9x_reset(struct ncr53c9x_softc *sc);
| |
468void ncr53c9x_intr(void *arg);
| 477void ncr53c9x_intr(void *arg);
|
469void ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset);
| |
470
471#endif /* _DEV_IC_NCR53C9XVAR_H_ */
| 478
479#endif /* _DEV_IC_NCR53C9XVAR_H_ */
|