1/*- 2 * Copyright (c) 2004 Scott Long |
3 * Copyright (c) 2005, 2008 Marius Strobl <marius@FreeBSD.org> |
4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright --- 9 unchanged lines hidden (view full) --- 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 |
29/* $NetBSD: ncr53c9x.c,v 1.125 2007/01/09 12:53:12 itohy Exp $ */ |
30 31/*- 32 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Charles M. Hannum. 37 * --- 62 unchanged lines hidden (view full) --- 100 * Based on aic6360 by Jarle Greipsland 101 * 102 * Acknowledgements: Many of the algorithms used in this driver are 103 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and 104 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 105 */ 106 107#include <sys/cdefs.h> |
108__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 182876 2008-09-08 20:20:44Z marius $"); |
109 110#include <sys/param.h> 111#include <sys/systm.h> 112#include <sys/bus.h> 113#include <sys/kernel.h> 114#include <sys/malloc.h> |
115#include <sys/lock.h> |
116#include <sys/module.h> |
117#include <sys/mutex.h> 118#include <sys/queue.h> 119#include <sys/time.h> 120#include <sys/callout.h> 121 122#include <cam/cam.h> 123#include <cam/cam_ccb.h> 124#include <cam/cam_debug.h> 125#include <cam/cam_sim.h> 126#include <cam/cam_xpt_sim.h> 127#include <cam/scsi/scsi_all.h> 128#include <cam/scsi/scsi_message.h> 129 130#include <dev/esp/ncr53c9xreg.h> 131#include <dev/esp/ncr53c9xvar.h> 132 |
133MODULE_DEPEND(esp, cam, 1, 1, 1); 134 135#ifdef NCR53C9X_DEBUG 136static int ncr53c9x_debug = |
137 NCR_SHOWMISC /* | NCR_SHOWPHASE | NCR_SHOWTRAC | NCR_SHOWCMDS */; |
138#endif 139 140static void ncr53c9x_abort(struct ncr53c9x_softc *sc, 141 struct ncr53c9x_ecb *ecb); |
142static void ncr53c9x_action(struct cam_sim *sim, union ccb *ccb); 143static void ncr53c9x_async(void *cbarg, uint32_t code, 144 struct cam_path *path, void *arg); 145static void ncr53c9x_callout(void *arg); 146static void ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result); 147static void ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target, 148 cam_status result); |
149static void ncr53c9x_dequeue(struct ncr53c9x_softc *sc, 150 struct ncr53c9x_ecb *ecb); 151static void ncr53c9x_done(struct ncr53c9x_softc *sc, 152 struct ncr53c9x_ecb *ecb); 153static void ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, 154 struct ncr53c9x_ecb *ecb); 155static void ncr53c9x_msgin(struct ncr53c9x_softc *sc); 156static void ncr53c9x_msgout(struct ncr53c9x_softc *sc); |
157static void ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset); 158static void ncr53c9x_intr1(struct ncr53c9x_softc *sc); |
159static void ncr53c9x_poll(struct cam_sim *sim); 160static int ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how); 161static int ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, 162 int tagtype, int tagid); |
163static void ncr53c9x_reset(struct ncr53c9x_softc *sc); |
164static void ncr53c9x_sense(struct ncr53c9x_softc *sc, 165 struct ncr53c9x_ecb *ecb); |
166static void ncr53c9x_sched(struct ncr53c9x_softc *sc); 167static void ncr53c9x_select(struct ncr53c9x_softc *sc, 168 struct ncr53c9x_ecb *ecb); |
169static void ncr53c9x_watch(void *arg); 170static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, 171 int len); 172 173static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *sc); 174static struct ncr53c9x_linfo *ncr53c9x_lunsearch(struct ncr53c9x_tinfo *sc, 175 int64_t lun); 176 --- 66 unchanged lines hidden (view full) --- 243ncr53c9x_attach(struct ncr53c9x_softc *sc) 244{ 245 struct cam_devq *devq; 246 struct cam_sim *sim; 247 struct cam_path *path; 248 struct ncr53c9x_ecb *ecb; 249 int error, i; 250 |
251 if (NCR_LOCK_INITIALIZED(sc) == 0) { 252 device_printf(sc->sc_dev, "mutex not initialized\n"); 253 return (ENXIO); 254 } |
255 |
256 callout_init_mtx(&sc->sc_watchdog, &sc->sc_lock, 0); 257 |
258 /* 259 * Note, the front-end has set us up to print the chip variation. 260 */ 261 if (sc->sc_rev >= NCR_VARIANT_MAX) { 262 device_printf(sc->sc_dev, "unknown variant %d, devices not " 263 "attached\n", sc->sc_rev); 264 return (EINVAL); 265 } --- 36 unchanged lines hidden (view full) --- 302 M_DEVBUF, M_NOWAIT | M_ZERO); 303 if (sc->sc_tinfo == NULL) { 304 device_printf(sc->sc_dev, 305 "cannot allocate target info buffer\n"); 306 error = ENOMEM; 307 goto fail_imess; 308 } 309 |
310 /* 311 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100 312 * from now on. 313 */ 314 if (sc->sc_rev == NCR_VARIANT_NCR53C90_86C01) 315 sc->sc_rev = NCR_VARIANT_ESP100; 316 317 sc->sc_ccf = FREQTOCCF(sc->sc_freq); --- 24 unchanged lines hidden (view full) --- 342 devq = cam_simq_alloc(sc->sc_ntarg); 343 if (devq == NULL) { 344 device_printf(sc->sc_dev, "cannot allocate device queue\n"); 345 error = ENOMEM; 346 goto fail_tinfo; 347 } 348 349 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc, |
350 device_get_unit(sc->sc_dev), &sc->sc_lock, 1, NCR_TAG_DEPTH, devq); |
351 if (sim == NULL) { 352 device_printf(sc->sc_dev, "cannot allocate SIM entry\n"); 353 error = ENOMEM; 354 goto fail_devq; 355 } |
356 357 NCR_LOCK(sc); 358 |
359 if (xpt_bus_register(sim, sc->sc_dev, 0) != CAM_SUCCESS) { 360 device_printf(sc->sc_dev, "cannot register bus\n"); 361 error = EIO; |
362 goto fail_lock; |
363 } 364 365 if (xpt_create_path(&path, NULL, cam_sim_path(sim), 366 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 367 device_printf(sc->sc_dev, "cannot create path\n"); 368 error = EIO; 369 goto fail_bus; 370 } 371 |
372 if (xpt_register_async(AC_LOST_DEVICE, ncr53c9x_async, sim, path) != 373 CAM_REQ_CMP) { 374 device_printf(sc->sc_dev, "cannot register async handler\n"); 375 error = EIO; 376 goto fail_path; 377 } 378 |
379 sc->sc_sim = sim; 380 sc->sc_path = path; 381 382 /* Reset state and bus. */ 383#if 0 384 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 385#else 386 sc->sc_cfflags = 0; 387#endif 388 sc->sc_state = 0; 389 ncr53c9x_init(sc, 1); 390 391 TAILQ_INIT(&sc->free_list); 392 if ((sc->ecb_array = 393 malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH, M_DEVBUF, 394 M_NOWAIT | M_ZERO)) == NULL) { 395 device_printf(sc->sc_dev, "cannot allocate ECB array\n"); 396 error = ENOMEM; |
397 goto fail_async; |
398 } 399 for (i = 0; i < NCR_TAG_DEPTH; i++) { 400 ecb = &sc->ecb_array[i]; 401 ecb->sc = sc; 402 ecb->tag_id = i; 403 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links); 404 } 405 |
406 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc); |
407 |
408 NCR_UNLOCK(sc); 409 |
410 return (0); 411 |
412fail_async: 413 xpt_register_async(0, ncr53c9x_async, sim, path); |
414fail_path: 415 xpt_free_path(path); 416fail_bus: 417 xpt_bus_deregister(cam_sim_path(sim)); |
418fail_lock: 419 NCR_UNLOCK(sc); |
420 cam_sim_free(sim, TRUE); 421fail_devq: 422 cam_simq_free(devq); 423fail_tinfo: 424 free(sc->sc_tinfo, M_DEVBUF); 425fail_imess: 426 if (sc->sc_imess_self) 427 free(sc->sc_imess, M_DEVBUF); 428fail_omess: 429 if (sc->sc_omess_self) 430 free(sc->sc_omess, M_DEVBUF); 431 return (error); 432} 433 434int 435ncr53c9x_detach(struct ncr53c9x_softc *sc) 436{ |
437 struct ncr53c9x_linfo *li, *nextli; 438 int t; |
439 440 callout_drain(&sc->sc_watchdog); |
441 442 NCR_LOCK(sc); 443 444 if (sc->sc_tinfo) { 445 /* Cancel all commands. */ 446 ncr53c9x_clear(sc, CAM_REQ_ABORTED); 447 448 /* Free logical units. */ 449 for (t = 0; t < sc->sc_ntarg; t++) { 450 for (li = LIST_FIRST(&sc->sc_tinfo[t].luns); li; 451 li = nextli) { 452 nextli = LIST_NEXT(li, link); 453 free(li, M_DEVBUF); 454 } 455 } 456 } 457 458 xpt_register_async(0, ncr53c9x_async, sc->sc_sim, sc->sc_path); |
459 xpt_free_path(sc->sc_path); 460 xpt_bus_deregister(cam_sim_path(sc->sc_sim)); |
461 462 NCR_UNLOCK(sc); 463 |
464 cam_sim_free(sc->sc_sim, TRUE); 465 free(sc->ecb_array, M_DEVBUF); 466 free(sc->sc_tinfo, M_DEVBUF); 467 if (sc->sc_imess_self) 468 free(sc->sc_imess, M_DEVBUF); 469 if (sc->sc_omess_self) 470 free(sc->sc_omess, M_DEVBUF); |
471 472 return (0); 473} 474 475/* 476 * This is the generic ncr53c9x reset function. It does not reset the SCSI 477 * bus, only this controller, but kills any on-going commands, and also stops 478 * and resets the DMA. 479 * 480 * After reset, registers are loaded with the defaults from the attach 481 * routine above. 482 */ |
483static void |
484ncr53c9x_reset(struct ncr53c9x_softc *sc) 485{ 486 |
487 NCR_LOCK_ASSERT(sc, MA_OWNED); 488 |
489 /* Reset DMA first. */ 490 NCRDMA_RESET(sc); 491 492 /* Reset SCSI chip. */ 493 NCRCMD(sc, NCRCMD_RSTCHIP); 494 NCRCMD(sc, NCRCMD_NOP); 495 DELAY(500); 496 --- 24 unchanged lines hidden (view full) --- 521 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 522 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 523 break; 524 525 case NCR_VARIANT_FAS366: 526 sc->sc_features |= 527 NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3; 528 sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO; |
529 if (sc->sc_id > 7) 530 sc->sc_cfg3 |= NCRFASCFG3_IDBIT3; |
531 sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI; 532 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); |
533 sc->sc_cfg2 = NCRCFG2_HMEFE | NCRCFG2_HME32; |
534 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 535 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 536 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 537 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 538 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 539 break; 540 541 default: --- 13 unchanged lines hidden (view full) --- 555 sc->sc_rev); 556 device_printf(sc->sc_dev, "ncr53c9x_reset: cfg1 0x%x, cfg2 0x%x, " 557 "cfg3 0x%x, ccf 0x%x, timeout 0x%x\n", 558 sc->sc_cfg1, sc->sc_cfg2, sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout); 559#endif 560} 561 562/* |
563 * Clear all commands. |
564 */ 565static void |
566ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result) |
567{ |
568 struct ncr53c9x_ecb *ecb; 569 int r; |
570 |
571 NCR_LOCK_ASSERT(sc, MA_OWNED); |
572 |
573 /* Cancel any active commands. */ 574 sc->sc_state = NCR_CLEANING; 575 sc->sc_msgify = 0; 576 if ((ecb = sc->sc_nexus) != NULL) { 577 ecb->ccb->ccb_h.status = result; 578 ncr53c9x_done(sc, ecb); 579 } 580 /* Cancel outstanding disconnected commands. */ 581 for (r = 0; r < sc->sc_ntarg; r++) 582 ncr53c9x_clear_target(sc, r, result); |
583} 584 585/* |
586 * Clear all commands for a specific target. |
587 */ |
588static void 589ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target, 590 cam_status result) |
591{ 592 struct ncr53c9x_ecb *ecb; 593 struct ncr53c9x_linfo *li; |
594 int i; 595 596 NCR_LOCK_ASSERT(sc, MA_OWNED); 597 598 /* Cancel outstanding disconnected commands on each LUN. */ 599 LIST_FOREACH(li, &sc->sc_tinfo[target].luns, link) { 600 if ((ecb = li->untagged) != NULL) { 601 li->untagged = NULL; 602 /* 603 * XXX should we terminate a command 604 * that never reached the disk? 605 */ 606 li->busy = 0; 607 ecb->ccb->ccb_h.status = result; 608 ncr53c9x_done(sc, ecb); 609 } 610 for (i = 0; i < NCR_TAG_DEPTH; i++) 611 if ((ecb = li->queued[i])) { 612 li->queued[i] = NULL; 613 ecb->ccb->ccb_h.status = result; 614 ncr53c9x_done(sc, ecb); 615 } 616 li->used = 0; 617 } 618} 619 620/* 621 * Initialize ncr53c9x state machine. 622 */ 623static void 624ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset) 625{ |
626 struct ncr53c9x_tinfo *ti; |
627 int r; |
628 |
629 NCR_LOCK_ASSERT(sc, MA_OWNED); 630 |
631 NCR_MISC(("[NCR_INIT(%d) %d] ", doreset, sc->sc_state)); 632 633 if (sc->sc_state == 0) { 634 /* First time through; initialize. */ 635 636 TAILQ_INIT(&sc->ready_list); 637 sc->sc_nexus = NULL; 638 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 639 for (r = 0; r < sc->sc_ntarg; r++) { 640 LIST_INIT(&sc->sc_tinfo[r].luns); 641 } |
642 } else 643 ncr53c9x_clear(sc, CAM_CMD_TIMEOUT); |
644 645 /* 646 * Reset the chip to a known state. 647 */ 648 ncr53c9x_reset(sc); 649 650 sc->sc_flags = 0; 651 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 652 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 653 |
654 /* 655 * If we're the first time through, set the default parameters 656 * for all targets. Otherwise we only clear their current transfer 657 * settings so we'll renegotiate their goal settings with the next 658 * command. 659 */ 660 if (sc->sc_state == 0) { 661 for (r = 0; r < sc->sc_ntarg; r++) { 662 ti = &sc->sc_tinfo[r]; |
663/* XXX - config flags per target: low bits: no reselect; high bits: no synch */ |
664 |
665 ti->flags = ((sc->sc_minsync != 0 && 666 (sc->sc_cfflags & (1 << ((r & 7) + 8))) == 0) ? 667 0 : T_SYNCHOFF) | 668 ((sc->sc_cfflags & (1 << (r & 7))) == 0 ? 669 0 : T_RSELECTOFF); 670 ti->curr.period = ti->goal.period = 0; 671 ti->curr.offset = ti->goal.offset = 0; 672 ti->curr.width = ti->goal.width = 673 MSG_EXT_WDTR_BUS_8_BIT; 674 } 675 } else { 676 for (r = 0; r < sc->sc_ntarg; r++) { 677 ti = &sc->sc_tinfo[r]; 678 ti->flags &= ~(T_SDTRSENT | T_WDTRSENT); 679 ti->curr.period = 0; 680 ti->curr.offset = 0; 681 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT; 682 } |
683 } 684 685 if (doreset) { 686 sc->sc_state = NCR_SBR; 687 NCRCMD(sc, NCRCMD_RSTSCSI); |
688 /* Give the bus a fighting chance to settle. */ 689 DELAY(250000); |
690 } else { 691 sc->sc_state = NCR_IDLE; 692 ncr53c9x_sched(sc); 693 } 694} 695 696/* 697 * Read the NCR registers, and save their contents for later use. 698 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 699 * NCR_INTR - so make sure it is the last read. 700 * 701 * I think that (from reading the docs) most bits in these registers 702 * only make sense when the DMA CSR has an interrupt showing. Call only 703 * if an interrupt is pending. 704 */ 705static inline void 706ncr53c9x_readregs(struct ncr53c9x_softc *sc) 707{ 708 |
709 NCR_LOCK_ASSERT(sc, MA_OWNED); 710 |
711 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 712 /* Only the step bits are of interest. */ 713 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 714 715 if (sc->sc_rev == NCR_VARIANT_FAS366) 716 sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2); 717 718 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); --- 14 unchanged lines hidden (view full) --- 733 734/* 735 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 736 */ 737static inline int 738ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period) 739{ 740 int v; |
741 742 NCR_LOCK_ASSERT(sc, MA_OWNED); 743 |
744 v = (sc->sc_freq * period) / 250; 745 if (ncr53c9x_cpb2stp(sc, v) < period) 746 /* Correct round-down error. */ 747 v++; 748 return (v); 749} 750 751static inline void 752ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti) 753{ |
754 u_char cfg3, syncoff, synctp; |
755 |
756 NCR_LOCK_ASSERT(sc, MA_OWNED); 757 758 cfg3 = sc->sc_cfg3; 759 if (ti->curr.offset != 0) { 760 syncoff = ti->curr.offset; 761 synctp = ncr53c9x_stp2cpb(sc, ti->curr.period); |
762 if (sc->sc_features & NCR_F_FASTSCSI) { 763 /* 764 * If the period is 200ns or less (ti->period <= 50), 765 * put the chip in Fast SCSI mode. 766 */ |
767 if (ti->curr.period <= 50) |
768 /* 769 * There are (at least) 4 variations of the 770 * configuration 3 register. The drive attach 771 * routine sets the appropriate bit to put the 772 * chip into Fast SCSI mode so that it doesn't 773 * have to be figured out here each time. 774 */ 775 cfg3 |= sc->sc_cfg3_fscsi; --- 6 unchanged lines hidden (view full) --- 782 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 783 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 784 synctp--; 785 } else { 786 syncoff = 0; 787 synctp = 0; 788 } 789 |
790 if (ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT) { 791 if (sc->sc_rev == NCR_VARIANT_FAS366) 792 cfg3 |= NCRFASCFG3_EWIDE; 793 } 794 |
795 if (sc->sc_features & NCR_F_HASCFG3) 796 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 797 798 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 799 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 800} 801 802/* --- 8 unchanged lines hidden (view full) --- 811{ 812 struct ncr53c9x_tinfo *ti; 813 u_char *cmd; 814 size_t dmasize; 815 int clen, selatn3, selatns; 816 int lun = ecb->ccb->ccb_h.target_lun; 817 int target = ecb->ccb->ccb_h.target_id; 818 |
819 NCR_LOCK_ASSERT(sc, MA_OWNED); 820 |
821 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x,tag:%x,%x)] ", 822 target, lun, ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1])); 823 824 ti = &sc->sc_tinfo[target]; 825 sc->sc_state = NCR_SELECTING; 826 /* |
827 * Schedule the callout now, the first time we will go away |
828 * expecting to come back due to an interrupt, because it is 829 * always possible that the interrupt may never happen. 830 */ |
831 callout_reset(&ecb->ch, mstohz(ecb->timeout), ncr53c9x_callout, ecb); |
832 833 /* 834 * The docs say the target register is never reset, and I 835 * can't think of a better place to set it. 836 */ 837 if (sc->sc_rev == NCR_VARIANT_FAS366) { 838 NCRCMD(sc, NCRCMD_FLUSH); |
839 NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HMEXC32 | 840 NCR_BUSID_HMEENCID); |
841 } else { 842 NCR_WRITE_REG(sc, NCR_SELID, target); 843 } |
844 |
845 /* 846 * If we are requesting sense, force a renegotiation if we are 847 * currently using anything different from asynchronous at 8 bit 848 * as the target might have lost our transfer negotiations. 849 */ 850 if ((ecb->flags & ECB_SENSE) != 0 && (ti->curr.offset != 0 || 851 ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT)) { 852 ti->curr.period = 0; 853 ti->curr.offset = 0; 854 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT; |
855 } |
856 ncr53c9x_setsync(sc, ti); |
857 858 selatn3 = selatns = 0; 859 if (ecb->tag[0] != 0) { 860 if (sc->sc_features & NCR_F_SELATN3) 861 /* Use SELATN3 to send tag messages. */ 862 selatn3 = 1; 863 else 864 /* We don't have SELATN3; use SELATNS to send tags. */ 865 selatns = 1; 866 } 867 |
868 if (ti->curr.period != ti->goal.period || 869 ti->curr.offset != ti->goal.offset || 870 ti->curr.width != ti->goal.width) { |
871 /* We have to use SELATNS to send sync/wide messages. */ 872 selatn3 = 0; 873 selatns = 1; 874 } 875 876 cmd = (u_char *)&ecb->cmd.cmd; 877 878 if (selatn3) { --- 10 unchanged lines hidden (view full) --- 889 cmd[0] = MSG_IDENTIFY(lun, (ti->flags & T_RSELECTOFF) == 0); 890 } 891 892 if ((sc->sc_features & NCR_F_DMASELECT) && !selatns) { 893 /* Setup DMA transfer for command. */ 894 dmasize = clen; 895 sc->sc_cmdlen = clen; 896 sc->sc_cmdp = cmd; |
897 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize); |
898 /* Program the SCSI counter. */ 899 NCR_SET_COUNT(sc, dmasize); 900 901 /* Load the count in. */ 902 /* if (sc->sc_rev != NCR_VARIANT_FAS366) */ 903 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 904 905 /* And get the target's attention. */ 906 if (selatn3) { 907 sc->sc_msgout = SEND_TAG; 908 sc->sc_flags |= NCR_ATN; 909 NCRCMD(sc, NCRCMD_SELATN3 | NCRCMD_DMA); 910 } else 911 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA); |
912 NCRDMA_GO(sc); 913 return; 914 } 915 916 /* 917 * Who am I? This is where we tell the target that we are 918 * happy for it to disconnect etc. 919 */ --- 13 unchanged lines hidden (view full) --- 933 } else 934 NCRCMD(sc, NCRCMD_SELATN); 935} 936 937static void 938ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 939{ 940 |
941 NCR_LOCK_ASSERT(sc, MA_OWNED); 942 |
943 ecb->flags = 0; 944 TAILQ_INSERT_TAIL(&sc->free_list, ecb, free_links); 945} 946 947static struct ncr53c9x_ecb * 948ncr53c9x_get_ecb(struct ncr53c9x_softc *sc) 949{ 950 struct ncr53c9x_ecb *ecb; 951 |
952 NCR_LOCK_ASSERT(sc, MA_OWNED); 953 |
954 ecb = TAILQ_FIRST(&sc->free_list); 955 if (ecb) { 956 if (ecb->flags != 0) 957 panic("ecb flags not cleared\n"); 958 TAILQ_REMOVE(&sc->free_list, ecb, free_links); 959 ecb->flags = ECB_ALLOC; 960 bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) - 961 offsetof(struct ncr53c9x_ecb, ccb)); --- 6 unchanged lines hidden (view full) --- 968 */ 969 970/* 971 * Start a SCSI-command. 972 * This function is called by the higher level SCSI-driver to queue/run 973 * SCSI-commands. 974 */ 975 |
976static void |
977ncr53c9x_action(struct cam_sim *sim, union ccb *ccb) 978{ 979 struct ccb_pathinq *cpi; 980 struct ccb_scsiio *csio; 981 struct ccb_trans_settings *cts; 982 struct ccb_trans_settings_scsi *scsi; 983 struct ccb_trans_settings_spi *spi; 984 struct ncr53c9x_ecb *ecb; 985 struct ncr53c9x_softc *sc; 986 struct ncr53c9x_tinfo *ti; 987 int target; 988 |
989 sc = cam_sim_softc(sim); |
990 |
991 NCR_LOCK_ASSERT(sc, MA_OWNED); 992 993 NCR_TRACE(("[ncr53c9x_action %d]", ccb->ccb_h.func_code)); 994 |
995 switch (ccb->ccb_h.func_code) { 996 case XPT_RESET_BUS: |
997 ncr53c9x_init(sc, 1); |
998 ccb->ccb_h.status = CAM_REQ_CMP; |
999 xpt_done(ccb); 1000 return; 1001 1002 case XPT_CALC_GEOMETRY: |
1003 cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom); 1004 xpt_done(ccb); 1005 return; 1006 1007 case XPT_PATH_INQ: 1008 cpi = &ccb->cpi; 1009 cpi->version_num = 1; 1010 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 1011 cpi->hba_inquiry |= 1012 (sc->sc_rev == NCR_VARIANT_FAS366) ? PI_WIDE_16 : 0; 1013 cpi->target_sprt = 0; 1014 cpi->hba_misc = 0; 1015 cpi->hba_eng_cnt = 0; 1016 cpi->max_target = sc->sc_ntarg - 1; |
1017 cpi->max_lun = 7; |
1018 cpi->initiator_id = sc->sc_id; 1019 cpi->bus_id = 0; 1020 cpi->base_transfer_speed = 3300; 1021 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1022 strncpy(cpi->hba_vid, "Sun", HBA_IDLEN); 1023 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1024 cpi->unit_number = cam_sim_unit(sim); 1025 cpi->transport = XPORT_SPI; 1026 cpi->transport_version = 2; 1027 cpi->protocol = PROTO_SCSI; 1028 cpi->protocol_version = SCSI_REV_2; 1029 ccb->ccb_h.status = CAM_REQ_CMP; |
1030 xpt_done(ccb); 1031 return; 1032 1033 case XPT_GET_TRAN_SETTINGS: 1034 cts = &ccb->cts; 1035 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1036 scsi = &cts->proto_specific.scsi; 1037 spi = &cts->xport_specific.spi; 1038 1039 cts->protocol = PROTO_SCSI; 1040 cts->protocol_version = SCSI_REV_2; 1041 cts->transport = XPORT_SPI; 1042 cts->transport_version = 2; 1043 1044 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) { |
1045 spi->sync_period = ti->curr.period; 1046 spi->sync_offset = ti->curr.offset; 1047 spi->bus_width = ti->curr.width; |
1048 if ((ti->flags & T_TAG) != 0) { 1049 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 1050 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 1051 } else { 1052 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 1053 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 1054 } 1055 } else { |
1056 if ((ti->flags & T_SYNCHOFF) != 0) { 1057 spi->sync_period = 0; 1058 spi->sync_offset = 0; 1059 } else { 1060 spi->sync_period = sc->sc_minsync; 1061 spi->sync_offset = sc->sc_maxoffset; 1062 } |
1063 spi->bus_width = sc->sc_maxwidth; 1064 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 1065 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 1066 } 1067 spi->valid = 1068 CTS_SPI_VALID_BUS_WIDTH | 1069 CTS_SPI_VALID_SYNC_RATE | 1070 CTS_SPI_VALID_SYNC_OFFSET | 1071 CTS_SPI_VALID_DISC; 1072 scsi->valid = CTS_SCSI_VALID_TQ; 1073 ccb->ccb_h.status = CAM_REQ_CMP; |
1074 xpt_done(ccb); 1075 return; 1076 1077 case XPT_ABORT: |
1078 device_printf(sc->sc_dev, "XPT_ABORT called\n"); |
1079 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; |
1080 xpt_done(ccb); 1081 return; 1082 1083 case XPT_TERM_IO: |
1084 device_printf(sc->sc_dev, "XPT_TERM_IO called\n"); |
1085 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL; |
1086 xpt_done(ccb); 1087 return; 1088 1089 case XPT_RESET_DEV: |
1090 case XPT_SCSI_IO: 1091 if (ccb->ccb_h.target_id < 0 || 1092 ccb->ccb_h.target_id >= sc->sc_ntarg) { 1093 ccb->ccb_h.status = CAM_PATH_INVALID; |
1094 xpt_done(ccb); 1095 return; 1096 } 1097 /* Get an ECB to use. */ 1098 ecb = ncr53c9x_get_ecb(sc); 1099 /* 1100 * This should never happen as we track resources 1101 * in the mid-layer. 1102 */ 1103 if (ecb == NULL) { 1104 xpt_freeze_simq(sim, 1); 1105 ccb->ccb_h.status = CAM_REQUEUE_REQ; |
1106 device_printf(sc->sc_dev, "unable to allocate ecb\n"); |
1107 xpt_done(ccb); 1108 return; 1109 } 1110 1111 /* Initialize ecb. */ 1112 ecb->ccb = ccb; 1113 ecb->timeout = ccb->ccb_h.timeout; 1114 --- 34 unchanged lines hidden (view full) --- 1149 NCR_MISC(("%s: target %d: tagged queuing\n", 1150 device_get_nameunit(sc->sc_dev), target)); 1151 ti->flags |= T_TAG; 1152 } else 1153 ti->flags &= ~T_TAG; 1154 } 1155 1156 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) { |
1157 NCR_MISC(("%s: target %d: wide negotiation\n", 1158 device_get_nameunit(sc->sc_dev), target)); 1159 ti->goal.width = spi->bus_width; |
1160 } 1161 1162 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 1163 NCR_MISC(("%s: target %d: sync period negotiation\n", 1164 device_get_nameunit(sc->sc_dev), target)); |
1165 ti->goal.period = spi->sync_period; |
1166 } 1167 1168 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) { 1169 NCR_MISC(("%s: target %d: sync offset negotiation\n", 1170 device_get_nameunit(sc->sc_dev), target)); |
1171 ti->goal.offset = spi->sync_offset; |
1172 } 1173 |
1174 ccb->ccb_h.status = CAM_REQ_CMP; 1175 xpt_done(ccb); 1176 return; 1177 1178 default: 1179 device_printf(sc->sc_dev, "Unhandled function code %d\n", 1180 ccb->ccb_h.func_code); 1181 ccb->ccb_h.status = CAM_PROVIDE_FAIL; |
1182 xpt_done(ccb); 1183 return; 1184 } |
1185} 1186 1187/* 1188 * Used when interrupt driven I/O is not allowed, e.g. during boot. 1189 */ 1190static void 1191ncr53c9x_poll(struct cam_sim *sim) 1192{ 1193 struct ncr53c9x_softc *sc; 1194 |
1195 sc = cam_sim_softc(sim); |
1196 1197 NCR_LOCK_ASSERT(sc, MA_OWNED); 1198 1199 NCR_TRACE(("[ncr53c9x_poll] ")); 1200 1201 if (NCRDMA_ISINTR(sc)) 1202 ncr53c9x_intr1(sc); 1203} 1204 1205/* 1206 * Asynchronous notification handler 1207 */ 1208static void 1209ncr53c9x_async(void *cbarg, uint32_t code, struct cam_path *path, void *arg) 1210{ 1211 struct ncr53c9x_softc *sc; 1212 struct ncr53c9x_tinfo *ti; 1213 int target; 1214 1215 sc = cam_sim_softc(cbarg); 1216 1217 NCR_LOCK_ASSERT(sc, MA_OWNED); 1218 1219 switch (code) { 1220 case AC_LOST_DEVICE: 1221 target = xpt_path_target_id(path); 1222 if (target < 0 || target >= sc->sc_ntarg) 1223 break; 1224 1225 /* Cancel outstanding disconnected commands. */ 1226 ncr53c9x_clear_target(sc, target, CAM_REQ_ABORTED); 1227 1228 /* Set the default parameters for the target. */ 1229 ti = &sc->sc_tinfo[target]; 1230/* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 1231 ti->flags = ((sc->sc_minsync != 0 && 1232 (sc->sc_cfflags & (1 << ((target & 7) + 8))) == 0) ? 1233 0 : T_SYNCHOFF) | 1234 ((sc->sc_cfflags & (1 << (target & 7))) == 0 ? 1235 0 : T_RSELECTOFF); 1236 ti->curr.period = ti->goal.period = 0; 1237 ti->curr.offset = ti->goal.offset = 0; 1238 ti->curr.width = ti->goal.width = MSG_EXT_WDTR_BUS_8_BIT; 1239 break; |
1240 } 1241} 1242 1243/* 1244 * LOW LEVEL SCSI UTILITIES 1245 */ 1246 1247/* 1248 * Schedule a SCSI operation. This has now been pulled out of the interrupt |
1249 * handler so that we may call it from ncr53c9x_action and ncr53c9x_done. 1250 * This may save us an unnecessary interrupt just to get things going. 1251 * Should only be called when state == NCR_IDLE and with sc_lock held. |
1252 */ 1253static void 1254ncr53c9x_sched(struct ncr53c9x_softc *sc) 1255{ 1256 struct ncr53c9x_ecb *ecb; 1257 struct ncr53c9x_linfo *li; 1258 struct ncr53c9x_tinfo *ti; 1259 int lun, tag; 1260 |
1261 NCR_LOCK_ASSERT(sc, MA_OWNED); 1262 |
1263 NCR_TRACE(("[ncr53c9x_sched] ")); 1264 1265 if (sc->sc_state != NCR_IDLE) 1266 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 1267 1268 /* 1269 * Find first ecb in ready queue that is for a target/lunit 1270 * combinations that is not busy. 1271 */ |
1272 TAILQ_FOREACH(ecb, &sc->ready_list, chain) { |
1273 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1274 lun = ecb->ccb->ccb_h.target_lun; 1275 1276 /* Select type of tag for this command */ |
1277 if ((ti->flags & (T_RSELECTOFF | T_TAG)) != T_TAG) |
1278 tag = 0; |
1279 else if ((ecb->flags & ECB_SENSE) != 0) 1280 tag = 0; 1281 else if ((ecb->ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0) 1282 tag = 0; 1283 else if (ecb->ccb->csio.tag_action == CAM_TAG_ACTION_NONE) 1284 tag = 0; 1285 else 1286 tag = ecb->ccb->csio.tag_action; --- 62 unchanged lines hidden (view full) --- 1349ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1350{ 1351 union ccb *ccb = ecb->ccb; 1352 struct ncr53c9x_linfo *li; 1353 struct ncr53c9x_tinfo *ti; 1354 struct scsi_request_sense *ss = (void *)&ecb->cmd.cmd; 1355 int lun; 1356 |
1357 NCR_LOCK_ASSERT(sc, MA_OWNED); 1358 |
1359 NCR_TRACE(("requesting sense ")); 1360 1361 lun = ccb->ccb_h.target_lun; 1362 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1363 1364 /* Next, setup a REQUEST SENSE command block. */ 1365 memset(ss, 0, sizeof(*ss)); 1366 ss->opcode = REQUEST_SENSE; --- 27 unchanged lines hidden (view full) --- 1394static void 1395ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1396{ 1397 union ccb *ccb = ecb->ccb; 1398 struct ncr53c9x_linfo *li; 1399 struct ncr53c9x_tinfo *ti; 1400 int lun; 1401 |
1402 NCR_LOCK_ASSERT(sc, MA_OWNED); 1403 |
1404 NCR_TRACE(("[ncr53c9x_done(status:%x)] ", ccb->ccb_h.status)); 1405 1406 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1407 lun = ccb->ccb_h.target_lun; 1408 li = TINFO_LUN(ti, lun); 1409 |
1410 callout_stop(&ecb->ch); |
1411 1412 /* 1413 * Now, if we've come here with no error code, i.e. we've kept the |
1414 * initial CAM_REQ_CMP, and the status code signals that we should |
1415 * check sense, we'll need to set up a request sense cmd block and 1416 * push the command back into the ready queue *before* any other 1417 * commands for this target/lunit, else we lose the sense info. 1418 * We don't support chk sense conditions for the request sense cmd. 1419 */ 1420 if (ccb->ccb_h.status == CAM_REQ_CMP) { |
1421 ccb->csio.scsi_status = ecb->stat; |
1422 if ((ecb->flags & ECB_ABORT) != 0) { 1423 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1424 } else if ((ecb->flags & ECB_SENSE) != 0 && 1425 (ecb->stat != SCSI_STATUS_CHECK_COND)) { |
1426 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1427 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR | 1428 CAM_AUTOSNS_VALID; |
1429 } else if (ecb->stat == SCSI_STATUS_CHECK_COND) { 1430 if ((ecb->flags & ECB_SENSE) != 0) 1431 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1432 else { 1433 /* First, save the return values. */ 1434 ccb->csio.resid = ecb->dleft; |
1435 if ((ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 1436 0) { 1437 ncr53c9x_sense(sc, ecb); 1438 return; 1439 } 1440 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; |
1441 } 1442 } else { 1443 ccb->csio.resid = ecb->dleft; 1444 } |
1445 if (ecb->stat == SCSI_STATUS_QUEUE_FULL) 1446 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 1447 else if (ecb->stat == SCSI_STATUS_BUSY) 1448 ccb->ccb_h.status = CAM_SCSI_BUSY; |
1449 } 1450 1451#ifdef NCR53C9X_DEBUG 1452 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1453 if (ccb->csio.resid != 0) 1454 printf("resid=%d ", ccb->csio.resid); |
1455 if ((ccb->ccb_h.status & CAM_AUTOSNS_VALID) != 0) |
1456 printf("sense=0x%02x\n", |
1457 ccb->csio.sense_data.error_code); |
1458 else |
1459 printf("status SCSI=0x%x CAM=0x%x\n", 1460 ccb->csio.scsi_status, ccb->ccb_h.status); |
1461 } 1462#endif 1463 1464 /* 1465 * Remove the ECB from whatever queue it's on. 1466 */ 1467 ncr53c9x_dequeue(sc, ecb); 1468 if (ecb == sc->sc_nexus) { --- 21 unchanged lines hidden (view full) --- 1490 1491static void 1492ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1493{ 1494 struct ncr53c9x_linfo *li; 1495 struct ncr53c9x_tinfo *ti; 1496 int64_t lun; 1497 |
1498 NCR_LOCK_ASSERT(sc, MA_OWNED); 1499 |
1500 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1501 lun = ecb->ccb->ccb_h.target_lun; 1502 li = TINFO_LUN(ti, lun); 1503#ifdef DIAGNOSTIC 1504 if (li == NULL || li->lun != lun) 1505 panic("ncr53c9x_dequeue: lun %qx for ecb %p does not exist", 1506 (long long)lun, ecb); 1507#endif --- 7 unchanged lines hidden (view full) --- 1515 (li->queued[ecb->tag[1]] != ecb)) 1516 panic("ncr53c9x_dequeue: slot %d for lun %qx has %p " 1517 "instead of ecb %p\n", ecb->tag[1], 1518 (long long)lun, li->queued[ecb->tag[1]], ecb); 1519#endif 1520 li->queued[ecb->tag[1]] = NULL; 1521 li->used--; 1522 } |
1523 ecb->tag[0] = ecb->tag[1] = 0; |
1524 1525 if ((ecb->flags & ECB_READY) != 0) { 1526 ecb->flags &= ~ECB_READY; 1527 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1528 } 1529} 1530 1531/* --- 10 unchanged lines hidden (view full) --- 1542 NCRCMD(sc, NCRCMD_SETATN); \ 1543 sc->sc_flags |= NCR_ATN; \ 1544 sc->sc_msgpriq |= (m); \ 1545} while (0) 1546 1547static void 1548ncr53c9x_flushfifo(struct ncr53c9x_softc *sc) 1549{ |
1550 1551 NCR_LOCK_ASSERT(sc, MA_OWNED); 1552 |
1553 NCR_TRACE(("[flushfifo] ")); 1554 1555 NCRCMD(sc, NCRCMD_FLUSH); 1556 1557 if (sc->sc_phase == COMMAND_PHASE || 1558 sc->sc_phase == MESSAGE_OUT_PHASE) 1559 DELAY(2); 1560} 1561 1562static int 1563ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how) 1564{ 1565 u_char *ibuf; 1566 int i, n; 1567 |
1568 NCR_LOCK_ASSERT(sc, MA_OWNED); 1569 |
1570 switch (how) { 1571 case NCR_RDFIFO_START: 1572 ibuf = sc->sc_imess; 1573 sc->sc_imlen = 0; 1574 break; 1575 1576 case NCR_RDFIFO_CONTINUE: 1577 ibuf = sc->sc_imess + sc->sc_imlen; --- 46 unchanged lines hidden (view full) --- 1624 return (sc->sc_imlen); 1625} 1626 1627static void 1628ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, int len) 1629{ 1630 int i; 1631 |
1632 NCR_LOCK_ASSERT(sc, MA_OWNED); 1633 |
1634#ifdef NCR53C9X_DEBUG 1635 NCR_MSGS(("[wrfifo(%d):", len)); 1636 if (ncr53c9x_debug & NCR_SHOWMSGS) { 1637 for (i = 0; i < len; i++) 1638 printf(" %02x", p[i]); 1639 printf("]\n"); 1640 } 1641#endif --- 10 unchanged lines hidden (view full) --- 1652ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype, 1653 int tagid) 1654{ 1655 struct ncr53c9x_ecb *ecb = NULL; 1656 struct ncr53c9x_linfo *li; 1657 struct ncr53c9x_tinfo *ti; 1658 u_char lun, selid, target; 1659 |
1660 NCR_LOCK_ASSERT(sc, MA_OWNED); |
1661 1662 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1663 target = sc->sc_selid; 1664 } else { 1665 /* 1666 * The SCSI chip made a snapshot of the data bus 1667 * while the reselection was being negotiated. 1668 * This enables us to determine which target did --- 98 unchanged lines hidden (view full) --- 1767ncr53c9x_msgin(struct ncr53c9x_softc *sc) 1768{ 1769 struct ncr53c9x_ecb *ecb; 1770 struct ncr53c9x_linfo *li; 1771 struct ncr53c9x_tinfo *ti; 1772 u_char *pb; 1773 int lun, plen; 1774 |
1775 NCR_LOCK_ASSERT(sc, MA_OWNED); 1776 |
1777 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1778 1779 if (sc->sc_imlen == 0) { 1780 device_printf(sc->sc_dev, "msgin: no msg byte available\n"); 1781 return; 1782 } 1783 1784 /* --- 11 unchanged lines hidden (view full) --- 1796 } 1797 1798 /* 1799 * If we're going to reject the message, don't bother storing 1800 * the incoming bytes. But still, we need to ACK them. 1801 */ 1802 if ((sc->sc_flags & NCR_DROP_MSGI) != 0) { 1803 NCRCMD(sc, NCRCMD_MSGOK); |
1804 device_printf(sc->sc_dev, "<dropping msg byte %x>", 1805 sc->sc_imess[sc->sc_imlen]); |
1806 return; 1807 } 1808 1809 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1810 ncr53c9x_sched_msgout(SEND_REJECT); 1811 sc->sc_flags |= NCR_DROP_MSGI; 1812 } else { 1813 switch (sc->sc_state) { --- 83 unchanged lines hidden (view full) --- 1897 li->busy = 1; 1898 break; 1899 1900 case SEND_SDTR: 1901 device_printf(sc->sc_dev, "sync transfer " 1902 "rejected: target %d\n", 1903 ecb->ccb->ccb_h.target_id); 1904 |
1905 ti->flags &= ~T_SDTRSENT; 1906 ti->curr.period = ti->goal.period = 0; 1907 ti->curr.offset = ti->goal.offset = 0; |
1908 ncr53c9x_setsync(sc, ti); 1909 break; 1910 1911 case SEND_WDTR: 1912 device_printf(sc->sc_dev, "wide transfer " 1913 "rejected: target %d\n", 1914 ecb->ccb->ccb_h.target_id); |
1915 1916 ti->flags &= ~T_WDTRSENT; 1917 ti->curr.width = ti->goal.width = 1918 MSG_EXT_WDTR_BUS_8_BIT; 1919 ncr53c9x_setsync(sc, ti); |
1920 break; 1921 1922 case SEND_INIT_DET_ERR: 1923 goto abort; 1924 } 1925 break; 1926 1927 case MSG_NOOP: --- 37 unchanged lines hidden (view full) --- 1965 case MSG_EXTENDED: 1966 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1967 switch (sc->sc_imess[2]) { 1968 case MSG_EXT_SDTR: 1969 NCR_MSGS(("SDTR period %d, offset %d ", 1970 sc->sc_imess[3], sc->sc_imess[4])); 1971 if (sc->sc_imess[1] != 3) 1972 goto reject; |
1973 ti->curr.period = sc->sc_imess[3]; 1974 ti->curr.offset = sc->sc_imess[4]; |
1975 if (sc->sc_minsync == 0 || |
1976 ti->curr.offset == 0 || 1977 ti->curr.period > 124) { |
1978#if 0 1979#ifdef NCR53C9X_DEBUG 1980 xpt_print_path(ecb->ccb->ccb_h.path); 1981 printf("async mode\n"); 1982#endif 1983#endif |
1984 if ((ti->flags & T_SDTRSENT) == 0) { |
1985 /* 1986 * target initiated negotiation 1987 */ |
1988 ti->curr.offset = 0; |
1989 ncr53c9x_sched_msgout( 1990 SEND_SDTR); 1991 } 1992 } else { |
1993 ti->curr.period = |
1994 ncr53c9x_cpb2stp(sc, 1995 ncr53c9x_stp2cpb(sc, |
1996 ti->curr.period)); 1997 if ((ti->flags & T_SDTRSENT) == 0) { |
1998 /* 1999 * target initiated negotiation 2000 */ |
2001 if (ti->curr.period < 2002 sc->sc_minsync) 2003 ti->curr.period = |
2004 sc->sc_minsync; |
2005 if (ti->curr.offset > 2006 sc->sc_maxoffset) 2007 ti->curr.offset = 2008 sc->sc_maxoffset; |
2009 ncr53c9x_sched_msgout( 2010 SEND_SDTR); |
2011 } 2012 } |
2013 ti->flags &= ~T_SDTRSENT; 2014 ti->goal.period = ti->curr.period; 2015 ti->goal.offset = ti->curr.offset; |
2016 ncr53c9x_setsync(sc, ti); 2017 break; 2018 2019 case MSG_EXT_WDTR: |
2020 NCR_MSGS(("wide mode %d ", sc->sc_imess[3])); 2021 ti->curr.width = sc->sc_imess[3]; |
2022 if (!(ti->flags & T_WDTRSENT)) |
2023 /* 2024 * target initiated negotiation 2025 */ |
2026 ncr53c9x_sched_msgout(SEND_WDTR); |
2027 ti->flags &= ~T_WDTRSENT; 2028 ti->goal.width = ti->curr.width; 2029 ncr53c9x_setsync(sc, ti); |
2030 break; 2031 2032 default: 2033 xpt_print_path(ecb->ccb->ccb_h.path); 2034 printf("unrecognized MESSAGE EXTENDED;" 2035 " sending REJECT\n"); 2036 goto reject; 2037 } --- 45 unchanged lines hidden (view full) --- 2083 ncr53c9x_sched_msgout(SEND_DEV_RESET); 2084 break; 2085 2086 abort: 2087 ncr53c9x_sched_msgout(SEND_ABORT); 2088 } 2089 2090 /* If we have more messages to send set ATN. */ |
2091 if (sc->sc_msgpriq) { |
2092 NCRCMD(sc, NCRCMD_SETATN); |
2093 sc->sc_flags |= NCR_ATN; 2094 } |
2095 2096 /* Acknowledge last message byte. */ 2097 NCRCMD(sc, NCRCMD_MSGOK); 2098 2099 /* Done, reset message pointer. */ 2100 sc->sc_flags &= ~NCR_DROP_MSGI; 2101 sc->sc_imlen = 0; 2102} --- 6 unchanged lines hidden (view full) --- 2109{ 2110 struct ncr53c9x_tinfo *ti; 2111 struct ncr53c9x_ecb *ecb; 2112 size_t size; 2113#ifdef NCR53C9X_DEBUG 2114 int i; 2115#endif 2116 |
2117 NCR_LOCK_ASSERT(sc, MA_OWNED); 2118 |
2119 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 2120 sc->sc_msgpriq, sc->sc_prevphase)); 2121 2122 /* 2123 * XXX - the NCR_ATN flag is not in sync with the actual ATN 2124 * condition on the SCSI bus. The 53c9x chip 2125 * automatically turns off ATN before sending the 2126 * message byte. (See also the comment below in the --- 25 unchanged lines hidden (view full) --- 2152 sc->sc_omlen = 1; /* "Default" message len */ 2153 switch (sc->sc_msgout) { 2154 case SEND_SDTR: 2155 ecb = sc->sc_nexus; 2156 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2157 sc->sc_omess[0] = MSG_EXTENDED; 2158 sc->sc_omess[1] = MSG_EXT_SDTR_LEN; 2159 sc->sc_omess[2] = MSG_EXT_SDTR; |
2160 sc->sc_omess[3] = ti->goal.period; 2161 sc->sc_omess[4] = ti->goal.offset; |
2162 sc->sc_omlen = 5; |
2163 break; 2164 2165 case SEND_WDTR: 2166 ecb = sc->sc_nexus; 2167 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2168 sc->sc_omess[0] = MSG_EXTENDED; 2169 sc->sc_omess[1] = MSG_EXT_WDTR_LEN; 2170 sc->sc_omess[2] = MSG_EXT_WDTR; |
2171 sc->sc_omess[3] = ti->goal.width; |
2172 sc->sc_omlen = 4; 2173 break; 2174 2175 case SEND_IDENTIFY: 2176 if (sc->sc_state != NCR_CONNECTED) { 2177 device_printf(sc->sc_dev, "at line %d: no " 2178 "nexus\n", __LINE__); 2179 } --- 13 unchanged lines hidden (view full) --- 2193 sc->sc_omlen = 2; 2194 break; 2195 2196 case SEND_DEV_RESET: 2197 sc->sc_flags |= NCR_ABORTING; 2198 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 2199 ecb = sc->sc_nexus; 2200 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; |
2201 ti->curr.period = 0; 2202 ti->curr.offset = 0; 2203 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT; |
2204 break; 2205 2206 case SEND_PARITY_ERROR: 2207 sc->sc_omess[0] = MSG_PARITY_ERROR; 2208 break; 2209 2210 case SEND_ABORT: 2211 sc->sc_flags |= NCR_ABORTING; --- 40 unchanged lines hidden (view full) --- 2252 /* 2253 * XXX FIFO size 2254 */ 2255 ncr53c9x_flushfifo(sc); 2256 ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen); 2257 NCRCMD(sc, NCRCMD_TRANS); 2258 } else { 2259 /* (Re)send the message. */ |
2260 size = ulmin(sc->sc_omlen, sc->sc_maxxfer); |
2261 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 2262 /* Program the SCSI counter. */ 2263 NCR_SET_COUNT(sc, size); 2264 2265 /* Load the count in and start the message-out transfer. */ 2266 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 2267 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2268 NCRDMA_GO(sc); 2269 } 2270} 2271 |
2272void 2273ncr53c9x_intr(void *arg) 2274{ 2275 struct ncr53c9x_softc *sc = arg; 2276 2277 if (!NCRDMA_ISINTR(sc)) 2278 return; 2279 2280 NCR_LOCK(sc); 2281 2282 ncr53c9x_intr1(sc); 2283 2284 NCR_UNLOCK(sc); 2285} 2286 |
2287/* 2288 * This is the most critical part of the driver, and has to know 2289 * how to deal with *all* error conditions and phases from the SCSI 2290 * bus. If there are no errors and the DMA was active, then call the 2291 * DMA pseudo-interrupt handler. If this returns 1, then that was it 2292 * and we can return from here without further processing. 2293 * 2294 * Most of this needs verifying. 2295 */ |
2296static void 2297ncr53c9x_intr1(struct ncr53c9x_softc *sc) |
2298{ |
2299 struct ncr53c9x_ecb *ecb; 2300 struct ncr53c9x_linfo *li; 2301 struct ncr53c9x_tinfo *ti; 2302 struct timeval cur, wait; 2303 size_t size; 2304 int i, nfifo; 2305 u_char msg; 2306 |
2307 NCR_LOCK_ASSERT(sc, MA_OWNED); 2308 |
2309 NCR_INTS(("[ncr53c9x_intr: state %d]", sc->sc_state)); 2310 |
2311again: 2312 /* and what do the registers say... */ 2313 ncr53c9x_readregs(sc); 2314 2315 /* 2316 * At the moment, only a SCSI Bus Reset or Illegal 2317 * Command are classed as errors. A disconnect is a 2318 * valid condition, and we let the code check is the --- 13 unchanged lines hidden (view full) --- 2332 if ((sc->sc_espintr & NCRINTR_SBR) != 0) { 2333 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 0) { 2334 NCRCMD(sc, NCRCMD_FLUSH); 2335 DELAY(1); 2336 } 2337 if (sc->sc_state != NCR_SBR) { 2338 device_printf(sc->sc_dev, "SCSI bus reset\n"); 2339 ncr53c9x_init(sc, 0); /* Restart everything. */ |
2340 return; |
2341 } 2342#if 0 |
2343/*XXX*/ device_printf(sc->sc_dev, "<expected bus reset: " |
2344 "[intr %x, stat %x, step %d]>\n", 2345 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2346#endif 2347 if (sc->sc_nexus != NULL) 2348 panic("%s: nexus in reset state", 2349 device_get_nameunit(sc->sc_dev)); 2350 goto sched; 2351 } --- 9 unchanged lines hidden (view full) --- 2361 NCRCMD(sc, NCRCMD_FLUSH); 2362 DELAY(1); 2363 } 2364 if (sc->sc_state == NCR_CONNECTED || 2365 sc->sc_state == NCR_SELECTING) { 2366 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2367 ncr53c9x_done(sc, ecb); 2368 } |
2369 return; |
2370 } 2371 2372 if ((sc->sc_espintr & NCRINTR_ILL) != 0) { 2373 if ((sc->sc_flags & NCR_EXPECT_ILLCMD) != 0) { 2374 /* 2375 * Eat away "Illegal command" interrupt 2376 * on a ESP100 caused by a re-selection 2377 * while we were trying to select 2378 * another target. 2379 */ 2380#ifdef DEBUG 2381 device_printf(sc->sc_dev, "ESP100 work-around " 2382 "activated\n"); 2383#endif 2384 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; |
2385 return; |
2386 } 2387 /* Illegal command, out of sync? */ 2388 device_printf(sc->sc_dev, "illegal command: 0x%x " 2389 "(state %d, phase %x, prevphase %x)\n", 2390 sc->sc_lastcmd, 2391 sc->sc_state, sc->sc_phase, sc->sc_prevphase); 2392 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2393 NCRCMD(sc, NCRCMD_FLUSH); 2394 DELAY(1); 2395 } |
2396 goto reset; |
2397 } 2398 } 2399 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 2400 2401 /* 2402 * Call if DMA is active. 2403 * 2404 * If DMA_INTR returns true, then maybe go 'round the loop 2405 * again in case there is no more DMA queued, but a phase 2406 * change is expected. 2407 */ 2408 if (NCRDMA_ISACTIVE(sc)) { 2409 if (NCRDMA_INTR(sc) == -1) { 2410 device_printf(sc->sc_dev, "DMA error; resetting\n"); |
2411 goto reset; |
2412 } 2413 /* If DMA active here, then go back to work... */ 2414 if (NCRDMA_ISACTIVE(sc)) |
2415 return; |
2416 2417 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 2418 /* 2419 * DMA not completed. If we can not find a 2420 * acceptable explanation, print a diagnostic. 2421 */ 2422 if (sc->sc_state == NCR_SELECTING) 2423 /* --- 33 unchanged lines hidden (view full) --- 2457 device_printf(sc->sc_dev, "!TC on DATA XFER" 2458 " [intr %x, stat %x, step %d]" 2459 " prevphase %x, resid %x\n", 2460 sc->sc_espintr, 2461 sc->sc_espstat, 2462 sc->sc_espstep, 2463 sc->sc_prevphase, 2464 ecb ? ecb->dleft : -1); |
2465 goto reset; |
2466 } 2467 } 2468 } 2469 2470 /* 2471 * Check for less serious errors. 2472 */ 2473 if ((sc->sc_espstat & NCRSTAT_PE) != 0) { --- 40 unchanged lines hidden (view full) --- 2514 li = LIST_FIRST(&ti->luns); 2515 continue; 2516 } 2517 li = LIST_NEXT(li, link); 2518 } 2519 goto finish; 2520 2521 case NCR_CONNECTED: |
2522 if (ecb != NULL) { |
2523 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; |
2524 if ((ti->flags & T_SDTRSENT) != 0) { 2525 xpt_print_path(ecb->ccb->ccb_h.path); 2526 printf("sync nego not completed!\n"); 2527 ti->flags &= ~T_SDTRSENT; 2528 ti->curr.period = ti->goal.period = 0; 2529 ti->curr.offset = ti->goal.offset = 0; 2530 ncr53c9x_setsync(sc, ti); 2531 } 2532 if ((ti->flags & T_WDTRSENT) != 0) { 2533 xpt_print_path(ecb->ccb->ccb_h.path); 2534 printf("wide nego not completed!\n"); 2535 ti->flags &= ~T_WDTRSENT; 2536 ti->curr.width = ti->goal.width = 2537 MSG_EXT_WDTR_BUS_8_BIT; 2538 ncr53c9x_setsync(sc, ti); 2539 } |
2540 } 2541 2542 /* It may be OK to disconnect. */ 2543 if ((sc->sc_flags & NCR_ABORTING) == 0) { 2544 /* 2545 * Section 5.1.1 of the SCSI 2 spec 2546 * suggests issuing a REQUEST SENSE 2547 * following an unexpected disconnect. --- 16 unchanged lines hidden (view full) --- 2564 * safely cancel the DMA that is in 2565 * progress. 2566 */ 2567 if (1 || (ecb->flags & ECB_SENSE) != 0) { 2568 printf("resetting\n"); 2569 goto reset; 2570 } 2571 printf("sending REQUEST SENSE\n"); |
2572 callout_stop(&ecb->ch); |
2573 ncr53c9x_sense(sc, ecb); |
2574 return; 2575 } else if (ecb != NULL && 2576 (ecb->flags & ECB_RESET) != 0) { 2577 ecb->ccb->ccb_h.status = CAM_REQ_CMP; 2578 goto finish; |
2579 } 2580 2581 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT; 2582 goto finish; 2583 2584 case NCR_DISCONNECT: 2585 sc->sc_nexus = NULL; 2586 goto sched; 2587 2588 case NCR_CMDCOMPLETE: 2589 ecb->ccb->ccb_h.status = CAM_REQ_CMP; 2590 goto finish; 2591 } 2592 } 2593 2594 switch (sc->sc_state) { 2595 case NCR_SBR: 2596 device_printf(sc->sc_dev, "waiting for Bus Reset to happen\n"); |
2597 return; |
2598 2599 case NCR_RESELECTED: 2600 /* 2601 * We must be continuing a message? 2602 */ 2603 device_printf(sc->sc_dev, "unhandled reselect continuation, " 2604 "state %d, intr %02x\n", sc->sc_state, sc->sc_espintr); |
2605 goto reset; |
2606 break; 2607 2608 case NCR_IDENTIFIED: 2609 ecb = sc->sc_nexus; 2610 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2611 i = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 2612 /* 2613 * Things are seriously screwed up. 2614 * Pull the brakes, i.e. reset. 2615 */ 2616 device_printf(sc->sc_dev, "target didn't send tag: %d " 2617 "bytes in FIFO\n", i); 2618 /* Drain and display FIFO. */ 2619 while (i-- > 0) 2620 printf("[%d] ", NCR_READ_REG(sc, NCR_FIFO)); 2621 |
2622 goto reset; |
2623 } else 2624 goto msgin; 2625 2626 case NCR_IDLE: 2627 case NCR_SELECTING: 2628 ecb = sc->sc_nexus; 2629 if (sc->sc_espintr & NCRINTR_RESEL) { 2630 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 2631 sc->sc_flags = 0; 2632 /* 2633 * If we're trying to select a 2634 * target ourselves, push our command 2635 * back into the ready list. 2636 */ 2637 if (sc->sc_state == NCR_SELECTING) { 2638 NCR_INTS(("backoff selector ")); |
2639 callout_stop(&ecb->ch); |
2640 ncr53c9x_dequeue(sc, ecb); 2641 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2642 ecb->flags |= ECB_READY; 2643 ecb = sc->sc_nexus = NULL; 2644 } 2645 sc->sc_state = NCR_RESELECTED; 2646 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2647 /* 2648 * Things are seriously screwed up. 2649 * Pull the brakes, i.e. reset 2650 */ 2651 device_printf(sc->sc_dev, "target didn't " 2652 "identify\n"); |
2653 goto reset; |
2654 } 2655 /* 2656 * The C90 only inhibits FIFO writes until reselection 2657 * is complete instead of waiting until the interrupt 2658 * status register has been read. So, if the reselect 2659 * happens while we were entering command bytes (for 2660 * another target) some of those bytes can appear in 2661 * the FIFO here, after the interrupt is taken. --- 25 unchanged lines hidden (view full) --- 2687 device_printf(sc->sc_dev, "RESELECT: %d bytes " 2688 "in FIFO! [intr %x, stat %x, step %d, " 2689 "prevphase %x]\n", 2690 nfifo, 2691 sc->sc_espintr, 2692 sc->sc_espstat, 2693 sc->sc_espstep, 2694 sc->sc_prevphase); |
2695 goto reset; |
2696 } 2697 sc->sc_selid = sc->sc_imess[0]; 2698 NCR_INTS(("selid=%02x ", sc->sc_selid)); 2699 2700 /* Handle IDENTIFY message. */ 2701 ncr53c9x_msgin(sc); 2702 2703 if (sc->sc_state != NCR_CONNECTED && 2704 sc->sc_state != NCR_IDENTIFIED) { 2705 /* IDENTIFY fail?! */ 2706 device_printf(sc->sc_dev, "identify failed, " 2707 "state %d, intr %02x\n", sc->sc_state, 2708 sc->sc_espintr); |
2709 goto reset; |
2710 } 2711 goto shortcut; /* i.e. next phase expected soon */ 2712 } 2713 2714#define NCRINTR_DONE (NCRINTR_FC | NCRINTR_BS) 2715 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 2716 /* 2717 * Arbitration won; examine the `step' register 2718 * to determine how far the selection could progress. 2719 */ 2720 if (ecb == NULL) { 2721 /* 2722 * When doing path inquiry during boot 2723 * FAS100A trigger a stray interrupt which 2724 * we just ignore instead of panicing. 2725 */ 2726 if (sc->sc_state == NCR_IDLE && 2727 sc->sc_espstep == 0) |
2728 return; |
2729 panic("ncr53c9x: no nexus"); 2730 } 2731 2732 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2733 2734 switch (sc->sc_espstep) { 2735 case 0: 2736 /* --- 4 unchanged lines hidden (view full) --- 2741 * target should be in the command 2742 * phase. 2743 * XXX check for command phase? 2744 */ 2745 NCRCMD(sc, NCRCMD_RSTATN); 2746 break; 2747 2748 case 1: |
2749 if (ti->curr.period == ti->goal.period && 2750 ti->curr.offset == ti->goal.offset && 2751 ti->curr.width == ti->goal.width && |
2752 ecb->tag[0] == 0) { |
2753 device_printf(sc->sc_dev, "step 1 " 2754 "and no negotiation to perform " 2755 "or tag to send\n"); |
2756 goto reset; 2757 } 2758 if (sc->sc_phase != MESSAGE_OUT_PHASE) { |
2759 device_printf(sc->sc_dev, "step 1 " 2760 "but not in MESSAGE_OUT_PHASE\n"); |
2761 goto reset; 2762 } |
2763 sc->sc_prevphase = MESSAGE_OUT_PHASE; /* XXX */ 2764 if (ecb->flags & ECB_RESET) { 2765 /* 2766 * A DEVICE RESET was scheduled and 2767 * ATNS used. As SEND_DEV_RESET has 2768 * the highest priority, the target 2769 * will reset and disconnect and we 2770 * will end up in ncr53c9x_done w/o 2771 * negotiating or sending a TAG. So 2772 * we just break here in order to 2773 * avoid warnings about negotiation 2774 * not having completed. 2775 */ 2776 ncr53c9x_sched_msgout(SEND_DEV_RESET); 2777 break; |
2778 } |
2779 if (ti->curr.width != ti->goal.width) { 2780 ti->flags |= T_WDTRSENT | T_SDTRSENT; 2781 ncr53c9x_sched_msgout(SEND_WDTR | 2782 SEND_SDTR); 2783 } 2784 if (ti->curr.period != ti->goal.period || 2785 ti->curr.offset != ti->goal.offset) { 2786 ti->flags |= T_SDTRSENT; 2787 ncr53c9x_sched_msgout(SEND_SDTR); 2788 } 2789 if (ecb->tag[0] != 0) |
2790 /* Could not do ATN3 so send TAG. */ 2791 ncr53c9x_sched_msgout(SEND_TAG); |
2792 break; 2793 2794 case 3: 2795 /* 2796 * Grr, this is supposed to mean 2797 * "target left command phase prematurely". 2798 * It seems to happen regularly when 2799 * sync mode is on. --- 4 unchanged lines hidden (view full) --- 2804 if (sc->sc_cmdlen == 0) 2805 /* Hope for the best... */ 2806 break; 2807 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 2808 & NCRFIFO_FF) == 0) { 2809 /* Hope for the best... */ 2810 break; 2811 } |
2812 xpt_print_path(ecb->ccb->ccb_h.path); 2813 printf("selection failed; %d left in FIFO " |
2814 "[intr %x, stat %x, step %d]\n", |
2815 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, 2816 sc->sc_espintr, sc->sc_espstat, 2817 sc->sc_espstep); 2818 NCRCMD(sc, NCRCMD_FLUSH); 2819 ncr53c9x_sched_msgout(SEND_ABORT); |
2820 return; |
2821 2822 case 2: 2823 /* Select stuck at Command Phase. */ 2824 NCRCMD(sc, NCRCMD_FLUSH); 2825 break; 2826 2827 case 4: 2828 if (sc->sc_features & NCR_F_DMASELECT && |
2829 sc->sc_cmdlen != 0) { 2830 xpt_print_path(ecb->ccb->ccb_h.path); 2831 printf("select; %lu left in DMA buffer " |
2832 "[intr %x, stat %x, step %d]\n", |
2833 (u_long)sc->sc_cmdlen, 2834 sc->sc_espintr, 2835 sc->sc_espstat, 2836 sc->sc_espstep); |
2837 } |
2838 /* So far, everything went fine. */ 2839 break; 2840 } 2841 2842 sc->sc_prevphase = INVALID_PHASE; /* ??? */ 2843 /* Do an implicit RESTORE POINTERS. */ 2844 sc->sc_dp = ecb->daddr; 2845 sc->sc_dleft = ecb->dleft; --- 4 unchanged lines hidden (view full) --- 2850 "select: [intr %x, stat %x, step %x]\n", 2851 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2852 NCRCMD(sc, NCRCMD_FLUSH); 2853 DELAY(1); 2854 goto reset; 2855 } 2856 if (sc->sc_state == NCR_IDLE) { 2857 device_printf(sc->sc_dev, "stray interrupt\n"); |
2858 return; |
2859 } 2860 break; 2861 2862 case NCR_CONNECTED: 2863 if ((sc->sc_flags & NCR_ICCS) != 0) { 2864 /* "Initiate Command Complete Steps" in progress */ 2865 sc->sc_flags &= ~NCR_ICCS; 2866 --- 88 unchanged lines hidden (view full) --- 2955 */ 2956 2957 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2958 ecb->cmd.cmd.opcode, ecb->clen)); 2959 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2960 NCRCMD(sc, NCRCMD_FLUSH); 2961/* DELAY(1);*/ 2962 } |
2963 /* 2964 * If we have more messages to send, e.g. WDTR or SDTR 2965 * after we've sent a TAG, set ATN so we'll go back to 2966 * MESSAGE_OUT_PHASE. 2967 */ 2968 if (sc->sc_msgpriq) { 2969 NCRCMD(sc, NCRCMD_SETATN); 2970 sc->sc_flags |= NCR_ATN; 2971 } |
2972 if (sc->sc_features & NCR_F_DMASELECT) { 2973 /* Setup DMA transfer for command. */ 2974 size = ecb->clen; 2975 sc->sc_cmdlen = size; 2976 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2977 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2978 0, &size); 2979 /* Program the SCSI counter. */ --- 10 unchanged lines hidden (view full) --- 2990 NCRCMD(sc, NCRCMD_TRANS); 2991 } 2992 sc->sc_prevphase = COMMAND_PHASE; 2993 break; 2994 2995 case DATA_OUT_PHASE: 2996 NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft)); 2997 NCRCMD(sc, NCRCMD_FLUSH); |
2998 size = ulmin(sc->sc_dleft, sc->sc_maxxfer); |
2999 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size); 3000 sc->sc_prevphase = DATA_OUT_PHASE; 3001 goto setup_xfer; 3002 3003 case DATA_IN_PHASE: 3004 NCR_PHASE(("DATA_IN_PHASE ")); 3005 if (sc->sc_rev == NCR_VARIANT_ESP100) 3006 NCRCMD(sc, NCRCMD_FLUSH); |
3007 size = ulmin(sc->sc_dleft, sc->sc_maxxfer); |
3008 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size); 3009 sc->sc_prevphase = DATA_IN_PHASE; 3010 setup_xfer: 3011 /* Target returned to data phase: wipe "done" memory */ 3012 ecb->flags &= ~ECB_TENTATIVE_DONE; 3013 3014 /* Program the SCSI counter. */ 3015 NCR_SET_COUNT(sc, size); --- 6 unchanged lines hidden (view full) --- 3022 * all the bytes we want but we're still in DATA PHASE. 3023 * Apparently, the device needs padding. Also, a 3024 * transfer size of 0 means "maximum" to the chip 3025 * DMA logic. 3026 */ 3027 NCRCMD(sc, 3028 (size == 0 ? NCRCMD_TRPAD : NCRCMD_TRANS) | NCRCMD_DMA); 3029 NCRDMA_GO(sc); |
3030 return; |
3031 3032 case STATUS_PHASE: 3033 NCR_PHASE(("STATUS_PHASE ")); 3034 sc->sc_flags |= NCR_ICCS; 3035 NCRCMD(sc, NCRCMD_ICCS); 3036 sc->sc_prevphase = STATUS_PHASE; 3037 goto shortcut; /* i.e. expect status results soon */ 3038 3039 case INVALID_PHASE: 3040 break; 3041 3042 default: 3043 device_printf(sc->sc_dev, 3044 "unexpected bus phase; resetting\n"); 3045 goto reset; 3046 } 3047 |
3048 return; 3049 3050reset: 3051 ncr53c9x_init(sc, 1); |
3052 return; |
3053 3054finish: 3055 ncr53c9x_done(sc, ecb); |
3056 return; |
3057 3058sched: 3059 sc->sc_state = NCR_IDLE; 3060 ncr53c9x_sched(sc); |
3061 return; |
3062 3063shortcut: 3064 /* 3065 * The idea is that many of the SCSI operations take very little 3066 * time, and going away and getting interrupted is too high an 3067 * overhead to pay. For example, selecting, sending a message 3068 * and command and then doing some work can be done in one "pass". 3069 * --- 6 unchanged lines hidden (view full) --- 3076 wait.tv_sec++; 3077 wait.tv_usec -= 1000000; 3078 } 3079 do { 3080 if (NCRDMA_ISINTR(sc)) 3081 goto again; 3082 microtime(&cur); 3083 } while (cur.tv_sec <= wait.tv_sec && cur.tv_usec <= wait.tv_usec); |
3084} 3085 3086static void 3087ncr53c9x_abort(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 3088{ 3089 |
3090 NCR_LOCK_ASSERT(sc, MA_OWNED); 3091 |
3092 /* 2 secs for the abort */ 3093 ecb->timeout = NCR_ABORT_TIMEOUT; 3094 ecb->flags |= ECB_ABORT; 3095 3096 if (ecb == sc->sc_nexus) { 3097 /* 3098 * If we're still selecting, the message will be scheduled 3099 * after selection is complete. 3100 */ 3101 if (sc->sc_state == NCR_CONNECTED) 3102 ncr53c9x_sched_msgout(SEND_ABORT); 3103 3104 /* |
3105 * Reschedule callout. |
3106 */ |
3107 callout_reset(&ecb->ch, mstohz(ecb->timeout), 3108 ncr53c9x_callout, ecb); |
3109 } else { 3110 /* 3111 * Just leave the command where it is. 3112 * XXX - what choice do we have but to reset the SCSI 3113 * eventually? 3114 */ 3115 if (sc->sc_state == NCR_IDLE) 3116 ncr53c9x_sched(sc); 3117 } 3118} 3119 3120static void |
3121ncr53c9x_callout(void *arg) |
3122{ 3123 struct ncr53c9x_ecb *ecb = arg; 3124 union ccb *ccb = ecb->ccb; 3125 struct ncr53c9x_softc *sc = ecb->sc; |
3126 struct ncr53c9x_tinfo *ti; |
3127 |
3128 NCR_LOCK_ASSERT(sc, MA_OWNED); 3129 3130 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; |
3131 xpt_print_path(ccb->ccb_h.path); 3132 device_printf(sc->sc_dev, "timed out [ecb %p (flags 0x%x, dleft %x, " 3133 "stat %x)], <state %d, nexus %p, phase(l %x, c %x, p %x), " 3134 "resid %lx, msg(q %x,o %x) %s>", 3135 ecb, ecb->flags, ecb->dleft, ecb->stat, 3136 sc->sc_state, sc->sc_nexus, 3137 NCR_READ_REG(sc, NCR_STAT), 3138 sc->sc_phase, sc->sc_prevphase, 3139 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 3140 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 3141#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 3142 printf("TRACE: %s.", ecb->trace); 3143#endif 3144 |
3145 if (ecb->flags & ECB_ABORT) { 3146 /* Abort timed out. */ 3147 printf(" AGAIN\n"); 3148 ncr53c9x_init(sc, 1); 3149 } else { 3150 /* Abort the operation that has timed out. */ 3151 printf("\n"); 3152 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 3153 ncr53c9x_abort(sc, ecb); 3154 3155 /* Disable sync mode if stuck in a data phase. */ 3156 if (ecb == sc->sc_nexus && |
3157 ti->curr.offset != 0 && 3158 (sc->sc_phase & (MSGI | CDI)) == 0) { |
3159 /* XXX ASYNC CALLBACK! */ |
3160 ti->goal.offset = 0; |
3161 xpt_print_path(ccb->ccb_h.path); 3162 printf("sync negotiation disabled\n"); |
3163 } 3164 } |
3165} 3166 3167static void 3168ncr53c9x_watch(void *arg) 3169{ 3170 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 3171 struct ncr53c9x_linfo *li; 3172 struct ncr53c9x_tinfo *ti; 3173 time_t old; 3174 int t; 3175 |
3176 NCR_LOCK_ASSERT(sc, MA_OWNED); 3177 |
3178 /* Delete any structures that have not been used in 10min. */ 3179 old = time_second - (10 * 60); 3180 |
3181 for (t = 0; t < sc->sc_ntarg; t++) { 3182 ti = &sc->sc_tinfo[t]; 3183 li = LIST_FIRST(&ti->luns); 3184 while (li) { 3185 if (li->last_used < old && 3186 li->untagged == NULL && 3187 li->used == 0) { 3188 if (li->lun < NCR_NLUN) 3189 ti->lun[li->lun] = NULL; 3190 LIST_REMOVE(li, link); 3191 free(li, M_DEVBUF); 3192 /* Restart the search at the beginning. */ 3193 li = LIST_FIRST(&ti->luns); 3194 continue; 3195 } 3196 li = LIST_NEXT(li, link); 3197 } 3198 } |
3199 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc); 3200} |