1/*- 2 * Copyright (c) 2004 Scott Long
| 1/*- 2 * Copyright (c) 2004 Scott Long
|
| 3 * Copyright (c) 2005, 2008 Marius Strobl <marius@FreeBSD.org>
|
3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27
| 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28
|
28/* $NetBSD: ncr53c9x.c,v 1.114 2005/02/27 00:27:02 perry Exp $ */
| 29/* $NetBSD: ncr53c9x.c,v 1.125 2007/01/09 12:53:12 itohy Exp $ */
|
29 30/*- 31 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc. 32 * All rights reserved. 33 * 34 * This code is derived from software contributed to The NetBSD Foundation 35 * by Charles M. Hannum. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by the NetBSD 48 * Foundation, Inc. and its contributors. 49 * 4. Neither the name of The NetBSD Foundation nor the names of its 50 * contributors may be used to endorse or promote products derived 51 * from this software without specific prior written permission. 52 * 53 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 55 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 56 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 57 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 58 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 59 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 60 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 61 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 62 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 63 * POSSIBILITY OF SUCH DAMAGE. 64 */ 65 66/*- 67 * Copyright (c) 1994 Peter Galbavy 68 * Copyright (c) 1995 Paul Kranenburg 69 * All rights reserved. 70 * 71 * Redistribution and use in source and binary forms, with or without 72 * modification, are permitted provided that the following conditions 73 * are met: 74 * 1. Redistributions of source code must retain the above copyright 75 * notice, this list of conditions and the following disclaimer. 76 * 2. Redistributions in binary form must reproduce the above copyright 77 * notice, this list of conditions and the following disclaimer in the 78 * documentation and/or other materials provided with the distribution. 79 * 3. All advertising materials mentioning features or use of this software 80 * must display the following acknowledgement: 81 * This product includes software developed by Peter Galbavy 82 * 4. The name of the author may not be used to endorse or promote products 83 * derived from this software without specific prior written permission. 84 * 85 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 86 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 87 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 88 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 89 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 90 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 92 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 93 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 94 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 95 * POSSIBILITY OF SUCH DAMAGE. 96 */ 97 98/* 99 * Based on aic6360 by Jarle Greipsland 100 * 101 * Acknowledgements: Many of the algorithms used in this driver are 102 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and 103 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 104 */ 105 106#include <sys/cdefs.h>
| 30 31/*- 32 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc. 33 * All rights reserved. 34 * 35 * This code is derived from software contributed to The NetBSD Foundation 36 * by Charles M. Hannum. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 3. All advertising materials mentioning features or use of this software 47 * must display the following acknowledgement: 48 * This product includes software developed by the NetBSD 49 * Foundation, Inc. and its contributors. 50 * 4. Neither the name of The NetBSD Foundation nor the names of its 51 * contributors may be used to endorse or promote products derived 52 * from this software without specific prior written permission. 53 * 54 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 55 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 56 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 57 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 58 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 59 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 60 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 61 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 62 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 63 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 64 * POSSIBILITY OF SUCH DAMAGE. 65 */ 66 67/*- 68 * Copyright (c) 1994 Peter Galbavy 69 * Copyright (c) 1995 Paul Kranenburg 70 * All rights reserved. 71 * 72 * Redistribution and use in source and binary forms, with or without 73 * modification, are permitted provided that the following conditions 74 * are met: 75 * 1. Redistributions of source code must retain the above copyright 76 * notice, this list of conditions and the following disclaimer. 77 * 2. Redistributions in binary form must reproduce the above copyright 78 * notice, this list of conditions and the following disclaimer in the 79 * documentation and/or other materials provided with the distribution. 80 * 3. All advertising materials mentioning features or use of this software 81 * must display the following acknowledgement: 82 * This product includes software developed by Peter Galbavy 83 * 4. The name of the author may not be used to endorse or promote products 84 * derived from this software without specific prior written permission. 85 * 86 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 87 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 88 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 89 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 90 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 91 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 93 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 94 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 95 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 96 * POSSIBILITY OF SUCH DAMAGE. 97 */ 98 99/* 100 * Based on aic6360 by Jarle Greipsland 101 * 102 * Acknowledgements: Many of the algorithms used in this driver are 103 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and 104 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million! 105 */ 106 107#include <sys/cdefs.h>
|
107__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 180692 2008-07-22 13:51:21Z marius $");
| 108__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 182876 2008-09-08 20:20:44Z marius $");
|
108 109#include <sys/param.h> 110#include <sys/systm.h> 111#include <sys/bus.h> 112#include <sys/kernel.h> 113#include <sys/malloc.h>
| 109 110#include <sys/param.h> 111#include <sys/systm.h> 112#include <sys/bus.h> 113#include <sys/kernel.h> 114#include <sys/malloc.h>
|
114#include <sys/resource.h>
| |
115#include <sys/lock.h>
| 115#include <sys/lock.h>
|
| 116#include <sys/module.h>
|
116#include <sys/mutex.h> 117#include <sys/queue.h> 118#include <sys/time.h> 119#include <sys/callout.h> 120 121#include <cam/cam.h> 122#include <cam/cam_ccb.h> 123#include <cam/cam_debug.h> 124#include <cam/cam_sim.h> 125#include <cam/cam_xpt_sim.h> 126#include <cam/scsi/scsi_all.h> 127#include <cam/scsi/scsi_message.h> 128 129#include <dev/esp/ncr53c9xreg.h> 130#include <dev/esp/ncr53c9xvar.h> 131
| 117#include <sys/mutex.h> 118#include <sys/queue.h> 119#include <sys/time.h> 120#include <sys/callout.h> 121 122#include <cam/cam.h> 123#include <cam/cam_ccb.h> 124#include <cam/cam_debug.h> 125#include <cam/cam_sim.h> 126#include <cam/cam_xpt_sim.h> 127#include <cam/scsi/scsi_all.h> 128#include <cam/scsi/scsi_message.h> 129 130#include <dev/esp/ncr53c9xreg.h> 131#include <dev/esp/ncr53c9xvar.h> 132
|
132int ncr53c9x_debug =
| 133MODULE_DEPEND(esp, cam, 1, 1, 1); 134 135#ifdef NCR53C9X_DEBUG 136static int ncr53c9x_debug =
|
133 NCR_SHOWMISC /* | NCR_SHOWPHASE | NCR_SHOWTRAC | NCR_SHOWCMDS */;
| 137 NCR_SHOWMISC /* | NCR_SHOWPHASE | NCR_SHOWTRAC | NCR_SHOWCMDS */;
|
134#ifdef DEBUG 135int ncr53c9x_notag = 0;
| |
136#endif 137 138static void ncr53c9x_abort(struct ncr53c9x_softc *sc, 139 struct ncr53c9x_ecb *ecb);
| 138#endif 139 140static void ncr53c9x_abort(struct ncr53c9x_softc *sc, 141 struct ncr53c9x_ecb *ecb);
|
| 142static void ncr53c9x_action(struct cam_sim *sim, union ccb *ccb); 143static void ncr53c9x_async(void *cbarg, uint32_t code, 144 struct cam_path *path, void *arg); 145static void ncr53c9x_callout(void *arg); 146static void ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result); 147static void ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target, 148 cam_status result);
|
140static void ncr53c9x_dequeue(struct ncr53c9x_softc *sc, 141 struct ncr53c9x_ecb *ecb); 142static void ncr53c9x_done(struct ncr53c9x_softc *sc, 143 struct ncr53c9x_ecb *ecb); 144static void ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, 145 struct ncr53c9x_ecb *ecb); 146static void ncr53c9x_msgin(struct ncr53c9x_softc *sc); 147static void ncr53c9x_msgout(struct ncr53c9x_softc *sc);
| 149static void ncr53c9x_dequeue(struct ncr53c9x_softc *sc, 150 struct ncr53c9x_ecb *ecb); 151static void ncr53c9x_done(struct ncr53c9x_softc *sc, 152 struct ncr53c9x_ecb *ecb); 153static void ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, 154 struct ncr53c9x_ecb *ecb); 155static void ncr53c9x_msgin(struct ncr53c9x_softc *sc); 156static void ncr53c9x_msgout(struct ncr53c9x_softc *sc);
|
| 157static void ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset); 158static void ncr53c9x_intr1(struct ncr53c9x_softc *sc);
|
148static void ncr53c9x_poll(struct cam_sim *sim); 149static int ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how); 150static int ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, 151 int tagtype, int tagid);
| 159static void ncr53c9x_poll(struct cam_sim *sim); 160static int ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how); 161static int ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, 162 int tagtype, int tagid);
|
| 163static void ncr53c9x_reset(struct ncr53c9x_softc *sc);
|
152static void ncr53c9x_sense(struct ncr53c9x_softc *sc, 153 struct ncr53c9x_ecb *ecb);
| 164static void ncr53c9x_sense(struct ncr53c9x_softc *sc, 165 struct ncr53c9x_ecb *ecb);
|
154static void ncr53c9x_scsi_reset(struct ncr53c9x_softc *sc);
| |
155static void ncr53c9x_sched(struct ncr53c9x_softc *sc); 156static void ncr53c9x_select(struct ncr53c9x_softc *sc, 157 struct ncr53c9x_ecb *ecb);
| 166static void ncr53c9x_sched(struct ncr53c9x_softc *sc); 167static void ncr53c9x_select(struct ncr53c9x_softc *sc, 168 struct ncr53c9x_ecb *ecb);
|
158static void ncr53c9x_timeout(void *arg);
| |
159static void ncr53c9x_watch(void *arg); 160static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, 161 int len); 162 163static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *sc); 164static struct ncr53c9x_linfo *ncr53c9x_lunsearch(struct ncr53c9x_tinfo *sc, 165 int64_t lun); 166 167static inline void ncr53c9x_readregs(struct ncr53c9x_softc *sc); 168static inline void ncr53c9x_setsync(struct ncr53c9x_softc *sc, 169 struct ncr53c9x_tinfo *ti); 170static inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, 171 int period); 172 173#define NCR_RDFIFO_START 0 174#define NCR_RDFIFO_CONTINUE 1 175 176#define NCR_SET_COUNT(sc, size) do { \ 177 NCR_WRITE_REG((sc), NCR_TCL, (size)); \ 178 NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \ 179 if ((sc->sc_cfg2 & NCRCFG2_FE) || \ 180 (sc->sc_rev == NCR_VARIANT_FAS366)) { \ 181 NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \ 182 } \ 183 if (sc->sc_rev == NCR_VARIANT_FAS366) { \ 184 NCR_WRITE_REG(sc, NCR_RCH, 0); \ 185 } \ 186} while (0) 187 188#ifndef mstohz 189#define mstohz(ms) \ 190 (((ms) < 0x20000) ? \ 191 ((ms +0u) / 1000u) * hz : \ 192 ((ms +0u) * hz) /1000u) 193#endif 194 195/* 196 * Names for the NCR53c9x variants, corresponding to the variant tags 197 * in ncr53c9xvar.h. 198 */ 199static const char *ncr53c9x_variant_names[] = { 200 "ESP100", 201 "ESP100A", 202 "ESP200", 203 "NCR53C94", 204 "NCR53C96", 205 "ESP406", 206 "FAS408", 207 "FAS216", 208 "AM53C974", 209 "FAS366/HME", 210 "NCR53C90 (86C01)", 211 "FAS100A", 212 "FAS236", 213}; 214 215/* 216 * Search linked list for LUN info by LUN id. 217 */ 218static struct ncr53c9x_linfo * 219ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun) 220{ 221 struct ncr53c9x_linfo *li; 222 223 LIST_FOREACH(li, &ti->luns, link) 224 if (li->lun == lun) 225 return (li); 226 return (NULL); 227} 228 229/* 230 * Attach this instance, and then all the sub-devices. 231 */ 232int 233ncr53c9x_attach(struct ncr53c9x_softc *sc) 234{ 235 struct cam_devq *devq; 236 struct cam_sim *sim; 237 struct cam_path *path; 238 struct ncr53c9x_ecb *ecb; 239 int error, i; 240
| 169static void ncr53c9x_watch(void *arg); 170static void ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, 171 int len); 172 173static struct ncr53c9x_ecb *ncr53c9x_get_ecb(struct ncr53c9x_softc *sc); 174static struct ncr53c9x_linfo *ncr53c9x_lunsearch(struct ncr53c9x_tinfo *sc, 175 int64_t lun); 176 177static inline void ncr53c9x_readregs(struct ncr53c9x_softc *sc); 178static inline void ncr53c9x_setsync(struct ncr53c9x_softc *sc, 179 struct ncr53c9x_tinfo *ti); 180static inline int ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, 181 int period); 182 183#define NCR_RDFIFO_START 0 184#define NCR_RDFIFO_CONTINUE 1 185 186#define NCR_SET_COUNT(sc, size) do { \ 187 NCR_WRITE_REG((sc), NCR_TCL, (size)); \ 188 NCR_WRITE_REG((sc), NCR_TCM, (size) >> 8); \ 189 if ((sc->sc_cfg2 & NCRCFG2_FE) || \ 190 (sc->sc_rev == NCR_VARIANT_FAS366)) { \ 191 NCR_WRITE_REG((sc), NCR_TCH, (size) >> 16); \ 192 } \ 193 if (sc->sc_rev == NCR_VARIANT_FAS366) { \ 194 NCR_WRITE_REG(sc, NCR_RCH, 0); \ 195 } \ 196} while (0) 197 198#ifndef mstohz 199#define mstohz(ms) \ 200 (((ms) < 0x20000) ? \ 201 ((ms +0u) / 1000u) * hz : \ 202 ((ms +0u) * hz) /1000u) 203#endif 204 205/* 206 * Names for the NCR53c9x variants, corresponding to the variant tags 207 * in ncr53c9xvar.h. 208 */ 209static const char *ncr53c9x_variant_names[] = { 210 "ESP100", 211 "ESP100A", 212 "ESP200", 213 "NCR53C94", 214 "NCR53C96", 215 "ESP406", 216 "FAS408", 217 "FAS216", 218 "AM53C974", 219 "FAS366/HME", 220 "NCR53C90 (86C01)", 221 "FAS100A", 222 "FAS236", 223}; 224 225/* 226 * Search linked list for LUN info by LUN id. 227 */ 228static struct ncr53c9x_linfo * 229ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun) 230{ 231 struct ncr53c9x_linfo *li; 232 233 LIST_FOREACH(li, &ti->luns, link) 234 if (li->lun == lun) 235 return (li); 236 return (NULL); 237} 238 239/* 240 * Attach this instance, and then all the sub-devices. 241 */ 242int 243ncr53c9x_attach(struct ncr53c9x_softc *sc) 244{ 245 struct cam_devq *devq; 246 struct cam_sim *sim; 247 struct cam_path *path; 248 struct ncr53c9x_ecb *ecb; 249 int error, i; 250
|
241 mtx_init(&sc->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
| 251 if (NCR_LOCK_INITIALIZED(sc) == 0) { 252 device_printf(sc->sc_dev, "mutex not initialized\n"); 253 return (ENXIO); 254 }
|
242
| 255
|
| 256 callout_init_mtx(&sc->sc_watchdog, &sc->sc_lock, 0); 257
|
243 /* 244 * Note, the front-end has set us up to print the chip variation. 245 */ 246 if (sc->sc_rev >= NCR_VARIANT_MAX) { 247 device_printf(sc->sc_dev, "unknown variant %d, devices not " 248 "attached\n", sc->sc_rev); 249 return (EINVAL); 250 } 251 252 device_printf(sc->sc_dev, "%s, %dMHz, SCSI ID %d\n", 253 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 254 255 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8; 256 257 /* 258 * Allocate SCSI message buffers. 259 * Front-ends can override allocation to avoid alignment 260 * handling in the DMA engines. Note that ncr53c9x_msgout() 261 * can request a 1 byte DMA transfer. 262 */ 263 if (sc->sc_omess == NULL) { 264 sc->sc_omess_self = 1; 265 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 266 if (sc->sc_omess == NULL) { 267 device_printf(sc->sc_dev, 268 "cannot allocate MSGOUT buffer\n"); 269 return (ENOMEM); 270 } 271 } else 272 sc->sc_omess_self = 0; 273 274 if (sc->sc_imess == NULL) { 275 sc->sc_imess_self = 1; 276 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT); 277 if (sc->sc_imess == NULL) { 278 device_printf(sc->sc_dev, 279 "cannot allocate MSGIN buffer\n"); 280 error = ENOMEM; 281 goto fail_omess; 282 } 283 } else 284 sc->sc_imess_self = 0; 285 286 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]), 287 M_DEVBUF, M_NOWAIT | M_ZERO); 288 if (sc->sc_tinfo == NULL) { 289 device_printf(sc->sc_dev, 290 "cannot allocate target info buffer\n"); 291 error = ENOMEM; 292 goto fail_imess; 293 } 294
| 258 /* 259 * Note, the front-end has set us up to print the chip variation. 260 */ 261 if (sc->sc_rev >= NCR_VARIANT_MAX) { 262 device_printf(sc->sc_dev, "unknown variant %d, devices not " 263 "attached\n", sc->sc_rev); 264 return (EINVAL); 265 } 266 267 device_printf(sc->sc_dev, "%s, %dMHz, SCSI ID %d\n", 268 ncr53c9x_variant_names[sc->sc_rev], sc->sc_freq, sc->sc_id); 269 270 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8; 271 272 /* 273 * Allocate SCSI message buffers. 274 * Front-ends can override allocation to avoid alignment 275 * handling in the DMA engines. Note that ncr53c9x_msgout() 276 * can request a 1 byte DMA transfer. 277 */ 278 if (sc->sc_omess == NULL) { 279 sc->sc_omess_self = 1; 280 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT); 281 if (sc->sc_omess == NULL) { 282 device_printf(sc->sc_dev, 283 "cannot allocate MSGOUT buffer\n"); 284 return (ENOMEM); 285 } 286 } else 287 sc->sc_omess_self = 0; 288 289 if (sc->sc_imess == NULL) { 290 sc->sc_imess_self = 1; 291 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT); 292 if (sc->sc_imess == NULL) { 293 device_printf(sc->sc_dev, 294 "cannot allocate MSGIN buffer\n"); 295 error = ENOMEM; 296 goto fail_omess; 297 } 298 } else 299 sc->sc_imess_self = 0; 300 301 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]), 302 M_DEVBUF, M_NOWAIT | M_ZERO); 303 if (sc->sc_tinfo == NULL) { 304 device_printf(sc->sc_dev, 305 "cannot allocate target info buffer\n"); 306 error = ENOMEM; 307 goto fail_imess; 308 } 309
|
295 callout_init(&sc->sc_watchdog, 0); 296
| |
297 /* 298 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100 299 * from now on. 300 */ 301 if (sc->sc_rev == NCR_VARIANT_NCR53C90_86C01) 302 sc->sc_rev = NCR_VARIANT_ESP100; 303 304 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 305 306 /* The value *must not* be == 1. Make it 2. */ 307 if (sc->sc_ccf == 1) 308 sc->sc_ccf = 2; 309 310 /* 311 * The recommended timeout is 250ms. This register is loaded 312 * with a value calculated as follows, from the docs: 313 * 314 * (timout period) x (CLK frequency) 315 * reg = ------------------------------------- 316 * 8192 x (Clock Conversion Factor) 317 * 318 * Since CCF has a linear relation to CLK, this generally computes 319 * to the constant of 153. 320 */ 321 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 322 323 /* The CCF register only has 3 bits; 0 is actually 8. */ 324 sc->sc_ccf &= 7; 325 326 /* 327 * Register with CAM. 328 */ 329 devq = cam_simq_alloc(sc->sc_ntarg); 330 if (devq == NULL) { 331 device_printf(sc->sc_dev, "cannot allocate device queue\n"); 332 error = ENOMEM; 333 goto fail_tinfo; 334 } 335 336 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc,
| 310 /* 311 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100 312 * from now on. 313 */ 314 if (sc->sc_rev == NCR_VARIANT_NCR53C90_86C01) 315 sc->sc_rev = NCR_VARIANT_ESP100; 316 317 sc->sc_ccf = FREQTOCCF(sc->sc_freq); 318 319 /* The value *must not* be == 1. Make it 2. */ 320 if (sc->sc_ccf == 1) 321 sc->sc_ccf = 2; 322 323 /* 324 * The recommended timeout is 250ms. This register is loaded 325 * with a value calculated as follows, from the docs: 326 * 327 * (timout period) x (CLK frequency) 328 * reg = ------------------------------------- 329 * 8192 x (Clock Conversion Factor) 330 * 331 * Since CCF has a linear relation to CLK, this generally computes 332 * to the constant of 153. 333 */ 334 sc->sc_timeout = ((250 * 1000) * sc->sc_freq) / (8192 * sc->sc_ccf); 335 336 /* The CCF register only has 3 bits; 0 is actually 8. */ 337 sc->sc_ccf &= 7; 338 339 /* 340 * Register with CAM. 341 */ 342 devq = cam_simq_alloc(sc->sc_ntarg); 343 if (devq == NULL) { 344 device_printf(sc->sc_dev, "cannot allocate device queue\n"); 345 error = ENOMEM; 346 goto fail_tinfo; 347 } 348 349 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc,
|
337 device_get_unit(sc->sc_dev), &Giant, 1, NCR_TAG_DEPTH, devq);
| 350 device_get_unit(sc->sc_dev), &sc->sc_lock, 1, NCR_TAG_DEPTH, devq);
|
338 if (sim == NULL) { 339 device_printf(sc->sc_dev, "cannot allocate SIM entry\n"); 340 error = ENOMEM; 341 goto fail_devq; 342 }
| 351 if (sim == NULL) { 352 device_printf(sc->sc_dev, "cannot allocate SIM entry\n"); 353 error = ENOMEM; 354 goto fail_devq; 355 }
|
| 356 357 NCR_LOCK(sc); 358
|
343 if (xpt_bus_register(sim, sc->sc_dev, 0) != CAM_SUCCESS) { 344 device_printf(sc->sc_dev, "cannot register bus\n"); 345 error = EIO;
| 359 if (xpt_bus_register(sim, sc->sc_dev, 0) != CAM_SUCCESS) { 360 device_printf(sc->sc_dev, "cannot register bus\n"); 361 error = EIO;
|
346 goto fail_sim;
| 362 goto fail_lock;
|
347 } 348 349 if (xpt_create_path(&path, NULL, cam_sim_path(sim), 350 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 351 device_printf(sc->sc_dev, "cannot create path\n"); 352 error = EIO; 353 goto fail_bus; 354 } 355
| 363 } 364 365 if (xpt_create_path(&path, NULL, cam_sim_path(sim), 366 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 367 device_printf(sc->sc_dev, "cannot create path\n"); 368 error = EIO; 369 goto fail_bus; 370 } 371
|
| 372 if (xpt_register_async(AC_LOST_DEVICE, ncr53c9x_async, sim, path) != 373 CAM_REQ_CMP) { 374 device_printf(sc->sc_dev, "cannot register async handler\n"); 375 error = EIO; 376 goto fail_path; 377 } 378
|
356 sc->sc_sim = sim; 357 sc->sc_path = path; 358 359 /* Reset state and bus. */ 360#if 0 361 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 362#else 363 sc->sc_cfflags = 0; 364#endif 365 sc->sc_state = 0; 366 ncr53c9x_init(sc, 1); 367 368 TAILQ_INIT(&sc->free_list); 369 if ((sc->ecb_array = 370 malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH, M_DEVBUF, 371 M_NOWAIT | M_ZERO)) == NULL) { 372 device_printf(sc->sc_dev, "cannot allocate ECB array\n"); 373 error = ENOMEM;
| 379 sc->sc_sim = sim; 380 sc->sc_path = path; 381 382 /* Reset state and bus. */ 383#if 0 384 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags; 385#else 386 sc->sc_cfflags = 0; 387#endif 388 sc->sc_state = 0; 389 ncr53c9x_init(sc, 1); 390 391 TAILQ_INIT(&sc->free_list); 392 if ((sc->ecb_array = 393 malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH, M_DEVBUF, 394 M_NOWAIT | M_ZERO)) == NULL) { 395 device_printf(sc->sc_dev, "cannot allocate ECB array\n"); 396 error = ENOMEM;
|
374 goto fail_path;
| 397 goto fail_async;
|
375 } 376 for (i = 0; i < NCR_TAG_DEPTH; i++) { 377 ecb = &sc->ecb_array[i]; 378 ecb->sc = sc; 379 ecb->tag_id = i; 380 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links); 381 } 382
| 398 } 399 for (i = 0; i < NCR_TAG_DEPTH; i++) { 400 ecb = &sc->ecb_array[i]; 401 ecb->sc = sc; 402 ecb->tag_id = i; 403 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links); 404 } 405
|
383 callout_reset(&sc->sc_watchdog, 60*hz, ncr53c9x_watch, sc);
| 406 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc);
|
384
| 407
|
| 408 NCR_UNLOCK(sc); 409
|
385 return (0); 386
| 410 return (0); 411
|
| 412fail_async: 413 xpt_register_async(0, ncr53c9x_async, sim, path);
|
387fail_path: 388 xpt_free_path(path); 389fail_bus: 390 xpt_bus_deregister(cam_sim_path(sim));
| 414fail_path: 415 xpt_free_path(path); 416fail_bus: 417 xpt_bus_deregister(cam_sim_path(sim));
|
391fail_sim:
| 418fail_lock: 419 NCR_UNLOCK(sc);
|
392 cam_sim_free(sim, TRUE); 393fail_devq: 394 cam_simq_free(devq); 395fail_tinfo: 396 free(sc->sc_tinfo, M_DEVBUF); 397fail_imess: 398 if (sc->sc_imess_self) 399 free(sc->sc_imess, M_DEVBUF); 400fail_omess: 401 if (sc->sc_omess_self) 402 free(sc->sc_omess, M_DEVBUF); 403 return (error); 404} 405 406int 407ncr53c9x_detach(struct ncr53c9x_softc *sc) 408{
| 420 cam_sim_free(sim, TRUE); 421fail_devq: 422 cam_simq_free(devq); 423fail_tinfo: 424 free(sc->sc_tinfo, M_DEVBUF); 425fail_imess: 426 if (sc->sc_imess_self) 427 free(sc->sc_imess, M_DEVBUF); 428fail_omess: 429 if (sc->sc_omess_self) 430 free(sc->sc_omess, M_DEVBUF); 431 return (error); 432} 433 434int 435ncr53c9x_detach(struct ncr53c9x_softc *sc) 436{
|
| 437 struct ncr53c9x_linfo *li, *nextli; 438 int t;
|
409 410 callout_drain(&sc->sc_watchdog);
| 439 440 callout_drain(&sc->sc_watchdog);
|
411 mtx_lock(&sc->sc_lock); 412 ncr53c9x_init(sc, 1); 413 mtx_unlock(&sc->sc_lock);
| 441 442 NCR_LOCK(sc); 443 444 if (sc->sc_tinfo) { 445 /* Cancel all commands. */ 446 ncr53c9x_clear(sc, CAM_REQ_ABORTED); 447 448 /* Free logical units. */ 449 for (t = 0; t < sc->sc_ntarg; t++) { 450 for (li = LIST_FIRST(&sc->sc_tinfo[t].luns); li; 451 li = nextli) { 452 nextli = LIST_NEXT(li, link); 453 free(li, M_DEVBUF); 454 } 455 } 456 } 457 458 xpt_register_async(0, ncr53c9x_async, sc->sc_sim, sc->sc_path);
|
414 xpt_free_path(sc->sc_path); 415 xpt_bus_deregister(cam_sim_path(sc->sc_sim));
| 459 xpt_free_path(sc->sc_path); 460 xpt_bus_deregister(cam_sim_path(sc->sc_sim));
|
| 461 462 NCR_UNLOCK(sc); 463
|
416 cam_sim_free(sc->sc_sim, TRUE); 417 free(sc->ecb_array, M_DEVBUF); 418 free(sc->sc_tinfo, M_DEVBUF); 419 if (sc->sc_imess_self) 420 free(sc->sc_imess, M_DEVBUF); 421 if (sc->sc_omess_self) 422 free(sc->sc_omess, M_DEVBUF);
| 464 cam_sim_free(sc->sc_sim, TRUE); 465 free(sc->ecb_array, M_DEVBUF); 466 free(sc->sc_tinfo, M_DEVBUF); 467 if (sc->sc_imess_self) 468 free(sc->sc_imess, M_DEVBUF); 469 if (sc->sc_omess_self) 470 free(sc->sc_omess, M_DEVBUF);
|
423 mtx_destroy(&sc->sc_lock);
| |
424 425 return (0); 426} 427 428/* 429 * This is the generic ncr53c9x reset function. It does not reset the SCSI 430 * bus, only this controller, but kills any on-going commands, and also stops 431 * and resets the DMA. 432 * 433 * After reset, registers are loaded with the defaults from the attach 434 * routine above. 435 */
| 471 472 return (0); 473} 474 475/* 476 * This is the generic ncr53c9x reset function. It does not reset the SCSI 477 * bus, only this controller, but kills any on-going commands, and also stops 478 * and resets the DMA. 479 * 480 * After reset, registers are loaded with the defaults from the attach 481 * routine above. 482 */
|
436void
| 483static void
|
437ncr53c9x_reset(struct ncr53c9x_softc *sc) 438{ 439
| 484ncr53c9x_reset(struct ncr53c9x_softc *sc) 485{ 486
|
| 487 NCR_LOCK_ASSERT(sc, MA_OWNED); 488
|
440 /* Reset DMA first. */ 441 NCRDMA_RESET(sc); 442 443 /* Reset SCSI chip. */ 444 NCRCMD(sc, NCRCMD_RSTCHIP); 445 NCRCMD(sc, NCRCMD_NOP); 446 DELAY(500); 447 448 /* Do these backwards, and fall through. */ 449 switch (sc->sc_rev) { 450 case NCR_VARIANT_ESP406: 451 case NCR_VARIANT_FAS408: 452 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT); 453 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4); 454 /* FALLTHROUGH */ 455 case NCR_VARIANT_AM53C974: 456 case NCR_VARIANT_FAS100A: 457 case NCR_VARIANT_FAS216: 458 case NCR_VARIANT_FAS236: 459 case NCR_VARIANT_NCR53C94: 460 case NCR_VARIANT_NCR53C96: 461 case NCR_VARIANT_ESP200: 462 sc->sc_features |= NCR_F_HASCFG3; 463 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 464 /* FALLTHROUGH */ 465 case NCR_VARIANT_ESP100A: 466 sc->sc_features |= NCR_F_SELATN3; 467 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 468 /* FALLTHROUGH */ 469 case NCR_VARIANT_ESP100: 470 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 471 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 472 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 473 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 474 break; 475 476 case NCR_VARIANT_FAS366: 477 sc->sc_features |= 478 NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3; 479 sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO;
| 489 /* Reset DMA first. */ 490 NCRDMA_RESET(sc); 491 492 /* Reset SCSI chip. */ 493 NCRCMD(sc, NCRCMD_RSTCHIP); 494 NCRCMD(sc, NCRCMD_NOP); 495 DELAY(500); 496 497 /* Do these backwards, and fall through. */ 498 switch (sc->sc_rev) { 499 case NCR_VARIANT_ESP406: 500 case NCR_VARIANT_FAS408: 501 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT); 502 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4); 503 /* FALLTHROUGH */ 504 case NCR_VARIANT_AM53C974: 505 case NCR_VARIANT_FAS100A: 506 case NCR_VARIANT_FAS216: 507 case NCR_VARIANT_FAS236: 508 case NCR_VARIANT_NCR53C94: 509 case NCR_VARIANT_NCR53C96: 510 case NCR_VARIANT_ESP200: 511 sc->sc_features |= NCR_F_HASCFG3; 512 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3); 513 /* FALLTHROUGH */ 514 case NCR_VARIANT_ESP100A: 515 sc->sc_features |= NCR_F_SELATN3; 516 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 517 /* FALLTHROUGH */ 518 case NCR_VARIANT_ESP100: 519 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 520 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 521 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 522 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 523 break; 524 525 case NCR_VARIANT_FAS366: 526 sc->sc_features |= 527 NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3; 528 sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO;
|
| 529 if (sc->sc_id > 7) 530 sc->sc_cfg3 |= NCRFASCFG3_IDBIT3;
|
480 sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI; 481 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
| 531 sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI; 532 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
|
482 sc->sc_cfg2 = 0; /* NCRCFG2_HMEFE | NCRCFG2_HME32 */
| 533 sc->sc_cfg2 = NCRCFG2_HMEFE | NCRCFG2_HME32;
|
483 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 484 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 485 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 486 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 487 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 488 break; 489 490 default: 491 device_printf(sc->sc_dev, 492 "unknown revision code, assuming ESP100\n"); 493 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 494 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 495 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 496 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 497 } 498 499 if (sc->sc_rev == NCR_VARIANT_AM53C974) 500 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4); 501 502#if 0 503 device_printf(sc->sc_dev, "ncr53c9x_reset: revision %d\n", 504 sc->sc_rev); 505 device_printf(sc->sc_dev, "ncr53c9x_reset: cfg1 0x%x, cfg2 0x%x, " 506 "cfg3 0x%x, ccf 0x%x, timeout 0x%x\n", 507 sc->sc_cfg1, sc->sc_cfg2, sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout); 508#endif 509} 510 511/*
| 534 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2); 535 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 536 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 537 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 538 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 539 break; 540 541 default: 542 device_printf(sc->sc_dev, 543 "unknown revision code, assuming ESP100\n"); 544 NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1); 545 NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf); 546 NCR_WRITE_REG(sc, NCR_SYNCOFF, 0); 547 NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout); 548 } 549 550 if (sc->sc_rev == NCR_VARIANT_AM53C974) 551 NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4); 552 553#if 0 554 device_printf(sc->sc_dev, "ncr53c9x_reset: revision %d\n", 555 sc->sc_rev); 556 device_printf(sc->sc_dev, "ncr53c9x_reset: cfg1 0x%x, cfg2 0x%x, " 557 "cfg3 0x%x, ccf 0x%x, timeout 0x%x\n", 558 sc->sc_cfg1, sc->sc_cfg2, sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout); 559#endif 560} 561 562/*
|
512 * Reset the SCSI bus, but not the chip.
| 563 * Clear all commands.
|
513 */ 514static void
| 564 */ 565static void
|
515ncr53c9x_scsi_reset(struct ncr53c9x_softc *sc)
| 566ncr53c9x_clear(struct ncr53c9x_softc *sc, cam_status result)
|
516{
| 567{
|
| 568 struct ncr53c9x_ecb *ecb; 569 int r;
|
517
| 570
|
518 (*sc->sc_glue->gl_dma_stop)(sc);
| 571 NCR_LOCK_ASSERT(sc, MA_OWNED);
|
519
| 572
|
520 NCR_MISC(("%s: resetting SCSI bus\n", device_get_nameunit(sc->sc_dev))); 521 NCRCMD(sc, NCRCMD_RSTSCSI); 522 DELAY(250000); /* Give the bus a fighting chance to settle */
| 573 /* Cancel any active commands. */ 574 sc->sc_state = NCR_CLEANING; 575 sc->sc_msgify = 0; 576 if ((ecb = sc->sc_nexus) != NULL) { 577 ecb->ccb->ccb_h.status = result; 578 ncr53c9x_done(sc, ecb); 579 } 580 /* Cancel outstanding disconnected commands. */ 581 for (r = 0; r < sc->sc_ntarg; r++) 582 ncr53c9x_clear_target(sc, r, result);
|
523} 524 525/*
| 583} 584 585/*
|
526 * Initialize ncr53c9x state machine.
| 586 * Clear all commands for a specific target.
|
527 */
| 587 */
|
528void 529ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset)
| 588static void 589ncr53c9x_clear_target(struct ncr53c9x_softc *sc, int target, 590 cam_status result)
|
530{ 531 struct ncr53c9x_ecb *ecb; 532 struct ncr53c9x_linfo *li;
| 591{ 592 struct ncr53c9x_ecb *ecb; 593 struct ncr53c9x_linfo *li;
|
| 594 int i; 595 596 NCR_LOCK_ASSERT(sc, MA_OWNED); 597 598 /* Cancel outstanding disconnected commands on each LUN. */ 599 LIST_FOREACH(li, &sc->sc_tinfo[target].luns, link) { 600 if ((ecb = li->untagged) != NULL) { 601 li->untagged = NULL; 602 /* 603 * XXX should we terminate a command 604 * that never reached the disk? 605 */ 606 li->busy = 0; 607 ecb->ccb->ccb_h.status = result; 608 ncr53c9x_done(sc, ecb); 609 } 610 for (i = 0; i < NCR_TAG_DEPTH; i++) 611 if ((ecb = li->queued[i])) { 612 li->queued[i] = NULL; 613 ecb->ccb->ccb_h.status = result; 614 ncr53c9x_done(sc, ecb); 615 } 616 li->used = 0; 617 } 618} 619 620/* 621 * Initialize ncr53c9x state machine. 622 */ 623static void 624ncr53c9x_init(struct ncr53c9x_softc *sc, int doreset) 625{
|
533 struct ncr53c9x_tinfo *ti;
| 626 struct ncr53c9x_tinfo *ti;
|
534 int i, r;
| 627 int r;
|
535
| 628
|
| 629 NCR_LOCK_ASSERT(sc, MA_OWNED); 630
|
536 NCR_MISC(("[NCR_INIT(%d) %d] ", doreset, sc->sc_state)); 537 538 if (sc->sc_state == 0) { 539 /* First time through; initialize. */ 540 541 TAILQ_INIT(&sc->ready_list); 542 sc->sc_nexus = NULL; 543 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 544 for (r = 0; r < sc->sc_ntarg; r++) { 545 LIST_INIT(&sc->sc_tinfo[r].luns); 546 }
| 631 NCR_MISC(("[NCR_INIT(%d) %d] ", doreset, sc->sc_state)); 632 633 if (sc->sc_state == 0) { 634 /* First time through; initialize. */ 635 636 TAILQ_INIT(&sc->ready_list); 637 sc->sc_nexus = NULL; 638 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo)); 639 for (r = 0; r < sc->sc_ntarg; r++) { 640 LIST_INIT(&sc->sc_tinfo[r].luns); 641 }
|
547 } else { 548 /* Cancel any active commands. */ 549 sc->sc_state = NCR_CLEANING; 550 sc->sc_msgify = 0; 551 if ((ecb = sc->sc_nexus) != NULL) { 552 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT; 553 ncr53c9x_done(sc, ecb); 554 } 555 /* Cancel outstanding disconnected commands on each LUN. */ 556 for (r = 0; r < sc->sc_ntarg; r++) { 557 LIST_FOREACH(li, &sc->sc_tinfo[r].luns, link) { 558 if ((ecb = li->untagged) != NULL) { 559 li->untagged = NULL; 560 /* 561 * XXX 562 * 563 * Should we terminate a command 564 * that never reached the disk? 565 */ 566 li->busy = 0; 567 ecb->ccb->ccb_h.status = 568 CAM_CMD_TIMEOUT; 569 ncr53c9x_done(sc, ecb); 570 } 571 for (i = 0; i < 256; i++) 572 if ((ecb = li->queued[i])) { 573 li->queued[i] = NULL; 574 ecb->ccb->ccb_h.status = 575 CAM_CMD_TIMEOUT; 576 ncr53c9x_done(sc, ecb); 577 } 578 li->used = 0; 579 } 580 } 581 }
| 642 } else 643 ncr53c9x_clear(sc, CAM_CMD_TIMEOUT);
|
582 583 /* 584 * Reset the chip to a known state. 585 */ 586 ncr53c9x_reset(sc); 587 588 sc->sc_flags = 0; 589 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 590 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 591
| 644 645 /* 646 * Reset the chip to a known state. 647 */ 648 ncr53c9x_reset(sc); 649 650 sc->sc_flags = 0; 651 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 652 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE; 653
|
592 for (r = 0; r < sc->sc_ntarg; r++) { 593 ti = &sc->sc_tinfo[r];
| 654 /* 655 * If we're the first time through, set the default parameters 656 * for all targets. Otherwise we only clear their current transfer 657 * settings so we'll renegotiate their goal settings with the next 658 * command. 659 */ 660 if (sc->sc_state == 0) { 661 for (r = 0; r < sc->sc_ntarg; r++) { 662 ti = &sc->sc_tinfo[r];
|
594/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
| 663/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
|
595 ti->flags = ((sc->sc_minsync != 0 && 596 (sc->sc_cfflags & (1 << ((r & 7) + 8))) == 0) ? 597 0 : T_SYNCHOFF) | 598 ((sc->sc_cfflags & (1 << (r & 7))) == 0 ? 599 0 : T_RSELECTOFF);
| |
600
| 664
|
601#ifdef DEBUG 602 if (ncr53c9x_notag) 603 ti->flags &= ~T_TAG; 604#endif 605 ti->period = sc->sc_minsync; 606 ti->offset = 0; 607 ti->cfg3 = 0;
| 665 ti->flags = ((sc->sc_minsync != 0 && 666 (sc->sc_cfflags & (1 << ((r & 7) + 8))) == 0) ? 667 0 : T_SYNCHOFF) | 668 ((sc->sc_cfflags & (1 << (r & 7))) == 0 ? 669 0 : T_RSELECTOFF); 670 ti->curr.period = ti->goal.period = 0; 671 ti->curr.offset = ti->goal.offset = 0; 672 ti->curr.width = ti->goal.width = 673 MSG_EXT_WDTR_BUS_8_BIT; 674 } 675 } else { 676 for (r = 0; r < sc->sc_ntarg; r++) { 677 ti = &sc->sc_tinfo[r]; 678 ti->flags &= ~(T_SDTRSENT | T_WDTRSENT); 679 ti->curr.period = 0; 680 ti->curr.offset = 0; 681 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT; 682 }
|
608 } 609 610 if (doreset) { 611 sc->sc_state = NCR_SBR; 612 NCRCMD(sc, NCRCMD_RSTSCSI);
| 683 } 684 685 if (doreset) { 686 sc->sc_state = NCR_SBR; 687 NCRCMD(sc, NCRCMD_RSTSCSI);
|
| 688 /* Give the bus a fighting chance to settle. */ 689 DELAY(250000);
|
613 } else { 614 sc->sc_state = NCR_IDLE; 615 ncr53c9x_sched(sc); 616 } 617} 618 619/* 620 * Read the NCR registers, and save their contents for later use. 621 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 622 * NCR_INTR - so make sure it is the last read. 623 * 624 * I think that (from reading the docs) most bits in these registers 625 * only make sense when the DMA CSR has an interrupt showing. Call only 626 * if an interrupt is pending. 627 */ 628static inline void 629ncr53c9x_readregs(struct ncr53c9x_softc *sc) 630{ 631
| 690 } else { 691 sc->sc_state = NCR_IDLE; 692 ncr53c9x_sched(sc); 693 } 694} 695 696/* 697 * Read the NCR registers, and save their contents for later use. 698 * NCR_STAT, NCR_STEP & NCR_INTR are mostly zeroed out when reading 699 * NCR_INTR - so make sure it is the last read. 700 * 701 * I think that (from reading the docs) most bits in these registers 702 * only make sense when the DMA CSR has an interrupt showing. Call only 703 * if an interrupt is pending. 704 */ 705static inline void 706ncr53c9x_readregs(struct ncr53c9x_softc *sc) 707{ 708
|
| 709 NCR_LOCK_ASSERT(sc, MA_OWNED); 710
|
632 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 633 /* Only the step bits are of interest. */ 634 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 635 636 if (sc->sc_rev == NCR_VARIANT_FAS366) 637 sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2); 638 639 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 640 641 if (sc->sc_glue->gl_clear_latched_intr != NULL) 642 (*sc->sc_glue->gl_clear_latched_intr)(sc); 643 644 /* 645 * Determine the SCSI bus phase, return either a real SCSI bus phase 646 * or some pseudo phase we use to detect certain exceptions. 647 */ 648 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) ? 649 BUSFREE_PHASE : sc->sc_espstat & NCRSTAT_PHASE; 650 651 NCR_INTS(("regs[intr=%02x,stat=%02x,step=%02x,stat2=%02x] ", 652 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep, sc->sc_espstat2)); 653} 654 655/* 656 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 657 */ 658static inline int 659ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period) 660{ 661 int v;
| 711 sc->sc_espstat = NCR_READ_REG(sc, NCR_STAT); 712 /* Only the step bits are of interest. */ 713 sc->sc_espstep = NCR_READ_REG(sc, NCR_STEP) & NCRSTEP_MASK; 714 715 if (sc->sc_rev == NCR_VARIANT_FAS366) 716 sc->sc_espstat2 = NCR_READ_REG(sc, NCR_STAT2); 717 718 sc->sc_espintr = NCR_READ_REG(sc, NCR_INTR); 719 720 if (sc->sc_glue->gl_clear_latched_intr != NULL) 721 (*sc->sc_glue->gl_clear_latched_intr)(sc); 722 723 /* 724 * Determine the SCSI bus phase, return either a real SCSI bus phase 725 * or some pseudo phase we use to detect certain exceptions. 726 */ 727 sc->sc_phase = (sc->sc_espintr & NCRINTR_DIS) ? 728 BUSFREE_PHASE : sc->sc_espstat & NCRSTAT_PHASE; 729 730 NCR_INTS(("regs[intr=%02x,stat=%02x,step=%02x,stat2=%02x] ", 731 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep, sc->sc_espstat2)); 732} 733 734/* 735 * Convert Synchronous Transfer Period to chip register Clock Per Byte value. 736 */ 737static inline int 738ncr53c9x_stp2cpb(struct ncr53c9x_softc *sc, int period) 739{ 740 int v;
|
| 741 742 NCR_LOCK_ASSERT(sc, MA_OWNED); 743
|
662 v = (sc->sc_freq * period) / 250; 663 if (ncr53c9x_cpb2stp(sc, v) < period) 664 /* Correct round-down error. */ 665 v++; 666 return (v); 667} 668 669static inline void 670ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti) 671{
| 744 v = (sc->sc_freq * period) / 250; 745 if (ncr53c9x_cpb2stp(sc, v) < period) 746 /* Correct round-down error. */ 747 v++; 748 return (v); 749} 750 751static inline void 752ncr53c9x_setsync(struct ncr53c9x_softc *sc, struct ncr53c9x_tinfo *ti) 753{
|
672 u_char syncoff, synctp; 673 u_char cfg3 = sc->sc_cfg3 | ti->cfg3;
| 754 u_char cfg3, syncoff, synctp;
|
674
| 755
|
675 if (ti->flags & T_SYNCMODE) { 676 syncoff = ti->offset; 677 synctp = ncr53c9x_stp2cpb(sc, ti->period);
| 756 NCR_LOCK_ASSERT(sc, MA_OWNED); 757 758 cfg3 = sc->sc_cfg3; 759 if (ti->curr.offset != 0) { 760 syncoff = ti->curr.offset; 761 synctp = ncr53c9x_stp2cpb(sc, ti->curr.period);
|
678 if (sc->sc_features & NCR_F_FASTSCSI) { 679 /* 680 * If the period is 200ns or less (ti->period <= 50), 681 * put the chip in Fast SCSI mode. 682 */
| 762 if (sc->sc_features & NCR_F_FASTSCSI) { 763 /* 764 * If the period is 200ns or less (ti->period <= 50), 765 * put the chip in Fast SCSI mode. 766 */
|
683 if (ti->period <= 50)
| 767 if (ti->curr.period <= 50)
|
684 /* 685 * There are (at least) 4 variations of the 686 * configuration 3 register. The drive attach 687 * routine sets the appropriate bit to put the 688 * chip into Fast SCSI mode so that it doesn't 689 * have to be figured out here each time. 690 */ 691 cfg3 |= sc->sc_cfg3_fscsi; 692 } 693 694 /* 695 * Am53c974 requires different SYNCTP values when the 696 * FSCSI bit is off. 697 */ 698 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 699 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 700 synctp--; 701 } else { 702 syncoff = 0; 703 synctp = 0; 704 } 705
| 768 /* 769 * There are (at least) 4 variations of the 770 * configuration 3 register. The drive attach 771 * routine sets the appropriate bit to put the 772 * chip into Fast SCSI mode so that it doesn't 773 * have to be figured out here each time. 774 */ 775 cfg3 |= sc->sc_cfg3_fscsi; 776 } 777 778 /* 779 * Am53c974 requires different SYNCTP values when the 780 * FSCSI bit is off. 781 */ 782 if (sc->sc_rev == NCR_VARIANT_AM53C974 && 783 (cfg3 & NCRAMDCFG3_FSCSI) == 0) 784 synctp--; 785 } else { 786 syncoff = 0; 787 synctp = 0; 788 } 789
|
| 790 if (ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT) { 791 if (sc->sc_rev == NCR_VARIANT_FAS366) 792 cfg3 |= NCRFASCFG3_EWIDE; 793 } 794
|
706 if (sc->sc_features & NCR_F_HASCFG3) 707 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 708 709 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 710 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 711} 712 713/* 714 * Send a command to a target, set the driver state to NCR_SELECTING 715 * and let the caller take care of the rest. 716 * 717 * Keeping this as a function allows me to say that this may be done 718 * by DMA instead of programmed I/O soon. 719 */ 720static void 721ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 722{ 723 struct ncr53c9x_tinfo *ti; 724 u_char *cmd; 725 size_t dmasize; 726 int clen, selatn3, selatns; 727 int lun = ecb->ccb->ccb_h.target_lun; 728 int target = ecb->ccb->ccb_h.target_id; 729
| 795 if (sc->sc_features & NCR_F_HASCFG3) 796 NCR_WRITE_REG(sc, NCR_CFG3, cfg3); 797 798 NCR_WRITE_REG(sc, NCR_SYNCOFF, syncoff); 799 NCR_WRITE_REG(sc, NCR_SYNCTP, synctp); 800} 801 802/* 803 * Send a command to a target, set the driver state to NCR_SELECTING 804 * and let the caller take care of the rest. 805 * 806 * Keeping this as a function allows me to say that this may be done 807 * by DMA instead of programmed I/O soon. 808 */ 809static void 810ncr53c9x_select(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 811{ 812 struct ncr53c9x_tinfo *ti; 813 u_char *cmd; 814 size_t dmasize; 815 int clen, selatn3, selatns; 816 int lun = ecb->ccb->ccb_h.target_lun; 817 int target = ecb->ccb->ccb_h.target_id; 818
|
| 819 NCR_LOCK_ASSERT(sc, MA_OWNED); 820
|
730 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x,tag:%x,%x)] ", 731 target, lun, ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1])); 732 733 ti = &sc->sc_tinfo[target]; 734 sc->sc_state = NCR_SELECTING; 735 /*
| 821 NCR_TRACE(("[ncr53c9x_select(t%d,l%d,cmd:%x,tag:%x,%x)] ", 822 target, lun, ecb->cmd.cmd.opcode, ecb->tag[0], ecb->tag[1])); 823 824 ti = &sc->sc_tinfo[target]; 825 sc->sc_state = NCR_SELECTING; 826 /*
|
736 * Schedule the timeout now, the first time we will go away
| 827 * Schedule the callout now, the first time we will go away
|
737 * expecting to come back due to an interrupt, because it is 738 * always possible that the interrupt may never happen. 739 */
| 828 * expecting to come back due to an interrupt, because it is 829 * always possible that the interrupt may never happen. 830 */
|
740 ecb->ccb->ccb_h.timeout_ch = 741 timeout(ncr53c9x_timeout, ecb, mstohz(ecb->timeout));
| 831 callout_reset(&ecb->ch, mstohz(ecb->timeout), ncr53c9x_callout, ecb);
|
742 743 /* 744 * The docs say the target register is never reset, and I 745 * can't think of a better place to set it. 746 */ 747 if (sc->sc_rev == NCR_VARIANT_FAS366) { 748 NCRCMD(sc, NCRCMD_FLUSH);
| 832 833 /* 834 * The docs say the target register is never reset, and I 835 * can't think of a better place to set it. 836 */ 837 if (sc->sc_rev == NCR_VARIANT_FAS366) { 838 NCRCMD(sc, NCRCMD_FLUSH);
|
749 NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HME);
| 839 NCR_WRITE_REG(sc, NCR_SELID, target | NCR_BUSID_HMEXC32 | 840 NCR_BUSID_HMEENCID);
|
750 } else { 751 NCR_WRITE_REG(sc, NCR_SELID, target); 752 }
| 841 } else { 842 NCR_WRITE_REG(sc, NCR_SELID, target); 843 }
|
753 ncr53c9x_setsync(sc, ti);
| |
754
| 844
|
755 if ((ecb->flags & ECB_SENSE) != 0) { 756 /* 757 * For REQUEST SENSE, we should not send an IDENTIFY or 758 * otherwise mangle the target. There should be no MESSAGE IN 759 * phase. 760 */ 761 if (sc->sc_features & NCR_F_DMASELECT) { 762 /* setup DMA transfer for command */ 763 dmasize = clen = ecb->clen; 764 sc->sc_cmdlen = clen; 765 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 766 767 /* Program the SCSI counter */ 768 NCR_SET_COUNT(sc, dmasize); 769 770 if (sc->sc_rev != NCR_VARIANT_FAS366) 771 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 772 773 /* And get the target's attention */ 774 NCRCMD(sc, NCRCMD_SELNATN | NCRCMD_DMA); 775 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, 776 &dmasize); 777 NCRDMA_GO(sc); 778 } else { 779 ncr53c9x_wrfifo(sc, (u_char *)&ecb->cmd.cmd, ecb->clen); 780 NCRCMD(sc, NCRCMD_SELNATN); 781 } 782 return;
| 845 /* 846 * If we are requesting sense, force a renegotiation if we are 847 * currently using anything different from asynchronous at 8 bit 848 * as the target might have lost our transfer negotiations. 849 */ 850 if ((ecb->flags & ECB_SENSE) != 0 && (ti->curr.offset != 0 || 851 ti->curr.width != MSG_EXT_WDTR_BUS_8_BIT)) { 852 ti->curr.period = 0; 853 ti->curr.offset = 0; 854 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
|
783 }
| 855 }
|
| 856 ncr53c9x_setsync(sc, ti);
|
784 785 selatn3 = selatns = 0; 786 if (ecb->tag[0] != 0) { 787 if (sc->sc_features & NCR_F_SELATN3) 788 /* Use SELATN3 to send tag messages. */ 789 selatn3 = 1; 790 else 791 /* We don't have SELATN3; use SELATNS to send tags. */ 792 selatns = 1; 793 } 794
| 857 858 selatn3 = selatns = 0; 859 if (ecb->tag[0] != 0) { 860 if (sc->sc_features & NCR_F_SELATN3) 861 /* Use SELATN3 to send tag messages. */ 862 selatn3 = 1; 863 else 864 /* We don't have SELATN3; use SELATNS to send tags. */ 865 selatns = 1; 866 } 867
|
795 if (ti->flags & T_NEGOTIATE) {
| 868 if (ti->curr.period != ti->goal.period || 869 ti->curr.offset != ti->goal.offset || 870 ti->curr.width != ti->goal.width) {
|
796 /* We have to use SELATNS to send sync/wide messages. */ 797 selatn3 = 0; 798 selatns = 1; 799 } 800 801 cmd = (u_char *)&ecb->cmd.cmd; 802 803 if (selatn3) { 804 /* We'll use tags with SELATN3. */ 805 clen = ecb->clen + 3; 806 cmd -= 3; 807 cmd[0] = MSG_IDENTIFY(lun, 1); /* msg[0] */ 808 cmd[1] = ecb->tag[0]; /* msg[1] */ 809 cmd[2] = ecb->tag[1]; /* msg[2] */ 810 } else { 811 /* We don't have tags, or will send messages with SELATNS. */ 812 clen = ecb->clen + 1; 813 cmd -= 1; 814 cmd[0] = MSG_IDENTIFY(lun, (ti->flags & T_RSELECTOFF) == 0); 815 } 816 817 if ((sc->sc_features & NCR_F_DMASELECT) && !selatns) { 818 /* Setup DMA transfer for command. */ 819 dmasize = clen; 820 sc->sc_cmdlen = clen; 821 sc->sc_cmdp = cmd;
| 871 /* We have to use SELATNS to send sync/wide messages. */ 872 selatn3 = 0; 873 selatns = 1; 874 } 875 876 cmd = (u_char *)&ecb->cmd.cmd; 877 878 if (selatn3) { 879 /* We'll use tags with SELATN3. */ 880 clen = ecb->clen + 3; 881 cmd -= 3; 882 cmd[0] = MSG_IDENTIFY(lun, 1); /* msg[0] */ 883 cmd[1] = ecb->tag[0]; /* msg[1] */ 884 cmd[2] = ecb->tag[1]; /* msg[2] */ 885 } else { 886 /* We don't have tags, or will send messages with SELATNS. */ 887 clen = ecb->clen + 1; 888 cmd -= 1; 889 cmd[0] = MSG_IDENTIFY(lun, (ti->flags & T_RSELECTOFF) == 0); 890 } 891 892 if ((sc->sc_features & NCR_F_DMASELECT) && !selatns) { 893 /* Setup DMA transfer for command. */ 894 dmasize = clen; 895 sc->sc_cmdlen = clen; 896 sc->sc_cmdp = cmd;
|
822
| 897 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize);
|
823 /* Program the SCSI counter. */ 824 NCR_SET_COUNT(sc, dmasize); 825 826 /* Load the count in. */ 827 /* if (sc->sc_rev != NCR_VARIANT_FAS366) */ 828 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 829 830 /* And get the target's attention. */ 831 if (selatn3) { 832 sc->sc_msgout = SEND_TAG; 833 sc->sc_flags |= NCR_ATN; 834 NCRCMD(sc, NCRCMD_SELATN3 | NCRCMD_DMA); 835 } else 836 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA);
| 898 /* Program the SCSI counter. */ 899 NCR_SET_COUNT(sc, dmasize); 900 901 /* Load the count in. */ 902 /* if (sc->sc_rev != NCR_VARIANT_FAS366) */ 903 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 904 905 /* And get the target's attention. */ 906 if (selatn3) { 907 sc->sc_msgout = SEND_TAG; 908 sc->sc_flags |= NCR_ATN; 909 NCRCMD(sc, NCRCMD_SELATN3 | NCRCMD_DMA); 910 } else 911 NCRCMD(sc, NCRCMD_SELATN | NCRCMD_DMA);
|
837 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 0, &dmasize);
| |
838 NCRDMA_GO(sc); 839 return; 840 } 841 842 /* 843 * Who am I? This is where we tell the target that we are 844 * happy for it to disconnect etc. 845 */ 846 847 /* Now get the command into the FIFO. */ 848 ncr53c9x_wrfifo(sc, cmd, clen); 849 850 /* And get the target's attention. */ 851 if (selatns) { 852 NCR_MSGS(("SELATNS \n")); 853 /* Arbitrate, select and stop after IDENTIFY message. */ 854 NCRCMD(sc, NCRCMD_SELATNS); 855 } else if (selatn3) { 856 sc->sc_msgout = SEND_TAG; 857 sc->sc_flags |= NCR_ATN; 858 NCRCMD(sc, NCRCMD_SELATN3); 859 } else 860 NCRCMD(sc, NCRCMD_SELATN); 861} 862 863static void 864ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 865{ 866
| 912 NCRDMA_GO(sc); 913 return; 914 } 915 916 /* 917 * Who am I? This is where we tell the target that we are 918 * happy for it to disconnect etc. 919 */ 920 921 /* Now get the command into the FIFO. */ 922 ncr53c9x_wrfifo(sc, cmd, clen); 923 924 /* And get the target's attention. */ 925 if (selatns) { 926 NCR_MSGS(("SELATNS \n")); 927 /* Arbitrate, select and stop after IDENTIFY message. */ 928 NCRCMD(sc, NCRCMD_SELATNS); 929 } else if (selatn3) { 930 sc->sc_msgout = SEND_TAG; 931 sc->sc_flags |= NCR_ATN; 932 NCRCMD(sc, NCRCMD_SELATN3); 933 } else 934 NCRCMD(sc, NCRCMD_SELATN); 935} 936 937static void 938ncr53c9x_free_ecb(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 939{ 940
|
| 941 NCR_LOCK_ASSERT(sc, MA_OWNED); 942
|
867 ecb->flags = 0; 868 TAILQ_INSERT_TAIL(&sc->free_list, ecb, free_links); 869} 870 871static struct ncr53c9x_ecb * 872ncr53c9x_get_ecb(struct ncr53c9x_softc *sc) 873{ 874 struct ncr53c9x_ecb *ecb; 875
| 943 ecb->flags = 0; 944 TAILQ_INSERT_TAIL(&sc->free_list, ecb, free_links); 945} 946 947static struct ncr53c9x_ecb * 948ncr53c9x_get_ecb(struct ncr53c9x_softc *sc) 949{ 950 struct ncr53c9x_ecb *ecb; 951
|
| 952 NCR_LOCK_ASSERT(sc, MA_OWNED); 953
|
876 ecb = TAILQ_FIRST(&sc->free_list); 877 if (ecb) { 878 if (ecb->flags != 0) 879 panic("ecb flags not cleared\n"); 880 TAILQ_REMOVE(&sc->free_list, ecb, free_links); 881 ecb->flags = ECB_ALLOC; 882 bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) - 883 offsetof(struct ncr53c9x_ecb, ccb)); 884 } 885 return (ecb); 886} 887 888/* 889 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS: 890 */ 891 892/* 893 * Start a SCSI-command. 894 * This function is called by the higher level SCSI-driver to queue/run 895 * SCSI-commands. 896 */ 897
| 954 ecb = TAILQ_FIRST(&sc->free_list); 955 if (ecb) { 956 if (ecb->flags != 0) 957 panic("ecb flags not cleared\n"); 958 TAILQ_REMOVE(&sc->free_list, ecb, free_links); 959 ecb->flags = ECB_ALLOC; 960 bzero(&ecb->ccb, sizeof(struct ncr53c9x_ecb) - 961 offsetof(struct ncr53c9x_ecb, ccb)); 962 } 963 return (ecb); 964} 965 966/* 967 * DRIVER FUNCTIONS CALLABLE FROM HIGHER LEVEL DRIVERS: 968 */ 969 970/* 971 * Start a SCSI-command. 972 * This function is called by the higher level SCSI-driver to queue/run 973 * SCSI-commands. 974 */ 975
|
898void
| 976static void
|
899ncr53c9x_action(struct cam_sim *sim, union ccb *ccb) 900{ 901 struct ccb_pathinq *cpi; 902 struct ccb_scsiio *csio; 903 struct ccb_trans_settings *cts; 904 struct ccb_trans_settings_scsi *scsi; 905 struct ccb_trans_settings_spi *spi; 906 struct ncr53c9x_ecb *ecb; 907 struct ncr53c9x_softc *sc; 908 struct ncr53c9x_tinfo *ti; 909 int target; 910
| 977ncr53c9x_action(struct cam_sim *sim, union ccb *ccb) 978{ 979 struct ccb_pathinq *cpi; 980 struct ccb_scsiio *csio; 981 struct ccb_trans_settings *cts; 982 struct ccb_trans_settings_scsi *scsi; 983 struct ccb_trans_settings_spi *spi; 984 struct ncr53c9x_ecb *ecb; 985 struct ncr53c9x_softc *sc; 986 struct ncr53c9x_tinfo *ti; 987 int target; 988
|
911 NCR_TRACE(("[ncr53c9x_action %d]", ccb->ccb_h.func_code)); 912
| |
913 sc = cam_sim_softc(sim);
| 989 sc = cam_sim_softc(sim);
|
914 mtx_lock(&sc->sc_lock);
| |
915
| 990
|
| 991 NCR_LOCK_ASSERT(sc, MA_OWNED); 992 993 NCR_TRACE(("[ncr53c9x_action %d]", ccb->ccb_h.func_code)); 994
|
916 switch (ccb->ccb_h.func_code) { 917 case XPT_RESET_BUS:
| 995 switch (ccb->ccb_h.func_code) { 996 case XPT_RESET_BUS:
|
918 ncr53c9x_scsi_reset(sc);
| 997 ncr53c9x_init(sc, 1);
|
919 ccb->ccb_h.status = CAM_REQ_CMP;
| 998 ccb->ccb_h.status = CAM_REQ_CMP;
|
920 mtx_unlock(&sc->sc_lock);
| |
921 xpt_done(ccb); 922 return; 923 924 case XPT_CALC_GEOMETRY:
| 999 xpt_done(ccb); 1000 return; 1001 1002 case XPT_CALC_GEOMETRY:
|
925 mtx_unlock(&sc->sc_lock);
| |
926 cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom); 927 xpt_done(ccb); 928 return; 929 930 case XPT_PATH_INQ: 931 cpi = &ccb->cpi; 932 cpi->version_num = 1; 933 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 934 cpi->hba_inquiry |= 935 (sc->sc_rev == NCR_VARIANT_FAS366) ? PI_WIDE_16 : 0; 936 cpi->target_sprt = 0; 937 cpi->hba_misc = 0; 938 cpi->hba_eng_cnt = 0; 939 cpi->max_target = sc->sc_ntarg - 1;
| 1003 cam_calc_geometry(&ccb->ccg, sc->sc_extended_geom); 1004 xpt_done(ccb); 1005 return; 1006 1007 case XPT_PATH_INQ: 1008 cpi = &ccb->cpi; 1009 cpi->version_num = 1; 1010 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 1011 cpi->hba_inquiry |= 1012 (sc->sc_rev == NCR_VARIANT_FAS366) ? PI_WIDE_16 : 0; 1013 cpi->target_sprt = 0; 1014 cpi->hba_misc = 0; 1015 cpi->hba_eng_cnt = 0; 1016 cpi->max_target = sc->sc_ntarg - 1;
|
940 cpi->max_lun = 8;
| 1017 cpi->max_lun = 7;
|
941 cpi->initiator_id = sc->sc_id; 942 cpi->bus_id = 0; 943 cpi->base_transfer_speed = 3300; 944 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 945 strncpy(cpi->hba_vid, "Sun", HBA_IDLEN); 946 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 947 cpi->unit_number = cam_sim_unit(sim); 948 cpi->transport = XPORT_SPI; 949 cpi->transport_version = 2; 950 cpi->protocol = PROTO_SCSI; 951 cpi->protocol_version = SCSI_REV_2; 952 ccb->ccb_h.status = CAM_REQ_CMP;
| 1018 cpi->initiator_id = sc->sc_id; 1019 cpi->bus_id = 0; 1020 cpi->base_transfer_speed = 3300; 1021 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 1022 strncpy(cpi->hba_vid, "Sun", HBA_IDLEN); 1023 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 1024 cpi->unit_number = cam_sim_unit(sim); 1025 cpi->transport = XPORT_SPI; 1026 cpi->transport_version = 2; 1027 cpi->protocol = PROTO_SCSI; 1028 cpi->protocol_version = SCSI_REV_2; 1029 ccb->ccb_h.status = CAM_REQ_CMP;
|
953 mtx_unlock(&sc->sc_lock);
| |
954 xpt_done(ccb); 955 return; 956 957 case XPT_GET_TRAN_SETTINGS: 958 cts = &ccb->cts; 959 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 960 scsi = &cts->proto_specific.scsi; 961 spi = &cts->xport_specific.spi; 962 963 cts->protocol = PROTO_SCSI; 964 cts->protocol_version = SCSI_REV_2; 965 cts->transport = XPORT_SPI; 966 cts->transport_version = 2; 967 968 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
| 1030 xpt_done(ccb); 1031 return; 1032 1033 case XPT_GET_TRAN_SETTINGS: 1034 cts = &ccb->cts; 1035 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1036 scsi = &cts->proto_specific.scsi; 1037 spi = &cts->xport_specific.spi; 1038 1039 cts->protocol = PROTO_SCSI; 1040 cts->protocol_version = SCSI_REV_2; 1041 cts->transport = XPORT_SPI; 1042 cts->transport_version = 2; 1043 1044 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
|
969 spi->sync_period = ti->period; 970 spi->sync_offset = ti->offset; 971 spi->bus_width = ti->width;
| 1045 spi->sync_period = ti->curr.period; 1046 spi->sync_offset = ti->curr.offset; 1047 spi->bus_width = ti->curr.width;
|
972 if ((ti->flags & T_TAG) != 0) { 973 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 974 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 975 } else { 976 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 977 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 978 } 979 } else {
| 1048 if ((ti->flags & T_TAG) != 0) { 1049 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 1050 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 1051 } else { 1052 spi->flags &= ~CTS_SPI_FLAGS_DISC_ENB; 1053 scsi->flags &= ~CTS_SCSI_FLAGS_TAG_ENB; 1054 } 1055 } else {
|
980 spi->sync_period = sc->sc_maxsync; 981 spi->sync_offset = sc->sc_maxoffset;
| 1056 if ((ti->flags & T_SYNCHOFF) != 0) { 1057 spi->sync_period = 0; 1058 spi->sync_offset = 0; 1059 } else { 1060 spi->sync_period = sc->sc_minsync; 1061 spi->sync_offset = sc->sc_maxoffset; 1062 }
|
982 spi->bus_width = sc->sc_maxwidth; 983 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 984 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 985 } 986 spi->valid = 987 CTS_SPI_VALID_BUS_WIDTH | 988 CTS_SPI_VALID_SYNC_RATE | 989 CTS_SPI_VALID_SYNC_OFFSET | 990 CTS_SPI_VALID_DISC; 991 scsi->valid = CTS_SCSI_VALID_TQ; 992 ccb->ccb_h.status = CAM_REQ_CMP;
| 1063 spi->bus_width = sc->sc_maxwidth; 1064 spi->flags |= CTS_SPI_FLAGS_DISC_ENB; 1065 scsi->flags |= CTS_SCSI_FLAGS_TAG_ENB; 1066 } 1067 spi->valid = 1068 CTS_SPI_VALID_BUS_WIDTH | 1069 CTS_SPI_VALID_SYNC_RATE | 1070 CTS_SPI_VALID_SYNC_OFFSET | 1071 CTS_SPI_VALID_DISC; 1072 scsi->valid = CTS_SCSI_VALID_TQ; 1073 ccb->ccb_h.status = CAM_REQ_CMP;
|
993 mtx_unlock(&sc->sc_lock);
| |
994 xpt_done(ccb); 995 return; 996 997 case XPT_ABORT:
| 1074 xpt_done(ccb); 1075 return; 1076 1077 case XPT_ABORT:
|
998 printf("XPT_ABORT called\n");
| 1078 device_printf(sc->sc_dev, "XPT_ABORT called\n");
|
999 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
| 1079 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
|
1000 mtx_unlock(&sc->sc_lock);
| |
1001 xpt_done(ccb); 1002 return; 1003 1004 case XPT_TERM_IO:
| 1080 xpt_done(ccb); 1081 return; 1082 1083 case XPT_TERM_IO:
|
1005 printf("XPT_TERM_IO called\n");
| 1084 device_printf(sc->sc_dev, "XPT_TERM_IO called\n");
|
1006 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
| 1085 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
|
1007 mtx_unlock(&sc->sc_lock);
| |
1008 xpt_done(ccb); 1009 return; 1010 1011 case XPT_RESET_DEV:
| 1086 xpt_done(ccb); 1087 return; 1088 1089 case XPT_RESET_DEV:
|
1012 printf("XPT_RESET_DEV called\n");
| |
1013 case XPT_SCSI_IO: 1014 if (ccb->ccb_h.target_id < 0 || 1015 ccb->ccb_h.target_id >= sc->sc_ntarg) { 1016 ccb->ccb_h.status = CAM_PATH_INVALID;
| 1090 case XPT_SCSI_IO: 1091 if (ccb->ccb_h.target_id < 0 || 1092 ccb->ccb_h.target_id >= sc->sc_ntarg) { 1093 ccb->ccb_h.status = CAM_PATH_INVALID;
|
1017 mtx_unlock(&sc->sc_lock);
| |
1018 xpt_done(ccb); 1019 return; 1020 } 1021 /* Get an ECB to use. */ 1022 ecb = ncr53c9x_get_ecb(sc); 1023 /* 1024 * This should never happen as we track resources 1025 * in the mid-layer. 1026 */ 1027 if (ecb == NULL) { 1028 xpt_freeze_simq(sim, 1); 1029 ccb->ccb_h.status = CAM_REQUEUE_REQ;
| 1094 xpt_done(ccb); 1095 return; 1096 } 1097 /* Get an ECB to use. */ 1098 ecb = ncr53c9x_get_ecb(sc); 1099 /* 1100 * This should never happen as we track resources 1101 * in the mid-layer. 1102 */ 1103 if (ecb == NULL) { 1104 xpt_freeze_simq(sim, 1); 1105 ccb->ccb_h.status = CAM_REQUEUE_REQ;
|
1030 printf("unable to allocate ecb\n"); 1031 mtx_unlock(&sc->sc_lock);
| 1106 device_printf(sc->sc_dev, "unable to allocate ecb\n");
|
1032 xpt_done(ccb); 1033 return; 1034 } 1035 1036 /* Initialize ecb. */ 1037 ecb->ccb = ccb; 1038 ecb->timeout = ccb->ccb_h.timeout; 1039 1040 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 1041 ecb->flags |= ECB_RESET; 1042 ecb->clen = 0; 1043 ecb->dleft = 0; 1044 } else { 1045 csio = &ccb->csio; 1046 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 1047 bcopy(csio->cdb_io.cdb_ptr, &ecb->cmd.cmd, 1048 csio->cdb_len); 1049 else 1050 bcopy(csio->cdb_io.cdb_bytes, &ecb->cmd.cmd, 1051 csio->cdb_len); 1052 ecb->clen = csio->cdb_len; 1053 ecb->daddr = csio->data_ptr; 1054 ecb->dleft = csio->dxfer_len; 1055 } 1056 ecb->stat = 0; 1057 1058 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 1059 ecb->flags |= ECB_READY; 1060 if (sc->sc_state == NCR_IDLE) 1061 ncr53c9x_sched(sc); 1062 break; 1063 1064 case XPT_SET_TRAN_SETTINGS: 1065 cts = &ccb->cts; 1066 target = ccb->ccb_h.target_id; 1067 ti = &sc->sc_tinfo[target]; 1068 scsi = &cts->proto_specific.scsi; 1069 spi = &cts->xport_specific.spi; 1070 1071 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 1072 if ((sc->sc_cfflags & (1<<((target & 7) + 16))) == 0 && 1073 (scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)) { 1074 NCR_MISC(("%s: target %d: tagged queuing\n", 1075 device_get_nameunit(sc->sc_dev), target)); 1076 ti->flags |= T_TAG; 1077 } else 1078 ti->flags &= ~T_TAG; 1079 } 1080 1081 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
| 1107 xpt_done(ccb); 1108 return; 1109 } 1110 1111 /* Initialize ecb. */ 1112 ecb->ccb = ccb; 1113 ecb->timeout = ccb->ccb_h.timeout; 1114 1115 if (ccb->ccb_h.func_code == XPT_RESET_DEV) { 1116 ecb->flags |= ECB_RESET; 1117 ecb->clen = 0; 1118 ecb->dleft = 0; 1119 } else { 1120 csio = &ccb->csio; 1121 if ((ccb->ccb_h.flags & CAM_CDB_POINTER) != 0) 1122 bcopy(csio->cdb_io.cdb_ptr, &ecb->cmd.cmd, 1123 csio->cdb_len); 1124 else 1125 bcopy(csio->cdb_io.cdb_bytes, &ecb->cmd.cmd, 1126 csio->cdb_len); 1127 ecb->clen = csio->cdb_len; 1128 ecb->daddr = csio->data_ptr; 1129 ecb->dleft = csio->dxfer_len; 1130 } 1131 ecb->stat = 0; 1132 1133 TAILQ_INSERT_TAIL(&sc->ready_list, ecb, chain); 1134 ecb->flags |= ECB_READY; 1135 if (sc->sc_state == NCR_IDLE) 1136 ncr53c9x_sched(sc); 1137 break; 1138 1139 case XPT_SET_TRAN_SETTINGS: 1140 cts = &ccb->cts; 1141 target = ccb->ccb_h.target_id; 1142 ti = &sc->sc_tinfo[target]; 1143 scsi = &cts->proto_specific.scsi; 1144 spi = &cts->xport_specific.spi; 1145 1146 if ((scsi->valid & CTS_SCSI_VALID_TQ) != 0) { 1147 if ((sc->sc_cfflags & (1<<((target & 7) + 16))) == 0 && 1148 (scsi->flags & CTS_SCSI_FLAGS_TAG_ENB)) { 1149 NCR_MISC(("%s: target %d: tagged queuing\n", 1150 device_get_nameunit(sc->sc_dev), target)); 1151 ti->flags |= T_TAG; 1152 } else 1153 ti->flags &= ~T_TAG; 1154 } 1155 1156 if ((spi->valid & CTS_SPI_VALID_BUS_WIDTH) != 0) {
|
1082 if (spi->bus_width != 0) { 1083 NCR_MISC(("%s: target %d: wide negotiation\n", 1084 device_get_nameunit(sc->sc_dev), target)); 1085 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1086 ti->flags |= T_WIDE; 1087 ti->width = 1; 1088 } 1089 } else { 1090 ti->flags &= ~T_WIDE; 1091 ti->width = 0; 1092 } 1093 ti->flags |= T_NEGOTIATE;
| 1157 NCR_MISC(("%s: target %d: wide negotiation\n", 1158 device_get_nameunit(sc->sc_dev), target)); 1159 ti->goal.width = spi->bus_width;
|
1094 } 1095 1096 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 1097 NCR_MISC(("%s: target %d: sync period negotiation\n", 1098 device_get_nameunit(sc->sc_dev), target));
| 1160 } 1161 1162 if ((spi->valid & CTS_SPI_VALID_SYNC_RATE) != 0) { 1163 NCR_MISC(("%s: target %d: sync period negotiation\n", 1164 device_get_nameunit(sc->sc_dev), target));
|
1099 ti->flags |= T_NEGOTIATE; 1100 ti->period = spi->sync_period;
| 1165 ti->goal.period = spi->sync_period;
|
1101 } 1102 1103 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) { 1104 NCR_MISC(("%s: target %d: sync offset negotiation\n", 1105 device_get_nameunit(sc->sc_dev), target));
| 1166 } 1167 1168 if ((spi->valid & CTS_SPI_VALID_SYNC_OFFSET) != 0) { 1169 NCR_MISC(("%s: target %d: sync offset negotiation\n", 1170 device_get_nameunit(sc->sc_dev), target));
|
1106 ti->flags |= T_NEGOTIATE; 1107 ti->offset = spi->sync_offset;
| 1171 ti->goal.offset = spi->sync_offset;
|
1108 } 1109
| 1172 } 1173
|
1110 mtx_unlock(&sc->sc_lock);
| |
1111 ccb->ccb_h.status = CAM_REQ_CMP; 1112 xpt_done(ccb); 1113 return; 1114 1115 default: 1116 device_printf(sc->sc_dev, "Unhandled function code %d\n", 1117 ccb->ccb_h.func_code); 1118 ccb->ccb_h.status = CAM_PROVIDE_FAIL;
| 1174 ccb->ccb_h.status = CAM_REQ_CMP; 1175 xpt_done(ccb); 1176 return; 1177 1178 default: 1179 device_printf(sc->sc_dev, "Unhandled function code %d\n", 1180 ccb->ccb_h.func_code); 1181 ccb->ccb_h.status = CAM_PROVIDE_FAIL;
|
1119 mtx_unlock(&sc->sc_lock);
| |
1120 xpt_done(ccb); 1121 return; 1122 }
| 1182 xpt_done(ccb); 1183 return; 1184 }
|
1123 1124 mtx_unlock(&sc->sc_lock);
| |
1125} 1126 1127/* 1128 * Used when interrupt driven I/O is not allowed, e.g. during boot. 1129 */ 1130static void 1131ncr53c9x_poll(struct cam_sim *sim) 1132{ 1133 struct ncr53c9x_softc *sc; 1134
| 1185} 1186 1187/* 1188 * Used when interrupt driven I/O is not allowed, e.g. during boot. 1189 */ 1190static void 1191ncr53c9x_poll(struct cam_sim *sim) 1192{ 1193 struct ncr53c9x_softc *sc; 1194
|
1135 NCR_TRACE(("[ncr53c9x_poll] "));
| |
1136 sc = cam_sim_softc(sim);
| 1195 sc = cam_sim_softc(sim);
|
1137 if (NCRDMA_ISINTR(sc)) { 1138 ncr53c9x_intr(sc);
| 1196 1197 NCR_LOCK_ASSERT(sc, MA_OWNED); 1198 1199 NCR_TRACE(("[ncr53c9x_poll] ")); 1200 1201 if (NCRDMA_ISINTR(sc)) 1202 ncr53c9x_intr1(sc); 1203} 1204 1205/* 1206 * Asynchronous notification handler 1207 */ 1208static void 1209ncr53c9x_async(void *cbarg, uint32_t code, struct cam_path *path, void *arg) 1210{ 1211 struct ncr53c9x_softc *sc; 1212 struct ncr53c9x_tinfo *ti; 1213 int target; 1214 1215 sc = cam_sim_softc(cbarg); 1216 1217 NCR_LOCK_ASSERT(sc, MA_OWNED); 1218 1219 switch (code) { 1220 case AC_LOST_DEVICE: 1221 target = xpt_path_target_id(path); 1222 if (target < 0 || target >= sc->sc_ntarg) 1223 break; 1224 1225 /* Cancel outstanding disconnected commands. */ 1226 ncr53c9x_clear_target(sc, target, CAM_REQ_ABORTED); 1227 1228 /* Set the default parameters for the target. */ 1229 ti = &sc->sc_tinfo[target]; 1230/* XXX - config flags per target: low bits: no reselect; high bits: no synch */ 1231 ti->flags = ((sc->sc_minsync != 0 && 1232 (sc->sc_cfflags & (1 << ((target & 7) + 8))) == 0) ? 1233 0 : T_SYNCHOFF) | 1234 ((sc->sc_cfflags & (1 << (target & 7))) == 0 ? 1235 0 : T_RSELECTOFF); 1236 ti->curr.period = ti->goal.period = 0; 1237 ti->curr.offset = ti->goal.offset = 0; 1238 ti->curr.width = ti->goal.width = MSG_EXT_WDTR_BUS_8_BIT; 1239 break;
|
1139 } 1140} 1141 1142/* 1143 * LOW LEVEL SCSI UTILITIES 1144 */ 1145 1146/* 1147 * Schedule a SCSI operation. This has now been pulled out of the interrupt
| 1240 } 1241} 1242 1243/* 1244 * LOW LEVEL SCSI UTILITIES 1245 */ 1246 1247/* 1248 * Schedule a SCSI operation. This has now been pulled out of the interrupt
|
1148 * handler so that we may call it from ncr53c9x_scsipi_request and 1149 * ncr53c9x_done. This may save us an unnecessary interrupt just to get 1150 * things going. Should only be called when state == NCR_IDLE and at bio pl.
| 1249 * handler so that we may call it from ncr53c9x_action and ncr53c9x_done. 1250 * This may save us an unnecessary interrupt just to get things going. 1251 * Should only be called when state == NCR_IDLE and with sc_lock held.
|
1151 */ 1152static void 1153ncr53c9x_sched(struct ncr53c9x_softc *sc) 1154{ 1155 struct ncr53c9x_ecb *ecb; 1156 struct ncr53c9x_linfo *li; 1157 struct ncr53c9x_tinfo *ti; 1158 int lun, tag; 1159
| 1252 */ 1253static void 1254ncr53c9x_sched(struct ncr53c9x_softc *sc) 1255{ 1256 struct ncr53c9x_ecb *ecb; 1257 struct ncr53c9x_linfo *li; 1258 struct ncr53c9x_tinfo *ti; 1259 int lun, tag; 1260
|
| 1261 NCR_LOCK_ASSERT(sc, MA_OWNED); 1262
|
1160 NCR_TRACE(("[ncr53c9x_sched] ")); 1161 1162 if (sc->sc_state != NCR_IDLE) 1163 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 1164 1165 /* 1166 * Find first ecb in ready queue that is for a target/lunit 1167 * combinations that is not busy. 1168 */
| 1263 NCR_TRACE(("[ncr53c9x_sched] ")); 1264 1265 if (sc->sc_state != NCR_IDLE) 1266 panic("ncr53c9x_sched: not IDLE (state=%d)", sc->sc_state); 1267 1268 /* 1269 * Find first ecb in ready queue that is for a target/lunit 1270 * combinations that is not busy. 1271 */
|
1169 for (ecb = TAILQ_FIRST(&sc->ready_list); ecb != NULL; 1170 ecb = TAILQ_NEXT(ecb, chain)) {
| 1272 TAILQ_FOREACH(ecb, &sc->ready_list, chain) {
|
1171 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1172 lun = ecb->ccb->ccb_h.target_lun; 1173 1174 /* Select type of tag for this command */
| 1273 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1274 lun = ecb->ccb->ccb_h.target_lun; 1275 1276 /* Select type of tag for this command */
|
1175 if ((ti->flags & (T_RSELECTOFF)) != 0)
| 1277 if ((ti->flags & (T_RSELECTOFF | T_TAG)) != T_TAG)
|
1176 tag = 0;
| 1278 tag = 0;
|
1177 else if ((ti->flags & (T_TAG)) == 0) 1178 tag = 0;
| |
1179 else if ((ecb->flags & ECB_SENSE) != 0) 1180 tag = 0; 1181 else if ((ecb->ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0) 1182 tag = 0; 1183 else if (ecb->ccb->csio.tag_action == CAM_TAG_ACTION_NONE) 1184 tag = 0; 1185 else 1186 tag = ecb->ccb->csio.tag_action; 1187 1188 li = TINFO_LUN(ti, lun); 1189 if (li == NULL) { 1190 /* Initialize LUN info and add to list. */ 1191 if ((li = malloc(sizeof(*li), 1192 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1193 continue; 1194 } 1195 li->lun = lun; 1196 1197 LIST_INSERT_HEAD(&ti->luns, li, link); 1198 if (lun < NCR_NLUN) 1199 ti->lun[lun] = li; 1200 } 1201 li->last_used = time_second; 1202 if (tag == 0) { 1203 /* Try to issue this as an untagged command. */ 1204 if (li->untagged == NULL) 1205 li->untagged = ecb; 1206 } 1207 if (li->untagged != NULL) { 1208 tag = 0; 1209 if ((li->busy != 1) && li->used == 0) { 1210 /* 1211 * We need to issue this untagged command 1212 * now. 1213 */ 1214 ecb = li->untagged; 1215 } else { 1216 /* not ready, yet */ 1217 continue; 1218 } 1219 } 1220 ecb->tag[0] = tag; 1221 if (tag != 0) { 1222 li->queued[ecb->tag_id] = ecb; 1223 ecb->tag[1] = ecb->tag_id; 1224 li->used++; 1225 } 1226 if (li->untagged != NULL && (li->busy != 1)) { 1227 li->busy = 1; 1228 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1229 ecb->flags &= ~ECB_READY; 1230 sc->sc_nexus = ecb; 1231 ncr53c9x_select(sc, ecb); 1232 break; 1233 } 1234 if (li->untagged == NULL && tag != 0) { 1235 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1236 ecb->flags &= ~ECB_READY; 1237 sc->sc_nexus = ecb; 1238 ncr53c9x_select(sc, ecb); 1239 break; 1240 } else { 1241 NCR_TRACE(("%d:%d busy\n", 1242 ecb->ccb->ccb_h.target_id, 1243 ecb->ccb->ccb_h.target_lun)); 1244 } 1245 } 1246} 1247 1248static void 1249ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1250{ 1251 union ccb *ccb = ecb->ccb; 1252 struct ncr53c9x_linfo *li; 1253 struct ncr53c9x_tinfo *ti; 1254 struct scsi_request_sense *ss = (void *)&ecb->cmd.cmd; 1255 int lun; 1256
| 1279 else if ((ecb->flags & ECB_SENSE) != 0) 1280 tag = 0; 1281 else if ((ecb->ccb->ccb_h.flags & CAM_TAG_ACTION_VALID) == 0) 1282 tag = 0; 1283 else if (ecb->ccb->csio.tag_action == CAM_TAG_ACTION_NONE) 1284 tag = 0; 1285 else 1286 tag = ecb->ccb->csio.tag_action; 1287 1288 li = TINFO_LUN(ti, lun); 1289 if (li == NULL) { 1290 /* Initialize LUN info and add to list. */ 1291 if ((li = malloc(sizeof(*li), 1292 M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) { 1293 continue; 1294 } 1295 li->lun = lun; 1296 1297 LIST_INSERT_HEAD(&ti->luns, li, link); 1298 if (lun < NCR_NLUN) 1299 ti->lun[lun] = li; 1300 } 1301 li->last_used = time_second; 1302 if (tag == 0) { 1303 /* Try to issue this as an untagged command. */ 1304 if (li->untagged == NULL) 1305 li->untagged = ecb; 1306 } 1307 if (li->untagged != NULL) { 1308 tag = 0; 1309 if ((li->busy != 1) && li->used == 0) { 1310 /* 1311 * We need to issue this untagged command 1312 * now. 1313 */ 1314 ecb = li->untagged; 1315 } else { 1316 /* not ready, yet */ 1317 continue; 1318 } 1319 } 1320 ecb->tag[0] = tag; 1321 if (tag != 0) { 1322 li->queued[ecb->tag_id] = ecb; 1323 ecb->tag[1] = ecb->tag_id; 1324 li->used++; 1325 } 1326 if (li->untagged != NULL && (li->busy != 1)) { 1327 li->busy = 1; 1328 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1329 ecb->flags &= ~ECB_READY; 1330 sc->sc_nexus = ecb; 1331 ncr53c9x_select(sc, ecb); 1332 break; 1333 } 1334 if (li->untagged == NULL && tag != 0) { 1335 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1336 ecb->flags &= ~ECB_READY; 1337 sc->sc_nexus = ecb; 1338 ncr53c9x_select(sc, ecb); 1339 break; 1340 } else { 1341 NCR_TRACE(("%d:%d busy\n", 1342 ecb->ccb->ccb_h.target_id, 1343 ecb->ccb->ccb_h.target_lun)); 1344 } 1345 } 1346} 1347 1348static void 1349ncr53c9x_sense(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1350{ 1351 union ccb *ccb = ecb->ccb; 1352 struct ncr53c9x_linfo *li; 1353 struct ncr53c9x_tinfo *ti; 1354 struct scsi_request_sense *ss = (void *)&ecb->cmd.cmd; 1355 int lun; 1356
|
| 1357 NCR_LOCK_ASSERT(sc, MA_OWNED); 1358
|
1257 NCR_TRACE(("requesting sense ")); 1258 1259 lun = ccb->ccb_h.target_lun; 1260 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1261 1262 /* Next, setup a REQUEST SENSE command block. */ 1263 memset(ss, 0, sizeof(*ss)); 1264 ss->opcode = REQUEST_SENSE; 1265 ss->byte2 = ccb->ccb_h.target_lun << SCSI_CMD_LUN_SHIFT; 1266 ss->length = sizeof(struct scsi_sense_data); 1267 ecb->clen = sizeof(*ss); 1268 ecb->daddr = (char *)&ecb->ccb->csio.sense_data; 1269 ecb->dleft = sizeof(struct scsi_sense_data); 1270 ecb->flags |= ECB_SENSE; 1271 ecb->timeout = NCR_SENSE_TIMEOUT; 1272 ti->senses++; 1273 li = TINFO_LUN(ti, lun); 1274 if (li->busy) 1275 li->busy = 0; 1276 ncr53c9x_dequeue(sc, ecb); 1277 li->untagged = ecb; /* Must be executed first to fix C/A. */ 1278 li->busy = 2; 1279 if (ecb == sc->sc_nexus) { 1280 ncr53c9x_select(sc, ecb); 1281 } else { 1282 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1283 ecb->flags |= ECB_READY; 1284 if (sc->sc_state == NCR_IDLE) 1285 ncr53c9x_sched(sc); 1286 } 1287} 1288 1289/* 1290 * POST PROCESSING OF SCSI_CMD (usually current) 1291 */ 1292static void 1293ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1294{ 1295 union ccb *ccb = ecb->ccb; 1296 struct ncr53c9x_linfo *li; 1297 struct ncr53c9x_tinfo *ti; 1298 int lun; 1299
| 1359 NCR_TRACE(("requesting sense ")); 1360 1361 lun = ccb->ccb_h.target_lun; 1362 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1363 1364 /* Next, setup a REQUEST SENSE command block. */ 1365 memset(ss, 0, sizeof(*ss)); 1366 ss->opcode = REQUEST_SENSE; 1367 ss->byte2 = ccb->ccb_h.target_lun << SCSI_CMD_LUN_SHIFT; 1368 ss->length = sizeof(struct scsi_sense_data); 1369 ecb->clen = sizeof(*ss); 1370 ecb->daddr = (char *)&ecb->ccb->csio.sense_data; 1371 ecb->dleft = sizeof(struct scsi_sense_data); 1372 ecb->flags |= ECB_SENSE; 1373 ecb->timeout = NCR_SENSE_TIMEOUT; 1374 ti->senses++; 1375 li = TINFO_LUN(ti, lun); 1376 if (li->busy) 1377 li->busy = 0; 1378 ncr53c9x_dequeue(sc, ecb); 1379 li->untagged = ecb; /* Must be executed first to fix C/A. */ 1380 li->busy = 2; 1381 if (ecb == sc->sc_nexus) { 1382 ncr53c9x_select(sc, ecb); 1383 } else { 1384 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 1385 ecb->flags |= ECB_READY; 1386 if (sc->sc_state == NCR_IDLE) 1387 ncr53c9x_sched(sc); 1388 } 1389} 1390 1391/* 1392 * POST PROCESSING OF SCSI_CMD (usually current) 1393 */ 1394static void 1395ncr53c9x_done(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1396{ 1397 union ccb *ccb = ecb->ccb; 1398 struct ncr53c9x_linfo *li; 1399 struct ncr53c9x_tinfo *ti; 1400 int lun; 1401
|
| 1402 NCR_LOCK_ASSERT(sc, MA_OWNED); 1403
|
1300 NCR_TRACE(("[ncr53c9x_done(status:%x)] ", ccb->ccb_h.status)); 1301 1302 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1303 lun = ccb->ccb_h.target_lun; 1304 li = TINFO_LUN(ti, lun); 1305
| 1404 NCR_TRACE(("[ncr53c9x_done(status:%x)] ", ccb->ccb_h.status)); 1405 1406 ti = &sc->sc_tinfo[ccb->ccb_h.target_id]; 1407 lun = ccb->ccb_h.target_lun; 1408 li = TINFO_LUN(ti, lun); 1409
|
1306 untimeout(ncr53c9x_timeout, ecb, ccb->ccb_h.timeout_ch);
| 1410 callout_stop(&ecb->ch);
|
1307 1308 /* 1309 * Now, if we've come here with no error code, i.e. we've kept the
| 1411 1412 /* 1413 * Now, if we've come here with no error code, i.e. we've kept the
|
1310 * initial XS_NOERROR, and the status code signals that we should
| 1414 * initial CAM_REQ_CMP, and the status code signals that we should
|
1311 * check sense, we'll need to set up a request sense cmd block and 1312 * push the command back into the ready queue *before* any other 1313 * commands for this target/lunit, else we lose the sense info. 1314 * We don't support chk sense conditions for the request sense cmd. 1315 */ 1316 if (ccb->ccb_h.status == CAM_REQ_CMP) {
| 1415 * check sense, we'll need to set up a request sense cmd block and 1416 * push the command back into the ready queue *before* any other 1417 * commands for this target/lunit, else we lose the sense info. 1418 * We don't support chk sense conditions for the request sense cmd. 1419 */ 1420 if (ccb->ccb_h.status == CAM_REQ_CMP) {
|
| 1421 ccb->csio.scsi_status = ecb->stat;
|
1317 if ((ecb->flags & ECB_ABORT) != 0) { 1318 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1319 } else if ((ecb->flags & ECB_SENSE) != 0 && 1320 (ecb->stat != SCSI_STATUS_CHECK_COND)) {
| 1422 if ((ecb->flags & ECB_ABORT) != 0) { 1423 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 1424 } else if ((ecb->flags & ECB_SENSE) != 0 && 1425 (ecb->stat != SCSI_STATUS_CHECK_COND)) {
|
1321 ccb->ccb_h.status = CAM_AUTOSNS_VALID;
| 1426 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1427 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR | 1428 CAM_AUTOSNS_VALID;
|
1322 } else if (ecb->stat == SCSI_STATUS_CHECK_COND) { 1323 if ((ecb->flags & ECB_SENSE) != 0) 1324 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1325 else { 1326 /* First, save the return values. */ 1327 ccb->csio.resid = ecb->dleft;
| 1429 } else if (ecb->stat == SCSI_STATUS_CHECK_COND) { 1430 if ((ecb->flags & ECB_SENSE) != 0) 1431 ccb->ccb_h.status = CAM_AUTOSENSE_FAIL; 1432 else { 1433 /* First, save the return values. */ 1434 ccb->csio.resid = ecb->dleft;
|
1328 ncr53c9x_sense(sc, ecb); 1329 return;
| 1435 if ((ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 1436 0) { 1437 ncr53c9x_sense(sc, ecb); 1438 return; 1439 } 1440 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR;
|
1330 } 1331 } else { 1332 ccb->csio.resid = ecb->dleft; 1333 }
| 1441 } 1442 } else { 1443 ccb->csio.resid = ecb->dleft; 1444 }
|
1334#if 0 1335 if (xs->status == SCSI_QUEUE_FULL || xs->status == XS_BUSY) 1336 xs->error = XS_BUSY; 1337#endif
| 1445 if (ecb->stat == SCSI_STATUS_QUEUE_FULL) 1446 ccb->ccb_h.status = CAM_SCSI_STATUS_ERROR; 1447 else if (ecb->stat == SCSI_STATUS_BUSY) 1448 ccb->ccb_h.status = CAM_SCSI_BUSY;
|
1338 } 1339 1340#ifdef NCR53C9X_DEBUG 1341 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1342 if (ccb->csio.resid != 0) 1343 printf("resid=%d ", ccb->csio.resid);
| 1449 } 1450 1451#ifdef NCR53C9X_DEBUG 1452 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1453 if (ccb->csio.resid != 0) 1454 printf("resid=%d ", ccb->csio.resid);
|
1344#if 0 1345 if (xs->error == XS_SENSE)
| 1455 if ((ccb->ccb_h.status & CAM_AUTOSNS_VALID) != 0)
|
1346 printf("sense=0x%02x\n",
| 1456 printf("sense=0x%02x\n",
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1347 xs->sense.scsi_sense.error_code);
| 1457 ccb->csio.sense_data.error_code);
|
1348 else
| 1458 else
|
1349 printf("error=%d\n", xs->error); 1350#endif
| 1459 printf("status SCSI=0x%x CAM=0x%x\n", 1460 ccb->csio.scsi_status, ccb->ccb_h.status);
|
1351 } 1352#endif 1353 1354 /* 1355 * Remove the ECB from whatever queue it's on. 1356 */ 1357 ncr53c9x_dequeue(sc, ecb); 1358 if (ecb == sc->sc_nexus) { 1359 sc->sc_nexus = NULL; 1360 if (sc->sc_state != NCR_CLEANING) { 1361 sc->sc_state = NCR_IDLE; 1362 ncr53c9x_sched(sc); 1363 } 1364 } 1365 1366 if (ccb->ccb_h.status == CAM_SEL_TIMEOUT) { 1367 /* Selection timeout -- discard this LUN if empty. */ 1368 if (li->untagged == NULL && li->used == 0) { 1369 if (lun < NCR_NLUN) 1370 ti->lun[lun] = NULL; 1371 LIST_REMOVE(li, link); 1372 free(li, M_DEVBUF); 1373 } 1374 } 1375 1376 ncr53c9x_free_ecb(sc, ecb); 1377 ti->cmds++; 1378 xpt_done(ccb); 1379} 1380 1381static void 1382ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1383{ 1384 struct ncr53c9x_linfo *li; 1385 struct ncr53c9x_tinfo *ti; 1386 int64_t lun; 1387
| 1461 } 1462#endif 1463 1464 /* 1465 * Remove the ECB from whatever queue it's on. 1466 */ 1467 ncr53c9x_dequeue(sc, ecb); 1468 if (ecb == sc->sc_nexus) { 1469 sc->sc_nexus = NULL; 1470 if (sc->sc_state != NCR_CLEANING) { 1471 sc->sc_state = NCR_IDLE; 1472 ncr53c9x_sched(sc); 1473 } 1474 } 1475 1476 if (ccb->ccb_h.status == CAM_SEL_TIMEOUT) { 1477 /* Selection timeout -- discard this LUN if empty. */ 1478 if (li->untagged == NULL && li->used == 0) { 1479 if (lun < NCR_NLUN) 1480 ti->lun[lun] = NULL; 1481 LIST_REMOVE(li, link); 1482 free(li, M_DEVBUF); 1483 } 1484 } 1485 1486 ncr53c9x_free_ecb(sc, ecb); 1487 ti->cmds++; 1488 xpt_done(ccb); 1489} 1490 1491static void 1492ncr53c9x_dequeue(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 1493{ 1494 struct ncr53c9x_linfo *li; 1495 struct ncr53c9x_tinfo *ti; 1496 int64_t lun; 1497
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| 1498 NCR_LOCK_ASSERT(sc, MA_OWNED); 1499
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1388 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1389 lun = ecb->ccb->ccb_h.target_lun; 1390 li = TINFO_LUN(ti, lun); 1391#ifdef DIAGNOSTIC 1392 if (li == NULL || li->lun != lun) 1393 panic("ncr53c9x_dequeue: lun %qx for ecb %p does not exist", 1394 (long long)lun, ecb); 1395#endif 1396 if (li->untagged == ecb) { 1397 li->busy = 0; 1398 li->untagged = NULL; 1399 } 1400 if (ecb->tag[0] && li->queued[ecb->tag[1]] != NULL) { 1401#ifdef DIAGNOSTIC 1402 if (li->queued[ecb->tag[1]] != NULL && 1403 (li->queued[ecb->tag[1]] != ecb)) 1404 panic("ncr53c9x_dequeue: slot %d for lun %qx has %p " 1405 "instead of ecb %p\n", ecb->tag[1], 1406 (long long)lun, li->queued[ecb->tag[1]], ecb); 1407#endif 1408 li->queued[ecb->tag[1]] = NULL; 1409 li->used--; 1410 }
| 1500 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1501 lun = ecb->ccb->ccb_h.target_lun; 1502 li = TINFO_LUN(ti, lun); 1503#ifdef DIAGNOSTIC 1504 if (li == NULL || li->lun != lun) 1505 panic("ncr53c9x_dequeue: lun %qx for ecb %p does not exist", 1506 (long long)lun, ecb); 1507#endif 1508 if (li->untagged == ecb) { 1509 li->busy = 0; 1510 li->untagged = NULL; 1511 } 1512 if (ecb->tag[0] && li->queued[ecb->tag[1]] != NULL) { 1513#ifdef DIAGNOSTIC 1514 if (li->queued[ecb->tag[1]] != NULL && 1515 (li->queued[ecb->tag[1]] != ecb)) 1516 panic("ncr53c9x_dequeue: slot %d for lun %qx has %p " 1517 "instead of ecb %p\n", ecb->tag[1], 1518 (long long)lun, li->queued[ecb->tag[1]], ecb); 1519#endif 1520 li->queued[ecb->tag[1]] = NULL; 1521 li->used--; 1522 }
|
| 1523 ecb->tag[0] = ecb->tag[1] = 0;
|
1411 1412 if ((ecb->flags & ECB_READY) != 0) { 1413 ecb->flags &= ~ECB_READY; 1414 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1415 } 1416} 1417 1418/* 1419 * INTERRUPT/PROTOCOL ENGINE 1420 */ 1421 1422/* 1423 * Schedule an outgoing message by prioritizing it, and asserting 1424 * attention on the bus. We can only do this when we are the initiator 1425 * else there will be an illegal command interrupt. 1426 */ 1427#define ncr53c9x_sched_msgout(m) do { \ 1428 NCR_MSGS(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \ 1429 NCRCMD(sc, NCRCMD_SETATN); \ 1430 sc->sc_flags |= NCR_ATN; \ 1431 sc->sc_msgpriq |= (m); \ 1432} while (0) 1433 1434static void 1435ncr53c9x_flushfifo(struct ncr53c9x_softc *sc) 1436{
| 1524 1525 if ((ecb->flags & ECB_READY) != 0) { 1526 ecb->flags &= ~ECB_READY; 1527 TAILQ_REMOVE(&sc->ready_list, ecb, chain); 1528 } 1529} 1530 1531/* 1532 * INTERRUPT/PROTOCOL ENGINE 1533 */ 1534 1535/* 1536 * Schedule an outgoing message by prioritizing it, and asserting 1537 * attention on the bus. We can only do this when we are the initiator 1538 * else there will be an illegal command interrupt. 1539 */ 1540#define ncr53c9x_sched_msgout(m) do { \ 1541 NCR_MSGS(("ncr53c9x_sched_msgout %x %d", m, __LINE__)); \ 1542 NCRCMD(sc, NCRCMD_SETATN); \ 1543 sc->sc_flags |= NCR_ATN; \ 1544 sc->sc_msgpriq |= (m); \ 1545} while (0) 1546 1547static void 1548ncr53c9x_flushfifo(struct ncr53c9x_softc *sc) 1549{
|
| 1550 1551 NCR_LOCK_ASSERT(sc, MA_OWNED); 1552
|
1437 NCR_TRACE(("[flushfifo] ")); 1438 1439 NCRCMD(sc, NCRCMD_FLUSH); 1440 1441 if (sc->sc_phase == COMMAND_PHASE || 1442 sc->sc_phase == MESSAGE_OUT_PHASE) 1443 DELAY(2); 1444} 1445 1446static int 1447ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how) 1448{ 1449 u_char *ibuf; 1450 int i, n; 1451
| 1553 NCR_TRACE(("[flushfifo] ")); 1554 1555 NCRCMD(sc, NCRCMD_FLUSH); 1556 1557 if (sc->sc_phase == COMMAND_PHASE || 1558 sc->sc_phase == MESSAGE_OUT_PHASE) 1559 DELAY(2); 1560} 1561 1562static int 1563ncr53c9x_rdfifo(struct ncr53c9x_softc *sc, int how) 1564{ 1565 u_char *ibuf; 1566 int i, n; 1567
|
| 1568 NCR_LOCK_ASSERT(sc, MA_OWNED); 1569
|
1452 switch (how) { 1453 case NCR_RDFIFO_START: 1454 ibuf = sc->sc_imess; 1455 sc->sc_imlen = 0; 1456 break; 1457 1458 case NCR_RDFIFO_CONTINUE: 1459 ibuf = sc->sc_imess + sc->sc_imlen; 1460 break; 1461 1462 default: 1463 panic("ncr53c9x_rdfifo: bad flag"); 1464 /* NOTREACHED */ 1465 } 1466 1467 /* 1468 * XXX buffer (sc_imess) size for message 1469 */ 1470 1471 n = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 1472 1473 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1474 n *= 2; 1475 1476 for (i = 0; i < n; i++) 1477 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO); 1478 1479 if (sc->sc_espstat2 & NCRFAS_STAT2_ISHUTTLE) { 1480 1481 NCR_WRITE_REG(sc, NCR_FIFO, 0); 1482 ibuf[i++] = NCR_READ_REG(sc, NCR_FIFO); 1483 1484 NCR_READ_REG(sc, NCR_FIFO); 1485 1486 ncr53c9x_flushfifo(sc); 1487 } 1488 } else { 1489 for (i = 0; i < n; i++) 1490 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO); 1491 } 1492 1493 sc->sc_imlen += i; 1494 1495#if 0 1496#ifdef NCR53C9X_DEBUG 1497 NCR_TRACE(("\n[rdfifo %s (%d):", 1498 (how == NCR_RDFIFO_START) ? "start" : "cont", (int)sc->sc_imlen)); 1499 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1500 for (i = 0; i < sc->sc_imlen; i++) 1501 printf(" %02x", sc->sc_imess[i]); 1502 printf("]\n"); 1503 } 1504#endif 1505#endif 1506 return (sc->sc_imlen); 1507} 1508 1509static void 1510ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, int len) 1511{ 1512 int i; 1513
| 1570 switch (how) { 1571 case NCR_RDFIFO_START: 1572 ibuf = sc->sc_imess; 1573 sc->sc_imlen = 0; 1574 break; 1575 1576 case NCR_RDFIFO_CONTINUE: 1577 ibuf = sc->sc_imess + sc->sc_imlen; 1578 break; 1579 1580 default: 1581 panic("ncr53c9x_rdfifo: bad flag"); 1582 /* NOTREACHED */ 1583 } 1584 1585 /* 1586 * XXX buffer (sc_imess) size for message 1587 */ 1588 1589 n = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 1590 1591 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1592 n *= 2; 1593 1594 for (i = 0; i < n; i++) 1595 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO); 1596 1597 if (sc->sc_espstat2 & NCRFAS_STAT2_ISHUTTLE) { 1598 1599 NCR_WRITE_REG(sc, NCR_FIFO, 0); 1600 ibuf[i++] = NCR_READ_REG(sc, NCR_FIFO); 1601 1602 NCR_READ_REG(sc, NCR_FIFO); 1603 1604 ncr53c9x_flushfifo(sc); 1605 } 1606 } else { 1607 for (i = 0; i < n; i++) 1608 ibuf[i] = NCR_READ_REG(sc, NCR_FIFO); 1609 } 1610 1611 sc->sc_imlen += i; 1612 1613#if 0 1614#ifdef NCR53C9X_DEBUG 1615 NCR_TRACE(("\n[rdfifo %s (%d):", 1616 (how == NCR_RDFIFO_START) ? "start" : "cont", (int)sc->sc_imlen)); 1617 if (ncr53c9x_debug & NCR_SHOWTRAC) { 1618 for (i = 0; i < sc->sc_imlen; i++) 1619 printf(" %02x", sc->sc_imess[i]); 1620 printf("]\n"); 1621 } 1622#endif 1623#endif 1624 return (sc->sc_imlen); 1625} 1626 1627static void 1628ncr53c9x_wrfifo(struct ncr53c9x_softc *sc, u_char *p, int len) 1629{ 1630 int i; 1631
|
| 1632 NCR_LOCK_ASSERT(sc, MA_OWNED); 1633
|
1514#ifdef NCR53C9X_DEBUG 1515 NCR_MSGS(("[wrfifo(%d):", len)); 1516 if (ncr53c9x_debug & NCR_SHOWMSGS) { 1517 for (i = 0; i < len; i++) 1518 printf(" %02x", p[i]); 1519 printf("]\n"); 1520 } 1521#endif 1522 1523 for (i = 0; i < len; i++) { 1524 NCR_WRITE_REG(sc, NCR_FIFO, p[i]); 1525 1526 if (sc->sc_rev == NCR_VARIANT_FAS366) 1527 NCR_WRITE_REG(sc, NCR_FIFO, 0); 1528 } 1529} 1530 1531static int 1532ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype, 1533 int tagid) 1534{ 1535 struct ncr53c9x_ecb *ecb = NULL; 1536 struct ncr53c9x_linfo *li; 1537 struct ncr53c9x_tinfo *ti; 1538 u_char lun, selid, target; 1539
| 1634#ifdef NCR53C9X_DEBUG 1635 NCR_MSGS(("[wrfifo(%d):", len)); 1636 if (ncr53c9x_debug & NCR_SHOWMSGS) { 1637 for (i = 0; i < len; i++) 1638 printf(" %02x", p[i]); 1639 printf("]\n"); 1640 } 1641#endif 1642 1643 for (i = 0; i < len; i++) { 1644 NCR_WRITE_REG(sc, NCR_FIFO, p[i]); 1645 1646 if (sc->sc_rev == NCR_VARIANT_FAS366) 1647 NCR_WRITE_REG(sc, NCR_FIFO, 0); 1648 } 1649} 1650 1651static int 1652ncr53c9x_reselect(struct ncr53c9x_softc *sc, int message, int tagtype, 1653 int tagid) 1654{ 1655 struct ncr53c9x_ecb *ecb = NULL; 1656 struct ncr53c9x_linfo *li; 1657 struct ncr53c9x_tinfo *ti; 1658 u_char lun, selid, target; 1659
|
| 1660 NCR_LOCK_ASSERT(sc, MA_OWNED);
|
1540 1541 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1542 target = sc->sc_selid; 1543 } else { 1544 /* 1545 * The SCSI chip made a snapshot of the data bus 1546 * while the reselection was being negotiated. 1547 * This enables us to determine which target did 1548 * the reselect. 1549 */ 1550 selid = sc->sc_selid & ~(1 << sc->sc_id); 1551 if (selid & (selid - 1)) { 1552 device_printf(sc->sc_dev, "reselect with invalid " 1553 "selid %02x; sending DEVICE RESET\n", selid); 1554 goto reset; 1555 } 1556 1557 target = ffs(selid) - 1; 1558 } 1559 lun = message & 0x07; 1560 1561 /* 1562 * Search wait queue for disconnected command. 1563 * The list should be short, so I haven't bothered with 1564 * any more sophisticated structures than a simple 1565 * singly linked list. 1566 */ 1567 ti = &sc->sc_tinfo[target]; 1568 li = TINFO_LUN(ti, lun); 1569 1570 /* 1571 * We can get as far as the LUN with the IDENTIFY 1572 * message. Check to see if we're running an 1573 * untagged command. Otherwise ack the IDENTIFY 1574 * and wait for a tag message. 1575 */ 1576 if (li != NULL) { 1577 if (li->untagged != NULL && li->busy) 1578 ecb = li->untagged; 1579 else if (tagtype != MSG_SIMPLE_Q_TAG) { 1580 /* Wait for tag to come by. */ 1581 sc->sc_state = NCR_IDENTIFIED; 1582 return (0); 1583 } else if (tagtype) 1584 ecb = li->queued[tagid]; 1585 } 1586 if (ecb == NULL) { 1587 device_printf(sc->sc_dev, "reselect from target %d lun %d " 1588 "tag %x:%x with no nexus; sending ABORT\n", 1589 target, lun, tagtype, tagid); 1590 goto abort; 1591 } 1592 1593 /* Make this nexus active again. */ 1594 sc->sc_state = NCR_CONNECTED; 1595 sc->sc_nexus = ecb; 1596 ncr53c9x_setsync(sc, ti); 1597 1598 if (ecb->flags & ECB_RESET) 1599 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1600 else if (ecb->flags & ECB_ABORT) 1601 ncr53c9x_sched_msgout(SEND_ABORT); 1602 1603 /* Do an implicit RESTORE POINTERS. */ 1604 sc->sc_dp = ecb->daddr; 1605 sc->sc_dleft = ecb->dleft; 1606 1607 return (0); 1608 1609reset: 1610 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1611 return (1); 1612 1613abort: 1614 ncr53c9x_sched_msgout(SEND_ABORT); 1615 return (1); 1616} 1617 1618/* From NetBSD; these should go into CAM at some point. */ 1619#define MSG_ISEXTENDED(m) ((m) == MSG_EXTENDED) 1620#define MSG_IS1BYTE(m) \ 1621 ((!MSG_ISEXTENDED(m) && (m) < 0x20) || MSG_ISIDENTIFY(m)) 1622#define MSG_IS2BYTE(m) (((m) & 0xf0) == 0x20) 1623 1624static inline int 1625__verify_msg_format(u_char *p, int len) 1626{ 1627 1628 if (len == 1 && MSG_IS1BYTE(p[0])) 1629 return (1); 1630 if (len == 2 && MSG_IS2BYTE(p[0])) 1631 return (1); 1632 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1633 len == p[1] + 2) 1634 return (1); 1635 1636 return (0); 1637} 1638 1639/* 1640 * Get an incoming message as initiator. 1641 * 1642 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1643 * byte in the FIFO. 1644 */ 1645static void 1646ncr53c9x_msgin(struct ncr53c9x_softc *sc) 1647{ 1648 struct ncr53c9x_ecb *ecb; 1649 struct ncr53c9x_linfo *li; 1650 struct ncr53c9x_tinfo *ti; 1651 u_char *pb; 1652 int lun, plen; 1653
| 1661 1662 if (sc->sc_rev == NCR_VARIANT_FAS366) { 1663 target = sc->sc_selid; 1664 } else { 1665 /* 1666 * The SCSI chip made a snapshot of the data bus 1667 * while the reselection was being negotiated. 1668 * This enables us to determine which target did 1669 * the reselect. 1670 */ 1671 selid = sc->sc_selid & ~(1 << sc->sc_id); 1672 if (selid & (selid - 1)) { 1673 device_printf(sc->sc_dev, "reselect with invalid " 1674 "selid %02x; sending DEVICE RESET\n", selid); 1675 goto reset; 1676 } 1677 1678 target = ffs(selid) - 1; 1679 } 1680 lun = message & 0x07; 1681 1682 /* 1683 * Search wait queue for disconnected command. 1684 * The list should be short, so I haven't bothered with 1685 * any more sophisticated structures than a simple 1686 * singly linked list. 1687 */ 1688 ti = &sc->sc_tinfo[target]; 1689 li = TINFO_LUN(ti, lun); 1690 1691 /* 1692 * We can get as far as the LUN with the IDENTIFY 1693 * message. Check to see if we're running an 1694 * untagged command. Otherwise ack the IDENTIFY 1695 * and wait for a tag message. 1696 */ 1697 if (li != NULL) { 1698 if (li->untagged != NULL && li->busy) 1699 ecb = li->untagged; 1700 else if (tagtype != MSG_SIMPLE_Q_TAG) { 1701 /* Wait for tag to come by. */ 1702 sc->sc_state = NCR_IDENTIFIED; 1703 return (0); 1704 } else if (tagtype) 1705 ecb = li->queued[tagid]; 1706 } 1707 if (ecb == NULL) { 1708 device_printf(sc->sc_dev, "reselect from target %d lun %d " 1709 "tag %x:%x with no nexus; sending ABORT\n", 1710 target, lun, tagtype, tagid); 1711 goto abort; 1712 } 1713 1714 /* Make this nexus active again. */ 1715 sc->sc_state = NCR_CONNECTED; 1716 sc->sc_nexus = ecb; 1717 ncr53c9x_setsync(sc, ti); 1718 1719 if (ecb->flags & ECB_RESET) 1720 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1721 else if (ecb->flags & ECB_ABORT) 1722 ncr53c9x_sched_msgout(SEND_ABORT); 1723 1724 /* Do an implicit RESTORE POINTERS. */ 1725 sc->sc_dp = ecb->daddr; 1726 sc->sc_dleft = ecb->dleft; 1727 1728 return (0); 1729 1730reset: 1731 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1732 return (1); 1733 1734abort: 1735 ncr53c9x_sched_msgout(SEND_ABORT); 1736 return (1); 1737} 1738 1739/* From NetBSD; these should go into CAM at some point. */ 1740#define MSG_ISEXTENDED(m) ((m) == MSG_EXTENDED) 1741#define MSG_IS1BYTE(m) \ 1742 ((!MSG_ISEXTENDED(m) && (m) < 0x20) || MSG_ISIDENTIFY(m)) 1743#define MSG_IS2BYTE(m) (((m) & 0xf0) == 0x20) 1744 1745static inline int 1746__verify_msg_format(u_char *p, int len) 1747{ 1748 1749 if (len == 1 && MSG_IS1BYTE(p[0])) 1750 return (1); 1751 if (len == 2 && MSG_IS2BYTE(p[0])) 1752 return (1); 1753 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1754 len == p[1] + 2) 1755 return (1); 1756 1757 return (0); 1758} 1759 1760/* 1761 * Get an incoming message as initiator. 1762 * 1763 * The SCSI bus must already be in MESSAGE_IN_PHASE and there is a 1764 * byte in the FIFO. 1765 */ 1766static void 1767ncr53c9x_msgin(struct ncr53c9x_softc *sc) 1768{ 1769 struct ncr53c9x_ecb *ecb; 1770 struct ncr53c9x_linfo *li; 1771 struct ncr53c9x_tinfo *ti; 1772 u_char *pb; 1773 int lun, plen; 1774
|
| 1775 NCR_LOCK_ASSERT(sc, MA_OWNED); 1776
|
1654 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1655 1656 if (sc->sc_imlen == 0) { 1657 device_printf(sc->sc_dev, "msgin: no msg byte available\n"); 1658 return; 1659 } 1660 1661 /* 1662 * Prepare for a new message. A message should (according 1663 * to the SCSI standard) be transmitted in one single 1664 * MESSAGE_IN_PHASE. If we have been in some other phase, 1665 * then this is a new message. 1666 */ 1667 if (sc->sc_prevphase != MESSAGE_IN_PHASE && 1668 sc->sc_state != NCR_RESELECTED) { 1669 device_printf(sc->sc_dev, "phase change, dropping message, " 1670 "prev %d, state %d\n", sc->sc_prevphase, sc->sc_state); 1671 sc->sc_flags &= ~NCR_DROP_MSGI; 1672 sc->sc_imlen = 0; 1673 } 1674 1675 /* 1676 * If we're going to reject the message, don't bother storing 1677 * the incoming bytes. But still, we need to ACK them. 1678 */ 1679 if ((sc->sc_flags & NCR_DROP_MSGI) != 0) { 1680 NCRCMD(sc, NCRCMD_MSGOK);
| 1777 NCR_TRACE(("[ncr53c9x_msgin(curmsglen:%ld)] ", (long)sc->sc_imlen)); 1778 1779 if (sc->sc_imlen == 0) { 1780 device_printf(sc->sc_dev, "msgin: no msg byte available\n"); 1781 return; 1782 } 1783 1784 /* 1785 * Prepare for a new message. A message should (according 1786 * to the SCSI standard) be transmitted in one single 1787 * MESSAGE_IN_PHASE. If we have been in some other phase, 1788 * then this is a new message. 1789 */ 1790 if (sc->sc_prevphase != MESSAGE_IN_PHASE && 1791 sc->sc_state != NCR_RESELECTED) { 1792 device_printf(sc->sc_dev, "phase change, dropping message, " 1793 "prev %d, state %d\n", sc->sc_prevphase, sc->sc_state); 1794 sc->sc_flags &= ~NCR_DROP_MSGI; 1795 sc->sc_imlen = 0; 1796 } 1797 1798 /* 1799 * If we're going to reject the message, don't bother storing 1800 * the incoming bytes. But still, we need to ACK them. 1801 */ 1802 if ((sc->sc_flags & NCR_DROP_MSGI) != 0) { 1803 NCRCMD(sc, NCRCMD_MSGOK);
|
1681 printf("<dropping msg byte %x>", sc->sc_imess[sc->sc_imlen]);
| 1804 device_printf(sc->sc_dev, "<dropping msg byte %x>", 1805 sc->sc_imess[sc->sc_imlen]);
|
1682 return; 1683 } 1684 1685 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1686 ncr53c9x_sched_msgout(SEND_REJECT); 1687 sc->sc_flags |= NCR_DROP_MSGI; 1688 } else { 1689 switch (sc->sc_state) { 1690 /* 1691 * if received message is the first of reselection 1692 * then first byte is selid, and then message 1693 */ 1694 case NCR_RESELECTED: 1695 pb = sc->sc_imess + 1; 1696 plen = sc->sc_imlen - 1; 1697 break; 1698 1699 default: 1700 pb = sc->sc_imess; 1701 plen = sc->sc_imlen; 1702 } 1703 1704 if (__verify_msg_format(pb, plen)) 1705 goto gotit; 1706 } 1707 1708 /* Acknowledge what we have so far. */ 1709 NCRCMD(sc, NCRCMD_MSGOK); 1710 return; 1711 1712gotit: 1713 NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state)); 1714 /* 1715 * We got a complete message, flush the imess. 1716 * XXX nobody uses imlen below. 1717 */ 1718 sc->sc_imlen = 0; 1719 /* 1720 * Now we should have a complete message (1 byte, 2 byte 1721 * and moderately long extended messages). We only handle 1722 * extended messages which total length is shorter than 1723 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1724 */ 1725 switch (sc->sc_state) { 1726 case NCR_CONNECTED: 1727 ecb = sc->sc_nexus; 1728 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1729 1730 switch (sc->sc_imess[0]) { 1731 case MSG_CMDCOMPLETE: 1732 NCR_MSGS(("cmdcomplete ")); 1733 if (sc->sc_dleft < 0) { 1734 xpt_print_path(ecb->ccb->ccb_h.path); 1735 printf("got %ld extra bytes\n", 1736 -(long)sc->sc_dleft); 1737 sc->sc_dleft = 0; 1738 } 1739 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) ? 1740 0 : sc->sc_dleft; 1741 if ((ecb->flags & ECB_SENSE) == 0) 1742 ecb->ccb->csio.resid = ecb->dleft; 1743 sc->sc_state = NCR_CMDCOMPLETE; 1744 break; 1745 1746 case MSG_MESSAGE_REJECT: 1747 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1748 switch (sc->sc_msgout) { 1749 case SEND_TAG: 1750 /* 1751 * Target does not like tagged queuing. 1752 * - Flush the command queue 1753 * - Disable tagged queuing for the target 1754 * - Dequeue ecb from the queued array. 1755 */ 1756 device_printf(sc->sc_dev, "tagged queuing " 1757 "rejected: target %d\n", 1758 ecb->ccb->ccb_h.target_id); 1759 1760 NCR_MSGS(("(rejected sent tag)")); 1761 NCRCMD(sc, NCRCMD_FLUSH); 1762 DELAY(1); 1763 ti->flags &= ~T_TAG; 1764 lun = ecb->ccb->ccb_h.target_lun; 1765 li = TINFO_LUN(ti, lun); 1766 if (ecb->tag[0] && 1767 li->queued[ecb->tag[1]] != NULL) { 1768 li->queued[ecb->tag[1]] = NULL; 1769 li->used--; 1770 } 1771 ecb->tag[0] = ecb->tag[1] = 0; 1772 li->untagged = ecb; 1773 li->busy = 1; 1774 break; 1775 1776 case SEND_SDTR: 1777 device_printf(sc->sc_dev, "sync transfer " 1778 "rejected: target %d\n", 1779 ecb->ccb->ccb_h.target_id); 1780
| 1806 return; 1807 } 1808 1809 if (sc->sc_imlen >= NCR_MAX_MSG_LEN) { 1810 ncr53c9x_sched_msgout(SEND_REJECT); 1811 sc->sc_flags |= NCR_DROP_MSGI; 1812 } else { 1813 switch (sc->sc_state) { 1814 /* 1815 * if received message is the first of reselection 1816 * then first byte is selid, and then message 1817 */ 1818 case NCR_RESELECTED: 1819 pb = sc->sc_imess + 1; 1820 plen = sc->sc_imlen - 1; 1821 break; 1822 1823 default: 1824 pb = sc->sc_imess; 1825 plen = sc->sc_imlen; 1826 } 1827 1828 if (__verify_msg_format(pb, plen)) 1829 goto gotit; 1830 } 1831 1832 /* Acknowledge what we have so far. */ 1833 NCRCMD(sc, NCRCMD_MSGOK); 1834 return; 1835 1836gotit: 1837 NCR_MSGS(("gotmsg(%x) state %d", sc->sc_imess[0], sc->sc_state)); 1838 /* 1839 * We got a complete message, flush the imess. 1840 * XXX nobody uses imlen below. 1841 */ 1842 sc->sc_imlen = 0; 1843 /* 1844 * Now we should have a complete message (1 byte, 2 byte 1845 * and moderately long extended messages). We only handle 1846 * extended messages which total length is shorter than 1847 * NCR_MAX_MSG_LEN. Longer messages will be amputated. 1848 */ 1849 switch (sc->sc_state) { 1850 case NCR_CONNECTED: 1851 ecb = sc->sc_nexus; 1852 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 1853 1854 switch (sc->sc_imess[0]) { 1855 case MSG_CMDCOMPLETE: 1856 NCR_MSGS(("cmdcomplete ")); 1857 if (sc->sc_dleft < 0) { 1858 xpt_print_path(ecb->ccb->ccb_h.path); 1859 printf("got %ld extra bytes\n", 1860 -(long)sc->sc_dleft); 1861 sc->sc_dleft = 0; 1862 } 1863 ecb->dleft = (ecb->flags & ECB_TENTATIVE_DONE) ? 1864 0 : sc->sc_dleft; 1865 if ((ecb->flags & ECB_SENSE) == 0) 1866 ecb->ccb->csio.resid = ecb->dleft; 1867 sc->sc_state = NCR_CMDCOMPLETE; 1868 break; 1869 1870 case MSG_MESSAGE_REJECT: 1871 NCR_MSGS(("msg reject (msgout=%x) ", sc->sc_msgout)); 1872 switch (sc->sc_msgout) { 1873 case SEND_TAG: 1874 /* 1875 * Target does not like tagged queuing. 1876 * - Flush the command queue 1877 * - Disable tagged queuing for the target 1878 * - Dequeue ecb from the queued array. 1879 */ 1880 device_printf(sc->sc_dev, "tagged queuing " 1881 "rejected: target %d\n", 1882 ecb->ccb->ccb_h.target_id); 1883 1884 NCR_MSGS(("(rejected sent tag)")); 1885 NCRCMD(sc, NCRCMD_FLUSH); 1886 DELAY(1); 1887 ti->flags &= ~T_TAG; 1888 lun = ecb->ccb->ccb_h.target_lun; 1889 li = TINFO_LUN(ti, lun); 1890 if (ecb->tag[0] && 1891 li->queued[ecb->tag[1]] != NULL) { 1892 li->queued[ecb->tag[1]] = NULL; 1893 li->used--; 1894 } 1895 ecb->tag[0] = ecb->tag[1] = 0; 1896 li->untagged = ecb; 1897 li->busy = 1; 1898 break; 1899 1900 case SEND_SDTR: 1901 device_printf(sc->sc_dev, "sync transfer " 1902 "rejected: target %d\n", 1903 ecb->ccb->ccb_h.target_id); 1904
|
1781 sc->sc_flags &= ~NCR_SYNCHNEGO; 1782 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE);
| 1905 ti->flags &= ~T_SDTRSENT; 1906 ti->curr.period = ti->goal.period = 0; 1907 ti->curr.offset = ti->goal.offset = 0;
|
1783 ncr53c9x_setsync(sc, ti); 1784 break; 1785 1786 case SEND_WDTR: 1787 device_printf(sc->sc_dev, "wide transfer " 1788 "rejected: target %d\n", 1789 ecb->ccb->ccb_h.target_id);
| 1908 ncr53c9x_setsync(sc, ti); 1909 break; 1910 1911 case SEND_WDTR: 1912 device_printf(sc->sc_dev, "wide transfer " 1913 "rejected: target %d\n", 1914 ecb->ccb->ccb_h.target_id);
|
1790 ti->flags &= ~(T_WIDE | T_WDTRSENT); 1791 ti->width = 0;
| 1915 1916 ti->flags &= ~T_WDTRSENT; 1917 ti->curr.width = ti->goal.width = 1918 MSG_EXT_WDTR_BUS_8_BIT; 1919 ncr53c9x_setsync(sc, ti);
|
1792 break; 1793 1794 case SEND_INIT_DET_ERR: 1795 goto abort; 1796 } 1797 break; 1798 1799 case MSG_NOOP: 1800 NCR_MSGS(("noop ")); 1801 break; 1802 1803 case MSG_HEAD_OF_Q_TAG: 1804 case MSG_SIMPLE_Q_TAG: 1805 case MSG_ORDERED_Q_TAG: 1806 NCR_MSGS(("TAG %x:%x", 1807 sc->sc_imess[0], sc->sc_imess[1])); 1808 break; 1809 1810 case MSG_DISCONNECT: 1811 NCR_MSGS(("disconnect ")); 1812 ti->dconns++; 1813 sc->sc_state = NCR_DISCONNECT; 1814 1815 /* 1816 * Mark the fact that all bytes have moved. The 1817 * target may not bother to do a SAVE POINTERS 1818 * at this stage. This flag will set the residual 1819 * count to zero on MSG COMPLETE. 1820 */ 1821 if (sc->sc_dleft == 0) 1822 ecb->flags |= ECB_TENTATIVE_DONE; 1823 break; 1824 1825 case MSG_SAVEDATAPOINTER: 1826 NCR_MSGS(("save datapointer ")); 1827 ecb->daddr = sc->sc_dp; 1828 ecb->dleft = sc->sc_dleft; 1829 break; 1830 1831 case MSG_RESTOREPOINTERS: 1832 NCR_MSGS(("restore datapointer ")); 1833 sc->sc_dp = ecb->daddr; 1834 sc->sc_dleft = ecb->dleft; 1835 break; 1836 1837 case MSG_EXTENDED: 1838 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1839 switch (sc->sc_imess[2]) { 1840 case MSG_EXT_SDTR: 1841 NCR_MSGS(("SDTR period %d, offset %d ", 1842 sc->sc_imess[3], sc->sc_imess[4])); 1843 if (sc->sc_imess[1] != 3) 1844 goto reject;
| 1920 break; 1921 1922 case SEND_INIT_DET_ERR: 1923 goto abort; 1924 } 1925 break; 1926 1927 case MSG_NOOP: 1928 NCR_MSGS(("noop ")); 1929 break; 1930 1931 case MSG_HEAD_OF_Q_TAG: 1932 case MSG_SIMPLE_Q_TAG: 1933 case MSG_ORDERED_Q_TAG: 1934 NCR_MSGS(("TAG %x:%x", 1935 sc->sc_imess[0], sc->sc_imess[1])); 1936 break; 1937 1938 case MSG_DISCONNECT: 1939 NCR_MSGS(("disconnect ")); 1940 ti->dconns++; 1941 sc->sc_state = NCR_DISCONNECT; 1942 1943 /* 1944 * Mark the fact that all bytes have moved. The 1945 * target may not bother to do a SAVE POINTERS 1946 * at this stage. This flag will set the residual 1947 * count to zero on MSG COMPLETE. 1948 */ 1949 if (sc->sc_dleft == 0) 1950 ecb->flags |= ECB_TENTATIVE_DONE; 1951 break; 1952 1953 case MSG_SAVEDATAPOINTER: 1954 NCR_MSGS(("save datapointer ")); 1955 ecb->daddr = sc->sc_dp; 1956 ecb->dleft = sc->sc_dleft; 1957 break; 1958 1959 case MSG_RESTOREPOINTERS: 1960 NCR_MSGS(("restore datapointer ")); 1961 sc->sc_dp = ecb->daddr; 1962 sc->sc_dleft = ecb->dleft; 1963 break; 1964 1965 case MSG_EXTENDED: 1966 NCR_MSGS(("extended(%x) ", sc->sc_imess[2])); 1967 switch (sc->sc_imess[2]) { 1968 case MSG_EXT_SDTR: 1969 NCR_MSGS(("SDTR period %d, offset %d ", 1970 sc->sc_imess[3], sc->sc_imess[4])); 1971 if (sc->sc_imess[1] != 3) 1972 goto reject;
|
1845 ti->period = sc->sc_imess[3]; 1846 ti->offset = sc->sc_imess[4]; 1847 ti->flags &= ~T_NEGOTIATE;
| 1973 ti->curr.period = sc->sc_imess[3]; 1974 ti->curr.offset = sc->sc_imess[4];
|
1848 if (sc->sc_minsync == 0 ||
| 1975 if (sc->sc_minsync == 0 ||
|
1849 ti->offset == 0 || 1850 ti->period > 124) {
| 1976 ti->curr.offset == 0 || 1977 ti->curr.period > 124) {
|
1851#if 0 1852#ifdef NCR53C9X_DEBUG 1853 xpt_print_path(ecb->ccb->ccb_h.path); 1854 printf("async mode\n"); 1855#endif 1856#endif
| 1978#if 0 1979#ifdef NCR53C9X_DEBUG 1980 xpt_print_path(ecb->ccb->ccb_h.path); 1981 printf("async mode\n"); 1982#endif 1983#endif
|
1857 ti->flags &= ~T_SYNCMODE; 1858 if ((sc->sc_flags & NCR_SYNCHNEGO) == 1859 0) {
| 1984 if ((ti->flags & T_SDTRSENT) == 0) {
|
1860 /* 1861 * target initiated negotiation 1862 */
| 1985 /* 1986 * target initiated negotiation 1987 */
|
1863 ti->offset = 0;
| 1988 ti->curr.offset = 0;
|
1864 ncr53c9x_sched_msgout( 1865 SEND_SDTR); 1866 } 1867 } else {
| 1989 ncr53c9x_sched_msgout( 1990 SEND_SDTR); 1991 } 1992 } else {
|
1868 ti->period =
| 1993 ti->curr.period =
|
1869 ncr53c9x_cpb2stp(sc, 1870 ncr53c9x_stp2cpb(sc,
| 1994 ncr53c9x_cpb2stp(sc, 1995 ncr53c9x_stp2cpb(sc,
|
1871 ti->period)); 1872 if ((sc->sc_flags & NCR_SYNCHNEGO) == 1873 0) {
| 1996 ti->curr.period)); 1997 if ((ti->flags & T_SDTRSENT) == 0) {
|
1874 /* 1875 * target initiated negotiation 1876 */
| 1998 /* 1999 * target initiated negotiation 2000 */
|
1877 if (ti->period < sc->sc_minsync) 1878 ti->period =
| 2001 if (ti->curr.period < 2002 sc->sc_minsync) 2003 ti->curr.period =
|
1879 sc->sc_minsync;
| 2004 sc->sc_minsync;
|
1880 if (ti->offset > 15) 1881 ti->offset = 15; 1882 ti->flags &= ~T_SYNCMODE;
| 2005 if (ti->curr.offset > 2006 sc->sc_maxoffset) 2007 ti->curr.offset = 2008 sc->sc_maxoffset;
|
1883 ncr53c9x_sched_msgout( 1884 SEND_SDTR);
| 2009 ncr53c9x_sched_msgout( 2010 SEND_SDTR);
|
1885 } else { 1886 /* We are sync. */ 1887 ti->flags |= T_SYNCMODE;
| |
1888 } 1889 }
| 2011 } 2012 }
|
1890 sc->sc_flags &= ~NCR_SYNCHNEGO;
| 2013 ti->flags &= ~T_SDTRSENT; 2014 ti->goal.period = ti->curr.period; 2015 ti->goal.offset = ti->curr.offset;
|
1891 ncr53c9x_setsync(sc, ti); 1892 break; 1893 1894 case MSG_EXT_WDTR:
| 2016 ncr53c9x_setsync(sc, ti); 2017 break; 2018 2019 case MSG_EXT_WDTR:
|
1895#ifdef NCR53C9X_DEBUG 1896 device_printf(sc->sc_dev, "wide mode %d\n", 1897 sc->sc_imess[3]); 1898#endif 1899 if (sc->sc_imess[3] == 1) { 1900 ti->cfg3 |= NCRFASCFG3_EWIDE; 1901 ncr53c9x_setsync(sc, ti); 1902 } else 1903 ti->width = 0; 1904 /* 1905 * Device started width negotiation. 1906 */
| 2020 NCR_MSGS(("wide mode %d ", sc->sc_imess[3])); 2021 ti->curr.width = sc->sc_imess[3];
|
1907 if (!(ti->flags & T_WDTRSENT))
| 2022 if (!(ti->flags & T_WDTRSENT))
|
| 2023 /* 2024 * target initiated negotiation 2025 */
|
1908 ncr53c9x_sched_msgout(SEND_WDTR);
| 2026 ncr53c9x_sched_msgout(SEND_WDTR);
|
1909 ti->flags &= ~(T_WIDE | T_WDTRSENT);
| 2027 ti->flags &= ~T_WDTRSENT; 2028 ti->goal.width = ti->curr.width; 2029 ncr53c9x_setsync(sc, ti);
|
1910 break; 1911 1912 default: 1913 xpt_print_path(ecb->ccb->ccb_h.path); 1914 printf("unrecognized MESSAGE EXTENDED;" 1915 " sending REJECT\n"); 1916 goto reject; 1917 } 1918 break; 1919 1920 default: 1921 NCR_MSGS(("ident ")); 1922 xpt_print_path(ecb->ccb->ccb_h.path); 1923 printf("unrecognized MESSAGE; sending REJECT\n"); 1924 /* FALLTHROUGH */ 1925 reject: 1926 ncr53c9x_sched_msgout(SEND_REJECT); 1927 break; 1928 } 1929 break; 1930 1931 case NCR_IDENTIFIED: 1932 /* 1933 * IDENTIFY message was received and queue tag is expected 1934 * now. 1935 */ 1936 if ((sc->sc_imess[0] != MSG_SIMPLE_Q_TAG) || 1937 (sc->sc_msgify == 0)) { 1938 device_printf(sc->sc_dev, "TAG reselect without " 1939 "IDENTIFY; MSG %x; sending DEVICE RESET\n", 1940 sc->sc_imess[0]); 1941 goto reset; 1942 } 1943 (void) ncr53c9x_reselect(sc, sc->sc_msgify, 1944 sc->sc_imess[0], sc->sc_imess[1]); 1945 break; 1946 1947 case NCR_RESELECTED: 1948 if (MSG_ISIDENTIFY(sc->sc_imess[1])) { 1949 sc->sc_msgify = sc->sc_imess[1]; 1950 } else { 1951 device_printf(sc->sc_dev, "reselect without IDENTIFY;" 1952 " MSG %x; sending DEVICE RESET\n", sc->sc_imess[1]); 1953 goto reset; 1954 } 1955 (void) ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0); 1956 break; 1957 1958 default: 1959 device_printf(sc->sc_dev, "unexpected MESSAGE IN; " 1960 "sending DEVICE RESET\n"); 1961 /* FALLTHROUGH */ 1962 reset: 1963 ncr53c9x_sched_msgout(SEND_DEV_RESET); 1964 break; 1965 1966 abort: 1967 ncr53c9x_sched_msgout(SEND_ABORT); 1968 } 1969 1970 /* If we have more messages to send set ATN. */
| 2030 break; 2031 2032 default: 2033 xpt_print_path(ecb->ccb->ccb_h.path); 2034 printf("unrecognized MESSAGE EXTENDED;" 2035 " sending REJECT\n"); 2036 goto reject; 2037 } 2038 break; 2039 2040 default: 2041 NCR_MSGS(("ident ")); 2042 xpt_print_path(ecb->ccb->ccb_h.path); 2043 printf("unrecognized MESSAGE; sending REJECT\n"); 2044 /* FALLTHROUGH */ 2045 reject: 2046 ncr53c9x_sched_msgout(SEND_REJECT); 2047 break; 2048 } 2049 break; 2050 2051 case NCR_IDENTIFIED: 2052 /* 2053 * IDENTIFY message was received and queue tag is expected 2054 * now. 2055 */ 2056 if ((sc->sc_imess[0] != MSG_SIMPLE_Q_TAG) || 2057 (sc->sc_msgify == 0)) { 2058 device_printf(sc->sc_dev, "TAG reselect without " 2059 "IDENTIFY; MSG %x; sending DEVICE RESET\n", 2060 sc->sc_imess[0]); 2061 goto reset; 2062 } 2063 (void) ncr53c9x_reselect(sc, sc->sc_msgify, 2064 sc->sc_imess[0], sc->sc_imess[1]); 2065 break; 2066 2067 case NCR_RESELECTED: 2068 if (MSG_ISIDENTIFY(sc->sc_imess[1])) { 2069 sc->sc_msgify = sc->sc_imess[1]; 2070 } else { 2071 device_printf(sc->sc_dev, "reselect without IDENTIFY;" 2072 " MSG %x; sending DEVICE RESET\n", sc->sc_imess[1]); 2073 goto reset; 2074 } 2075 (void) ncr53c9x_reselect(sc, sc->sc_msgify, 0, 0); 2076 break; 2077 2078 default: 2079 device_printf(sc->sc_dev, "unexpected MESSAGE IN; " 2080 "sending DEVICE RESET\n"); 2081 /* FALLTHROUGH */ 2082 reset: 2083 ncr53c9x_sched_msgout(SEND_DEV_RESET); 2084 break; 2085 2086 abort: 2087 ncr53c9x_sched_msgout(SEND_ABORT); 2088 } 2089 2090 /* If we have more messages to send set ATN. */
|
1971 if (sc->sc_msgpriq)
| 2091 if (sc->sc_msgpriq) {
|
1972 NCRCMD(sc, NCRCMD_SETATN);
| 2092 NCRCMD(sc, NCRCMD_SETATN);
|
| 2093 sc->sc_flags |= NCR_ATN; 2094 }
|
1973 1974 /* Acknowledge last message byte. */ 1975 NCRCMD(sc, NCRCMD_MSGOK); 1976 1977 /* Done, reset message pointer. */ 1978 sc->sc_flags &= ~NCR_DROP_MSGI; 1979 sc->sc_imlen = 0; 1980} 1981 1982/* 1983 * Send the highest priority, scheduled message. 1984 */ 1985static void 1986ncr53c9x_msgout(struct ncr53c9x_softc *sc) 1987{ 1988 struct ncr53c9x_tinfo *ti; 1989 struct ncr53c9x_ecb *ecb; 1990 size_t size; 1991#ifdef NCR53C9X_DEBUG 1992 int i; 1993#endif 1994
| 2095 2096 /* Acknowledge last message byte. */ 2097 NCRCMD(sc, NCRCMD_MSGOK); 2098 2099 /* Done, reset message pointer. */ 2100 sc->sc_flags &= ~NCR_DROP_MSGI; 2101 sc->sc_imlen = 0; 2102} 2103 2104/* 2105 * Send the highest priority, scheduled message. 2106 */ 2107static void 2108ncr53c9x_msgout(struct ncr53c9x_softc *sc) 2109{ 2110 struct ncr53c9x_tinfo *ti; 2111 struct ncr53c9x_ecb *ecb; 2112 size_t size; 2113#ifdef NCR53C9X_DEBUG 2114 int i; 2115#endif 2116
|
| 2117 NCR_LOCK_ASSERT(sc, MA_OWNED); 2118
|
1995 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 1996 sc->sc_msgpriq, sc->sc_prevphase)); 1997 1998 /* 1999 * XXX - the NCR_ATN flag is not in sync with the actual ATN 2000 * condition on the SCSI bus. The 53c9x chip 2001 * automatically turns off ATN before sending the 2002 * message byte. (See also the comment below in the 2003 * default case when picking out a message to send.) 2004 */ 2005 if (sc->sc_flags & NCR_ATN) { 2006 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 2007 new: 2008 NCRCMD(sc, NCRCMD_FLUSH); 2009/* DELAY(1); */ 2010 sc->sc_msgoutq = 0; 2011 sc->sc_omlen = 0; 2012 } 2013 } else { 2014 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 2015 ncr53c9x_sched_msgout(sc->sc_msgoutq); 2016 goto new; 2017 } else { 2018 device_printf(sc->sc_dev, "at line %d: unexpected " 2019 "MESSAGE OUT phase\n", __LINE__); 2020 } 2021 } 2022 2023 if (sc->sc_omlen == 0) { 2024 /* Pick up highest priority message. */ 2025 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 2026 sc->sc_msgoutq |= sc->sc_msgout; 2027 sc->sc_msgpriq &= ~sc->sc_msgout; 2028 sc->sc_omlen = 1; /* "Default" message len */ 2029 switch (sc->sc_msgout) { 2030 case SEND_SDTR: 2031 ecb = sc->sc_nexus; 2032 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2033 sc->sc_omess[0] = MSG_EXTENDED; 2034 sc->sc_omess[1] = MSG_EXT_SDTR_LEN; 2035 sc->sc_omess[2] = MSG_EXT_SDTR;
| 2119 NCR_TRACE(("[ncr53c9x_msgout(priq:%x, prevphase:%x)]", 2120 sc->sc_msgpriq, sc->sc_prevphase)); 2121 2122 /* 2123 * XXX - the NCR_ATN flag is not in sync with the actual ATN 2124 * condition on the SCSI bus. The 53c9x chip 2125 * automatically turns off ATN before sending the 2126 * message byte. (See also the comment below in the 2127 * default case when picking out a message to send.) 2128 */ 2129 if (sc->sc_flags & NCR_ATN) { 2130 if (sc->sc_prevphase != MESSAGE_OUT_PHASE) { 2131 new: 2132 NCRCMD(sc, NCRCMD_FLUSH); 2133/* DELAY(1); */ 2134 sc->sc_msgoutq = 0; 2135 sc->sc_omlen = 0; 2136 } 2137 } else { 2138 if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 2139 ncr53c9x_sched_msgout(sc->sc_msgoutq); 2140 goto new; 2141 } else { 2142 device_printf(sc->sc_dev, "at line %d: unexpected " 2143 "MESSAGE OUT phase\n", __LINE__); 2144 } 2145 } 2146 2147 if (sc->sc_omlen == 0) { 2148 /* Pick up highest priority message. */ 2149 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq; 2150 sc->sc_msgoutq |= sc->sc_msgout; 2151 sc->sc_msgpriq &= ~sc->sc_msgout; 2152 sc->sc_omlen = 1; /* "Default" message len */ 2153 switch (sc->sc_msgout) { 2154 case SEND_SDTR: 2155 ecb = sc->sc_nexus; 2156 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2157 sc->sc_omess[0] = MSG_EXTENDED; 2158 sc->sc_omess[1] = MSG_EXT_SDTR_LEN; 2159 sc->sc_omess[2] = MSG_EXT_SDTR;
|
2036 sc->sc_omess[3] = ti->period; 2037 sc->sc_omess[4] = ti->offset;
| 2160 sc->sc_omess[3] = ti->goal.period; 2161 sc->sc_omess[4] = ti->goal.offset;
|
2038 sc->sc_omlen = 5;
| 2162 sc->sc_omlen = 5;
|
2039 if ((sc->sc_flags & NCR_SYNCHNEGO) == 0) { 2040 ti->flags |= T_SYNCMODE; 2041 ncr53c9x_setsync(sc, ti); 2042 }
| |
2043 break; 2044 2045 case SEND_WDTR: 2046 ecb = sc->sc_nexus; 2047 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2048 sc->sc_omess[0] = MSG_EXTENDED; 2049 sc->sc_omess[1] = MSG_EXT_WDTR_LEN; 2050 sc->sc_omess[2] = MSG_EXT_WDTR;
| 2163 break; 2164 2165 case SEND_WDTR: 2166 ecb = sc->sc_nexus; 2167 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2168 sc->sc_omess[0] = MSG_EXTENDED; 2169 sc->sc_omess[1] = MSG_EXT_WDTR_LEN; 2170 sc->sc_omess[2] = MSG_EXT_WDTR;
|
2051 sc->sc_omess[3] = ti->width;
| 2171 sc->sc_omess[3] = ti->goal.width;
|
2052 sc->sc_omlen = 4; 2053 break; 2054 2055 case SEND_IDENTIFY: 2056 if (sc->sc_state != NCR_CONNECTED) { 2057 device_printf(sc->sc_dev, "at line %d: no " 2058 "nexus\n", __LINE__); 2059 } 2060 ecb = sc->sc_nexus; 2061 sc->sc_omess[0] = 2062 MSG_IDENTIFY(ecb->ccb->ccb_h.target_lun, 0); 2063 break; 2064 2065 case SEND_TAG: 2066 if (sc->sc_state != NCR_CONNECTED) { 2067 device_printf(sc->sc_dev, "at line %d: no " 2068 "nexus\n", __LINE__); 2069 } 2070 ecb = sc->sc_nexus; 2071 sc->sc_omess[0] = ecb->tag[0]; 2072 sc->sc_omess[1] = ecb->tag[1]; 2073 sc->sc_omlen = 2; 2074 break; 2075 2076 case SEND_DEV_RESET: 2077 sc->sc_flags |= NCR_ABORTING; 2078 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 2079 ecb = sc->sc_nexus; 2080 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
| 2172 sc->sc_omlen = 4; 2173 break; 2174 2175 case SEND_IDENTIFY: 2176 if (sc->sc_state != NCR_CONNECTED) { 2177 device_printf(sc->sc_dev, "at line %d: no " 2178 "nexus\n", __LINE__); 2179 } 2180 ecb = sc->sc_nexus; 2181 sc->sc_omess[0] = 2182 MSG_IDENTIFY(ecb->ccb->ccb_h.target_lun, 0); 2183 break; 2184 2185 case SEND_TAG: 2186 if (sc->sc_state != NCR_CONNECTED) { 2187 device_printf(sc->sc_dev, "at line %d: no " 2188 "nexus\n", __LINE__); 2189 } 2190 ecb = sc->sc_nexus; 2191 sc->sc_omess[0] = ecb->tag[0]; 2192 sc->sc_omess[1] = ecb->tag[1]; 2193 sc->sc_omlen = 2; 2194 break; 2195 2196 case SEND_DEV_RESET: 2197 sc->sc_flags |= NCR_ABORTING; 2198 sc->sc_omess[0] = MSG_BUS_DEV_RESET; 2199 ecb = sc->sc_nexus; 2200 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
|
2081 ti->flags &= ~T_SYNCMODE; 2082 if ((ti->flags & T_SYNCHOFF) == 0) 2083 /* We can re-start sync negotiation. */ 2084 ti->flags |= T_NEGOTIATE;
| 2201 ti->curr.period = 0; 2202 ti->curr.offset = 0; 2203 ti->curr.width = MSG_EXT_WDTR_BUS_8_BIT;
|
2085 break; 2086 2087 case SEND_PARITY_ERROR: 2088 sc->sc_omess[0] = MSG_PARITY_ERROR; 2089 break; 2090 2091 case SEND_ABORT: 2092 sc->sc_flags |= NCR_ABORTING; 2093 sc->sc_omess[0] = MSG_ABORT; 2094 break; 2095 2096 case SEND_INIT_DET_ERR: 2097 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 2098 break; 2099 2100 case SEND_REJECT: 2101 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 2102 break; 2103 2104 default: 2105 /* 2106 * We normally do not get here, since the chip 2107 * automatically turns off ATN before the last 2108 * byte of a message is sent to the target. 2109 * However, if the target rejects our (multi-byte) 2110 * message early by switching to MSG IN phase 2111 * ATN remains on, so the target may return to 2112 * MSG OUT phase. If there are no scheduled messages 2113 * left we send a NO-OP. 2114 * 2115 * XXX - Note that this leaves no useful purpose for 2116 * the NCR_ATN flag. 2117 */ 2118 sc->sc_flags &= ~NCR_ATN; 2119 sc->sc_omess[0] = MSG_NOOP; 2120 } 2121 sc->sc_omp = sc->sc_omess; 2122 } 2123 2124#ifdef NCR53C9X_DEBUG 2125 if (ncr53c9x_debug & NCR_SHOWMSGS) { 2126 NCR_MSGS(("<msgout:")); 2127 for (i = 0; i < sc->sc_omlen; i++) 2128 NCR_MSGS((" %02x", sc->sc_omess[i])); 2129 NCR_MSGS(("> ")); 2130 } 2131#endif 2132 if (sc->sc_rev == NCR_VARIANT_FAS366) { 2133 /* 2134 * XXX FIFO size 2135 */ 2136 ncr53c9x_flushfifo(sc); 2137 ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen); 2138 NCRCMD(sc, NCRCMD_TRANS); 2139 } else { 2140 /* (Re)send the message. */
| 2204 break; 2205 2206 case SEND_PARITY_ERROR: 2207 sc->sc_omess[0] = MSG_PARITY_ERROR; 2208 break; 2209 2210 case SEND_ABORT: 2211 sc->sc_flags |= NCR_ABORTING; 2212 sc->sc_omess[0] = MSG_ABORT; 2213 break; 2214 2215 case SEND_INIT_DET_ERR: 2216 sc->sc_omess[0] = MSG_INITIATOR_DET_ERR; 2217 break; 2218 2219 case SEND_REJECT: 2220 sc->sc_omess[0] = MSG_MESSAGE_REJECT; 2221 break; 2222 2223 default: 2224 /* 2225 * We normally do not get here, since the chip 2226 * automatically turns off ATN before the last 2227 * byte of a message is sent to the target. 2228 * However, if the target rejects our (multi-byte) 2229 * message early by switching to MSG IN phase 2230 * ATN remains on, so the target may return to 2231 * MSG OUT phase. If there are no scheduled messages 2232 * left we send a NO-OP. 2233 * 2234 * XXX - Note that this leaves no useful purpose for 2235 * the NCR_ATN flag. 2236 */ 2237 sc->sc_flags &= ~NCR_ATN; 2238 sc->sc_omess[0] = MSG_NOOP; 2239 } 2240 sc->sc_omp = sc->sc_omess; 2241 } 2242 2243#ifdef NCR53C9X_DEBUG 2244 if (ncr53c9x_debug & NCR_SHOWMSGS) { 2245 NCR_MSGS(("<msgout:")); 2246 for (i = 0; i < sc->sc_omlen; i++) 2247 NCR_MSGS((" %02x", sc->sc_omess[i])); 2248 NCR_MSGS(("> ")); 2249 } 2250#endif 2251 if (sc->sc_rev == NCR_VARIANT_FAS366) { 2252 /* 2253 * XXX FIFO size 2254 */ 2255 ncr53c9x_flushfifo(sc); 2256 ncr53c9x_wrfifo(sc, sc->sc_omp, sc->sc_omlen); 2257 NCRCMD(sc, NCRCMD_TRANS); 2258 } else { 2259 /* (Re)send the message. */
|
2141 size = min(sc->sc_omlen, sc->sc_maxxfer);
| 2260 size = ulmin(sc->sc_omlen, sc->sc_maxxfer);
|
2142 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 2143 /* Program the SCSI counter. */ 2144 NCR_SET_COUNT(sc, size); 2145 2146 /* Load the count in and start the message-out transfer. */ 2147 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 2148 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2149 NCRDMA_GO(sc); 2150 } 2151} 2152
| 2261 NCRDMA_SETUP(sc, &sc->sc_omp, &sc->sc_omlen, 0, &size); 2262 /* Program the SCSI counter. */ 2263 NCR_SET_COUNT(sc, size); 2264 2265 /* Load the count in and start the message-out transfer. */ 2266 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 2267 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2268 NCRDMA_GO(sc); 2269 } 2270} 2271
|
| 2272void 2273ncr53c9x_intr(void *arg) 2274{ 2275 struct ncr53c9x_softc *sc = arg; 2276 2277 if (!NCRDMA_ISINTR(sc)) 2278 return; 2279 2280 NCR_LOCK(sc); 2281 2282 ncr53c9x_intr1(sc); 2283 2284 NCR_UNLOCK(sc); 2285} 2286
|
2153/* 2154 * This is the most critical part of the driver, and has to know 2155 * how to deal with *all* error conditions and phases from the SCSI 2156 * bus. If there are no errors and the DMA was active, then call the 2157 * DMA pseudo-interrupt handler. If this returns 1, then that was it 2158 * and we can return from here without further processing. 2159 * 2160 * Most of this needs verifying. 2161 */
| 2287/* 2288 * This is the most critical part of the driver, and has to know 2289 * how to deal with *all* error conditions and phases from the SCSI 2290 * bus. If there are no errors and the DMA was active, then call the 2291 * DMA pseudo-interrupt handler. If this returns 1, then that was it 2292 * and we can return from here without further processing. 2293 * 2294 * Most of this needs verifying. 2295 */
|
2162void 2163ncr53c9x_intr(void *arg)
| 2296static void 2297ncr53c9x_intr1(struct ncr53c9x_softc *sc)
|
2164{
| 2298{
|
2165 struct ncr53c9x_softc *sc = arg;
| |
2166 struct ncr53c9x_ecb *ecb; 2167 struct ncr53c9x_linfo *li; 2168 struct ncr53c9x_tinfo *ti; 2169 struct timeval cur, wait; 2170 size_t size; 2171 int i, nfifo; 2172 u_char msg; 2173
| 2299 struct ncr53c9x_ecb *ecb; 2300 struct ncr53c9x_linfo *li; 2301 struct ncr53c9x_tinfo *ti; 2302 struct timeval cur, wait; 2303 size_t size; 2304 int i, nfifo; 2305 u_char msg; 2306
|
| 2307 NCR_LOCK_ASSERT(sc, MA_OWNED); 2308
|
2174 NCR_INTS(("[ncr53c9x_intr: state %d]", sc->sc_state)); 2175
| 2309 NCR_INTS(("[ncr53c9x_intr: state %d]", sc->sc_state)); 2310
|
2176 if (!NCRDMA_ISINTR(sc)) 2177 return; 2178 2179 mtx_lock(&sc->sc_lock);
| |
2180again: 2181 /* and what do the registers say... */ 2182 ncr53c9x_readregs(sc); 2183 2184 /* 2185 * At the moment, only a SCSI Bus Reset or Illegal 2186 * Command are classed as errors. A disconnect is a 2187 * valid condition, and we let the code check is the 2188 * "NCR_BUSFREE_OK" flag was set before declaring it 2189 * and error. 2190 * 2191 * Also, the status register tells us about "Gross 2192 * Errors" and "Parity errors". Only the Gross Error 2193 * is really bad, and the parity errors are dealt 2194 * with later. 2195 * 2196 * TODO 2197 * If there are too many parity error, go to slow 2198 * cable mode? 2199 */ 2200 2201 if ((sc->sc_espintr & NCRINTR_SBR) != 0) { 2202 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 0) { 2203 NCRCMD(sc, NCRCMD_FLUSH); 2204 DELAY(1); 2205 } 2206 if (sc->sc_state != NCR_SBR) { 2207 device_printf(sc->sc_dev, "SCSI bus reset\n"); 2208 ncr53c9x_init(sc, 0); /* Restart everything. */
| 2311again: 2312 /* and what do the registers say... */ 2313 ncr53c9x_readregs(sc); 2314 2315 /* 2316 * At the moment, only a SCSI Bus Reset or Illegal 2317 * Command are classed as errors. A disconnect is a 2318 * valid condition, and we let the code check is the 2319 * "NCR_BUSFREE_OK" flag was set before declaring it 2320 * and error. 2321 * 2322 * Also, the status register tells us about "Gross 2323 * Errors" and "Parity errors". Only the Gross Error 2324 * is really bad, and the parity errors are dealt 2325 * with later. 2326 * 2327 * TODO 2328 * If there are too many parity error, go to slow 2329 * cable mode? 2330 */ 2331 2332 if ((sc->sc_espintr & NCRINTR_SBR) != 0) { 2333 if ((NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) != 0) { 2334 NCRCMD(sc, NCRCMD_FLUSH); 2335 DELAY(1); 2336 } 2337 if (sc->sc_state != NCR_SBR) { 2338 device_printf(sc->sc_dev, "SCSI bus reset\n"); 2339 ncr53c9x_init(sc, 0); /* Restart everything. */
|
2209 goto out;
| 2340 return;
|
2210 } 2211#if 0
| 2341 } 2342#if 0
|
2212/*XXX*/ printf("<expected bus reset: "
| 2343/*XXX*/ device_printf(sc->sc_dev, "<expected bus reset: "
|
2213 "[intr %x, stat %x, step %d]>\n", 2214 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2215#endif 2216 if (sc->sc_nexus != NULL) 2217 panic("%s: nexus in reset state", 2218 device_get_nameunit(sc->sc_dev)); 2219 goto sched; 2220 } 2221 2222 ecb = sc->sc_nexus; 2223 2224#define NCRINTR_ERR (NCRINTR_SBR | NCRINTR_ILL) 2225 if (sc->sc_espintr & NCRINTR_ERR || 2226 sc->sc_espstat & NCRSTAT_GE) { 2227 if ((sc->sc_espstat & NCRSTAT_GE) != 0) { 2228 /* Gross Error; no target? */ 2229 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2230 NCRCMD(sc, NCRCMD_FLUSH); 2231 DELAY(1); 2232 } 2233 if (sc->sc_state == NCR_CONNECTED || 2234 sc->sc_state == NCR_SELECTING) { 2235 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2236 ncr53c9x_done(sc, ecb); 2237 }
| 2344 "[intr %x, stat %x, step %d]>\n", 2345 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2346#endif 2347 if (sc->sc_nexus != NULL) 2348 panic("%s: nexus in reset state", 2349 device_get_nameunit(sc->sc_dev)); 2350 goto sched; 2351 } 2352 2353 ecb = sc->sc_nexus; 2354 2355#define NCRINTR_ERR (NCRINTR_SBR | NCRINTR_ILL) 2356 if (sc->sc_espintr & NCRINTR_ERR || 2357 sc->sc_espstat & NCRSTAT_GE) { 2358 if ((sc->sc_espstat & NCRSTAT_GE) != 0) { 2359 /* Gross Error; no target? */ 2360 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2361 NCRCMD(sc, NCRCMD_FLUSH); 2362 DELAY(1); 2363 } 2364 if (sc->sc_state == NCR_CONNECTED || 2365 sc->sc_state == NCR_SELECTING) { 2366 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2367 ncr53c9x_done(sc, ecb); 2368 }
|
2238 goto out;
| 2369 return;
|
2239 } 2240 2241 if ((sc->sc_espintr & NCRINTR_ILL) != 0) { 2242 if ((sc->sc_flags & NCR_EXPECT_ILLCMD) != 0) { 2243 /* 2244 * Eat away "Illegal command" interrupt 2245 * on a ESP100 caused by a re-selection 2246 * while we were trying to select 2247 * another target. 2248 */ 2249#ifdef DEBUG 2250 device_printf(sc->sc_dev, "ESP100 work-around " 2251 "activated\n"); 2252#endif 2253 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
| 2370 } 2371 2372 if ((sc->sc_espintr & NCRINTR_ILL) != 0) { 2373 if ((sc->sc_flags & NCR_EXPECT_ILLCMD) != 0) { 2374 /* 2375 * Eat away "Illegal command" interrupt 2376 * on a ESP100 caused by a re-selection 2377 * while we were trying to select 2378 * another target. 2379 */ 2380#ifdef DEBUG 2381 device_printf(sc->sc_dev, "ESP100 work-around " 2382 "activated\n"); 2383#endif 2384 sc->sc_flags &= ~NCR_EXPECT_ILLCMD;
|
2254 goto out;
| 2385 return;
|
2255 } 2256 /* Illegal command, out of sync? */ 2257 device_printf(sc->sc_dev, "illegal command: 0x%x " 2258 "(state %d, phase %x, prevphase %x)\n", 2259 sc->sc_lastcmd, 2260 sc->sc_state, sc->sc_phase, sc->sc_prevphase); 2261 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2262 NCRCMD(sc, NCRCMD_FLUSH); 2263 DELAY(1); 2264 }
| 2386 } 2387 /* Illegal command, out of sync? */ 2388 device_printf(sc->sc_dev, "illegal command: 0x%x " 2389 "(state %d, phase %x, prevphase %x)\n", 2390 sc->sc_lastcmd, 2391 sc->sc_state, sc->sc_phase, sc->sc_prevphase); 2392 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2393 NCRCMD(sc, NCRCMD_FLUSH); 2394 DELAY(1); 2395 }
|
2265 ncr53c9x_init(sc, 1); /* Restart everything. */ 2266 goto out;
| 2396 goto reset;
|
2267 } 2268 } 2269 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 2270 2271 /* 2272 * Call if DMA is active. 2273 * 2274 * If DMA_INTR returns true, then maybe go 'round the loop 2275 * again in case there is no more DMA queued, but a phase 2276 * change is expected. 2277 */ 2278 if (NCRDMA_ISACTIVE(sc)) { 2279 if (NCRDMA_INTR(sc) == -1) { 2280 device_printf(sc->sc_dev, "DMA error; resetting\n");
| 2397 } 2398 } 2399 sc->sc_flags &= ~NCR_EXPECT_ILLCMD; 2400 2401 /* 2402 * Call if DMA is active. 2403 * 2404 * If DMA_INTR returns true, then maybe go 'round the loop 2405 * again in case there is no more DMA queued, but a phase 2406 * change is expected. 2407 */ 2408 if (NCRDMA_ISACTIVE(sc)) { 2409 if (NCRDMA_INTR(sc) == -1) { 2410 device_printf(sc->sc_dev, "DMA error; resetting\n");
|
2281 ncr53c9x_init(sc, 1); 2282 goto out;
| 2411 goto reset;
|
2283 } 2284 /* If DMA active here, then go back to work... */ 2285 if (NCRDMA_ISACTIVE(sc))
| 2412 } 2413 /* If DMA active here, then go back to work... */ 2414 if (NCRDMA_ISACTIVE(sc))
|
2286 goto out;
| 2415 return;
|
2287 2288 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 2289 /* 2290 * DMA not completed. If we can not find a 2291 * acceptable explanation, print a diagnostic. 2292 */ 2293 if (sc->sc_state == NCR_SELECTING) 2294 /* 2295 * This can happen if we are reselected 2296 * while using DMA to select a target. 2297 */ 2298 /*void*/; 2299 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 2300 /* 2301 * Our (multi-byte) message (eg SDTR) was 2302 * interrupted by the target to send 2303 * a MSG REJECT. 2304 * Print diagnostic if current phase 2305 * is not MESSAGE IN. 2306 */ 2307 if (sc->sc_phase != MESSAGE_IN_PHASE) 2308 device_printf(sc->sc_dev,"!TC on MSGOUT" 2309 " [intr %x, stat %x, step %d]" 2310 " prevphase %x, resid %lx\n", 2311 sc->sc_espintr, 2312 sc->sc_espstat, 2313 sc->sc_espstep, 2314 sc->sc_prevphase, 2315 (u_long)sc->sc_omlen); 2316 } else if (sc->sc_dleft == 0) { 2317 /* 2318 * The DMA operation was started for 2319 * a DATA transfer. Print a diagnostic 2320 * if the DMA counter and TC bit 2321 * appear to be out of sync. 2322 * 2323 * XXX This is fatal and usually means that 2324 * the DMA engine is hopelessly out of 2325 * sync with reality. A disk is likely 2326 * getting spammed at this point. 2327 */ 2328 device_printf(sc->sc_dev, "!TC on DATA XFER" 2329 " [intr %x, stat %x, step %d]" 2330 " prevphase %x, resid %x\n", 2331 sc->sc_espintr, 2332 sc->sc_espstat, 2333 sc->sc_espstep, 2334 sc->sc_prevphase, 2335 ecb ? ecb->dleft : -1);
| 2416 2417 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 2418 /* 2419 * DMA not completed. If we can not find a 2420 * acceptable explanation, print a diagnostic. 2421 */ 2422 if (sc->sc_state == NCR_SELECTING) 2423 /* 2424 * This can happen if we are reselected 2425 * while using DMA to select a target. 2426 */ 2427 /*void*/; 2428 else if (sc->sc_prevphase == MESSAGE_OUT_PHASE) { 2429 /* 2430 * Our (multi-byte) message (eg SDTR) was 2431 * interrupted by the target to send 2432 * a MSG REJECT. 2433 * Print diagnostic if current phase 2434 * is not MESSAGE IN. 2435 */ 2436 if (sc->sc_phase != MESSAGE_IN_PHASE) 2437 device_printf(sc->sc_dev,"!TC on MSGOUT" 2438 " [intr %x, stat %x, step %d]" 2439 " prevphase %x, resid %lx\n", 2440 sc->sc_espintr, 2441 sc->sc_espstat, 2442 sc->sc_espstep, 2443 sc->sc_prevphase, 2444 (u_long)sc->sc_omlen); 2445 } else if (sc->sc_dleft == 0) { 2446 /* 2447 * The DMA operation was started for 2448 * a DATA transfer. Print a diagnostic 2449 * if the DMA counter and TC bit 2450 * appear to be out of sync. 2451 * 2452 * XXX This is fatal and usually means that 2453 * the DMA engine is hopelessly out of 2454 * sync with reality. A disk is likely 2455 * getting spammed at this point. 2456 */ 2457 device_printf(sc->sc_dev, "!TC on DATA XFER" 2458 " [intr %x, stat %x, step %d]" 2459 " prevphase %x, resid %x\n", 2460 sc->sc_espintr, 2461 sc->sc_espstat, 2462 sc->sc_espstep, 2463 sc->sc_prevphase, 2464 ecb ? ecb->dleft : -1);
|
2336 panic("esp: unrecoverable DMA error");
| 2465 goto reset;
|
2337 } 2338 } 2339 } 2340 2341 /* 2342 * Check for less serious errors. 2343 */ 2344 if ((sc->sc_espstat & NCRSTAT_PE) != 0) { 2345 device_printf(sc->sc_dev, "SCSI bus parity error\n"); 2346 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 2347 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 2348 else 2349 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 2350 } 2351 2352 if ((sc->sc_espintr & NCRINTR_DIS) != 0) { 2353 sc->sc_msgify = 0; 2354 NCR_INTS(("<DISC [intr %x, stat %x, step %d]>", 2355 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 2356 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2357 NCRCMD(sc, NCRCMD_FLUSH); 2358/* DELAY(1); */ 2359 } 2360 /* 2361 * This command must (apparently) be issued within 2362 * 250mS of a disconnect. So here you are... 2363 */ 2364 NCRCMD(sc, NCRCMD_ENSEL); 2365 2366 switch (sc->sc_state) { 2367 case NCR_RESELECTED: 2368 goto sched; 2369 2370 case NCR_SELECTING: 2371 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2372 2373 /* Selection timeout -- discard all LUNs if empty. */ 2374 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2375 li = LIST_FIRST(&ti->luns); 2376 while (li != NULL) { 2377 if (li->untagged == NULL && li->used == 0) { 2378 if (li->lun < NCR_NLUN) 2379 ti->lun[li->lun] = NULL; 2380 LIST_REMOVE(li, link); 2381 free(li, M_DEVBUF); 2382 /* 2383 * Restart the search at the beginning. 2384 */ 2385 li = LIST_FIRST(&ti->luns); 2386 continue; 2387 } 2388 li = LIST_NEXT(li, link); 2389 } 2390 goto finish; 2391 2392 case NCR_CONNECTED:
| 2466 } 2467 } 2468 } 2469 2470 /* 2471 * Check for less serious errors. 2472 */ 2473 if ((sc->sc_espstat & NCRSTAT_PE) != 0) { 2474 device_printf(sc->sc_dev, "SCSI bus parity error\n"); 2475 if (sc->sc_prevphase == MESSAGE_IN_PHASE) 2476 ncr53c9x_sched_msgout(SEND_PARITY_ERROR); 2477 else 2478 ncr53c9x_sched_msgout(SEND_INIT_DET_ERR); 2479 } 2480 2481 if ((sc->sc_espintr & NCRINTR_DIS) != 0) { 2482 sc->sc_msgify = 0; 2483 NCR_INTS(("<DISC [intr %x, stat %x, step %d]>", 2484 sc->sc_espintr,sc->sc_espstat,sc->sc_espstep)); 2485 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2486 NCRCMD(sc, NCRCMD_FLUSH); 2487/* DELAY(1); */ 2488 } 2489 /* 2490 * This command must (apparently) be issued within 2491 * 250mS of a disconnect. So here you are... 2492 */ 2493 NCRCMD(sc, NCRCMD_ENSEL); 2494 2495 switch (sc->sc_state) { 2496 case NCR_RESELECTED: 2497 goto sched; 2498 2499 case NCR_SELECTING: 2500 ecb->ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2501 2502 /* Selection timeout -- discard all LUNs if empty. */ 2503 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2504 li = LIST_FIRST(&ti->luns); 2505 while (li != NULL) { 2506 if (li->untagged == NULL && li->used == 0) { 2507 if (li->lun < NCR_NLUN) 2508 ti->lun[li->lun] = NULL; 2509 LIST_REMOVE(li, link); 2510 free(li, M_DEVBUF); 2511 /* 2512 * Restart the search at the beginning. 2513 */ 2514 li = LIST_FIRST(&ti->luns); 2515 continue; 2516 } 2517 li = LIST_NEXT(li, link); 2518 } 2519 goto finish; 2520 2521 case NCR_CONNECTED:
|
2393 if ((sc->sc_flags & NCR_SYNCHNEGO) != 0) { 2394#ifdef NCR53C9X_DEBUG 2395 if (ecb != NULL) 2396 xpt_print_path(ecb->ccb->ccb_h.path); 2397 printf("sync nego not completed!\n"); 2398#endif
| 2522 if (ecb != NULL) {
|
2399 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
| 2523 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
|
2400 sc->sc_flags &= ~NCR_SYNCHNEGO; 2401 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE);
| 2524 if ((ti->flags & T_SDTRSENT) != 0) { 2525 xpt_print_path(ecb->ccb->ccb_h.path); 2526 printf("sync nego not completed!\n"); 2527 ti->flags &= ~T_SDTRSENT; 2528 ti->curr.period = ti->goal.period = 0; 2529 ti->curr.offset = ti->goal.offset = 0; 2530 ncr53c9x_setsync(sc, ti); 2531 } 2532 if ((ti->flags & T_WDTRSENT) != 0) { 2533 xpt_print_path(ecb->ccb->ccb_h.path); 2534 printf("wide nego not completed!\n"); 2535 ti->flags &= ~T_WDTRSENT; 2536 ti->curr.width = ti->goal.width = 2537 MSG_EXT_WDTR_BUS_8_BIT; 2538 ncr53c9x_setsync(sc, ti); 2539 }
|
2402 } 2403 2404 /* It may be OK to disconnect. */ 2405 if ((sc->sc_flags & NCR_ABORTING) == 0) { 2406 /* 2407 * Section 5.1.1 of the SCSI 2 spec 2408 * suggests issuing a REQUEST SENSE 2409 * following an unexpected disconnect. 2410 * Some devices go into a contingent 2411 * allegiance condition when 2412 * disconnecting, and this is necessary 2413 * to clean up their state. 2414 */ 2415 device_printf(sc->sc_dev, "unexpected " 2416 "disconnect [state %d, intr %x, stat %x, " 2417 "phase(c %x, p %x)]; ", sc->sc_state, 2418 sc->sc_espintr, sc->sc_espstat, 2419 sc->sc_phase, sc->sc_prevphase); 2420 2421 /* 2422 * XXX This will cause a chip reset and will 2423 * prevent us from finding out the real 2424 * problem with the device. However, it's 2425 * neccessary until a way can be found to 2426 * safely cancel the DMA that is in 2427 * progress. 2428 */ 2429 if (1 || (ecb->flags & ECB_SENSE) != 0) { 2430 printf("resetting\n"); 2431 goto reset; 2432 } 2433 printf("sending REQUEST SENSE\n");
| 2540 } 2541 2542 /* It may be OK to disconnect. */ 2543 if ((sc->sc_flags & NCR_ABORTING) == 0) { 2544 /* 2545 * Section 5.1.1 of the SCSI 2 spec 2546 * suggests issuing a REQUEST SENSE 2547 * following an unexpected disconnect. 2548 * Some devices go into a contingent 2549 * allegiance condition when 2550 * disconnecting, and this is necessary 2551 * to clean up their state. 2552 */ 2553 device_printf(sc->sc_dev, "unexpected " 2554 "disconnect [state %d, intr %x, stat %x, " 2555 "phase(c %x, p %x)]; ", sc->sc_state, 2556 sc->sc_espintr, sc->sc_espstat, 2557 sc->sc_phase, sc->sc_prevphase); 2558 2559 /* 2560 * XXX This will cause a chip reset and will 2561 * prevent us from finding out the real 2562 * problem with the device. However, it's 2563 * neccessary until a way can be found to 2564 * safely cancel the DMA that is in 2565 * progress. 2566 */ 2567 if (1 || (ecb->flags & ECB_SENSE) != 0) { 2568 printf("resetting\n"); 2569 goto reset; 2570 } 2571 printf("sending REQUEST SENSE\n");
|
2434 untimeout(ncr53c9x_timeout, ecb, 2435 ecb->ccb->ccb_h.timeout_ch);
| 2572 callout_stop(&ecb->ch);
|
2436 ncr53c9x_sense(sc, ecb);
| 2573 ncr53c9x_sense(sc, ecb);
|
2437 goto out;
| 2574 return; 2575 } else if (ecb != NULL && 2576 (ecb->flags & ECB_RESET) != 0) { 2577 ecb->ccb->ccb_h.status = CAM_REQ_CMP; 2578 goto finish;
|
2438 } 2439 2440 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT; 2441 goto finish; 2442 2443 case NCR_DISCONNECT: 2444 sc->sc_nexus = NULL; 2445 goto sched; 2446 2447 case NCR_CMDCOMPLETE: 2448 ecb->ccb->ccb_h.status = CAM_REQ_CMP; 2449 goto finish; 2450 } 2451 } 2452 2453 switch (sc->sc_state) { 2454 case NCR_SBR: 2455 device_printf(sc->sc_dev, "waiting for Bus Reset to happen\n");
| 2579 } 2580 2581 ecb->ccb->ccb_h.status = CAM_CMD_TIMEOUT; 2582 goto finish; 2583 2584 case NCR_DISCONNECT: 2585 sc->sc_nexus = NULL; 2586 goto sched; 2587 2588 case NCR_CMDCOMPLETE: 2589 ecb->ccb->ccb_h.status = CAM_REQ_CMP; 2590 goto finish; 2591 } 2592 } 2593 2594 switch (sc->sc_state) { 2595 case NCR_SBR: 2596 device_printf(sc->sc_dev, "waiting for Bus Reset to happen\n");
|
2456 goto out;
| 2597 return;
|
2457 2458 case NCR_RESELECTED: 2459 /* 2460 * We must be continuing a message? 2461 */ 2462 device_printf(sc->sc_dev, "unhandled reselect continuation, " 2463 "state %d, intr %02x\n", sc->sc_state, sc->sc_espintr);
| 2598 2599 case NCR_RESELECTED: 2600 /* 2601 * We must be continuing a message? 2602 */ 2603 device_printf(sc->sc_dev, "unhandled reselect continuation, " 2604 "state %d, intr %02x\n", sc->sc_state, sc->sc_espintr);
|
2464 ncr53c9x_init(sc, 1); 2465 goto out;
| 2605 goto reset;
|
2466 break; 2467 2468 case NCR_IDENTIFIED: 2469 ecb = sc->sc_nexus; 2470 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2471 i = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 2472 /* 2473 * Things are seriously screwed up. 2474 * Pull the brakes, i.e. reset. 2475 */ 2476 device_printf(sc->sc_dev, "target didn't send tag: %d " 2477 "bytes in FIFO\n", i); 2478 /* Drain and display FIFO. */ 2479 while (i-- > 0) 2480 printf("[%d] ", NCR_READ_REG(sc, NCR_FIFO)); 2481
| 2606 break; 2607 2608 case NCR_IDENTIFIED: 2609 ecb = sc->sc_nexus; 2610 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2611 i = NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 2612 /* 2613 * Things are seriously screwed up. 2614 * Pull the brakes, i.e. reset. 2615 */ 2616 device_printf(sc->sc_dev, "target didn't send tag: %d " 2617 "bytes in FIFO\n", i); 2618 /* Drain and display FIFO. */ 2619 while (i-- > 0) 2620 printf("[%d] ", NCR_READ_REG(sc, NCR_FIFO)); 2621
|
2482 ncr53c9x_init(sc, 1); 2483 goto out;
| 2622 goto reset;
|
2484 } else 2485 goto msgin; 2486 2487 case NCR_IDLE: 2488 case NCR_SELECTING: 2489 ecb = sc->sc_nexus; 2490 if (sc->sc_espintr & NCRINTR_RESEL) { 2491 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 2492 sc->sc_flags = 0; 2493 /* 2494 * If we're trying to select a 2495 * target ourselves, push our command 2496 * back into the ready list. 2497 */ 2498 if (sc->sc_state == NCR_SELECTING) { 2499 NCR_INTS(("backoff selector "));
| 2623 } else 2624 goto msgin; 2625 2626 case NCR_IDLE: 2627 case NCR_SELECTING: 2628 ecb = sc->sc_nexus; 2629 if (sc->sc_espintr & NCRINTR_RESEL) { 2630 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0; 2631 sc->sc_flags = 0; 2632 /* 2633 * If we're trying to select a 2634 * target ourselves, push our command 2635 * back into the ready list. 2636 */ 2637 if (sc->sc_state == NCR_SELECTING) { 2638 NCR_INTS(("backoff selector "));
|
2500 untimeout(ncr53c9x_timeout, ecb, 2501 ecb->ccb->ccb_h.timeout_ch);
| 2639 callout_stop(&ecb->ch);
|
2502 ncr53c9x_dequeue(sc, ecb); 2503 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2504 ecb->flags |= ECB_READY; 2505 ecb = sc->sc_nexus = NULL; 2506 } 2507 sc->sc_state = NCR_RESELECTED; 2508 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2509 /* 2510 * Things are seriously screwed up. 2511 * Pull the brakes, i.e. reset 2512 */ 2513 device_printf(sc->sc_dev, "target didn't " 2514 "identify\n");
| 2640 ncr53c9x_dequeue(sc, ecb); 2641 TAILQ_INSERT_HEAD(&sc->ready_list, ecb, chain); 2642 ecb->flags |= ECB_READY; 2643 ecb = sc->sc_nexus = NULL; 2644 } 2645 sc->sc_state = NCR_RESELECTED; 2646 if (sc->sc_phase != MESSAGE_IN_PHASE) { 2647 /* 2648 * Things are seriously screwed up. 2649 * Pull the brakes, i.e. reset 2650 */ 2651 device_printf(sc->sc_dev, "target didn't " 2652 "identify\n");
|
2515 ncr53c9x_init(sc, 1); 2516 goto out;
| 2653 goto reset;
|
2517 } 2518 /* 2519 * The C90 only inhibits FIFO writes until reselection 2520 * is complete instead of waiting until the interrupt 2521 * status register has been read. So, if the reselect 2522 * happens while we were entering command bytes (for 2523 * another target) some of those bytes can appear in 2524 * the FIFO here, after the interrupt is taken. 2525 * 2526 * To remedy this situation, pull the Selection ID 2527 * and Identify message from the FIFO directly, and 2528 * ignore any extraneous FIFO contents. Also, set 2529 * a flag that allows one Illegal Command Interrupt 2530 * to occur which the chip also generates as a result 2531 * of writing to the FIFO during a reselect. 2532 */ 2533 if (sc->sc_rev == NCR_VARIANT_ESP100) { 2534 nfifo = 2535 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 2536 sc->sc_imess[0] = NCR_READ_REG(sc, NCR_FIFO); 2537 sc->sc_imess[1] = NCR_READ_REG(sc, NCR_FIFO); 2538 sc->sc_imlen = 2; 2539 if (nfifo != 2) { 2540 /* Flush the rest. */ 2541 NCRCMD(sc, NCRCMD_FLUSH); 2542 } 2543 sc->sc_flags |= NCR_EXPECT_ILLCMD; 2544 if (nfifo > 2) 2545 nfifo = 2; /* We fixed it... */ 2546 } else 2547 nfifo = ncr53c9x_rdfifo(sc, NCR_RDFIFO_START); 2548 2549 if (nfifo != 2) { 2550 device_printf(sc->sc_dev, "RESELECT: %d bytes " 2551 "in FIFO! [intr %x, stat %x, step %d, " 2552 "prevphase %x]\n", 2553 nfifo, 2554 sc->sc_espintr, 2555 sc->sc_espstat, 2556 sc->sc_espstep, 2557 sc->sc_prevphase);
| 2654 } 2655 /* 2656 * The C90 only inhibits FIFO writes until reselection 2657 * is complete instead of waiting until the interrupt 2658 * status register has been read. So, if the reselect 2659 * happens while we were entering command bytes (for 2660 * another target) some of those bytes can appear in 2661 * the FIFO here, after the interrupt is taken. 2662 * 2663 * To remedy this situation, pull the Selection ID 2664 * and Identify message from the FIFO directly, and 2665 * ignore any extraneous FIFO contents. Also, set 2666 * a flag that allows one Illegal Command Interrupt 2667 * to occur which the chip also generates as a result 2668 * of writing to the FIFO during a reselect. 2669 */ 2670 if (sc->sc_rev == NCR_VARIANT_ESP100) { 2671 nfifo = 2672 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF; 2673 sc->sc_imess[0] = NCR_READ_REG(sc, NCR_FIFO); 2674 sc->sc_imess[1] = NCR_READ_REG(sc, NCR_FIFO); 2675 sc->sc_imlen = 2; 2676 if (nfifo != 2) { 2677 /* Flush the rest. */ 2678 NCRCMD(sc, NCRCMD_FLUSH); 2679 } 2680 sc->sc_flags |= NCR_EXPECT_ILLCMD; 2681 if (nfifo > 2) 2682 nfifo = 2; /* We fixed it... */ 2683 } else 2684 nfifo = ncr53c9x_rdfifo(sc, NCR_RDFIFO_START); 2685 2686 if (nfifo != 2) { 2687 device_printf(sc->sc_dev, "RESELECT: %d bytes " 2688 "in FIFO! [intr %x, stat %x, step %d, " 2689 "prevphase %x]\n", 2690 nfifo, 2691 sc->sc_espintr, 2692 sc->sc_espstat, 2693 sc->sc_espstep, 2694 sc->sc_prevphase);
|
2558 ncr53c9x_init(sc, 1); 2559 goto out;
| 2695 goto reset;
|
2560 } 2561 sc->sc_selid = sc->sc_imess[0]; 2562 NCR_INTS(("selid=%02x ", sc->sc_selid)); 2563 2564 /* Handle IDENTIFY message. */ 2565 ncr53c9x_msgin(sc); 2566 2567 if (sc->sc_state != NCR_CONNECTED && 2568 sc->sc_state != NCR_IDENTIFIED) { 2569 /* IDENTIFY fail?! */ 2570 device_printf(sc->sc_dev, "identify failed, " 2571 "state %d, intr %02x\n", sc->sc_state, 2572 sc->sc_espintr);
| 2696 } 2697 sc->sc_selid = sc->sc_imess[0]; 2698 NCR_INTS(("selid=%02x ", sc->sc_selid)); 2699 2700 /* Handle IDENTIFY message. */ 2701 ncr53c9x_msgin(sc); 2702 2703 if (sc->sc_state != NCR_CONNECTED && 2704 sc->sc_state != NCR_IDENTIFIED) { 2705 /* IDENTIFY fail?! */ 2706 device_printf(sc->sc_dev, "identify failed, " 2707 "state %d, intr %02x\n", sc->sc_state, 2708 sc->sc_espintr);
|
2573 ncr53c9x_init(sc, 1); 2574 goto out;
| 2709 goto reset;
|
2575 } 2576 goto shortcut; /* i.e. next phase expected soon */ 2577 } 2578 2579#define NCRINTR_DONE (NCRINTR_FC | NCRINTR_BS) 2580 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 2581 /* 2582 * Arbitration won; examine the `step' register 2583 * to determine how far the selection could progress. 2584 */ 2585 if (ecb == NULL) { 2586 /* 2587 * When doing path inquiry during boot 2588 * FAS100A trigger a stray interrupt which 2589 * we just ignore instead of panicing. 2590 */ 2591 if (sc->sc_state == NCR_IDLE && 2592 sc->sc_espstep == 0)
| 2710 } 2711 goto shortcut; /* i.e. next phase expected soon */ 2712 } 2713 2714#define NCRINTR_DONE (NCRINTR_FC | NCRINTR_BS) 2715 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) { 2716 /* 2717 * Arbitration won; examine the `step' register 2718 * to determine how far the selection could progress. 2719 */ 2720 if (ecb == NULL) { 2721 /* 2722 * When doing path inquiry during boot 2723 * FAS100A trigger a stray interrupt which 2724 * we just ignore instead of panicing. 2725 */ 2726 if (sc->sc_state == NCR_IDLE && 2727 sc->sc_espstep == 0)
|
2593 goto out;
| 2728 return;
|
2594 panic("ncr53c9x: no nexus"); 2595 } 2596 2597 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2598 2599 switch (sc->sc_espstep) { 2600 case 0: 2601 /* 2602 * The target did not respond with a 2603 * message out phase - probably an old 2604 * device that doesn't recognize ATN. 2605 * Clear ATN and just continue, the 2606 * target should be in the command 2607 * phase. 2608 * XXX check for command phase? 2609 */ 2610 NCRCMD(sc, NCRCMD_RSTATN); 2611 break; 2612 2613 case 1:
| 2729 panic("ncr53c9x: no nexus"); 2730 } 2731 2732 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id]; 2733 2734 switch (sc->sc_espstep) { 2735 case 0: 2736 /* 2737 * The target did not respond with a 2738 * message out phase - probably an old 2739 * device that doesn't recognize ATN. 2740 * Clear ATN and just continue, the 2741 * target should be in the command 2742 * phase. 2743 * XXX check for command phase? 2744 */ 2745 NCRCMD(sc, NCRCMD_RSTATN); 2746 break; 2747 2748 case 1:
|
2614 if ((ti->flags & T_NEGOTIATE) == 0 &&
| 2749 if (ti->curr.period == ti->goal.period && 2750 ti->curr.offset == ti->goal.offset && 2751 ti->curr.width == ti->goal.width &&
|
2615 ecb->tag[0] == 0) {
| 2752 ecb->tag[0] == 0) {
|
2616 device_printf(sc->sc_dev, "step 1 & " 2617 "!NEG\n");
| 2753 device_printf(sc->sc_dev, "step 1 " 2754 "and no negotiation to perform " 2755 "or tag to send\n");
|
2618 goto reset; 2619 } 2620 if (sc->sc_phase != MESSAGE_OUT_PHASE) {
| 2756 goto reset; 2757 } 2758 if (sc->sc_phase != MESSAGE_OUT_PHASE) {
|
2621 device_printf(sc->sc_dev, "!MSGOUT\n");
| 2759 device_printf(sc->sc_dev, "step 1 " 2760 "but not in MESSAGE_OUT_PHASE\n");
|
2622 goto reset; 2623 }
| 2761 goto reset; 2762 }
|
2624 if (ti->flags & T_WIDE) { 2625 ti->flags |= T_WDTRSENT; 2626 ncr53c9x_sched_msgout(SEND_WDTR);
| 2763 sc->sc_prevphase = MESSAGE_OUT_PHASE; /* XXX */ 2764 if (ecb->flags & ECB_RESET) { 2765 /* 2766 * A DEVICE RESET was scheduled and 2767 * ATNS used. As SEND_DEV_RESET has 2768 * the highest priority, the target 2769 * will reset and disconnect and we 2770 * will end up in ncr53c9x_done w/o 2771 * negotiating or sending a TAG. So 2772 * we just break here in order to 2773 * avoid warnings about negotiation 2774 * not having completed. 2775 */ 2776 ncr53c9x_sched_msgout(SEND_DEV_RESET); 2777 break;
|
2627 }
| 2778 }
|
2628 if (ti->flags & T_NEGOTIATE) { 2629 /* Start negotiating */ 2630 sc->sc_flags |= NCR_SYNCHNEGO; 2631 if (ecb->tag[0]) 2632 ncr53c9x_sched_msgout( 2633 SEND_TAG|SEND_SDTR); 2634 else 2635 ncr53c9x_sched_msgout( 2636 SEND_SDTR); 2637 } else {
| 2779 if (ti->curr.width != ti->goal.width) { 2780 ti->flags |= T_WDTRSENT | T_SDTRSENT; 2781 ncr53c9x_sched_msgout(SEND_WDTR | 2782 SEND_SDTR); 2783 } 2784 if (ti->curr.period != ti->goal.period || 2785 ti->curr.offset != ti->goal.offset) { 2786 ti->flags |= T_SDTRSENT; 2787 ncr53c9x_sched_msgout(SEND_SDTR); 2788 } 2789 if (ecb->tag[0] != 0)
|
2638 /* Could not do ATN3 so send TAG. */ 2639 ncr53c9x_sched_msgout(SEND_TAG);
| 2790 /* Could not do ATN3 so send TAG. */ 2791 ncr53c9x_sched_msgout(SEND_TAG);
|
2640 } 2641 sc->sc_prevphase = MESSAGE_OUT_PHASE; /* XXXX */
| |
2642 break; 2643 2644 case 3: 2645 /* 2646 * Grr, this is supposed to mean 2647 * "target left command phase prematurely". 2648 * It seems to happen regularly when 2649 * sync mode is on. 2650 * Look at FIFO to see if command went out. 2651 * (Timing problems?) 2652 */ 2653 if (sc->sc_features & NCR_F_DMASELECT) { 2654 if (sc->sc_cmdlen == 0) 2655 /* Hope for the best... */ 2656 break; 2657 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 2658 & NCRFIFO_FF) == 0) { 2659 /* Hope for the best... */ 2660 break; 2661 }
| 2792 break; 2793 2794 case 3: 2795 /* 2796 * Grr, this is supposed to mean 2797 * "target left command phase prematurely". 2798 * It seems to happen regularly when 2799 * sync mode is on. 2800 * Look at FIFO to see if command went out. 2801 * (Timing problems?) 2802 */ 2803 if (sc->sc_features & NCR_F_DMASELECT) { 2804 if (sc->sc_cmdlen == 0) 2805 /* Hope for the best... */ 2806 break; 2807 } else if ((NCR_READ_REG(sc, NCR_FFLAG) 2808 & NCRFIFO_FF) == 0) { 2809 /* Hope for the best... */ 2810 break; 2811 }
|
2662 printf("(%s:%d:%d): selection failed;" 2663 " %d left in FIFO "
| 2812 xpt_print_path(ecb->ccb->ccb_h.path); 2813 printf("selection failed; %d left in FIFO "
|
2664 "[intr %x, stat %x, step %d]\n",
| 2814 "[intr %x, stat %x, step %d]\n",
|
2665 device_get_nameunit(sc->sc_dev), 2666 ecb->ccb->ccb_h.target_id, 2667 ecb->ccb->ccb_h.target_lun,
| |
2668 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, 2669 sc->sc_espintr, sc->sc_espstat, 2670 sc->sc_espstep); 2671 NCRCMD(sc, NCRCMD_FLUSH); 2672 ncr53c9x_sched_msgout(SEND_ABORT);
| 2815 NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF, 2816 sc->sc_espintr, sc->sc_espstat, 2817 sc->sc_espstep); 2818 NCRCMD(sc, NCRCMD_FLUSH); 2819 ncr53c9x_sched_msgout(SEND_ABORT);
|
2673 goto out;
| 2820 return;
|
2674 2675 case 2: 2676 /* Select stuck at Command Phase. */ 2677 NCRCMD(sc, NCRCMD_FLUSH); 2678 break; 2679 2680 case 4: 2681 if (sc->sc_features & NCR_F_DMASELECT &&
| 2821 2822 case 2: 2823 /* Select stuck at Command Phase. */ 2824 NCRCMD(sc, NCRCMD_FLUSH); 2825 break; 2826 2827 case 4: 2828 if (sc->sc_features & NCR_F_DMASELECT &&
|
2682 sc->sc_cmdlen != 0) 2683 printf("(%s:%d:%d): select; " 2684 "%lu left in DMA buffer "
| 2829 sc->sc_cmdlen != 0) { 2830 xpt_print_path(ecb->ccb->ccb_h.path); 2831 printf("select; %lu left in DMA buffer "
|
2685 "[intr %x, stat %x, step %d]\n",
| 2832 "[intr %x, stat %x, step %d]\n",
|
2686 device_get_nameunit(sc->sc_dev), 2687 ecb->ccb->ccb_h.target_id, 2688 ecb->ccb->ccb_h.target_lun,
| |
2689 (u_long)sc->sc_cmdlen, 2690 sc->sc_espintr, 2691 sc->sc_espstat, 2692 sc->sc_espstep);
| 2833 (u_long)sc->sc_cmdlen, 2834 sc->sc_espintr, 2835 sc->sc_espstat, 2836 sc->sc_espstep);
|
| 2837 }
|
2693 /* So far, everything went fine. */ 2694 break; 2695 } 2696 2697 sc->sc_prevphase = INVALID_PHASE; /* ??? */ 2698 /* Do an implicit RESTORE POINTERS. */ 2699 sc->sc_dp = ecb->daddr; 2700 sc->sc_dleft = ecb->dleft; 2701 sc->sc_state = NCR_CONNECTED; 2702 break; 2703 } else { 2704 device_printf(sc->sc_dev, "unexpected status after " 2705 "select: [intr %x, stat %x, step %x]\n", 2706 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2707 NCRCMD(sc, NCRCMD_FLUSH); 2708 DELAY(1); 2709 goto reset; 2710 } 2711 if (sc->sc_state == NCR_IDLE) { 2712 device_printf(sc->sc_dev, "stray interrupt\n");
| 2838 /* So far, everything went fine. */ 2839 break; 2840 } 2841 2842 sc->sc_prevphase = INVALID_PHASE; /* ??? */ 2843 /* Do an implicit RESTORE POINTERS. */ 2844 sc->sc_dp = ecb->daddr; 2845 sc->sc_dleft = ecb->dleft; 2846 sc->sc_state = NCR_CONNECTED; 2847 break; 2848 } else { 2849 device_printf(sc->sc_dev, "unexpected status after " 2850 "select: [intr %x, stat %x, step %x]\n", 2851 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2852 NCRCMD(sc, NCRCMD_FLUSH); 2853 DELAY(1); 2854 goto reset; 2855 } 2856 if (sc->sc_state == NCR_IDLE) { 2857 device_printf(sc->sc_dev, "stray interrupt\n");
|
2713 goto out;
| 2858 return;
|
2714 } 2715 break; 2716 2717 case NCR_CONNECTED: 2718 if ((sc->sc_flags & NCR_ICCS) != 0) { 2719 /* "Initiate Command Complete Steps" in progress */ 2720 sc->sc_flags &= ~NCR_ICCS; 2721 2722 if (!(sc->sc_espintr & NCRINTR_DONE)) { 2723 device_printf(sc->sc_dev, "ICCS: " 2724 ": [intr %x, stat %x, step %x]\n", 2725 sc->sc_espintr, sc->sc_espstat, 2726 sc->sc_espstep); 2727 } 2728 ncr53c9x_rdfifo(sc, NCR_RDFIFO_START); 2729 if (sc->sc_imlen < 2) 2730 device_printf(sc->sc_dev, "can't get status, " 2731 "only %d bytes\n", (int)sc->sc_imlen); 2732 ecb->stat = sc->sc_imess[sc->sc_imlen - 2]; 2733 msg = sc->sc_imess[sc->sc_imlen - 1]; 2734 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2735 if (msg == MSG_CMDCOMPLETE) { 2736 ecb->dleft = 2737 (ecb->flags & ECB_TENTATIVE_DONE) ? 2738 0 : sc->sc_dleft; 2739 if ((ecb->flags & ECB_SENSE) == 0) 2740 ecb->ccb->csio.resid = ecb->dleft; 2741 sc->sc_state = NCR_CMDCOMPLETE; 2742 } else 2743 device_printf(sc->sc_dev, "STATUS_PHASE: " 2744 "msg %d\n", msg); 2745 sc->sc_imlen = 0; 2746 NCRCMD(sc, NCRCMD_MSGOK); 2747 goto shortcut; /* i.e. wait for disconnect */ 2748 } 2749 break; 2750 2751 default: 2752 device_printf(sc->sc_dev, "invalid state: %d [intr %x, " 2753 "phase(c %x, p %x)]\n", sc->sc_state, 2754 sc->sc_espintr, sc->sc_phase, sc->sc_prevphase); 2755 goto reset; 2756 } 2757 2758 /* 2759 * Driver is now in state NCR_CONNECTED, i.e. we 2760 * have a current command working the SCSI bus. 2761 */ 2762 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 2763 panic("ncr53c9x: no nexus"); 2764 } 2765 2766 switch (sc->sc_phase) { 2767 case MESSAGE_OUT_PHASE: 2768 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 2769 ncr53c9x_msgout(sc); 2770 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2771 break; 2772 2773 case MESSAGE_IN_PHASE: 2774msgin: 2775 NCR_PHASE(("MESSAGE_IN_PHASE ")); 2776 if ((sc->sc_espintr & NCRINTR_BS) != 0) { 2777 if ((sc->sc_rev != NCR_VARIANT_FAS366) || 2778 !(sc->sc_espstat2 & NCRFAS_STAT2_EMPTY)) { 2779 NCRCMD(sc, NCRCMD_FLUSH); 2780 } 2781 sc->sc_flags |= NCR_WAITI; 2782 NCRCMD(sc, NCRCMD_TRANS); 2783 } else if ((sc->sc_espintr & NCRINTR_FC) != 0) { 2784 if ((sc->sc_flags & NCR_WAITI) == 0) { 2785 device_printf(sc->sc_dev, "MSGIN: unexpected " 2786 "FC bit: [intr %x, stat %x, step %x]\n", 2787 sc->sc_espintr, sc->sc_espstat, 2788 sc->sc_espstep); 2789 } 2790 sc->sc_flags &= ~NCR_WAITI; 2791 ncr53c9x_rdfifo(sc, 2792 (sc->sc_prevphase == sc->sc_phase) ? 2793 NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START); 2794 ncr53c9x_msgin(sc); 2795 } else { 2796 device_printf(sc->sc_dev, "MSGIN: weird bits: " 2797 "[intr %x, stat %x, step %x]\n", 2798 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2799 } 2800 sc->sc_prevphase = MESSAGE_IN_PHASE; 2801 goto shortcut; /* i.e. expect data to be ready */ 2802 2803 case COMMAND_PHASE: 2804 /* 2805 * Send the command block. Normally we don't see this 2806 * phase because the SEL_ATN command takes care of 2807 * all this. However, we end up here if either the 2808 * target or we wanted to exchange some more messages 2809 * first (e.g. to start negotiations). 2810 */ 2811 2812 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2813 ecb->cmd.cmd.opcode, ecb->clen)); 2814 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2815 NCRCMD(sc, NCRCMD_FLUSH); 2816/* DELAY(1);*/ 2817 }
| 2859 } 2860 break; 2861 2862 case NCR_CONNECTED: 2863 if ((sc->sc_flags & NCR_ICCS) != 0) { 2864 /* "Initiate Command Complete Steps" in progress */ 2865 sc->sc_flags &= ~NCR_ICCS; 2866 2867 if (!(sc->sc_espintr & NCRINTR_DONE)) { 2868 device_printf(sc->sc_dev, "ICCS: " 2869 ": [intr %x, stat %x, step %x]\n", 2870 sc->sc_espintr, sc->sc_espstat, 2871 sc->sc_espstep); 2872 } 2873 ncr53c9x_rdfifo(sc, NCR_RDFIFO_START); 2874 if (sc->sc_imlen < 2) 2875 device_printf(sc->sc_dev, "can't get status, " 2876 "only %d bytes\n", (int)sc->sc_imlen); 2877 ecb->stat = sc->sc_imess[sc->sc_imlen - 2]; 2878 msg = sc->sc_imess[sc->sc_imlen - 1]; 2879 NCR_PHASE(("<stat:(%x,%x)>", ecb->stat, msg)); 2880 if (msg == MSG_CMDCOMPLETE) { 2881 ecb->dleft = 2882 (ecb->flags & ECB_TENTATIVE_DONE) ? 2883 0 : sc->sc_dleft; 2884 if ((ecb->flags & ECB_SENSE) == 0) 2885 ecb->ccb->csio.resid = ecb->dleft; 2886 sc->sc_state = NCR_CMDCOMPLETE; 2887 } else 2888 device_printf(sc->sc_dev, "STATUS_PHASE: " 2889 "msg %d\n", msg); 2890 sc->sc_imlen = 0; 2891 NCRCMD(sc, NCRCMD_MSGOK); 2892 goto shortcut; /* i.e. wait for disconnect */ 2893 } 2894 break; 2895 2896 default: 2897 device_printf(sc->sc_dev, "invalid state: %d [intr %x, " 2898 "phase(c %x, p %x)]\n", sc->sc_state, 2899 sc->sc_espintr, sc->sc_phase, sc->sc_prevphase); 2900 goto reset; 2901 } 2902 2903 /* 2904 * Driver is now in state NCR_CONNECTED, i.e. we 2905 * have a current command working the SCSI bus. 2906 */ 2907 if (sc->sc_state != NCR_CONNECTED || ecb == NULL) { 2908 panic("ncr53c9x: no nexus"); 2909 } 2910 2911 switch (sc->sc_phase) { 2912 case MESSAGE_OUT_PHASE: 2913 NCR_PHASE(("MESSAGE_OUT_PHASE ")); 2914 ncr53c9x_msgout(sc); 2915 sc->sc_prevphase = MESSAGE_OUT_PHASE; 2916 break; 2917 2918 case MESSAGE_IN_PHASE: 2919msgin: 2920 NCR_PHASE(("MESSAGE_IN_PHASE ")); 2921 if ((sc->sc_espintr & NCRINTR_BS) != 0) { 2922 if ((sc->sc_rev != NCR_VARIANT_FAS366) || 2923 !(sc->sc_espstat2 & NCRFAS_STAT2_EMPTY)) { 2924 NCRCMD(sc, NCRCMD_FLUSH); 2925 } 2926 sc->sc_flags |= NCR_WAITI; 2927 NCRCMD(sc, NCRCMD_TRANS); 2928 } else if ((sc->sc_espintr & NCRINTR_FC) != 0) { 2929 if ((sc->sc_flags & NCR_WAITI) == 0) { 2930 device_printf(sc->sc_dev, "MSGIN: unexpected " 2931 "FC bit: [intr %x, stat %x, step %x]\n", 2932 sc->sc_espintr, sc->sc_espstat, 2933 sc->sc_espstep); 2934 } 2935 sc->sc_flags &= ~NCR_WAITI; 2936 ncr53c9x_rdfifo(sc, 2937 (sc->sc_prevphase == sc->sc_phase) ? 2938 NCR_RDFIFO_CONTINUE : NCR_RDFIFO_START); 2939 ncr53c9x_msgin(sc); 2940 } else { 2941 device_printf(sc->sc_dev, "MSGIN: weird bits: " 2942 "[intr %x, stat %x, step %x]\n", 2943 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep); 2944 } 2945 sc->sc_prevphase = MESSAGE_IN_PHASE; 2946 goto shortcut; /* i.e. expect data to be ready */ 2947 2948 case COMMAND_PHASE: 2949 /* 2950 * Send the command block. Normally we don't see this 2951 * phase because the SEL_ATN command takes care of 2952 * all this. However, we end up here if either the 2953 * target or we wanted to exchange some more messages 2954 * first (e.g. to start negotiations). 2955 */ 2956 2957 NCR_PHASE(("COMMAND_PHASE 0x%02x (%d) ", 2958 ecb->cmd.cmd.opcode, ecb->clen)); 2959 if (NCR_READ_REG(sc, NCR_FFLAG) & NCRFIFO_FF) { 2960 NCRCMD(sc, NCRCMD_FLUSH); 2961/* DELAY(1);*/ 2962 }
|
| 2963 /* 2964 * If we have more messages to send, e.g. WDTR or SDTR 2965 * after we've sent a TAG, set ATN so we'll go back to 2966 * MESSAGE_OUT_PHASE. 2967 */ 2968 if (sc->sc_msgpriq) { 2969 NCRCMD(sc, NCRCMD_SETATN); 2970 sc->sc_flags |= NCR_ATN; 2971 }
|
2818 if (sc->sc_features & NCR_F_DMASELECT) { 2819 /* Setup DMA transfer for command. */ 2820 size = ecb->clen; 2821 sc->sc_cmdlen = size; 2822 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2823 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2824 0, &size); 2825 /* Program the SCSI counter. */ 2826 NCR_SET_COUNT(sc, size); 2827 2828 /* Load the count in. */ 2829 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 2830 2831 /* Start the command transfer. */ 2832 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2833 NCRDMA_GO(sc); 2834 } else { 2835 ncr53c9x_wrfifo(sc, (u_char *)&ecb->cmd.cmd, ecb->clen); 2836 NCRCMD(sc, NCRCMD_TRANS); 2837 } 2838 sc->sc_prevphase = COMMAND_PHASE; 2839 break; 2840 2841 case DATA_OUT_PHASE: 2842 NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft)); 2843 NCRCMD(sc, NCRCMD_FLUSH);
| 2972 if (sc->sc_features & NCR_F_DMASELECT) { 2973 /* Setup DMA transfer for command. */ 2974 size = ecb->clen; 2975 sc->sc_cmdlen = size; 2976 sc->sc_cmdp = (caddr_t)&ecb->cmd.cmd; 2977 NCRDMA_SETUP(sc, &sc->sc_cmdp, &sc->sc_cmdlen, 2978 0, &size); 2979 /* Program the SCSI counter. */ 2980 NCR_SET_COUNT(sc, size); 2981 2982 /* Load the count in. */ 2983 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 2984 2985 /* Start the command transfer. */ 2986 NCRCMD(sc, NCRCMD_TRANS | NCRCMD_DMA); 2987 NCRDMA_GO(sc); 2988 } else { 2989 ncr53c9x_wrfifo(sc, (u_char *)&ecb->cmd.cmd, ecb->clen); 2990 NCRCMD(sc, NCRCMD_TRANS); 2991 } 2992 sc->sc_prevphase = COMMAND_PHASE; 2993 break; 2994 2995 case DATA_OUT_PHASE: 2996 NCR_PHASE(("DATA_OUT_PHASE [%ld] ", (long)sc->sc_dleft)); 2997 NCRCMD(sc, NCRCMD_FLUSH);
|
2844 size = min(sc->sc_dleft, sc->sc_maxxfer);
| 2998 size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
|
2845 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size); 2846 sc->sc_prevphase = DATA_OUT_PHASE; 2847 goto setup_xfer; 2848 2849 case DATA_IN_PHASE: 2850 NCR_PHASE(("DATA_IN_PHASE ")); 2851 if (sc->sc_rev == NCR_VARIANT_ESP100) 2852 NCRCMD(sc, NCRCMD_FLUSH);
| 2999 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 0, &size); 3000 sc->sc_prevphase = DATA_OUT_PHASE; 3001 goto setup_xfer; 3002 3003 case DATA_IN_PHASE: 3004 NCR_PHASE(("DATA_IN_PHASE ")); 3005 if (sc->sc_rev == NCR_VARIANT_ESP100) 3006 NCRCMD(sc, NCRCMD_FLUSH);
|
2853 size = min(sc->sc_dleft, sc->sc_maxxfer);
| 3007 size = ulmin(sc->sc_dleft, sc->sc_maxxfer);
|
2854 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size); 2855 sc->sc_prevphase = DATA_IN_PHASE; 2856 setup_xfer: 2857 /* Target returned to data phase: wipe "done" memory */ 2858 ecb->flags &= ~ECB_TENTATIVE_DONE; 2859 2860 /* Program the SCSI counter. */ 2861 NCR_SET_COUNT(sc, size); 2862 2863 /* Load the count in. */ 2864 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 2865 2866 /* 2867 * Note that if `size' is 0, we've already transceived 2868 * all the bytes we want but we're still in DATA PHASE. 2869 * Apparently, the device needs padding. Also, a 2870 * transfer size of 0 means "maximum" to the chip 2871 * DMA logic. 2872 */ 2873 NCRCMD(sc, 2874 (size == 0 ? NCRCMD_TRPAD : NCRCMD_TRANS) | NCRCMD_DMA); 2875 NCRDMA_GO(sc);
| 3008 NCRDMA_SETUP(sc, &sc->sc_dp, &sc->sc_dleft, 1, &size); 3009 sc->sc_prevphase = DATA_IN_PHASE; 3010 setup_xfer: 3011 /* Target returned to data phase: wipe "done" memory */ 3012 ecb->flags &= ~ECB_TENTATIVE_DONE; 3013 3014 /* Program the SCSI counter. */ 3015 NCR_SET_COUNT(sc, size); 3016 3017 /* Load the count in. */ 3018 NCRCMD(sc, NCRCMD_NOP | NCRCMD_DMA); 3019 3020 /* 3021 * Note that if `size' is 0, we've already transceived 3022 * all the bytes we want but we're still in DATA PHASE. 3023 * Apparently, the device needs padding. Also, a 3024 * transfer size of 0 means "maximum" to the chip 3025 * DMA logic. 3026 */ 3027 NCRCMD(sc, 3028 (size == 0 ? NCRCMD_TRPAD : NCRCMD_TRANS) | NCRCMD_DMA); 3029 NCRDMA_GO(sc);
|
2876 goto out;
| 3030 return;
|
2877 2878 case STATUS_PHASE: 2879 NCR_PHASE(("STATUS_PHASE ")); 2880 sc->sc_flags |= NCR_ICCS; 2881 NCRCMD(sc, NCRCMD_ICCS); 2882 sc->sc_prevphase = STATUS_PHASE; 2883 goto shortcut; /* i.e. expect status results soon */ 2884 2885 case INVALID_PHASE: 2886 break; 2887 2888 default: 2889 device_printf(sc->sc_dev, 2890 "unexpected bus phase; resetting\n"); 2891 goto reset; 2892 } 2893
| 3031 3032 case STATUS_PHASE: 3033 NCR_PHASE(("STATUS_PHASE ")); 3034 sc->sc_flags |= NCR_ICCS; 3035 NCRCMD(sc, NCRCMD_ICCS); 3036 sc->sc_prevphase = STATUS_PHASE; 3037 goto shortcut; /* i.e. expect status results soon */ 3038 3039 case INVALID_PHASE: 3040 break; 3041 3042 default: 3043 device_printf(sc->sc_dev, 3044 "unexpected bus phase; resetting\n"); 3045 goto reset; 3046 } 3047
|
2894out: 2895 mtx_unlock(&sc->sc_lock);
| |
2896 return; 2897 2898reset: 2899 ncr53c9x_init(sc, 1);
| 3048 return; 3049 3050reset: 3051 ncr53c9x_init(sc, 1);
|
2900 goto out;
| 3052 return;
|
2901 2902finish: 2903 ncr53c9x_done(sc, ecb);
| 3053 3054finish: 3055 ncr53c9x_done(sc, ecb);
|
2904 goto out;
| 3056 return;
|
2905 2906sched: 2907 sc->sc_state = NCR_IDLE; 2908 ncr53c9x_sched(sc);
| 3057 3058sched: 3059 sc->sc_state = NCR_IDLE; 3060 ncr53c9x_sched(sc);
|
2909 goto out;
| 3061 return;
|
2910 2911shortcut: 2912 /* 2913 * The idea is that many of the SCSI operations take very little 2914 * time, and going away and getting interrupted is too high an 2915 * overhead to pay. For example, selecting, sending a message 2916 * and command and then doing some work can be done in one "pass". 2917 * 2918 * The delay is a heuristic. It is 2 when at 20MHz, 2 at 25MHz and 1 2919 * at 40MHz. This needs testing. 2920 */ 2921 microtime(&wait); 2922 wait.tv_usec += 50 / sc->sc_freq; 2923 if (wait.tv_usec > 1000000) { 2924 wait.tv_sec++; 2925 wait.tv_usec -= 1000000; 2926 } 2927 do { 2928 if (NCRDMA_ISINTR(sc)) 2929 goto again; 2930 microtime(&cur); 2931 } while (cur.tv_sec <= wait.tv_sec && cur.tv_usec <= wait.tv_usec);
| 3062 3063shortcut: 3064 /* 3065 * The idea is that many of the SCSI operations take very little 3066 * time, and going away and getting interrupted is too high an 3067 * overhead to pay. For example, selecting, sending a message 3068 * and command and then doing some work can be done in one "pass". 3069 * 3070 * The delay is a heuristic. It is 2 when at 20MHz, 2 at 25MHz and 1 3071 * at 40MHz. This needs testing. 3072 */ 3073 microtime(&wait); 3074 wait.tv_usec += 50 / sc->sc_freq; 3075 if (wait.tv_usec > 1000000) { 3076 wait.tv_sec++; 3077 wait.tv_usec -= 1000000; 3078 } 3079 do { 3080 if (NCRDMA_ISINTR(sc)) 3081 goto again; 3082 microtime(&cur); 3083 } while (cur.tv_sec <= wait.tv_sec && cur.tv_usec <= wait.tv_usec);
|
2932 goto out;
| |
2933} 2934 2935static void 2936ncr53c9x_abort(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 2937{ 2938
| 3084} 3085 3086static void 3087ncr53c9x_abort(struct ncr53c9x_softc *sc, struct ncr53c9x_ecb *ecb) 3088{ 3089
|
| 3090 NCR_LOCK_ASSERT(sc, MA_OWNED); 3091
|
2939 /* 2 secs for the abort */ 2940 ecb->timeout = NCR_ABORT_TIMEOUT; 2941 ecb->flags |= ECB_ABORT; 2942 2943 if (ecb == sc->sc_nexus) { 2944 /* 2945 * If we're still selecting, the message will be scheduled 2946 * after selection is complete. 2947 */ 2948 if (sc->sc_state == NCR_CONNECTED) 2949 ncr53c9x_sched_msgout(SEND_ABORT); 2950 2951 /*
| 3092 /* 2 secs for the abort */ 3093 ecb->timeout = NCR_ABORT_TIMEOUT; 3094 ecb->flags |= ECB_ABORT; 3095 3096 if (ecb == sc->sc_nexus) { 3097 /* 3098 * If we're still selecting, the message will be scheduled 3099 * after selection is complete. 3100 */ 3101 if (sc->sc_state == NCR_CONNECTED) 3102 ncr53c9x_sched_msgout(SEND_ABORT); 3103 3104 /*
|
2952 * Reschedule timeout.
| 3105 * Reschedule callout.
|
2953 */
| 3106 */
|
2954 ecb->ccb->ccb_h.timeout_ch = 2955 timeout(ncr53c9x_timeout, ecb, mstohz(ecb->timeout));
| 3107 callout_reset(&ecb->ch, mstohz(ecb->timeout), 3108 ncr53c9x_callout, ecb);
|
2956 } else { 2957 /* 2958 * Just leave the command where it is. 2959 * XXX - what choice do we have but to reset the SCSI 2960 * eventually? 2961 */ 2962 if (sc->sc_state == NCR_IDLE) 2963 ncr53c9x_sched(sc); 2964 } 2965} 2966 2967static void
| 3109 } else { 3110 /* 3111 * Just leave the command where it is. 3112 * XXX - what choice do we have but to reset the SCSI 3113 * eventually? 3114 */ 3115 if (sc->sc_state == NCR_IDLE) 3116 ncr53c9x_sched(sc); 3117 } 3118} 3119 3120static void
|
2968ncr53c9x_timeout(void *arg)
| 3121ncr53c9x_callout(void *arg)
|
2969{ 2970 struct ncr53c9x_ecb *ecb = arg; 2971 union ccb *ccb = ecb->ccb; 2972 struct ncr53c9x_softc *sc = ecb->sc;
| 3122{ 3123 struct ncr53c9x_ecb *ecb = arg; 3124 union ccb *ccb = ecb->ccb; 3125 struct ncr53c9x_softc *sc = ecb->sc;
|
2973 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
| 3126 struct ncr53c9x_tinfo *ti;
|
2974
| 3127
|
| 3128 NCR_LOCK_ASSERT(sc, MA_OWNED); 3129 3130 ti = &sc->sc_tinfo[ccb->ccb_h.target_id];
|
2975 xpt_print_path(ccb->ccb_h.path); 2976 device_printf(sc->sc_dev, "timed out [ecb %p (flags 0x%x, dleft %x, " 2977 "stat %x)], <state %d, nexus %p, phase(l %x, c %x, p %x), " 2978 "resid %lx, msg(q %x,o %x) %s>", 2979 ecb, ecb->flags, ecb->dleft, ecb->stat, 2980 sc->sc_state, sc->sc_nexus, 2981 NCR_READ_REG(sc, NCR_STAT), 2982 sc->sc_phase, sc->sc_prevphase, 2983 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 2984 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 2985#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 2986 printf("TRACE: %s.", ecb->trace); 2987#endif 2988
| 3131 xpt_print_path(ccb->ccb_h.path); 3132 device_printf(sc->sc_dev, "timed out [ecb %p (flags 0x%x, dleft %x, " 3133 "stat %x)], <state %d, nexus %p, phase(l %x, c %x, p %x), " 3134 "resid %lx, msg(q %x,o %x) %s>", 3135 ecb, ecb->flags, ecb->dleft, ecb->stat, 3136 sc->sc_state, sc->sc_nexus, 3137 NCR_READ_REG(sc, NCR_STAT), 3138 sc->sc_phase, sc->sc_prevphase, 3139 (long)sc->sc_dleft, sc->sc_msgpriq, sc->sc_msgout, 3140 NCRDMA_ISACTIVE(sc) ? "DMA active" : ""); 3141#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 3142 printf("TRACE: %s.", ecb->trace); 3143#endif 3144
|
2989 mtx_lock(&sc->sc_lock); 2990
| |
2991 if (ecb->flags & ECB_ABORT) { 2992 /* Abort timed out. */ 2993 printf(" AGAIN\n"); 2994 ncr53c9x_init(sc, 1); 2995 } else { 2996 /* Abort the operation that has timed out. */ 2997 printf("\n"); 2998 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 2999 ncr53c9x_abort(sc, ecb); 3000 3001 /* Disable sync mode if stuck in a data phase. */ 3002 if (ecb == sc->sc_nexus &&
| 3145 if (ecb->flags & ECB_ABORT) { 3146 /* Abort timed out. */ 3147 printf(" AGAIN\n"); 3148 ncr53c9x_init(sc, 1); 3149 } else { 3150 /* Abort the operation that has timed out. */ 3151 printf("\n"); 3152 ccb->ccb_h.status = CAM_CMD_TIMEOUT; 3153 ncr53c9x_abort(sc, ecb); 3154 3155 /* Disable sync mode if stuck in a data phase. */ 3156 if (ecb == sc->sc_nexus &&
|
3003 (ti->flags & T_SYNCMODE) != 0 && 3004 (sc->sc_phase & (MSGI|CDI)) == 0) {
| 3157 ti->curr.offset != 0 && 3158 (sc->sc_phase & (MSGI | CDI)) == 0) {
|
3005 /* XXX ASYNC CALLBACK! */
| 3159 /* XXX ASYNC CALLBACK! */
|
| 3160 ti->goal.offset = 0;
|
3006 xpt_print_path(ccb->ccb_h.path); 3007 printf("sync negotiation disabled\n");
| 3161 xpt_print_path(ccb->ccb_h.path); 3162 printf("sync negotiation disabled\n");
|
3008 sc->sc_cfflags |= 3009 (1 << ((ccb->ccb_h.target_id & 7) + 8));
| |
3010 } 3011 }
| 3163 } 3164 }
|
3012 3013 mtx_unlock(&sc->sc_lock);
| |
3014} 3015 3016static void 3017ncr53c9x_watch(void *arg) 3018{ 3019 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 3020 struct ncr53c9x_linfo *li; 3021 struct ncr53c9x_tinfo *ti; 3022 time_t old; 3023 int t; 3024
| 3165} 3166 3167static void 3168ncr53c9x_watch(void *arg) 3169{ 3170 struct ncr53c9x_softc *sc = (struct ncr53c9x_softc *)arg; 3171 struct ncr53c9x_linfo *li; 3172 struct ncr53c9x_tinfo *ti; 3173 time_t old; 3174 int t; 3175
|
| 3176 NCR_LOCK_ASSERT(sc, MA_OWNED); 3177
|
3025 /* Delete any structures that have not been used in 10min. */ 3026 old = time_second - (10 * 60); 3027
| 3178 /* Delete any structures that have not been used in 10min. */ 3179 old = time_second - (10 * 60); 3180
|
3028 mtx_lock(&sc->sc_lock);
| |
3029 for (t = 0; t < sc->sc_ntarg; t++) { 3030 ti = &sc->sc_tinfo[t]; 3031 li = LIST_FIRST(&ti->luns); 3032 while (li) { 3033 if (li->last_used < old && 3034 li->untagged == NULL && 3035 li->used == 0) { 3036 if (li->lun < NCR_NLUN) 3037 ti->lun[li->lun] = NULL; 3038 LIST_REMOVE(li, link); 3039 free(li, M_DEVBUF); 3040 /* Restart the search at the beginning. */ 3041 li = LIST_FIRST(&ti->luns); 3042 continue; 3043 } 3044 li = LIST_NEXT(li, link); 3045 } 3046 }
| 3181 for (t = 0; t < sc->sc_ntarg; t++) { 3182 ti = &sc->sc_tinfo[t]; 3183 li = LIST_FIRST(&ti->luns); 3184 while (li) { 3185 if (li->last_used < old && 3186 li->untagged == NULL && 3187 li->used == 0) { 3188 if (li->lun < NCR_NLUN) 3189 ti->lun[li->lun] = NULL; 3190 LIST_REMOVE(li, link); 3191 free(li, M_DEVBUF); 3192 /* Restart the search at the beginning. */ 3193 li = LIST_FIRST(&ti->luns); 3194 continue; 3195 } 3196 li = LIST_NEXT(li, link); 3197 } 3198 }
|
3047 mtx_unlock(&sc->sc_lock);
| |
3048 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc); 3049}
| 3199 callout_reset(&sc->sc_watchdog, 60 * hz, ncr53c9x_watch, sc); 3200}
|