1/*-
2 * Copyright (c) 2004 Scott Long
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28/* $NetBSD: ncr53c9x.c,v 1.110 2003/11/02 11:07:45 wiz Exp $ */
29
30/*-
31 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
32 * All rights reserved.
33 *
34 * This code is derived from software contributed to The NetBSD Foundation
35 * by Charles M. Hannum.
36 *
--- 62 unchanged lines hidden (view full) ---
99 * Based on aic6360 by Jarle Greipsland
100 *
101 * Acknowledgements: Many of the algorithms used in this driver are
102 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and
103 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
104 */
105
106#include <sys/cdefs.h>
107__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 145535 2005-04-25 22:11:43Z scottl $");
108
109#include <sys/param.h>
110#include <sys/systm.h>
111#include <sys/bus.h>
112#include <sys/kernel.h>
113#include <sys/malloc.h>
114#include <sys/resource.h>
115#include <sys/lock.h>
--- 79 unchanged lines hidden (view full) ---
195 "NCR53C94",
196 "NCR53C96",
197 "ESP406",
198 "FAS408",
199 "FAS216",
200 "AM53C974",
201 "FAS366/HME",
202 "NCR53C90 (86C01)",
203};
204
205/*
206 * Search linked list for LUN info by LUN id.
207 */
208static struct ncr53c9x_linfo *
209ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun)
210{
--- 9 unchanged lines hidden (view full) ---
220 */
221int
222ncr53c9x_attach(struct ncr53c9x_softc *sc)
223{
224 struct cam_devq *devq;
225 struct cam_sim *sim;
226 struct cam_path *path;
227 struct ncr53c9x_ecb *ecb;
228 int i;
229
230 mtx_init(&sc->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
231
232 /*
233 * Note, the front-end has set us up to print the chip variation.
234 */
235 if (sc->sc_rev >= NCR_VARIANT_MAX) {
236 device_printf(sc->sc_dev, "unknown variant %d, devices not "
--- 7 unchanged lines hidden (view full) ---
244 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8;
245
246 /*
247 * Allocate SCSI message buffers.
248 * Front-ends can override allocation to avoid alignment
249 * handling in the DMA engines. Note that that ncr53c9x_msgout()
250 * can request a 1 byte DMA transfer.
251 */
252 if (sc->sc_omess == NULL)
253 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT);
254
255 if (sc->sc_imess == NULL)
256 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT);
257
258 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]),
259 M_DEVBUF, M_NOWAIT | M_ZERO);
260
261 if (!sc->sc_omess || !sc->sc_imess || !sc->sc_tinfo) {
262 printf("out of memory\n");
263 return (ENOMEM);
264 }
265
266 callout_init(&sc->sc_watchdog, 0);
267
268 /*
269 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100
270 * from now on.
271 */
--- 21 unchanged lines hidden (view full) ---
293
294 /* CCF register only has 3 bits; 0 is actually 8 */
295 sc->sc_ccf &= 7;
296
297 /*
298 * Register with CAM
299 */
300 devq = cam_simq_alloc(sc->sc_ntarg);
301 if (devq == NULL)
302 return (ENOMEM);
303
304 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc,
305 device_get_unit(sc->sc_dev), 1,
306 NCR_TAG_DEPTH, devq);
307 if (sim == NULL) {
308 cam_simq_free(devq);
309 return (ENOMEM);
310 }
311 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) {
312 cam_sim_free(sim, TRUE);
313 return (EIO);
314 }
315
316 if (xpt_create_path(&path, NULL, cam_sim_path(sim),
317 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
318 != CAM_REQ_CMP) {
319 xpt_bus_deregister(cam_sim_path(sim));
320 cam_sim_free(sim, TRUE);
321 return (EIO);
322 }
323
324 sc->sc_sim = sim;
325 sc->sc_path = path;
326
327 /* Reset state & bus */
328#if 0
329 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags;
330#endif
331 sc->sc_state = 0;
332 ncr53c9x_init(sc, 1);
333
334 TAILQ_INIT(&sc->free_list);
335 if ((sc->ecb_array = malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH,
336 M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) {
337 device_printf(sc->sc_dev, "cannot allocate ECB array\n");
338 return (ENOMEM);
339 }
340 for (i = 0; i < NCR_TAG_DEPTH; i++) {
341 ecb = &sc->ecb_array[i];
342 ecb->sc = sc;
343 ecb->tag_id = i;
344 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links);
345 }
346
347 callout_reset(&sc->sc_watchdog, 60*hz, ncr53c9x_watch, sc);
348
349 return (0);
350}
351
352int
353ncr53c9x_detach(struct ncr53c9x_softc *sc, int flags)
354{
355
356#if 0 /* don't allow detach for now */
357 free(sc->sc_imess, M_DEVBUF);
358 free(sc->sc_omess, M_DEVBUF);
359#endif
360
361 return (EINVAL);
362}
363
364/*
365 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus,
366 * only this controller, but kills any on-going commands, and also stops
367 * and resets the DMA.
368 *
369 * After reset, registers are loaded with the defaults from the attach
--- 13 unchanged lines hidden (view full) ---
383
384 /* do these backwards, and fall through */
385 switch (sc->sc_rev) {
386 case NCR_VARIANT_ESP406:
387 case NCR_VARIANT_FAS408:
388 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT);
389 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4);
390 case NCR_VARIANT_AM53C974:
391 case NCR_VARIANT_FAS216:
392 case NCR_VARIANT_NCR53C94:
393 case NCR_VARIANT_NCR53C96:
394 case NCR_VARIANT_ESP200:
395 sc->sc_features |= NCR_F_HASCFG3;
396 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
397 case NCR_VARIANT_ESP100A:
398 sc->sc_features |= NCR_F_SELATN3;
399 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
--- 110 unchanged lines hidden (view full) ---
510 }
511 }
512
513 /*
514 * reset the chip to a known state
515 */
516 ncr53c9x_reset(sc);
517
518 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
519 for (r = 0; r < sc->sc_ntarg; r++) {
520 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r];
521/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
522
523 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<((r&7)+8))))
524 ? 0 : T_SYNCHOFF) |
525 ((sc->sc_cfflags & (1<<(r&7))) ? T_RSELECTOFF : 0);
526#ifdef DEBUG
--- 1261 unchanged lines hidden (view full) ---
1788 int p;
1789
1790 p = ncr53c9x_stp2cpb(sc, ti->period);
1791 ti->period = ncr53c9x_cpb2stp(sc, p);
1792 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) {
1793 /*
1794 * target initiated negotiation
1795 */
1796 if (ti->period <
1797 sc->sc_minsync)
1798 ti->period =
1799 sc->sc_minsync;
1800 if (ti->offset > 15)
1801 ti->offset = 15;
1802 ti->flags &= ~T_SYNCMODE;
1803 ncr53c9x_sched_msgout(
1804 SEND_SDTR);
1805 } else {
--- 683 unchanged lines hidden (view full) ---
2489 }
2490
2491#define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS)
2492 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) {
2493 /*
2494 * Arbitration won; examine the `step' register
2495 * to determine how far the selection could progress.
2496 */
2497 ecb = sc->sc_nexus;
2498 if (ecb == NULL)
2499 panic("ncr53c9x: no nexus");
2500
2501 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2502
2503 switch (sc->sc_espstep) {
2504 case 0:
2505 /*
2506 * The target did not respond with a
2507 * message out phase - probably an old
--- 100 unchanged lines hidden (view full) ---
2608 "select: [intr %x, stat %x, step %x]\n",
2609 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2610 NCRCMD(sc, NCRCMD_FLUSH);
2611 DELAY(1);
2612 goto reset;
2613 }
2614 if (sc->sc_state == NCR_IDLE) {
2615 device_printf(sc->sc_dev, "stray interrupt\n");
2616 mtx_unlock(&sc->sc_lock);
2617 return;
2618 }
2619 break;
2620
2621 case NCR_CONNECTED:
2622 if ((sc->sc_flags & NCR_ICCS) != 0) {
2623 /* "Initiate Command Complete Steps" in progress */
2624 u_char msg;
2625
--- 334 unchanged lines hidden ---
2 * Copyright (c) 2004 Scott Long
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
--- 11 unchanged lines hidden (view full) ---
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28/* $NetBSD: ncr53c9x.c,v 1.110 2003/11/02 11:07:45 wiz Exp $ */
29
30/*-
31 * Copyright (c) 1998, 2002 The NetBSD Foundation, Inc.
32 * All rights reserved.
33 *
34 * This code is derived from software contributed to The NetBSD Foundation
35 * by Charles M. Hannum.
36 *
--- 62 unchanged lines hidden (view full) ---
99 * Based on aic6360 by Jarle Greipsland
100 *
101 * Acknowledgements: Many of the algorithms used in this driver are
102 * inspired by the work of Julian Elischer (julian@FreeBSD.org) and
103 * Charles Hannum (mycroft@duality.gnu.ai.mit.edu). Thanks a million!
104 */
105
106#include <sys/cdefs.h>
107__FBSDID("$FreeBSD: head/sys/dev/esp/ncr53c9x.c 145535 2005-04-25 22:11:43Z scottl $");
108
109#include <sys/param.h>
110#include <sys/systm.h>
111#include <sys/bus.h>
112#include <sys/kernel.h>
113#include <sys/malloc.h>
114#include <sys/resource.h>
115#include <sys/lock.h>
--- 79 unchanged lines hidden (view full) ---
195 "NCR53C94",
196 "NCR53C96",
197 "ESP406",
198 "FAS408",
199 "FAS216",
200 "AM53C974",
201 "FAS366/HME",
202 "NCR53C90 (86C01)",
203};
204
205/*
206 * Search linked list for LUN info by LUN id.
207 */
208static struct ncr53c9x_linfo *
209ncr53c9x_lunsearch(struct ncr53c9x_tinfo *ti, int64_t lun)
210{
--- 9 unchanged lines hidden (view full) ---
220 */
221int
222ncr53c9x_attach(struct ncr53c9x_softc *sc)
223{
224 struct cam_devq *devq;
225 struct cam_sim *sim;
226 struct cam_path *path;
227 struct ncr53c9x_ecb *ecb;
228 int i;
229
230 mtx_init(&sc->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF);
231
232 /*
233 * Note, the front-end has set us up to print the chip variation.
234 */
235 if (sc->sc_rev >= NCR_VARIANT_MAX) {
236 device_printf(sc->sc_dev, "unknown variant %d, devices not "
--- 7 unchanged lines hidden (view full) ---
244 sc->sc_ntarg = (sc->sc_rev == NCR_VARIANT_FAS366) ? 16 : 8;
245
246 /*
247 * Allocate SCSI message buffers.
248 * Front-ends can override allocation to avoid alignment
249 * handling in the DMA engines. Note that that ncr53c9x_msgout()
250 * can request a 1 byte DMA transfer.
251 */
252 if (sc->sc_omess == NULL)
253 sc->sc_omess = malloc(NCR_MAX_MSG_LEN, M_DEVBUF, M_NOWAIT);
254
255 if (sc->sc_imess == NULL)
256 sc->sc_imess = malloc(NCR_MAX_MSG_LEN + 1, M_DEVBUF, M_NOWAIT);
257
258 sc->sc_tinfo = malloc(sc->sc_ntarg * sizeof(sc->sc_tinfo[0]),
259 M_DEVBUF, M_NOWAIT | M_ZERO);
260
261 if (!sc->sc_omess || !sc->sc_imess || !sc->sc_tinfo) {
262 printf("out of memory\n");
263 return (ENOMEM);
264 }
265
266 callout_init(&sc->sc_watchdog, 0);
267
268 /*
269 * Treat NCR53C90 with the 86C01 DMA chip exactly as ESP100
270 * from now on.
271 */
--- 21 unchanged lines hidden (view full) ---
293
294 /* CCF register only has 3 bits; 0 is actually 8 */
295 sc->sc_ccf &= 7;
296
297 /*
298 * Register with CAM
299 */
300 devq = cam_simq_alloc(sc->sc_ntarg);
301 if (devq == NULL)
302 return (ENOMEM);
303
304 sim = cam_sim_alloc(ncr53c9x_action, ncr53c9x_poll, "esp", sc,
305 device_get_unit(sc->sc_dev), 1,
306 NCR_TAG_DEPTH, devq);
307 if (sim == NULL) {
308 cam_simq_free(devq);
309 return (ENOMEM);
310 }
311 if (xpt_bus_register(sim, 0) != CAM_SUCCESS) {
312 cam_sim_free(sim, TRUE);
313 return (EIO);
314 }
315
316 if (xpt_create_path(&path, NULL, cam_sim_path(sim),
317 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD)
318 != CAM_REQ_CMP) {
319 xpt_bus_deregister(cam_sim_path(sim));
320 cam_sim_free(sim, TRUE);
321 return (EIO);
322 }
323
324 sc->sc_sim = sim;
325 sc->sc_path = path;
326
327 /* Reset state & bus */
328#if 0
329 sc->sc_cfflags = sc->sc_dev.dv_cfdata->cf_flags;
330#endif
331 sc->sc_state = 0;
332 ncr53c9x_init(sc, 1);
333
334 TAILQ_INIT(&sc->free_list);
335 if ((sc->ecb_array = malloc(sizeof(struct ncr53c9x_ecb) * NCR_TAG_DEPTH,
336 M_DEVBUF, M_NOWAIT|M_ZERO)) == NULL) {
337 device_printf(sc->sc_dev, "cannot allocate ECB array\n");
338 return (ENOMEM);
339 }
340 for (i = 0; i < NCR_TAG_DEPTH; i++) {
341 ecb = &sc->ecb_array[i];
342 ecb->sc = sc;
343 ecb->tag_id = i;
344 TAILQ_INSERT_HEAD(&sc->free_list, ecb, free_links);
345 }
346
347 callout_reset(&sc->sc_watchdog, 60*hz, ncr53c9x_watch, sc);
348
349 return (0);
350}
351
352int
353ncr53c9x_detach(struct ncr53c9x_softc *sc, int flags)
354{
355
356#if 0 /* don't allow detach for now */
357 free(sc->sc_imess, M_DEVBUF);
358 free(sc->sc_omess, M_DEVBUF);
359#endif
360
361 return (EINVAL);
362}
363
364/*
365 * This is the generic ncr53c9x reset function. It does not reset the SCSI bus,
366 * only this controller, but kills any on-going commands, and also stops
367 * and resets the DMA.
368 *
369 * After reset, registers are loaded with the defaults from the attach
--- 13 unchanged lines hidden (view full) ---
383
384 /* do these backwards, and fall through */
385 switch (sc->sc_rev) {
386 case NCR_VARIANT_ESP406:
387 case NCR_VARIANT_FAS408:
388 NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT);
389 NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4);
390 case NCR_VARIANT_AM53C974:
391 case NCR_VARIANT_FAS216:
392 case NCR_VARIANT_NCR53C94:
393 case NCR_VARIANT_NCR53C96:
394 case NCR_VARIANT_ESP200:
395 sc->sc_features |= NCR_F_HASCFG3;
396 NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
397 case NCR_VARIANT_ESP100A:
398 sc->sc_features |= NCR_F_SELATN3;
399 NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
--- 110 unchanged lines hidden (view full) ---
510 }
511 }
512
513 /*
514 * reset the chip to a known state
515 */
516 ncr53c9x_reset(sc);
517
518 sc->sc_phase = sc->sc_prevphase = INVALID_PHASE;
519 for (r = 0; r < sc->sc_ntarg; r++) {
520 struct ncr53c9x_tinfo *ti = &sc->sc_tinfo[r];
521/* XXX - config flags per target: low bits: no reselect; high bits: no synch */
522
523 ti->flags = ((sc->sc_minsync && !(sc->sc_cfflags & (1<<((r&7)+8))))
524 ? 0 : T_SYNCHOFF) |
525 ((sc->sc_cfflags & (1<<(r&7))) ? T_RSELECTOFF : 0);
526#ifdef DEBUG
--- 1261 unchanged lines hidden (view full) ---
1788 int p;
1789
1790 p = ncr53c9x_stp2cpb(sc, ti->period);
1791 ti->period = ncr53c9x_cpb2stp(sc, p);
1792 if ((sc->sc_flags&NCR_SYNCHNEGO) == 0) {
1793 /*
1794 * target initiated negotiation
1795 */
1796 if (ti->period <
1797 sc->sc_minsync)
1798 ti->period =
1799 sc->sc_minsync;
1800 if (ti->offset > 15)
1801 ti->offset = 15;
1802 ti->flags &= ~T_SYNCMODE;
1803 ncr53c9x_sched_msgout(
1804 SEND_SDTR);
1805 } else {
--- 683 unchanged lines hidden (view full) ---
2489 }
2490
2491#define NCRINTR_DONE (NCRINTR_FC|NCRINTR_BS)
2492 if ((sc->sc_espintr & NCRINTR_DONE) == NCRINTR_DONE) {
2493 /*
2494 * Arbitration won; examine the `step' register
2495 * to determine how far the selection could progress.
2496 */
2497 ecb = sc->sc_nexus;
2498 if (ecb == NULL)
2499 panic("ncr53c9x: no nexus");
2500
2501 ti = &sc->sc_tinfo[ecb->ccb->ccb_h.target_id];
2502
2503 switch (sc->sc_espstep) {
2504 case 0:
2505 /*
2506 * The target did not respond with a
2507 * message out phase - probably an old
--- 100 unchanged lines hidden (view full) ---
2608 "select: [intr %x, stat %x, step %x]\n",
2609 sc->sc_espintr, sc->sc_espstat, sc->sc_espstep);
2610 NCRCMD(sc, NCRCMD_FLUSH);
2611 DELAY(1);
2612 goto reset;
2613 }
2614 if (sc->sc_state == NCR_IDLE) {
2615 device_printf(sc->sc_dev, "stray interrupt\n");
2616 mtx_unlock(&sc->sc_lock);
2617 return;
2618 }
2619 break;
2620
2621 case NCR_CONNECTED:
2622 if ((sc->sc_flags & NCR_ICCS) != 0) {
2623 /* "Initiate Command Complete Steps" in progress */
2624 u_char msg;
2625
--- 334 unchanged lines hidden ---