Cross Reference: /freebsd-10.3-release/sys/dev/ep/if

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if_epreg.h (121206)	if_epreg.h (121492)
1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from --- 5 unchanged lines hidden (view full) --- 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 *	1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from --- 5 unchanged lines hidden (view full) --- 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 *
22 * $FreeBSD: head/sys/dev/ep/if_epreg.h 121206 2003-10-18 15:22:43Z imp $	22 * $FreeBSD: head/sys/dev/ep/if_epreg.h 121492 2003-10-25 04:09:49Z imp $
23 / 24 25/ 26 * DELAY_MULTIPLE: How much to boost "base" delays, except 27 * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 28 / 29#define DELAY_MULTIPLE 10 30#define BIT_DELAY_MULTIPLE 10 --- 6 unchanged lines hidden* (view full) --- 37#define RX_INIT_LATENCY 64 38#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */ 39#define RX_NEXT_EARLY_THRESH 500 40 41#define EEPROMSIZE 0x40 42#define MAX_EEPROMBUSY 1000 43#define EP_LAST_TAG 0xd7 44#define EP_MAX_BOARDS 16	23 / 24 25/ 26 * DELAY_MULTIPLE: How much to boost "base" delays, except 27 * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 28 / 29#define DELAY_MULTIPLE 10 30#define BIT_DELAY_MULTIPLE 10 --- 6 unchanged lines hidden* (view full) --- 37#define RX_INIT_LATENCY 64 38#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */ 39#define RX_NEXT_EARLY_THRESH 500 40 41#define EEPROMSIZE 0x40 42#define MAX_EEPROMBUSY 1000 43#define EP_LAST_TAG 0xd7 44#define EP_MAX_BOARDS 16
45/* 46 * This `ID' port is a mere hack. There's currently no chance to register 47 * it with config's idea of the ports that are in use. 48 * 49 * "After the automatic configuration is completed, the IDS is in its initial 50 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where 51 * 'x' is any hex digit. If a zero is written to any one of these ports, then 52 * that address is remembered and becomes the ID port. A second zero written 53 * to that port resets the ID sequence to its initial state. The IDS watches 54 * for the ID sequence to be written to the ID port." 55 * 56 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray 57 * ports. 58 */ 59#define EP_ID_PORT 0x110
60#define EP_IOSIZE 16 /* 16 bytes of I/O space used. / 61 62/ 63 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 64 * Offset 0xa) 65 / 66#define EEPROM_CMD_RD 0x0080 / Read: Address required (5 bits) / 67#define EEPROM_CMD_WR 0x0040 / Write: Address required (5 bits) / 68#define EEPROM_CMD_ERASE 0x00c0 / Erase: Address required (5 bits) / 69#define EEPROM_CMD_EWEN 0x0030 / Erase/Write Enable: No data required / 70 71#define EEPROM_BUSY (1<<15) 72#define EEPROM_TST_MODE (1<<14) 73 74/ 75 * Some short functions, worth to let them be a macro 76 */	45#define EP_IOSIZE 16 /* 16 bytes of I/O space used. / 46 47/ 48 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 49 * Offset 0xa) 50 / 51#define EEPROM_CMD_RD 0x0080 / Read: Address required (5 bits) / 52#define EEPROM_CMD_WR 0x0040 / Write: Address required (5 bits) / 53#define EEPROM_CMD_ERASE 0x00c0 / Erase: Address required (5 bits) / 54#define EEPROM_CMD_EWEN 0x0030 / Erase/Write Enable: No data required / 55 56#define EEPROM_BUSY (1<<15) 57#define EEPROM_TST_MODE (1<<14) 58 59/ 60 * Some short functions, worth to let them be a macro 61 */
77#define is_eeprom_busy(sc) (EP_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 78#define GO_WINDOW(x) EP_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT\|(x))	62#define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 63#define GO_WINDOW(x) CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT\|(x))
79 80/************************************************************************** 81 * * 82 * These define the EEPROM data structure. They are used in the probe 83 * function to verify the existence of the adapter after having sent 84 * the ID_Sequence. 85 * 86 ************************************************************************/ --- 57 unchanged lines hidden** (view full) --- 144 * Window 0 registers. Setup. 145 / 146/ Write / 147#define EP_W0_EEPROM_DATA 0x0c 148#define EP_W0_EEPROM_COMMAND 0x0a 149#define EP_W0_RESOURCE_CFG 0x08 150#define EP_W0_ADDRESS_CFG 0x06 151*#define EP_W0_CONFIG_CTRL 0x04	64 65/************************************************************************** 66 * * 67 * These define the EEPROM data structure. They are used in the probe 68 * function to verify the existence of the adapter after having sent 69 * the ID_Sequence. 70 * 71 ************************************************************************/ --- 57 unchanged lines hidden** (view full) --- 129 * Window 0 registers. Setup. 130 / 131/ Write / 132#define EP_W0_EEPROM_DATA 0x0c 133#define EP_W0_EEPROM_COMMAND 0x0a 134#define EP_W0_RESOURCE_CFG 0x08 135#define EP_W0_ADDRESS_CFG 0x06 136*#define EP_W0_CONFIG_CTRL 0x04
152/* Read */	137 /* Read */
153#define EP_W0_PRODUCT_ID 0x02 154#define EP_W0_MFG_ID 0x00 155 156/* 157 * Window 1 registers. Operating Set. 158 / 159/ Write / 160#define EP_W1_TX_PIO_WR_2 0x02 --- 99 unchanged lines hidden* (view full) --- 260 * power-up / 261#define RX_ENABLE (u_short) (0x4<<11) 262#define RX_RESET (u_short) (0x5<<11) 263#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 264#define TX_ENABLE (u_short) (0x9<<11) 265#define TX_DISABLE (u_short) (0xa<<11) 266#define TX_RESET (u_short) (0xb<<11) 267*#define REQ_INTR (u_short) (0xc<<11)	138#define EP_W0_PRODUCT_ID 0x02 139#define EP_W0_MFG_ID 0x00 140 141/* 142 * Window 1 registers. Operating Set. 143 / 144/ Write / 145#define EP_W1_TX_PIO_WR_2 0x02 --- 99 unchanged lines hidden* (view full) --- 245 * power-up / 246#define RX_ENABLE (u_short) (0x4<<11) 247#define RX_RESET (u_short) (0x5<<11) 248#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 249#define TX_ENABLE (u_short) (0x9<<11) 250#define TX_DISABLE (u_short) (0xa<<11) 251#define TX_RESET (u_short) (0xb<<11) 252*#define REQ_INTR (u_short) (0xc<<11)
	253/* 254 * The following C_* acknowledge the various interrupts. Some of them don't 255 * do anything. See the manual. 256 / 257#define ACK_INTR (u_short) (0x6800) 258# define C_INTR_LATCH (u_short) (ACK_INTR\|0x1) 259# define C_CARD_FAILURE (u_short) (ACK_INTR\|0x2) 260# define C_TX_COMPLETE (u_short) (ACK_INTR\|0x4) 261# define C_TX_AVAIL (u_short) (ACK_INTR\|0x8) 262# define C_RX_COMPLETE (u_short) (ACK_INTR\|0x10) 263# define C_RX_EARLY (u_short) (ACK_INTR\|0x20) 264# define C_INT_RQD (u_short) (ACK_INTR\|0x40) 265*# define C_UPD_STATS (u_short) (ACK_INTR\|0x80)
268#define SET_INTR_MASK (u_short) (0xe<<11) 269#define SET_RD_0_MASK (u_short) (0xf<<11) 270#define SET_RX_FILTER (u_short) (0x10<<11)	266#define SET_INTR_MASK (u_short) (0xe<<11) 267#define SET_RD_0_MASK (u_short) (0xf<<11) 268#define SET_RX_FILTER (u_short) (0x10<<11)
271#define FIL_INDIVIDUAL (u_short) (0x1) 272#define FIL_GROUP (u_short) (0x2) 273#define FIL_BRDCST (u_short) (0x4) 274#define FIL_ALL (u_short) (0x8)	269# define FIL_INDIVIDUAL (u_short) (0x1) 270# define FIL_MULTICAST (u_short) (0x02) 271# define FIL_BRDCST (u_short) (0x04) 272# define FIL_PROMISC (u_short) (0x08)
275#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 276#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 277#define SET_TX_START_THRESH (u_short) (0x13<<11) 278#define STATS_ENABLE (u_short) (0x15<<11) 279#define STATS_DISABLE (u_short) (0x16<<11) 280#define STOP_TRANSCEIVER (u_short) (0x17<<11)	273#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 274#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 275#define SET_TX_START_THRESH (u_short) (0x13<<11) 276#define STATS_ENABLE (u_short) (0x15<<11) 277#define STATS_DISABLE (u_short) (0x16<<11) 278#define STOP_TRANSCEIVER (u_short) (0x17<<11)
281/* 282 * The following C_* acknowledge the various interrupts. Some of them don't 283 * do anything. See the manual. 284 / 285#define ACK_INTR (u_short) (0x6800) 286#define C_INTR_LATCH (u_short) (ACK_INTR\|0x1) 287#define C_CARD_FAILURE (u_short) (ACK_INTR\|0x2) 288#define C_TX_COMPLETE (u_short) (ACK_INTR\|0x4) 289#define C_TX_AVAIL (u_short) (ACK_INTR\|0x8) 290#define C_RX_COMPLETE (u_short) (ACK_INTR\|0x10) 291#define C_RX_EARLY (u_short) (ACK_INTR\|0x20) 292#define C_INT_RQD (u_short) (ACK_INTR\|0x40) 293#define C_UPD_STATS (u_short) (ACK_INTR\|0x80) 294#define C_MASK (u_short) 0xFF / mask of C_* */
295 296/* 297 * Status register. All windows. 298 * 299 * 15-13: Window number(0-7). 300 * 12: Command_in_progress. 301 * 11: reserved. 302 * 10: reserved. --- 16 unchanged lines hidden (view full) --- 319#define S_RX_EARLY (u_short) (0x20) 320#define S_INT_RQD (u_short) (0x40) 321#define S_UPD_STATS (u_short) (0x80) 322#define S_MASK (u_short) 0xFF /* mask of S_* / 323#define S_5_INTS (S_CARD_FAILURE\|S_TX_COMPLETE\|\ 324* S_TX_AVAIL\|S_RX_COMPLETE\|S_RX_EARLY) 325#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 326	279 280/* 281 * Status register. All windows. 282 * 283 * 15-13: Window number(0-7). 284 * 12: Command_in_progress. 285 * 11: reserved. 286 * 10: reserved. --- 16 unchanged lines hidden (view full) --- 303#define S_RX_EARLY (u_short) (0x20) 304#define S_INT_RQD (u_short) (0x40) 305#define S_UPD_STATS (u_short) (0x80) 306#define S_MASK (u_short) 0xFF /* mask of S_* / 307#define S_5_INTS (S_CARD_FAILURE\|S_TX_COMPLETE\|\ 308* S_TX_AVAIL\|S_RX_COMPLETE\|S_RX_EARLY) 309#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 310
	311#define EP_BUSY_WAIT while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS) 312
327/* Address Config. Register. 328 * Window 0/Port 06 329 / 330* 331#define ACF_CONNECTOR_BITS 14 332#define ACF_CONNECTOR_UTP 0 333#define ACF_CONNECTOR_AUI 1 334#define ACF_CONNECTOR_BNC 3 335 336/* Resource configuration register. 337 * Window 0/Port 08 338 * 339 / 340*	313/* Address Config. Register. 314 * Window 0/Port 06 315 / 316* 317#define ACF_CONNECTOR_BITS 14 318#define ACF_CONNECTOR_UTP 0 319#define ACF_CONNECTOR_AUI 1 320#define ACF_CONNECTOR_BNC 3 321 322/* Resource configuration register. 323 * Window 0/Port 08 324 * 325 / 326*
341#define SET_IRQ(sc, irq) EP_WRITE_2((sc), EP_W0_RESOURCE_CFG, \ 342 ((EP_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) \| \ 343 ((u_short)(irq)<<12)) ) /* set IRQ i */	327#define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \ 328 ((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) \| \ 329 ((u_short)(irq)<<12)) ) /* set IRQ i */
344 345/* 346 * FIFO Registers. 347 * RX Status. Window 1/Port 08 348 * 349 * 15: Incomplete or FIFO empty. 350 * 14: 1: Error in RX Packet 0: Incomplete or no error. 351 * 13-11: Type of error. --- 48 unchanged lines hidden (view full) --- 400/* Read / 401#define IS_AUI (1<<13) 402#define IS_BNC (1<<12) 403#define IS_UTP (1<<9) 404/ Write / 405#define ENABLE_DRQ_IRQ 0x0001 406#define W0_P4_CMD_RESET_ADAPTER 0x4 407*#define W0_P4_CMD_ENABLE_ADAPTER 0x1	330 331/* 332 * FIFO Registers. 333 * RX Status. Window 1/Port 08 334 * 335 * 15: Incomplete or FIFO empty. 336 * 14: 1: Error in RX Packet 0: Incomplete or no error. 337 * 13-11: Type of error. --- 48 unchanged lines hidden (view full) --- 386/* Read / 387#define IS_AUI (1<<13) 388#define IS_BNC (1<<12) 389#define IS_UTP (1<<9) 390/ Write / 391#define ENABLE_DRQ_IRQ 0x0001 392#define W0_P4_CMD_RESET_ADAPTER 0x4 393*#define W0_P4_CMD_ENABLE_ADAPTER 0x1
	394
408/* 409 * Media type and status. 410 * Window 4/Port 0A 411 */	395/* 396 * Media type and status. 397 * Window 4/Port 0A 398 */
412#define ENABLE_UTP 0xc0 413#define DISABLE_UTP 0x0	399#define JABBER_GUARD_ENABLE 0x40 400#define LINKBEAT_ENABLE 0x80 401#define ENABLE_UTP (JABBER_GUARD_ENABLE \| LINKBEAT_ENABLE) 402#define DISABLE_UTP 0x0
414 415/* 416 * Misc defines for various things. 417 / 418#define ACTIVATE_ADAPTER_TO_CONFIG 0xff / to the id_port / 419#define MFG_ID 0x6d50 / in EEPROM and W0 420 * ADDR_CONFIG / 421#define PROD_ID 0x9150 422* 423#define AUI 0x1 424#define BNC 0x2 425#define UTP 0x4 426 427#define RX_BYTES_MASK (u_short) (0x07ff)	403 404/* 405 * Misc defines for various things. 406 / 407#define ACTIVATE_ADAPTER_TO_CONFIG 0xff / to the id_port / 408#define MFG_ID 0x6d50 / in EEPROM and W0 409 * ADDR_CONFIG / 410#define PROD_ID 0x9150 411* 412#define AUI 0x1 413#define BNC 0x2 414#define UTP 0x4 415 416#define RX_BYTES_MASK (u_short) (0x07ff)
428 429/* 430 * Config flags 431 / 432*#define EP_FLAGS_100TX 0x1

if_epreg.h (121206)	if_epreg.h (121492)
1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from --- 5 unchanged lines hidden (view full) --- 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 *	1/* 2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: 1. Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 2. The name 8 * of the author may not be used to endorse or promote products derived from --- 5 unchanged lines hidden (view full) --- 14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 21 *
22 * $FreeBSD: head/sys/dev/ep/if_epreg.h 121206 2003-10-18 15:22:43Z imp $	22 * $FreeBSD: head/sys/dev/ep/if_epreg.h 121492 2003-10-25 04:09:49Z imp $
23 / 24 25/ 26 * DELAY_MULTIPLE: How much to boost "base" delays, except 27 * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 28 / 29#define DELAY_MULTIPLE 10 30#define BIT_DELAY_MULTIPLE 10 --- 6 unchanged lines hidden* (view full) --- 37#define RX_INIT_LATENCY 64 38#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */ 39#define RX_NEXT_EARLY_THRESH 500 40 41#define EEPROMSIZE 0x40 42#define MAX_EEPROMBUSY 1000 43#define EP_LAST_TAG 0xd7 44#define EP_MAX_BOARDS 16	23 / 24 25/ 26 * DELAY_MULTIPLE: How much to boost "base" delays, except 27 * for the inter-bit delays in get_eeprom_data. A cyrix Media GX needed this. 28 / 29#define DELAY_MULTIPLE 10 30#define BIT_DELAY_MULTIPLE 10 --- 6 unchanged lines hidden* (view full) --- 37#define RX_INIT_LATENCY 64 38#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */ 39#define RX_NEXT_EARLY_THRESH 500 40 41#define EEPROMSIZE 0x40 42#define MAX_EEPROMBUSY 1000 43#define EP_LAST_TAG 0xd7 44#define EP_MAX_BOARDS 16
45/* 46 * This `ID' port is a mere hack. There's currently no chance to register 47 * it with config's idea of the ports that are in use. 48 * 49 * "After the automatic configuration is completed, the IDS is in its initial 50 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where 51 * 'x' is any hex digit. If a zero is written to any one of these ports, then 52 * that address is remembered and becomes the ID port. A second zero written 53 * to that port resets the ID sequence to its initial state. The IDS watches 54 * for the ID sequence to be written to the ID port." 55 * 56 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray 57 * ports. 58 */ 59#define EP_ID_PORT 0x110
60#define EP_IOSIZE 16 /* 16 bytes of I/O space used. / 61 62/ 63 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 64 * Offset 0xa) 65 / 66#define EEPROM_CMD_RD 0x0080 / Read: Address required (5 bits) / 67#define EEPROM_CMD_WR 0x0040 / Write: Address required (5 bits) / 68#define EEPROM_CMD_ERASE 0x00c0 / Erase: Address required (5 bits) / 69#define EEPROM_CMD_EWEN 0x0030 / Erase/Write Enable: No data required / 70 71#define EEPROM_BUSY (1<<15) 72#define EEPROM_TST_MODE (1<<14) 73 74/ 75 * Some short functions, worth to let them be a macro 76 */	45#define EP_IOSIZE 16 /* 16 bytes of I/O space used. / 46 47/ 48 * Commands to read/write EEPROM trough EEPROM command register (Window 0, 49 * Offset 0xa) 50 / 51#define EEPROM_CMD_RD 0x0080 / Read: Address required (5 bits) / 52#define EEPROM_CMD_WR 0x0040 / Write: Address required (5 bits) / 53#define EEPROM_CMD_ERASE 0x00c0 / Erase: Address required (5 bits) / 54#define EEPROM_CMD_EWEN 0x0030 / Erase/Write Enable: No data required / 55 56#define EEPROM_BUSY (1<<15) 57#define EEPROM_TST_MODE (1<<14) 58 59/ 60 * Some short functions, worth to let them be a macro 61 */
77#define is_eeprom_busy(sc) (EP_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 78#define GO_WINDOW(x) EP_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT\|(x))	62#define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY) 63#define GO_WINDOW(x) CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT\|(x))
79 80/************************************************************************** 81 * * 82 * These define the EEPROM data structure. They are used in the probe 83 * function to verify the existence of the adapter after having sent 84 * the ID_Sequence. 85 * 86 ************************************************************************/ --- 57 unchanged lines hidden** (view full) --- 144 * Window 0 registers. Setup. 145 / 146/ Write / 147#define EP_W0_EEPROM_DATA 0x0c 148#define EP_W0_EEPROM_COMMAND 0x0a 149#define EP_W0_RESOURCE_CFG 0x08 150#define EP_W0_ADDRESS_CFG 0x06 151*#define EP_W0_CONFIG_CTRL 0x04	64 65/************************************************************************** 66 * * 67 * These define the EEPROM data structure. They are used in the probe 68 * function to verify the existence of the adapter after having sent 69 * the ID_Sequence. 70 * 71 ************************************************************************/ --- 57 unchanged lines hidden** (view full) --- 129 * Window 0 registers. Setup. 130 / 131/ Write / 132#define EP_W0_EEPROM_DATA 0x0c 133#define EP_W0_EEPROM_COMMAND 0x0a 134#define EP_W0_RESOURCE_CFG 0x08 135#define EP_W0_ADDRESS_CFG 0x06 136*#define EP_W0_CONFIG_CTRL 0x04
152/* Read */	137 /* Read */
153#define EP_W0_PRODUCT_ID 0x02 154#define EP_W0_MFG_ID 0x00 155 156/* 157 * Window 1 registers. Operating Set. 158 / 159/ Write / 160#define EP_W1_TX_PIO_WR_2 0x02 --- 99 unchanged lines hidden* (view full) --- 260 * power-up / 261#define RX_ENABLE (u_short) (0x4<<11) 262#define RX_RESET (u_short) (0x5<<11) 263#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 264#define TX_ENABLE (u_short) (0x9<<11) 265#define TX_DISABLE (u_short) (0xa<<11) 266#define TX_RESET (u_short) (0xb<<11) 267*#define REQ_INTR (u_short) (0xc<<11)	138#define EP_W0_PRODUCT_ID 0x02 139#define EP_W0_MFG_ID 0x00 140 141/* 142 * Window 1 registers. Operating Set. 143 / 144/ Write / 145#define EP_W1_TX_PIO_WR_2 0x02 --- 99 unchanged lines hidden* (view full) --- 245 * power-up / 246#define RX_ENABLE (u_short) (0x4<<11) 247#define RX_RESET (u_short) (0x5<<11) 248#define RX_DISCARD_TOP_PACK (u_short) (0x8<<11) 249#define TX_ENABLE (u_short) (0x9<<11) 250#define TX_DISABLE (u_short) (0xa<<11) 251#define TX_RESET (u_short) (0xb<<11) 252*#define REQ_INTR (u_short) (0xc<<11)
	253/* 254 * The following C_* acknowledge the various interrupts. Some of them don't 255 * do anything. See the manual. 256 / 257#define ACK_INTR (u_short) (0x6800) 258# define C_INTR_LATCH (u_short) (ACK_INTR\|0x1) 259# define C_CARD_FAILURE (u_short) (ACK_INTR\|0x2) 260# define C_TX_COMPLETE (u_short) (ACK_INTR\|0x4) 261# define C_TX_AVAIL (u_short) (ACK_INTR\|0x8) 262# define C_RX_COMPLETE (u_short) (ACK_INTR\|0x10) 263# define C_RX_EARLY (u_short) (ACK_INTR\|0x20) 264# define C_INT_RQD (u_short) (ACK_INTR\|0x40) 265*# define C_UPD_STATS (u_short) (ACK_INTR\|0x80)
268#define SET_INTR_MASK (u_short) (0xe<<11) 269#define SET_RD_0_MASK (u_short) (0xf<<11) 270#define SET_RX_FILTER (u_short) (0x10<<11)	266#define SET_INTR_MASK (u_short) (0xe<<11) 267#define SET_RD_0_MASK (u_short) (0xf<<11) 268#define SET_RX_FILTER (u_short) (0x10<<11)
271#define FIL_INDIVIDUAL (u_short) (0x1) 272#define FIL_GROUP (u_short) (0x2) 273#define FIL_BRDCST (u_short) (0x4) 274#define FIL_ALL (u_short) (0x8)	269# define FIL_INDIVIDUAL (u_short) (0x1) 270# define FIL_MULTICAST (u_short) (0x02) 271# define FIL_BRDCST (u_short) (0x04) 272# define FIL_PROMISC (u_short) (0x08)
275#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 276#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 277#define SET_TX_START_THRESH (u_short) (0x13<<11) 278#define STATS_ENABLE (u_short) (0x15<<11) 279#define STATS_DISABLE (u_short) (0x16<<11) 280#define STOP_TRANSCEIVER (u_short) (0x17<<11)	273#define SET_RX_EARLY_THRESH (u_short) (0x11<<11) 274#define SET_TX_AVAIL_THRESH (u_short) (0x12<<11) 275#define SET_TX_START_THRESH (u_short) (0x13<<11) 276#define STATS_ENABLE (u_short) (0x15<<11) 277#define STATS_DISABLE (u_short) (0x16<<11) 278#define STOP_TRANSCEIVER (u_short) (0x17<<11)
281/* 282 * The following C_* acknowledge the various interrupts. Some of them don't 283 * do anything. See the manual. 284 / 285#define ACK_INTR (u_short) (0x6800) 286#define C_INTR_LATCH (u_short) (ACK_INTR\|0x1) 287#define C_CARD_FAILURE (u_short) (ACK_INTR\|0x2) 288#define C_TX_COMPLETE (u_short) (ACK_INTR\|0x4) 289#define C_TX_AVAIL (u_short) (ACK_INTR\|0x8) 290#define C_RX_COMPLETE (u_short) (ACK_INTR\|0x10) 291#define C_RX_EARLY (u_short) (ACK_INTR\|0x20) 292#define C_INT_RQD (u_short) (ACK_INTR\|0x40) 293#define C_UPD_STATS (u_short) (ACK_INTR\|0x80) 294#define C_MASK (u_short) 0xFF / mask of C_* */
295 296/* 297 * Status register. All windows. 298 * 299 * 15-13: Window number(0-7). 300 * 12: Command_in_progress. 301 * 11: reserved. 302 * 10: reserved. --- 16 unchanged lines hidden (view full) --- 319#define S_RX_EARLY (u_short) (0x20) 320#define S_INT_RQD (u_short) (0x40) 321#define S_UPD_STATS (u_short) (0x80) 322#define S_MASK (u_short) 0xFF /* mask of S_* / 323#define S_5_INTS (S_CARD_FAILURE\|S_TX_COMPLETE\|\ 324* S_TX_AVAIL\|S_RX_COMPLETE\|S_RX_EARLY) 325#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 326	279 280/* 281 * Status register. All windows. 282 * 283 * 15-13: Window number(0-7). 284 * 12: Command_in_progress. 285 * 11: reserved. 286 * 10: reserved. --- 16 unchanged lines hidden (view full) --- 303#define S_RX_EARLY (u_short) (0x20) 304#define S_INT_RQD (u_short) (0x40) 305#define S_UPD_STATS (u_short) (0x80) 306#define S_MASK (u_short) 0xFF /* mask of S_* / 307#define S_5_INTS (S_CARD_FAILURE\|S_TX_COMPLETE\|\ 308* S_TX_AVAIL\|S_RX_COMPLETE\|S_RX_EARLY) 309#define S_COMMAND_IN_PROGRESS (u_short) (0x1000) 310
	311#define EP_BUSY_WAIT while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS) 312
327/* Address Config. Register. 328 * Window 0/Port 06 329 / 330* 331#define ACF_CONNECTOR_BITS 14 332#define ACF_CONNECTOR_UTP 0 333#define ACF_CONNECTOR_AUI 1 334#define ACF_CONNECTOR_BNC 3 335 336/* Resource configuration register. 337 * Window 0/Port 08 338 * 339 / 340*	313/* Address Config. Register. 314 * Window 0/Port 06 315 / 316* 317#define ACF_CONNECTOR_BITS 14 318#define ACF_CONNECTOR_UTP 0 319#define ACF_CONNECTOR_AUI 1 320#define ACF_CONNECTOR_BNC 3 321 322/* Resource configuration register. 323 * Window 0/Port 08 324 * 325 / 326*
341#define SET_IRQ(sc, irq) EP_WRITE_2((sc), EP_W0_RESOURCE_CFG, \ 342 ((EP_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) \| \ 343 ((u_short)(irq)<<12)) ) /* set IRQ i */	327#define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \ 328 ((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) \| \ 329 ((u_short)(irq)<<12)) ) /* set IRQ i */
344 345/* 346 * FIFO Registers. 347 * RX Status. Window 1/Port 08 348 * 349 * 15: Incomplete or FIFO empty. 350 * 14: 1: Error in RX Packet 0: Incomplete or no error. 351 * 13-11: Type of error. --- 48 unchanged lines hidden (view full) --- 400/* Read / 401#define IS_AUI (1<<13) 402#define IS_BNC (1<<12) 403#define IS_UTP (1<<9) 404/ Write / 405#define ENABLE_DRQ_IRQ 0x0001 406#define W0_P4_CMD_RESET_ADAPTER 0x4 407*#define W0_P4_CMD_ENABLE_ADAPTER 0x1	330 331/* 332 * FIFO Registers. 333 * RX Status. Window 1/Port 08 334 * 335 * 15: Incomplete or FIFO empty. 336 * 14: 1: Error in RX Packet 0: Incomplete or no error. 337 * 13-11: Type of error. --- 48 unchanged lines hidden (view full) --- 386/* Read / 387#define IS_AUI (1<<13) 388#define IS_BNC (1<<12) 389#define IS_UTP (1<<9) 390/ Write / 391#define ENABLE_DRQ_IRQ 0x0001 392#define W0_P4_CMD_RESET_ADAPTER 0x4 393*#define W0_P4_CMD_ENABLE_ADAPTER 0x1
	394
408/* 409 * Media type and status. 410 * Window 4/Port 0A 411 */	395/* 396 * Media type and status. 397 * Window 4/Port 0A 398 */
412#define ENABLE_UTP 0xc0 413#define DISABLE_UTP 0x0	399#define JABBER_GUARD_ENABLE 0x40 400#define LINKBEAT_ENABLE 0x80 401#define ENABLE_UTP (JABBER_GUARD_ENABLE \| LINKBEAT_ENABLE) 402#define DISABLE_UTP 0x0
414 415/* 416 * Misc defines for various things. 417 / 418#define ACTIVATE_ADAPTER_TO_CONFIG 0xff / to the id_port / 419#define MFG_ID 0x6d50 / in EEPROM and W0 420 * ADDR_CONFIG / 421#define PROD_ID 0x9150 422* 423#define AUI 0x1 424#define BNC 0x2 425#define UTP 0x4 426 427#define RX_BYTES_MASK (u_short) (0x07ff)	403 404/* 405 * Misc defines for various things. 406 / 407#define ACTIVATE_ADAPTER_TO_CONFIG 0xff / to the id_port / 408#define MFG_ID 0x6d50 / in EEPROM and W0 409 * ADDR_CONFIG / 410#define PROD_ID 0x9150 411* 412#define AUI 0x1 413#define BNC 0x2 414#define UTP 0x4 415 416#define RX_BYTES_MASK (u_short) (0x07ff)
428 429/* 430 * Config flags 431 / 432*#define EP_FLAGS_100TX 0x1