1/* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 10 unchanged lines hidden (view full) --- 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * |
27 * $FreeBSD: head/sys/dev/ed/if_edvar.h 64777 2000-08-17 12:15:45Z nyan $ |
28 */ 29 30/* 31 * ed_softc: per line info and status 32 */ 33struct ed_softc { 34 struct arpcom arpcom; /* ethernet common */ 35 --- 7 unchanged lines hidden (view full) --- 43 struct resource* port_res; /* resource for port range */ 44 int mem_rid; /* resource id for memory range */ 45 int mem_used; /* nonzero if memory used */ 46 struct resource* mem_res; /* resource for memory range */ 47 int irq_rid; /* resource id for irq */ 48 struct resource* irq_res; /* resource for irq */ 49 void* irq_handle; /* handle for irq handler */ 50 |
51 int nic_offset; /* NIC (DS8390) I/O bus address offset */ 52 int asic_offset; /* ASIC I/O bus address offset */ |
53 |
54/* 55 * The following 'proto' variable is part of a work-around for 8013EBT asics 56 * being write-only. It's sort of a prototype/shadow of the real thing. 57 */ 58 u_char wd_laar_proto; 59 u_char cr_proto; 60 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 61 int chip_type; /* the type of chip (one of ED_CHIP_TYPE_*) */ 62 63/* 64 * HP PC LAN PLUS card support. 65 */ 66 67 u_short hpp_options; /* flags controlling behaviour of the HP card */ 68 u_short hpp_id; /* software revision and other fields */ |
69 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ |
70 |
71 caddr_t mem_start; /* NIC memory start address */ 72 caddr_t mem_end; /* NIC memory end address */ |
73 u_int32_t mem_size; /* total NIC memory size */ |
74 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ |
75 76 u_char mem_shared; /* NIC memory is shared with host */ 77 u_char xmit_busy; /* transmitter is busy */ 78 u_char txb_cnt; /* number of transmit buffers */ 79 u_char txb_inuse; /* number of TX buffers currently in-use */ 80 81 u_char txb_new; /* pointer to where new buffer will be added */ 82 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 83 u_short txb_len[8]; /* buffered xmit buffer lengths */ 84 u_char tx_page_start; /* first page of TX buffer area */ 85 u_char rec_page_start; /* first page of RX ring-buffer */ 86 u_char rec_page_stop; /* last page of RX ring-buffer */ 87 u_char next_packet; /* pointer to next unread RX packet */ 88 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 89}; 90 |
91#define ed_nic_inb(sc, port) \ 92 bus_space_read_1(rman_get_bustag((sc)->port_res), \ 93 rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port)) 94 95#define ed_nic_outb(sc, port, value) \ 96 bus_space_write_1(rman_get_bustag((sc)->port_res), \ 97 rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port), \ 98 (value)) 99 100#define ed_nic_inw(sc, port) \ 101 bus_space_read_2(rman_get_bustag((sc)->port_res), \ 102 rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port)) 103 104#define ed_nic_outw(sc, port, value) \ 105 bus_space_write_2(rman_get_bustag((sc)->port_res), \ 106 rman_get_bushandle((sc)->port_res), (sc)->nic_offset + (port), \ 107 (value)) 108 109#define ed_nic_insb(sc, port, addr, count) \ 110 bus_space_read_multi_1(rman_get_bustag((sc)->port_res), \ 111 rman_get_bushandle((sc)->port_res), \ 112 (sc)->nic_offset + (port), (addr), (count)) 113 114#define ed_nic_outsb(sc, port, addr, count) \ 115 bus_space_write_multi_1(rman_get_bustag((sc)->port_res), \ 116 rman_get_bushandle((sc)->port_res), \ 117 (sc)->nic_offset + (port), (addr), (count)) 118 119#define ed_nic_insw(sc, port, addr, count) \ 120 bus_space_read_multi_2(rman_get_bustag((sc)->port_res), \ 121 rman_get_bushandle((sc)->port_res), \ 122 (sc)->nic_offset + (port), (u_int16_t *)(addr), (count)) 123 124#define ed_nic_outsw(sc, port, addr, count) \ 125 bus_space_write_multi_2(rman_get_bustag((sc)->port_res), \ 126 rman_get_bushandle((sc)->port_res), \ 127 (sc)->nic_offset + (port), (u_int16_t *)(addr), (count)) 128 129#define ed_nic_insl(sc, port, addr, count) \ 130 bus_space_read_multi_4(rman_get_bustag((sc)->port_res), \ 131 rman_get_bushandle((sc)->port_res), \ 132 (sc)->nic_offset + (port), (u_int32_t *)(addr), (count)) 133 134#define ed_nic_outsl(sc, port, addr, count) \ 135 bus_space_write_multi_4(rman_get_bustag((sc)->port_res), \ 136 rman_get_bushandle((sc)->port_res), \ 137 (sc)->nic_offset + (port), (u_int32_t *)(addr), (count)) 138 139#define ed_asic_inb(sc, port) \ 140 bus_space_read_1(rman_get_bustag((sc)->port_res), \ 141 rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port)) 142 143#define ed_asic_outb(sc, port, value) \ 144 bus_space_write_1(rman_get_bustag((sc)->port_res), \ 145 rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port), \ 146 (value)) 147 148#define ed_asic_inw(sc, port) \ 149 bus_space_read_2(rman_get_bustag((sc)->port_res), \ 150 rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port)) 151 152#define ed_asic_outw(sc, port, value) \ 153 bus_space_write_2(rman_get_bustag((sc)->port_res), \ 154 rman_get_bushandle((sc)->port_res), (sc)->asic_offset + (port), \ 155 (value)) 156 157#define ed_asic_insb(sc, port, addr, count) \ 158 bus_space_read_multi_1(rman_get_bustag((sc)->port_res), \ 159 rman_get_bushandle((sc)->port_res), \ 160 (sc)->asic_offset + (port), (addr), (count)) 161 162#define ed_asic_outsb(sc, port, addr, count) \ 163 bus_space_write_multi_1(rman_get_bustag((sc)->port_res), \ 164 rman_get_bushandle((sc)->port_res), \ 165 (sc)->asic_offset + (port), (addr), (count)) 166 167#define ed_asic_insw(sc, port, addr, count) \ 168 bus_space_read_multi_2(rman_get_bustag((sc)->port_res), \ 169 rman_get_bushandle((sc)->port_res), \ 170 (sc)->asic_offset + (port), (u_int16_t *)(addr), (count)) 171 172#define ed_asic_outsw(sc, port, addr, count) \ 173 bus_space_write_multi_2(rman_get_bustag((sc)->port_res), \ 174 rman_get_bushandle((sc)->port_res), \ 175 (sc)->asic_offset + (port), (u_int16_t *)(addr), (count)) 176 177#define ed_asic_insl(sc, port, addr, count) \ 178 bus_space_read_multi_4(rman_get_bustag((sc)->port_res), \ 179 rman_get_bushandle((sc)->port_res), \ 180 (sc)->asic_offset + (port), (u_int32_t *)(addr), (count)) 181 182#define ed_asic_outsl(sc, port, addr, count) \ 183 bus_space_write_multi_4(rman_get_bustag((sc)->port_res), \ 184 rman_get_bushandle((sc)->port_res), \ 185 (sc)->asic_offset + (port), (u_int32_t *)(addr), (count)) 186 |
187void ed_release_resources __P((device_t)); 188int ed_alloc_port __P((device_t, int, int)); 189int ed_alloc_memory __P((device_t, int, int)); 190int ed_alloc_irq __P((device_t, int, int)); 191 192int ed_probe_generic8390 __P((struct ed_softc *)); |
193int ed_probe_WD80x3 __P((device_t, int, int)); 194int ed_probe_WD80x3_generic __P((device_t, int, unsigned short *[])); 195int ed_probe_3Com __P((device_t, int, int)); 196int ed_probe_Novell __P((device_t, int, int)); 197int ed_probe_Novell_generic __P((device_t, int)); 198int ed_probe_HP_pclanp __P((device_t, int, int)); 199 |
200int ed_get_Linksys __P((struct ed_softc *)); |
201 202int ed_attach __P((struct ed_softc *, int, int)); 203void ed_stop __P((struct ed_softc *)); |
204void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 205 unsigned short)); 206void ed_pio_writemem __P((struct ed_softc *, char *, 207 unsigned short, unsigned short)); |
208 209driver_intr_t edintr; 210 |